TP2435 TP2435 Low Threshold P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information * Order Number / Package BVDSS / RDS(ON) VGS(th) ID(ON) BVDGS (max) (max) (min) TO-243AA* Die** -350V 15 -2.4V -800mA TP2435N8 TP2435NW Same as SOT-89. Product supplied on 2000 piece carrier tape reels. ** Die in wafer form. Features Low Threshold DMOS Technology Low threshold These low threshold enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's wellproven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, these devices are free from thermal runaway and thermally induced secondary breakdown. High input impedance Low input capacitance Fast switching speeds Free from secondary breakdown Low input and output leakage Complementary N- and P-channel devices Supertex's vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Applications Logic level interfaces Solid state relays Package Options Linear Amplifiers Power Management Analog switches Telecom switches D G Absolute Maximum Ratings Drain-to-Source Voltage BVDSS Drain-to-Gate Voltage BVDGS Gate-to-Source Voltage 20V Operating and Storage Temperature Soldering Temperature* D S TO-243AA (SOT-89) -55C to +150C 300C * Distance of 1.6 mm from case for 10 seconds. Note: See Package Outline section for dimensions. 08/17/99 Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For complete liability information covering this and other Supertex products, refer to the Supertex 1998 Databook. 1 TP2435 Thermal Characteristics Package ID (continuous)* TO-243AA ID (pulsed) -231mA Power Dissipation jc ja @ TA = 25C C/W C/W 1.6W 15 78 -1.1A IDR* IDRM -231mA -1.1A * ID (continuous) is limited by max rated Tj. Mounted on FR5 board, 25mm x 25mm x 1.57mm. Significant PD increase possible on ceramic substrate. Electrical Characteristics (@ 25C unless otherwise specified) Symbol Parameter Min Typ BVDSS Drain-to-Source Breakdown Voltage -350 VGS(th) Gate Threshold Voltage -1.0 VGS(th) Change in VGS(th) with Temperature IGSS Gate Body Leakage IDSS Zero Gate Voltage Drain Current ID(ON) ON-State Drain Current Max Conditions V VGS = 0V, ID = -250A -2.4 V VGS = VDS, ID= -1.0mA 4.5 mV/C VGS = VDS, ID= -1.0mA -100 nA VGS = 20V, VDS = 0V -10.0 A VGS = 0V, VDS = Max Rating -1.0 mA VGS = 0V, VDS = 0.8 Max Rating TA = 125C -0.3 A -0.8 RDS(ON) Unit Static Drain-to-Source ON-State Resistance 15 15 GFS Forward Transconductance CISS Input Capacitance COSS Common Source Output Capacitance 70 CRSS Reverse Transfer Capacitance 25 td(ON) Turn-ON Delay Time 15 tr Rise Time 20 1.7 125 VGS = -4.5V, ID = -150mA VGS = -10V, ID = -500mA %/C VGS = -10V, ID = -150mA Change in RDS(ON) with Temperature VGS = -10V, VDS = -25V VGS = -3.0V, ID = -20mA 15 RDS(ON) VGS = -4.5V, VDS = -25V VDS = -25V, ID = -350mA m 200 td(OFF) Turn-OFF Delay Time 25 tf Fall Time 50 VSD Diode Forward Voltage Drop trr Reverse Recovery Time -1.5 300 pF VGS = 0V, VDS = -25V f = 1.0 MHz ns VDD = -25V, ID = -250mA, RGEN = 25 V VGS = 0V, ISD = -750mA ns VGS = 0V, ISD = -750mA Notes: 1.All D.C. parameters 100% tested at 25C unless otherwise stated. (Pulse test: 300s pulse, 2% duty cycle.) 2.All A.C. parameters sample tested. Switching Waveforms and Test Circuit 0V 10% PULSE GENERATOR INPUT 90% -10V t(ON) td(ON) Rgen t(OFF) td(OFF) tr tF D.U.T. 0V 90% OUTPUT INPUT 90% RL OUTPUT VDD 10% 10% VDD 2 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 * FAX: (408) 222-4895 www.supertex.com 08/17/99 VF24 Die Specifications VF24 S G Backside: Drain All dimensions in mils. Bonding Pads3 Dimensions Recommended Assembly Material 2 Die Geometry Length1 Width VF24 55 55 Thickness Backside Metal Material Size Wire4 Wire Size4 Preform5 11 1.5 Au Al-Si 5x7 Au 1.5 Epoxy Notes: 1. Maximum values 2. Standard Au back is alloyed for optimum eutectic die attach. Ag backing is optional. 3. Al-Cu-Si is used for higher operating current densities. Bond pad size represents smaller gate pad. 4. Bond wire size and material depends on AuTCB, TSB or Al USB. 5. Soft solder or organic die attach methods may be used with appropriate backmetal option. CH06F SOT-23 K1 TO-92 N3 SOT-89 N8 Die ND *2 LP07 * VF25 Device Number BVDSS min (V) RDS(ON) max () CISS typ (pf) VGS(th) max (V) LP0701 -16.5 1.5 120 -1.0 TP2502 -20 2.0 100 -2.4 TP06045 -40 2.0 95 -2.4 TP2104 -40 6.0 45 -2.0 TP0606 -60 3.5 80 -2.4 TP0610 -60 10.0 60 -2.4 TP2510 -100 3.5 80 -2.4 TP0620 -200 12.0 85 -2.4 TP2520 -200 12.0 75 -2.4 * TP2522 -220 12.0 75 -2.4 * VF25 TP2424 -240 8.0 200 -2.4 * VF24 TP2635 -350 15.0 220 -2.0 TP2435 -350 15.0 2004 -2.4 * VF24 TP2535 -350 25.0 60 -2.4 TP5335 -350 25.0 65 -2.4 TP2640 -400 15.0 220 -2.0 * *2 VF26 TP2540 -400 25.0 60 -2.4 * * VF25 Quad1 * * * * VF21 * * *3 * VF25 * * * * Add package suffix for complete part number, e.g., TP2510N8 is TP2510 in a SOT-89 package. Notes: 1. Package options are defined on individual data sheets. 2. SO-8 (LG) package. 3. Use package suffix "T" instead of "K1". 4. Rated at Maximum Value. 5. Not recommended for new designs. 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