PRELIMINARY
100MHz Pentium®I I Clock Synt hesizer/ Driver
with Spread Spectrum for Mobile PCs
CY2281
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
July 21, 1999
Features
•Mixed 2.5V and 3.3V operation
•Complete cloc k solution f or P entium® II, and other sim-
ilar processor-based m o therboards
—Two CPU clocks at 2.5V up to 100 MHz
—Six synchronous PCI clocks, one free- running
—One 3.3V Ref. clock at 14.318 MHz
—One 3.3V USB clock at 48 MHz (-2S onl y)
• Spread Spectrum cloc king for EMI control (- 11S, -2S)
• 1.5–4.0 ns del ay be tween CPU and PCI cloc ks
•Power-down, CPU stop and PCI stop pins
•Low skew outputs, ≤ 175 ps between CPU clocks
•Factory-EPROM pr ogrammable output drive and slew
rate for EMI customization
• Available in space-saving 28-pin SSO P package
Functional Description
The CY2281 is a clock synthesizer/driver for Pentium II, or
other simila r processor-based mobile PCs requiri ng up to 10 0
MHz support. The CY2281 outputs two CPU clocks at 2.5V.
There are six PCI clocks, running at one-half or one-third the
CPU clock frequency of 66.6 MHz and 100 MHz respect ively.
One of the PCI clocks is free-running. Additionally, the part
outputs one 3.3V reference clock at 14.318 MHz. The
CY2281-2S also provides one 3.3V USB clock at 48 MHz.
The CY2281-11S and CY2281-2S incor porate the I ntel®-de-
fined spread spectrum feature. They provide a –0.6%
downspread on the CPU and PCI clocks, which can help re-
duce EMI in cer tain high-speed systems. A summar y of clock
outputs for both devices is shown bel ow.
The part poss esses power-do wn, CPU stop , and PCI stop pins
for power man agem ent control. T he signals are synchr onized
on-chip, and ensure glitch-free transitions on the outputs.
When the CPU_STOP input is asserted, the CPU clock out-
puts are dr iven LOW. When the PCI_STOP input is asserted,
the PCI clock outputs (except the free-running PCI clock) are
driven LOW. When the PWR_DWN pin is asserted, the refer-
ence oscillator and PLLs are shut down, and all outputs are
driv en LOW.
The CY2281 clock outputs are designed for low EMI emis-
sions. Controlled rise and fall times, unique output driver cir-
cuits, and innovative circuit layout techniques enable the
CY2281 to ha ve low er EMI than cloc k de vices fro m other man-
uf acturers . Addi tionally, f actory-EPROM prog rammab le ou tput
drive and slew- rate control enab le optimal conf igurations .
CY2281 Selector Guide
Note:
1. One free-running PCI clock.
Clo ck O u t p u ts - 1 - 1 1S - 2S
CPU (66, 100 MHz) 2 2 2
PCI (CPU/2, CPU/3) 6[1] 6[1] 6[1]
REF (14.318 MHz) 1 1 1
USB (48 MHz) N/A N/A 1
CPU-PCI del ay 1.5–4.0 ns 1.5–4.0 ns 1.5–4.0 ns
Spread Spectrum None –0.6% –0.6%
Intel an d Pentium are reg ister ed trademarks of Intel Corpo ration.
Pin Configuration
Logic Bloc k Diagram
EPROM
XTALOUT
XTALIN 14.318
MHz
OSC. CPU
PLL
SEL100
Delay
REF
CPUCLK [0–1]
VDDCPU
PCI [1-5]
PCICLK_F
STOP
STOP
LOGIC
LOGIC
SEL
CPU_STOP
PWR_DWN Divider
PCI_STOP
VDDPCI
VDDPCI
VDDREF
1
2
3
4
5
6
7
8
9
16
15
19
18
17
28-Pin SSOP
Top View
10
11
12
13
14
28
27
26
25
24
20
21
22
23
CY2281
XTALIN
XTALOUT
PCICLK_F
VSS
PCICLK1
PCICLK2
VDDPCI
PCICLK3
VDDPCI
PCICLK4
VSS
PCICLK5
VSS
VSS
VDDREF
REF
VDDCPU
CPUCLK0
CPUCLK1
VSS
AVDD
VSS
PCI_STOP
CPU_STOP
PWR_DWN
SEE CHART BELOW
SEL100
VDDUSB
Option
-1,-11S
-2S
Pin 16
SEL
USBCLK
USBCLK (-2S only )
VDDUSB
SYS
PLL
(-1/-11S only)
CY2281
PRELIMINARY
2
Pin Summary
Name Pins Description
VDDPCI 6, 9 3.3V Di gital voltage supply for PCI clocks
VDDREF 27 3.3V Digital voltage supply for REF clocks
VDDCPU 25 2.5V Digital voltage suppl y for CPU clocks
VDDUSB 13 3.3V Digital voltage supply for USB clock
AVDD 21 Analog vol tage supply, 3.3V
VSS 3, 12, 14, 20, 22, 28 Ground
XTALIN[2] 1Refer ence cryst al input
XTALOUT[2] 2Reference crystal feedbac k
PCI_STOP 19 Active LOW contr ol input to stop PCI clocks
CPU_STOP 18 Active LOW contr ol input to st op CPU clocks
PWR_DWN 17 Active LOW control input to power down device
SEL 16 CPU frequency select input (- 1 and -11S opti ons on ly)
USBCLK 16 USB clock output, 48 MHz fixed (-2S optio n only)
SEL100 15 CPU frequency select inp ut, selects between 100 MH z and 66.6 MHz
(see table belo w )
CPUCLK[0:1] 23, 24 CPU clock outputs
PCICLK[1:5] 5, 7, 8, 10, 11 PCI clock outputs, at one-half or one-third the CPU frequency of 66.6 MHz
or 100 MHz respectively
PCICLK_F 4Free-runnin g PCI cloc k output
REF 26 3.3V Reference cl ock output
Function Table
SEL100 SEL[4] CPU/PCI
Ratio CPUCLK PCICLK_F
PCICLK USBCLK[5] REF
0 0 2 Hi-Z Hi-Z Hi-Z
0 1 2 66.66 MHz 33.33 MHz 48 MHz 14.318 MHz
1 0 3 TCLK/2 TCLK/6 TCLK[3]
1 1 3 100 MHz 33.33 MHz 48 MHz 14.318 MHz
Notes:
2. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF.
3. TCLK supplied on the XTALIN pin in Test Mode.
4. SEL available on options -1 and -11S only. SEL tied HIGH internally on option -2S
5. USBCLK a vailable on option -2S only.
CY2281
PRELIMINARY
3
Actual Clock Frequency Va lues
Clock Output Target Frequency
(MHz) Actual Frequency
(MHz) PPM
CPUCLK 66.67 66.654 –195
CPUCLK 100 99.77 –2346
USB 48 48.008 167
Power Management Logic
CPU_STOP PCI_STOP PWR_DWN CPUCLK PCICLK PCICLK_F Other
Clocks Osc. PLLs
X X 0 Low Low Low Low Off Off
0 0 1 Low Low Running Running Running Running
0 1 1 Low Running Running Running Running Running
1 0 1 Running Low Running Running Running Running
1 1 1 Running Running Running Running Running Running
CY2281
PRELIMINARY
4
Maximum Ratings
(Above which the useful l ife ma y be impaired. For user gui de-
li nes, not tested .)
Su pply Volta g e... .. .. ..... ... ..... .. .. ..... ... .. ..... ... .... . –0.5V to +7.0V
Input Voltage....... .... ... ........ .... ....... ... ........ ..–0.5V to VDD+0.5
Storage Temperature (Non- Condensing) ... –65°C to +150°C
Max. Solderi ng Temperature (10 sec)....... ....... ........ +260°C
Junction Temperature............................................... +150°C
Static Discharge Voltage .......................................... >1700V
(per MIL- STD-883, Method 3015 , like VDD pins ti ed together)
Operating Conditions [6]
Parameter Description Min. Max. Unit
AVDD, VDDPCI,
VDDREF, VDDUSB Analog and Digital Supply Voltage 3.135 3.465 V
VDDCPU CPU Supply Voltage 2.375 2.625 V
TAOper ating Temperature, Ambi ent 0 70 °C
CLMax. Capacitive Load on
CPUCLK
PCICLK
REF
20
30
20
pF
f(REF) Reference Frequency, Oscillat or Nominal Value 14.318 14.318 MHz
Electrical Characteristics Over the Operating Range
Parameter Descripti on Test Conditions Min. Max. Unit
VIH High-level Input Voltage Except Cr ystal Inputs[7] 2.0 V
VIL Low-level Input Voltage Except Crystal Inputs[7] 0.8 V
VOH High-level Output Voltage VDDCPU = 2.375V IOH = 12 mA CPUCLK 2.0 V
VOL Low-lev el Output Voltage VDDCPU = 2.375V I OL = 12 mA CPUCLK 0.4 V
VOH High-level Output Voltage VDDPCI, AVDD, VDDREF = 3.135V IOH = 14.5 mA PCICLK 2.4 V
IOH = 16 mA REF, USB
VOL Low-lev el Output Voltage VDDPCI, AVDD, VDDREF = 3.135V IOL = 9.4 mA PCICLK 0.4V V
IOL = 9 mA REF, USB
IIH Input High Current VIH = VDD –10 +10 µA
IIL Input Lo w Curr ent VIL = 0V 10 µA
IOZ Output Leakage Current Three- state –10 +10 µA
IDD25 P ower Supply Curren t for
2.5V Clocks VDDCPU = 2.625V, VIN = 0 or V DD, Loaded Outpu ts, CPU = 66.6 MHz 70 mA
IDD25 P ower Supply Curren t for
2.5V Clocks VDDCPU = 2.625V, VIN = 0 or VDD, Loaded Outputs, CPU = 100 MHz 100 mA
IDD33 P ower Supply Curren t for
3.3V Clocks VDD = 3.465V, VIN = 0 or VDD, Loaded Outputs 170 mA
IDDS P owerdown Cur rent Curre nt draw in powerdown state 500 µA
Notes:
6. Electrical parameters are guaranteed with these operating conditions.
7. Crystal Inputs have CMOS thresholds.
CY2281
PRELIMINARY
5
Switching Characteristics[8] Over the Operati ng Range
Parameter Output Description Test Condi tions Min. Typ. Max. Unit
t1All Output Duty Cycle[9] t1 = t1A ÷ t1B 45 50 55 %
t2CPUCLK CPU Clock Rising and
Falling Edge Rat e Between 0.4V and 2.0V 0.85 4.0 V/ns
t2PCICLK PCI Cloc k Risi ng and
Falling Edge Rat e Between 0.4V and 2.4V 1.0 4.0 V/ns
t2REF, USB REF Clock Rising and
Falling Edge Rat e Between 0.4V and 2.4V 0.5 2.0 V/ns
t3CPUCLK CPU Clock Rise Ti me Between 0.4V and 2.0V 0.4 1.6 ns
t4CPUCLK CPU Clock Fall Time Between 2.0V and 0.4V 0.4 1.6 ns
t5CPUCLK CPU-CPU Clock Skew Measured at 1.25V 100 175 ps
t6CPUCLK,
PCICLK CPU-PCI Clock Skew Measur ed at 1 .25V for 2. 5V cl ocks , and
at 1.5V for 3.3V clocks 1.5 4.0 ns
t7PCICLK,
PCICLK PCI-PCI Clock Skew Measured at 1.5V 250 ps
t10 CPUCLK Cycle-Cycle Clock Jitt er Me asured at 1.25V 550 ps
t11 PCICLK Cycle-Cycle Clock Jitt er Me asured at 1.5V 550 ps
t12 CPUCLK,
PCICLK Power-up Time CPU and PCI clock stabi lizati on from
power-up 3ms
Notes:
8. All parameters specified with loaded outputs.
9. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cy cle is measured at 1.25V.
Swi tchi n g Wavef o rms
Duty Cycle Timing
t1A t1B
OUTPUT
All Outp uts Ri se/Fall Time
OUTPUT
t2
t3
VDD
0V
t2
t4
CPU-CPU Clock Skew
t5
CPUCLK
CPUCLK
CY2281
PRELIMINARY
6
Swi tchi n g Wavef o rms (continued)
CPU-PCI Clock Skew
CPUCLK
t6
PCICLK
t7
PCICLK
PCICLK
PCI-PCI Clock Skew
CPU_STOP
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK
(Free-Running)
CPU_STOP
CPUCLK
(External)
PCI_STOP
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK
PCI_STOP
PCICLK
(External)
(Free-Running)
PWR_DOWN
CPUCLK
(Internal)
PCICLK
(Internal)
PWR_DWN
PCICLK
CPUCLK
(External)
(External)
VCO
Crystal
Shaded section on the V CO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock.
CY2281
PRELIMINARY
7
Application Information
Clock traces must be ter minated with either series or parallel termination, as they are normally done.
Application Circuit
Summary
•A parallel-resonant crysta l should be used as the r eference to the cloc k generator. The operating f requency and CLOAD of
this crystal should be as spec ified in the data sheet. Optional trim m ing capacitors may be needed if a crystal wi th a different
CLOAD is used . Footp r in ts mus t be la id out for flexib ility.
•Surface mount, l ow-ESR, ceramic capacitors should be used for fil tering. Typically, these capacitors have a value of 0.1 µF.
In some ca ses, smaller value capacitors may be required .
•The value of the series t erminati ng resistor satisf ies the followi ng equation, where Rtrace is t he loaded c haracterist ic imped-
ance of t he tr ace , Rout is the output i mped ance of t he cloc k generat or (sp eci fied in t he da ta sheet ), and Rs eries i s the series
terminating resistor.
Rseries > Rtrace – Rout
•F ootpri nts must be laid out for optional EM I-reducing capaci tors , which should be placed as close to the terminati ng resistor
as is physicall y possible. Typical values of these capacitors r ange f rom 4.7 pF to 22 pF.
•A Ferr ite Bead may be use d to isolate the Board VDD from the clock gener ator VDD island. Ensure that the Ferri te Bead
offers greater than 50Ω impedance at the cloc k frequency, under l oaded DC conditions . Pl ease ref er t o the applicat ion note
“Layout and Termination Techniques for Cypress Clock Generators” for more details.
•If a F errit e Bead is used, a 10 µF–22 µF tantal um bypass ca pacitor should be plac ed close to the F errite Bead. Thi s capacitor
prevents power supply droop during current surges.
Cd = DECOUPLING CAPACITORS
Ct = OPTIONAL EMI-REDUCING CAPACITORS
Cx = OPTIONAL LOAD MATCHING CAPACITOR
Rs = SERIES TERMINATING RESISTORS
SEL
REF
CPUCLK
PCICLK
PCICLK_F
Cd
Cd Ct
Rs
Cx
0.1µF
0.1µF
PWR_DWN#
CPU_STOP#
PCI_STOP#
SEL100
VDD 2.5V
VDD 3.3V
CY2281 28-PIN SSOP
XTALIN
XTALOUT
SEL
VDDPCI/VDDREF
VSS
AVDD/VDDUSB
VDDCPU
REF
CPUCLK
PCICLK
PCICLK_F
PWR_DWN#
CPU_STOP#
PCI_STOP#
SEL100
CY2281
PRELIMINARY
8
Document #: 38-00660-C
Test Circuit
3, 12, 14, 20, 22, 28
6, 9, 13, 21, 27
VDDPCI, AVDD,
CLOAD
OUTPUTS
0.1 µF
0.1µF
VDDCPU
Notes:
CY2281-1, -11S, -2S
25
Each supply pin must have an individual decoupling capacitor
All capacitors must be placed as close to the pins as is possible.
VDDREF
Orde ring Information
Ordering Code Package
Name Package Typ e Operating
Range
CY2281PVC-1 O28 28-Pi n SSOP Commercial
CY2281PVC-11S O28 28-Pi n SSOP Commercial
CY2281PVC-2S O28 28-Pin SSO P Commercial
CY2281
PRELIMINARY
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuit ry other than circuitry embodied in a Cypress Semic onductor product. Nor does it conv ey or imply any license under patent or other rights. C ypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package D i ag ra m
28-Lead (210-Mil) Shrunk Sm all Outline Package O28
51-85079-B
