TS68040DESC02ZA - Atmel Corporation

TS 68040

THIRD-GENERATION

32-BIT MICROPROCESSOR

DESCRIPTION

The TS 68040 is Thomson’s third generation of 68000-com-

patible, high-performance, 32-bit microprocessors. The

TS 68040 is a virtual memory microprocessor employing mul-

tiple, concurrent execution units and a highly integrated archi-

tecture to provide very high performance in a monolithic

HCMOS devic e. On a sin gle chip, the TS 68 040 integr ates an

68030-compatible integer unit, an IEEE 754-compatible floa-

ting-point unit (FPU), and fully independent instruction and

data demand-paged memory management units (MMUs), in-

cluding independent 4K-byte instruction and data caches. A

high degree of instruction execution parallelism is achieved

through the use of multiple independent execution pipelines,

multiple internal buses, and a full internal Harvard architec-

ture, including separate physical caches for both instruction

and data accesses. The TS 68040 also directly supports ca-

che coherency in multimaster applications with dedicated on-

chip bus snooping logic.

The TS 68040 is user-object-code compatible with previous

members of the TS 68000 Family and is specifically opti-

mized to reduce the execution time of compiler-generated

code. The 68040 HCMOS technology, provides an ideal ba-

lance between speed, power, and physical device size.

Figure 1 is a simplified block diagram of the TS 68040. Ins-

truction execution is pipelined in both the integer unit and FPU.

Independent data and instruction MMUs control the main ca-

ches and the address translation caches (ATCs). The ATCs

speed up logical-to-physical address translations by storing re-

cently used translations. The bus snooper circuit ensures cache

coherency in multimaster and multiprocessing applications.

MAIN FEATURES

26-42 MIPS integer performance.

3.5-5.6 MFLOPS floating-point-performance.

IEEE 754-Compatible FPU.

Independant instruction and data MMUs.

4K-byte physical instruction cache and 4K-byte physical

data cache accessed simultaneously.

32-bit, nonmultiplexed external address and data buses

with synchronous interface.

User-object-code compatibility with all earlier TS 68000

microprocessors.

Multimaster / multiprocessor support via bus snooping.

Concurrent integer unit, FPU, MMU, bus controller, and

bus snooper maximize throughput.

4-Gbyte direct addressing range.

Software support including optimizing C compiler and

unix* system V port.

IEEE P 1149-1 test mode (J tag).

f = 25 MHz, 33 MHz ; VCC = 5 V ± 5 % ; PD = 7 W.

The use of the TS 88915T clock driver is suggested.

SCREENING

MIL-STD-883.

DESC. Drawing 5962-93143.

TCS standards.

February 1998 1/38

R suffix

PGA 179

Ceramic Pin Grid Array

Cavity down

F suffix

CQFP 196

Gullwing shape lead Ceramic Quad Flat Pack

This document contains information on a new product. Specifica-

tions and information herein are subject to change without notice.

2/38

SUMMARY

A - GENERAL DESCRIPTION

1 - INTRODUCTION

2 - PIN ASSIGNMENTS

2.1 - PGA 179

2.2 - CQFP 196

3 - SIGNAL DESCRIPTION

B - DETAILED SPECIFICATIONS

1 - SCOPE

2 - APPLICABLE DOCUMENTS

3 - REQUIREMENTS

3.1 - General

3.2 - Design and construction

3.2.1 - Terminal connections

3.2.2 - Lead material and finish

3.2.3 - Package

3.3 - Electrical characteristics

3.3.1 - Absolute maximum rating

3.3.2 - Recommended condition of use

3.4 - Thermal consideration

3.4.1 - General thermal consideration

3.4.2 - Thermal characteristics

3.5 - Mechanical and environment

3.6 - Marking

4 - QUALITY CONFORMANCE

4 - INSPECTION

4.1 - DESC / MIL-STD-883

5 - ELECTRICAL CHARACTERISTICS

5.1 - General requirements

5.2 - Static characteristics

5.3 - Dynamic characteristics

5.4 - Switching test circuit and waveforms

6 - FUNCTIONAL DESCRIPTION

6.1 - Programming model

6.2 - Data types and addressing modes

6.3 - Instruction set overview

6.4 - Instruction and data caches

6.5 - Operand transfer mechanism

6.5 - Exception processing

6.7 - Memory management units

7 - PREPARATION FOR DELIVERY

7.1 - Packaging

7.2 - Certificate of compliance

8 - HANDLING

9 - PACKAGE MECHANICAL DATA

9.1 - 179 pins - PGA

9.2 - 196 pins - Tie bar CQFP

9.3 - 196 pins - Gullwing CQFP

10 - ORDERING INFORMATION

10.1 - MIL-STD-883 C

10.2 - DESC Drawing 5962-93143.

10.3 - Detailed TS 68040 part list

TS 68040

A - GENERAL DESCRIPTION

Figure 1 : Block diagram.

1 - INTRODUCTION

The TS 68040 is an enhanced, 32-bit, HCMOS microprocessor that combines the integer unit processing capabilities of the

TS 68030 microprocessor with independent 4K-byte data and instruction caches and an on-chip FPU. The TS 68040 maintains

the 32-bit registers available with the entire TS 68000 Family as well as the 32-bit address and data paths, rich instruction

set, and versatile addressing modes. Instruction execution proceeds in parallel with accesses to the internal caches, MMU

operations, and bus controller activity. Additionally, the integer unit is optimized for high-level language environments.

The TS 68040 FPU is user-object-code compatible with the TS 68882 floating-point coprocessor and conforms to the

ANSI / IEEE Standard 754 for binary floating-point arithmetic. The FPU has been optimized to execute the most commonly

used subset of the TS 68882 instruction set, and includes additional instruction formats for single and double-precision

rounding of results. Floating-point instructions in the FPU execute concurrently with integer instructions in the integer unit.

The MMUs support multiprocessing, virtual memory systems by translating logical addresses to physical addresses using

translation tables stored in memory. The MMUs store recently used address mappings in two separate ATCs-on-chip. When

an ATC contains the physical address for a bus cycle requested by the processor, a translation table search is avoided and

the physical address is supplied immediately, incurring no delay for adress translation. Each MMU has two transparent

translation registers available that define a one-to-one mapping for adress space segments ranging in size from 16 Mbytes

to 4 Gbytes each.

Each MMU provides read-only and supervisor-only protections on a page basis. Also, processes can be given isolated

address spaces by assigning each a unique table structure and updating the root pointer upon a task swap. Isolated address

spaces protect the integrity of independent processes.

The instruction and data caches operate independently from the rest of the machine, storing information for fast access by

the execution units. Each cache resides on its own internal address bus and internal data bus, allowing simultaneous access

to both. The data cache provides writethrough or copyback write modes that can be configured on a page-by-page basis.

The TS 68040 bus controller supports a high-speed, nonmultiplexed, synchronous external bus interface, which allows the

following transfer sizes : byte, word (2 bytes), long word (4 bytes), and line (16 bytes). Line accesses are performed using

burst transfers for both reads and writes to provide high data transfer rates.

3/38

TS 68040

2 - PIN ASSIGNMENTS

2.1 - PGA 179

Figure 2 : Bottom view.

Table 1

GND VCC

PLL S8

Internal logic C6, C7, C9, C11, C13, K3, K16, L3,

M16, R4, R11, R13, S10, T4, S9, R6,

R10 C5, C8, C10, C12, C14, H3, H16, J3,

J16, L16, M3, R5, R12, R8

Output drivers B2, B4, B6, B8, B10, B13, B15, B17,

D2, D17, F2, F17, H2, H17, L2, L17,

N2, N17, Q2, Q17, S2, S15, S17 B5, B9, B14, C2, C17, G2, G17, M2,

M17, R2, R17, S16

4/38

TS 68040

2.2 - CQFP 196

Figure 3 : Pin assignments.

Table 2

GND VCC

PLL 127

Internal logic 4, 9, 10, 19, 32, 45, 73, 88, 113, 119,

121, 122, 124, 125, 129, 130, 141, 159,

172 3, 18, 31, 40, 46, 60, 72, 87, 114, 126,

137, 158, 173, 186

Output drivers 7, 15, 22, 28, 35, 42, 49, 50, 51, 57,

63, 69, 76, 77, 83, 84, 91, 97, 98, 99,

105, 106, 146, 147, 148, 149, 155, 162,

163, 169, 176, 182, 183, 189, 195, 196

12, 25, 38, 54, 66, 80, 94, 102, 152,

166, 179, 192

5/38

TS 68040

3 - SIGNAL DESCRIPTION

Figure 4 and Table 3 describe the signals on the TS 68040 and indicate signal functions. The test signals, TRST, TMS, TCK,

TDI, and TDO, comply with subset P-1149.1 of the IEEE testability bus standard.

Figure 4 : Functional signal groups.

6/38

TS 68040

Table 3 - Signal index

Signal Name Mnemonic Function

Address bus A31-A0 32-bit address bus used to address any of 4 Gbytes

Data bus D31-D0 32-bit data bus used to transfer up to 32 bits of data per bus transfer

Transfer type TT1, TT0 Indicates the general transfer type : nor mal, MOVE 16, alternate logical

function code, and acknowledge

Transfer modifier TM2, TM0 Indicates supplemental information about the access

Transfer line number TLN1, TLN0 Indicates which cache line in a set is being pushed or loaded by the

current line transfer

User programmable attributes UPA1, UPA0 User-defined signals, controlled by the corresponding user attr ibute bits

from the address translation entry

Read write R/W Identifies the transfer as a read or write

Transfer size SIZ1, SIZ0 Indicates the data transfer size. These signals, together with A0 and

A1, define the active sections of the data bus

Bus lock LOCK Indicates a bus transfer is part of a read-modify-write operation, and

that the sequence of transfers should not be interrupted

Bus lock end LOCKE Indicates the cur rent transfer is the last in a locked sequence of transfer

Cache inhibit out CIOUT Indicates the processor will not cache the current bus transfer

Transfer start TS Indicates the beginning of a bus transfer

Transfer in progress TIP Asserted for the duration of a bus transfer

Transfer acknowledge TA Asserted to acknowledge a bus transfer

Transfer error acknowledge TEA Indicates an error condition exists for a bus transfer

Transfer cache inhibit TCI Indicates the current bus transfer should not be cached

Transfer burst inhibit TBI Indicates the slave cannot handle a line burst acces

Data latch enable DLE Alternate clock input used to latch input data when the processor is

operating in DLE mode

Snoop control SC1, SC0 Indicates the snooping operation required during an alternate master

access

Memory inhibit MI Inhibits memory devices from responding to an alternate master access

during snooping operations

Bus request BR Asserted by the processor to request bus mastership

Bus grant BG Asserted by an arbiter to grant bus mastership to the processor

Bus busy BB Asserted by the current bus master to indicate it has assumed

ownership of the bus

Cache disable CDIS Dynamically disables the internal caches to assist emulator support

MMU disable MDIS Disables the translation mechanism of the MMUs

Reset in RSTI Processor reset

Reset out RSTO Asserted during execution of the RESET instruction to reset external

devices

Interrupt priority level IPL2-IPL0 Provides an encoded interrupt level to the processor

Interrupt pending IPEND Indicates an interrupt is pending

Autovector AVEC Used during an interrupt acknowledge transfer to request internal

generation of the vector number

Processor status PST3-PST0 Indicates internal processor status

Bus clock BCLK Clock input used to derive all bus signal timing

7/38

TS 68040

Table 3 - Signal index (Continued)

Signal Name Mnemonic Function

Processor clock PCLK Clock input used for internal logic timing. The PCLK frequency is

exactly 2X the BCLK frequency

Test clock TCK Clock signal for the IEEE P1149.1 test access port (TAP)

Test mode select TMS Selects the principle operations of the test-support circuitry

Test data input TDI Serial data input for the TAP

Test data output TDO Serial data output for the TAP

Test reset TRST Provides an asynchronous reset of the TAP controller

Power supply VCC Power supply

Ground GND Ground connection

B - DETAILED SPECIFICATIONS

1 - SCOPE

This drawing describes the specific requirements for the microprocessor TS 68040 - 25 MHz and 33 MHz, in compliance

with MIL-STD-883 class B or TCS standard screening.

2 - APPLICABLE DOCUMENTS

MIL-STD-883

1) MIL-STD-883 : test methods and procedures for electronics.

2) MIL-I-38535 : general specifications for microcircuits.

3) DESC 5962-93143.

3 - REQUIREMENTS

3.1 - General

The microcircuits are in accordance with the applicable document and as specified herein.

3.2 - Design and construction

3.2.1 - Terminal connections

Depending on the package, the terminal connections shall be is shown in Figures 2 and 3 (§ A).

3.2.2 - Lead material and finish

Lead material and finish shall be as specified in MIL-STD-853 (see enclosed § 10).

3.2.3 - Package

The macrocircuits are packaged in hermetically sealed ceramic packages which are conform to case outlines of MIL-STD-

1835-or as follow :

– CMGA 10-179-PAK pin grid array, but see § 9.1.

– similar to CQCC1-F196C-U6 ceramic uniform lead chip carrier package with ceramic non conductiv tie-bar but use our

internal drawing see § 9.2,

– gullwing shape CQFP see § 9.3.

The precise case outlines are described at the end of the specification (§ 9) and into MIL-STD-1835.

3.3 - Electrical characteristics

3.3.1 - Absolute maximum ratings

Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maxi-

mum levels may degrade performance and affect reliability.

8/38

TS 68040

Table 4 - Absolute maximum ratings

Symbol Parameter Condition Min. Max. Unit

VCC Supply voltage range – 0.3 7.0 V

VIInput voltage range – 0.3 7.0 V

PDPower dissipation Large buffers enabled 7.7 W

Small buffers enabled 6.3 W

TCOperating temperature – 55 TJ°C

Tstg Storage temperature range – 65 + 150 °C

TJJunction temperature (see Note) + 125 °C

Tlead Lead temperature Max.10 sec soldering + 300 °C

Note : This device is not tested at TC = + 125°C. Testing is performed by setting the junction temperature Tj = + 125°C

Note : and allowing the case and ambient temperatures to rise and fall as necessary so as not to exceed the maximum

Note : junction temperature.

3.3.2 - Recommended conditions of use

Table 5

Unless otherwise stated, all voltages are referenced to the reference terminal (see § A.3).

Symbol Parameter Min. Typ. Max. Unit

VCC Supply voltage range + 4.75 + 5.25 V

VIL Logic low level input voltage range GND

– 0.3 0.8 V

VIH Logic high level input voltage range + 2.0 VCC

+ 0.3 V

VOH High level output voltage 2.4 V

VOL Low level output voltage 0.5 V

fcClock frequency – 25 MHz version 25 MHz

– 33 MHz version 33 MHz

TCCase operating temperature range (see Note) – 55 TJmax °C

TJMaximum operating junction temperature + 125 °C

Note : This device is not tested at TC = + 125°C. Testing is performed by setting the junction temperature TJ = + 125°C

Note : and allowing the case and ambient temperatures to rise and fall as necessary so as not to exceed the maximum

Note : junction temperature.

3.4 - Thermal considerations

3.4.1 - General thermal considerations

This section is given for information only of user.

As microprocessors are becoming more complex and requiring more power, the need to efficiently cool the device becomes

increasingly more important. In the past, the TS 68000 Family, has been able to provide a 0-70°C ambient temperature part

for speeds less than 40 MHz. However, the TS 68040, which has a 50 MHz arithmetic logic unit (ALU) speed, is specified

with a maximum power dissipation for a particular mode, a maximum junction temperature, and a thermal resistance from

the die junction to the case. This provides a more accurate method of evaluating the environment, taking into consideration

both the air-flow and ambient temperature available. This also allows a user the information to design a cooling method

which meets both thermal performance requirements and constraints of the board environment.

This section discusses the device charateristics for thermal management, several methods of thermal management, and an

example of one method of cooling the TS 68040.

9/38

TS 68040

Thermal device characteristics

The TS 68040 presents some inherent characteristics which should be considered when evaluating a method of cooling the

device. The following paragraphs discuss these die / package and power considerations.

Die and package

The TS 68040 is being placed in a cavity-down alumina-ceramic 179-pin PGA that has a specified thermal resistance from

junction to case of 1°C/W. This package differs from previous TS 68000 Family PGA packages which were cavity up. This

cavity-down design allows the die to be attached to the top surface of the package, which increases the ability of the part

to dissipate heat through the package surface or an attached heat sink. The maximum perimeter that the TS 68040 allows

for a heat sink on its surface without interfering with the capacitor pads is 1.48" × 1.48". The specific dimensions and design

of the particular heat sink will need to be determined by the system designer considering both thermal performance requi-

rements and size requirements.

Power considerations

The TS 68040 has a maximum power rating, which varies depending on the operating frequency and the output buffer mode

combination being used. The large buffer output mode dissipates more power than the small, and the higher frequencies of

operation dissipate more power than the lower frequencies. The following paragraphs discuss tradeoffs in using the different

output buffer modes, calculation of specific maximum power dissipation for different modes, and the relationship of thermal

resistances and temperatures.

Output buffer mode

The 68040 is capable of resetting to enable for a combination of either large buffers or small buffers on the outputs of the

miscellaneous control signals, data bus, and address bus / transfer attribute pins. The large buffers offer quicker output times,

which allow for an easier logic design. However, they do so by driving about 11 times as much current as the small buffers

(refer to TS 68040 Electrical specifications for current output). The designer should consider whether the quicker timings

present enough advantage to justify the additional consideration to the individual signal terminations, the die power con-

sumption, and the required cooling for the device. Since the TS 68040 can be powered-up in one of eight output buffer

modes upon reset, the actual maximum power consumption for TS 68040 rated at a particular maximum operating frequency

is dependent upon the power up mode. Therefore, the TS 68040 is rated at a maximum power dissipation for either the large

buffers or small buffers at a particular frequency (refer to TS 68040 Electrical specifications). This allows the possibility of

some of the thermal management to be controlled upon reset. The following equation provides a rough method to calculate

the maximum power consumption for a chosen output buffer mode :

PD = PDSB + (PDLB – PDSB) ∗ (PINSLB ⁄ PINSCLB)(Equation 4.1)

where :

PD= Max. power dissipation for output buffer mode selected

PDSB = Max. power dissipation for small buffer mode (all outputs)

PDLB = Max. power dissipation for large buffer mode (all outputs)

PINSLB = Number of pins large buffer mode

PINSCLB = Number of pins capable of the large buffer mode

Table 6 shows the simplified relationship on the maximum power dissipation for eight possible configurations of output buffer

modes.

Table 6 - Maximum power dissipation for output buffer mode configurations

Output configuration Maximum power dissipation

Data bus Address bus and

transfer attrib. Misc. control signals PD

Small buffer Small buffer Small buffer PDSB

Small buffer Small buffer Large buffer PDSB + (PDLB – PDSB) ∗ 13 %

Small buffer Large buffer Small buffer PDSB + (PDLB – PDSB) ∗ 52 %

Small buffer Large buffer Large buffer PDSB + (PDLB – PDSB) ∗ 65 %

Large buffer Small buffer Small buffer PDSB + (PDLB – PDSB) ∗ 35 %

Large buffer Small buffer Large buffer PDSB + (PDLB – PDSB) ∗ 48 %

Large buffer Large buffer Small buffer PDSB + (PDLB – PDSB) ∗ 87 %

Large buffer Large buffer Large buffer PDSB + (PDLB – PDSB) ∗ 100 %

To calculate the specific power dissipation of a specific design, the termination method of each signal must be considered.

For example, a signal output that is not connected would not dissipate any additional power if it were configured in the large

buffer rather than the small buffer mode.

10/38

TS 68040

Relationships between thermal resistances and temperatures

Since the maximum operating junction temperature has been specified to be 125°C. The maximum case temperature, TC,

in °C can be obtained from : TC = TJ – PD ∗ ΦJC (Equation 4.2)

where :

TC= Maximum case temperature

TJ= Maximum junction temperature

PD= Maximum power dissipation of the device

ΦJC = Thermal resistance between the junction of the die and the case

In general, the ambient temperature, TA, in °C is a function of the following formula :

TA = TJ – PD ∗ ΦJC – PD ∗ ΦCA (Equation 4.3)

Where the thermal resistance from case to ambient, ΦCA, is the only user-dependent parameter once a buffer output

configuration has been determined. As seen from equation (4.3), reducing the case to ambient thermal resistance increases

the maximum operating ambient temperature. Therefore, by utilizing such methods as heat sinks and ambient air cooling to

minimize the ΦCA, a higher ambient operating temperature and / or a lower junction temperature can be achieved.

However, an easier approach to thermal evaluation uses the following formulas :

TA = TJ – PD ∗ ΦJA (Equation 4.4)

or alternatively, TJ = TA + PD ∗ ΦJA (Equation 4.5)

where :

ΦJA = thermal resistance from the junction to the ambient (ΦJC + ΦCA).

This total thermal resistance of a package, ΦJA, is a combination of its two components, ΦJC and ΦCA. These components

represent the barrier to heat flow from the semiconductor junction to the package (case) surface (ΦJC) and from the case

to the outside ambient (ΦJC). Although ΦJC is device related and cannot be influenced by the user, ΦCA is user dependent.

Thus, good thermal management by the user can significantly reduce ΦCA achieving either a lower semiconductor junction

temperature or a higher ambient operating temperature.

Thermal management techniques

To attain a reasonable maximum ambient operating temperature, a user must reduce the barrier to heat flow from the

semiconductor junction to the outside ambient (ΦJA). The only way to accomplish this is to significantly reduce ΦCA by

applying such thermal management techniques as heat sinks and ambient air cooling.

The following paragraphs discuss some results of a thermal study of the TS 68040 device without using any thermal mana-

gement techniques ; using only air-flow cooling, using only a heat sink, and using heat sink combined with air-flow cooling.

Thermal characteristics in still air

A sample size of three TS 68040 packages was tested in free-air cooling with no heat sink. Measurements showed that the

average ΦJA was 22.8°C /W with a standar d deviation of 0.44°C/W. The test was per for med with 3 W of power being dissipated

from within the package. The test determined that ΦJA will decrease slightly for the increasing power dissipation range

possible. Therefore, since the variance in ΦJA within the possible power dissipation range is negligible, it can be assumed

for calculation purposes that ΦJA is valid at all power levels. Using the formulas introduced previously, Table 7 shows the

results of a maximum power dissipation of 3 and 5 W with no heat sink or air-flow (refer to Table 6 to calculate other power

dissipation values).

Table 7 - Thermal parameters with no heat sink or air-flow

Defined paramaters Measured Calculated

PDTJΦJC ΦJA ΦCA

= ΦJA – ΦJC

= TJ – PD ∗ ΦJC TA

= TJ – PD ∗ ΦJA

3 Watts 125°C 1°C/W 21.8°C/W 20.8°C/W 122°C 59.6°C

5 Watts 125°C 1°C/W 21.8°C/W 20.8°C/W 120°C 16°C

As seen by looking at the ambient temperature results, most users will want to implement some type of thermal management

to obtain a more reasonable maximum ambient temperature.

Thermal characteristics in forced air

A sample size of three TS 68040 packages was tested in forced air cooling in a wind tunnel with no heat sink. This test

was performed with 3 W of power being dissipated from within the package. As previously mentioned, since the variance in

ΦJA within the possible power range is negligible, it can be assumed for calculation purposes that ΦJA is constant at all

power levels. Using the previous formulas, Table 8 shows the results of the maximum power dissipation at 3 and 5 W with

air-flow and no heat sink (refer to Table 6 to calculate other power dissipation values).

11/38

TS 68040

Table 8 - Thermal parameters with forced air flow and no heat sink

Thermal Mgmt.

Technique Defined parameters Measured Calculated

Air-flow velocity PDTJΦJC ΦJA ΦCA TCTA

100 LFM 3 W 125°C 1°C/W 11.7°C/W 10.7°C/W 122°C 89.9°C

250 LFM 3 W 125°C 1°C/W 10°C/W 9°C/W 122°C 95°C

500 LFM 3 W 125°C 1°C/W 8.9°C/W 7.9°C/W 122°C 98.3°C

750 LFM 3 W 125°C 1°C/W 8.5°C/W 7.5°C/W 122°C 99.5°C

1 000 LFM 3 W 125°C 1°C/W 8.3°C/W 7.3°C/W 122°C 100.1°C

100 LFM 5 W 125°C 1°C/W 11.7°C/W 10.7°C/W 120°C 66.5°C

250 LFM 5 W 125°C 1°C/W 10°C/W 9°C/W 120°C 75°C

500 LFM 5 W 125°C 1°C/W 8.9°C/W 7.9°C/W 120°C 80.5°C

750 LFM 5 W 125°C 1°C/W 8.5°C/W 7.5°C/W 120°C 82.5°C

1 000 LFM 5 W 125°C 1°C/W 8.3°C/W 7.3°C/W 120°C 83.5°C

By reviewing the maximum ambient operating temperatures, it can be seen that by using the all-small-buffer configuration

of the TS 68040 with a relatively small amount of air flow (100 LFM), a 0-70°C ambient operating temperature can be

achieved. However, depending on the output buffer configuration and available forced-air cooling, additional thermal mana-

gement techniques may be required.

Thermal characteristics with a heat sink

In choosing a heat sink the designer must consider many factors : heat sink size and composition, method of attachment,

and choice of a wet or dry connection. The following paragraphs discuss the relationship of these decisions to the thermal

performance of the design noticed during experimentation.

The heat sink size is one of the most significant parameters to consider in the selection of a heat sink. Obviously a larger

heat sink will provide better cooling. However, it is less obvious that the most benefit of the larger heat sink of the pin fin

type used in the experimentation would be at still air conditions. Under forced-air conditions as low as 100 LFM, the differenc e

between the ΦCA becoms very small (0.4°C/W or less) . This difference continues to decrease as the forced air flow increases.

The particular heat sink used in our testing fit the perimeter package surface area available within the capacitor pads on

the TS 68040 (1.48" × 1.48") and showed a nice compromise between height and thermal performance needs. The heat

sink base perimeter area was 1.24" × 1.30" and its heigh was 0.49". It was a pin-fin-type (i.e. bed of nails) design composed

of Al alloy. The heat sink is shown in Figure 5 can be obtained through Thermalloy Inc. by referencing part number 2338B.

Figure 5 : Heat sink example.

12/38

TS 68040

All pin fin heat sinks tested were made from extrusion Al products. The planar face of the heat sink mating to the package

should have a good degree of planarity ; if it has any curvature, the curvature should be convex at the central region of the

heat sink surface to provide intimate physical contact to the PGA surface. All heat sinks tested met this criteria. Nonplanar,

concave curvature the central regions of the heat sink will result in poor thermal contact to the package. A specification

needs to be determined for the planarity of the surface as part of any heat sink design.

Although there are several ways to attach a heat sink to the package, it was easiest to use a demountable heat sink attach

called «E-Z attach for PGA packages» developed by Thermalloy (see Figure 6). The heat sink is clamped to the package

with the help of a steel spring to a plastic frame (or plastic shoes Besides the height of the heat sink and plastic frame, no

additional height added to the package. The interface between the ceramic package and the heat sink was evaluated for

both dry and wet (e.i., thermal grease) interfaces in still air. The thermal grease reduced the ΦCA quite significantly (about

2.5 °C/W) in still air. Therefore, it was used in all other testing done with the heat sink. According to other testing, attachment

with thermal grease provided about the same thermal performance as if a thermal epoxy were used.

Figure 6 : Heat sink with attachment.

A sample size of one TS 68040 package was tested in still air with the heat sink and attachment method previously described.

This test was performed with 3 W of power being dissipated from within the package. Since the variance in ΦJA within the

possible power range is negligible, it can be assumed for calculation purposes that ΦJA is constant at all power levels.

Table 9 shows the result assuming a maximum power dissipation of the part at 3 and 5 W (refer to Table 6 to calculate

other power dissipation values).

Table 9 - Thermal parameters with heat sink and no air-flow

Thermal Mgmt.

Technique Defined parameters Measured Calculated

Heat sink PDTJΦJC ΦJA ΦCA TCTA

2338B 3 W 125°C 1°C/W 14°C/W 13°C/W 122°C 83°C

2338B 5 W 125°C 1°C/W 14°C/W 13°C/W 120°C 55°C

Thermal characteristics with a heat sink and forced air

A sample size of three TS 68040 packages was tested in forced-air cooling in a wind tunnel with a heat sink. This test was

performed with 3 W of power being dissipated from within the package. As mentioned previously, the variance in ΦJA within

the possible power range is negligible ; it can be assumed for calculation purposes that ΦJA is valid at all power levels.

Table 10 shows the results, assuming a maximum power dissipation at 3 and 5 W with air flow and heat sink thermal

management (refer to Table 6 to calculate other power dissipation values).

13/38

TS 68040

Table 10 - Thermal parameters with heat sink and air-flow

Thermal Mgmt.

Technique Defined parameters Measured Calculated

Air-flow Heat sink PDTJΦJC ΦJA ΦCA TCTA

100 LFM 2338B 3 W 125°C 1°C/W 3.1°C/W 2.1°C/W 122°C 115.7°C

250 LFM 2338B 3 W 125°C 1°C/W 2.2°C/W 1.2°C/W 122°C 118.4°C

500 LFM 2338B 3 W 125°C 1°C/W 1.7°C/W 0.7°C/W 122°C 119.9°C

750 LFM 2338B 3 W 125°C 1°C/W 1.5°C/W 0.5°C/W 122°C 120.5°C

1 000 LFM 2338B 3 W 125°C 1°C/W 1.4°C/W 0.4°C/W 122°C 120.8°C

100 LFM 2338B 5 W 125°C 1°C/W 3.1°C/W 2.1°C/W 120°C 109.5°C

250 LFM 2338B 5 W 125°C 1°C/W 2.2°C/W 1.2°C/W 120°C 114°C

500 LFM 2338B 5 W 125°C 1°C/W 1.7°C/W 0.7°C/W 120°C 116.5°C

750 LFM 2338B 5 W 125°C 1°C/W 1.5°C/W 0.5°C/W 120°C 117.5°C

1 000 LFM 2338B 5 W 125°C 1°C/W 1.4°C/W 0.4°C/W 120°C 118°C

Thermal testing summary

Testing proved that a heat sink in combination with a relatively small amount of air-flow (100 LFM or less) will easily realize

a 0-70°C ambient operating temperature for the TS 68040 with almost any configuration of the output buffers. A heat sink

alone may be capable of providing all necessary cooling, depending on the particular heat sink height / size restraints, the

maximum ambient operating temperature required, and the output buffer configuration chosen. Also forced air cooling alone

may attain a 0-70°C ambient operating temperature. However this factor is highly dependent on the output buffer configuration

chosen and the available forced air for cooling. Figure 7 is a summary of the test results of the relationship between ΦJA

and air-flow for the TS 68040.

Figure 7 : Relationship of ΦJA air-flow for PGA.

3.4.2 - Characteristics guaranted

Table 11

Package Symbol Parameter Value Unit

PGA 179 θJ-A Thermal resistance junction-to-ambient See Figure 7 °C/W

θJ-C Thermal resistance junction-to-case 1 °C/W

CQFP 196 θJ-A Thermal resistance junction-to-ambient TBD °C/W

θJ-C Thermal resistance junction-to-case 1 °C/W

14/38

TS 68040

3.5 - Mechanical and environment

The microcircuits shall meet all mechanical environmental requirements of either MIL-STD-883 for class B devices or for

TCS standard screening.

3.6 - Marking

The document where are defined the marking are identified in the related reference documents. Each microcircuit are legible

and permanently marked with the following information as minimum :

– Thomson logo,

– Manufacturer’s part number,

– Class B identification,

– Date-code of inspection lot,

– ESD identifier if available,

– Country of manufacturing.

4 - QUALITY CONFORMANCE INSPECTION

4.1 - DESC / MIL-STD-883

Is in accordance with MIL-M-38535 and method 5005 of MIL-STD-883. Group A and B inspections are performed on each

production lot. Group C and D inspection are performed on a periodical basis.

5 - ELECTRICAL CHARACTERISTICS

5.1 - General requirements

All static and dynamic electrical characteristics specified for inspection purposes and the relevant measurement conditions

are given below :

– Table 12 : Static electrical characteristics for the electrical variants,

– Table 13 : Dynamic electrical characteristics for TS 68040 (25 MHz, 33 MHz).

For static characteristics (Table 12), test methods refer to IEC 748-2 method number, where existing.

For dynamic characteristics (Table 13), test methods refer to clause 5.2 of this specification.

Indication of «min.» or «max.» in the column «test temperature» means minimum or maximum operating temperature as

defined in sub-clause 3.3.2. here above.

5.2 - Static characteristics

Table 12 - Electrical characteristics

– 55°C ≤ TC ≤ TJmax

; 4.75 V

≤ VCC ≤ 5.25 V unless otherwise specified - Notes 1, 2, 3 and 4

Symbol Characteristic Min. Max. Unit

VIH Input high voltage 2 VCC V

VIL Input low voltage GND 0.8 V

VUUndershoot – 0.8 V

Iin Input leakage current

@ 0.5 / 2.4 V AVEC

______, BCLK, BG

___, CDIS

_____,

IPLn

_____, MDIS

_____, PCLK, RSTI

_____, SCn,

TBI

____, TCI

____, TCK, TEA

____ – 20 20 µA

ITSI Hi-Z (off-state) leakage current

@ 0.5 / 2.4 V An, BB

___, CIOUT

_______, Dn

LOCK

______,

LOCKE

_______, R ⁄ W

__, SIZn, TA

___, TDO,

TIP

____, TLNn, TMn, TS

___, TTn, UPAn

– 20 20 µA

IIL Signal low input current

IL = 0.8 V TMS, TDI, TRST

______ – 1.1 – 0.18 mA

IIH Signal high input current

IH = 2.0 V TMS, TDI, TRST

______ – 0.94 – 0.16 mA

VOH Output high voltage

Larger buffers - IOH = 35 mA

Small buffers - IOH = 5 mA 2.4 V

15/38

TS 68040

Table 12 - Electrical characteristics (Continued)

Symbol Characteristic Min. Max. Unit

VOL Output low voltage

Larger buffers - IOL = 35 mA

Small buffers - IOL = 5 mA 0.5 V

PDPower dissipation (TJ = 125°C)

Larger buffers enabled

Small buffers enabled 7.7

6.3 W

Cin Capacitance - Note 4

in = 0 V, f = 1 MHz 25 pF

Note 1 : All testing to be performed using worst-case test conditions unless otherwise specified.

Note 2 : Maximum operating junction temperature (TJ) = + 125°C. Minimum case operating temperature (TC) = – 55°C. This

Note 3 : device is not tested at TC = + 125°C. Testing is performed by setting the junction temperature TJ = + 125°C and

Note 3 : allowing the case and ambient temperatures to rise and fall as necessary so as not to exceed the maximum

Note 3 : junction temperature.

Note 3 : Capacitance is periodically sampled rather than 100 % tested.

Note 4 : Power dissipation may vary in between limits depending on the application.

5.3 - Dynamic characteristics

Table 13 - Clock AC timing specifications (see Figure 8)

– 55°C ≤ TC ≤ TJmax

; 4.75 V

≤ VCC ≤ 5.25 V unless otherwise specified - Notes 1, 2, 3 and 4

Num Characteristic 25 MHz 33 MHz Unit

Min. Max. Min. Max.

Frequency of operation 20 25 20 33 MHz

1 PCLK cycle time 20 25 15 25 ns

2 PCLK rise time - Note 4 1.7 1.7 ns

3 PCLK fall time - Note 4 1.6 1.6 ns

4 PCLK duty cycle measured at 1.5 V - Note 4 47.5 52.5 46.67 53.33 %

4a PCLK pulse width high measured at 1.5 V - Notes 3 and 4 9.5 10.5 7 8 ns

4b PCLK pulse width low measured at 1.5 V - Notes 3 and 4 9.5 10.5 7 8 ns

5 BCLK cycle time 40 50 30 60 ns

6, 7 BCLK rise and fall time 4 3 ns

8 BCLK duty cycle measured at 1.5 V - Note 4 40 60 40 60 %

8a BCLK pulse width high measured at 1.5 V - Note 4 16 24 12 18 ns

8b BCLK pulse width low measured at 1.5 V - Note 4 16 24 12 18 ns

9 PCLK, BCLK frequency stability - Note 4 1000 1000 ppm

10 PCLK to BCLK skew 9n/ans

Note 1 : All testing to be performed using worst-case test conditions unless otherwise specified.

Note 2 : Maximum operating junction temperature (TJ) = + 125°C. Minimum case operating temperature (TC) = – 55°C. This

Note 3 : device is not tested at TC = + 125°C. Testing is performed by setting the junction temperature TJ = + 125°C and

Note 3 : allowing the case and ambient temperatures to rise and fall as necessary so as not to exceed the maximum

Note 3 : junction temperature.

Note 3 : Specification value at maximum frequency of operation.

Note 4 : If not tested, shall be guaranteed to the limits specified.

16/38

TS 68040

Figure 8 : Clock input timing.

Table 14 - Output AC timing specifications (Note 1) (Figures 9 - 15)

These output specifications are for only 25 MHz they must be scaled for lower operating frequencies. Refer to TS 6804DH/AD

for further information.

– 55°C ≤ TC ≤ TJmax

; 4.75 V

≤ VCC ≤ 5.25 V unless otherwise specified - Notes 2, 3 and 4

Num Characteristic

25 MHz 33 MHz

Unit

Large buffer

Note 1 Small buffer

Note 1 Large buffer

Note 1 Small buffer

Note 1

Min. Max. Min. Max. Min. Max. Min. Max.

11 BCLK to adress CIOUT

_______, LOCK

______, LOCKE

_______, R ⁄ W

__,

SIZn, TLN, TMn, TTn, UPAn valid - Note 5 9 21 9 30 6.50 18 6.50 25 ns

12 BCLK to output invalid (output hold) 9 9 6.50 6.50 ns

13 BCLK to TS

___ valid 9 21 9 30 6.50 18 6.50 25 ns

14 BCLK to TIP

____ valid 9 21 9 30 6.50 18 6.50 25 ns

18 BCLK to data-out valid - Note 6 9 23 9 32 6.50 20 6.50 27 ns

19 BCLK to data-out invalid (output hold) - Note 6 9 9 6.50 6.50 ns

20 BCLK to output low impedance - Notes 5 and 6 9 9 6.50 6.50 ns

21 BCLK to data-out high impedance 9 20 9 20 6.50 17 6.50 17 ns

26 BCLK to multiplexed address valid - Note 5 19 31 19 40 14 26 14 33 ns

27 BCLK to multiplexed address driven - Note 5 19 19 14 14 ns

28 BCLK to multiplexed address high impedance

Notes 5 and 6 9 18 9 18 6.50 15 6.50 15 ns

29 BCLK to multiplexed data driven - Note 6 19 19 14 20 14 20 ns

30BCLK to multiplexed data valid - Note 6 1933194214281435ns

38 BCLK to address, CIOUT

_______, LOCK

______, LOCKE

_______, R

⁄

__,

SIZn, TS

___, TLNn, TMn, TTn, UPAn high impedance

Note 5 9 18 9 18 6.50 15 6.50 15 ns

39 BCLK to BB

___, TA

___, TIP

____ high impedance 19 28 19 28 14 23 14 23 ns

40 BCLK to BR

___, BB

___ valid 9 21 9 30 6.50 18 6.50 25 ns

17/38

TS 68040

Table 14 - Output AC timing specifications (Continued)

Num Characteristic

25 MHz 33 MHz

Unit

Large buffer

Note 1 Small buffer

Note 1 Large buffer

Note 1 Small buffer

Note 1

Min. Max. Min. Max. Min. Max. Min. Max.

43 BCLK to MI

___ valid 9 21 9 30 6.50 18 6.50 25 ns

48 BCLK to TA

___ valid 9 21 9 30 6.50 18 6.50 25 ns

50 BCLK to IPEND

_______, PSTn, RSTO

______ valid 9 21 9 30 6.50 18 6.50 25 ns

Note 1 : Output timing is specified for a valid signal measured at the pin. Large buffer timing is specified driving a 50 Ω

Note 1 : transmission line with a length characterized by a 2.5 ns one-way propagation delay, terminated through 50 Ω

Note 1 : to 2.5 V. Large buffer output impedance is typically 3 Ω, resulting in incident wave switching for this environ-

Note 1 : nement. Small buffer timing is specified driving an unterminated 30 Ω transmission line with a length characte-

Note 1 : rized by a 2.5 ns one-way propagation delay. Small buffer output impedance is typically 30 Ω ; the small buffer

Note 1 : specifications include approximately 5 ns for the signal to propagate the lenght of the transmission line and

Note 1 : back.

Note 2 : All testing to be performed using worst-case test conditions unless otherwise specified.

Note 3 : The following pins are active low : AVEC

______, BG

___, BS

___, BR

___, CDIS

_____, CIOUT

_______, IPEND

_______, IPLO

_____, IPL1

_____, IPL2

_____, LOCK

______, LOCKE

_______,

Note 2 : MDIS

_____, MI

___, RST0

______, RSTI

_____, TA

___, TBI

____, TCI

____, TEA

____, TIP

____, TRST

______, TS

___ and W

__ of R ⁄ W

__.

Note 4 : Maximum operating junction temperature (TJ) = + 125° C. Minimum case operating temperature (TC) = – 55°C. This

Note 3 : device is not tested at TC = + 125°C. Testing is performed by setting the junction temperature TJ = + 125°C and

Note 3 : allowing the case and ambient temperatures to rise and fall as necessary so as not to exceed the maximum

Note 3 : junction temperature.

Note 5 : Timing specifications 11, 20 and 38 for address bus output timing apply when normal bus operation is selected.

Note 5 : Specifications 26, 27 and 28 should be used when the multiplexed bus mode of operation is enabled.

Note 6 : Timing specifications 18 and 19 for data bus output timing apply when normal bus operation is selected. Spe-

Note 3 : cifications 28 and 29 should be used when the multiplexed bus mode of operation is enabled.

18/38

TS 68040

Table 15 - Input AC timing specifications (Figures 9 - 15)

– 55°C ≤ TC ≤ TJmax

; 4.75 V

≤ VCC ≤ 5.25 V unless otherwise specified - Notes 1, 2, 3 and 4

Num Characteristic 25 MHz 33 MHz Unit

Min. Max. Min. Max.

15 Data-in valid to BCLK (setup) 5 4 ns

16 BCLK to data-in invalid (hold) 4 4 ns

17 BCLK to data-in high impedance (read followed by write) 49 36.5 ns

22a TA valid to BCLK (setup) 10 10 ns

22b TEA valid to BCLK (setup) 10 10 ns

22c TCI valid to BCLK (setup) 10 10 ns

22d TBI valid to BCLK (setup) 11 10 ns

23 BCLK to TA, TEA, TCI, TBI invalid (hold) 2 2 ns

24 AVEC valid to BCLK (setup) 5 5 ns

25 BCLK to AVEC invalid (hold) 2 2 ns

31 DLE width high 8 8 ns

32 Data-in valid to DLE (setup) 2 2 ns

33 DLE to data-in invalid (hold) 8 8 ns

34 BCLK to DLE hold 3 3 ns

35 DLE high to BCLK 16 12 ns

36 Data-in valid to BCLK (DLE mode setup) 5 5 ns

37 BCLK Data-in invalid (DLE mode hold) 4 4 ns

41a BB valid to BCLK (setup) 7 7 ns

41b BG valid to BCLK (setup) 8 7 ns

41c CDIS, MDIS valid to BCLK (setup) 10 8 ns

41d IPLn valid to BCLK (setup) 4 3 ns

42 BCLK to BB, BG, CDIS, IPLn, MDIS invalid (hold) 2 2 ns

44a Address valid to BCLK (setup) 8 7 ns

44b SIZn valid BCLK (setup) 12 8 ns

44c TTn valid to BCLK (setup) 6 8.5 ns

44d R/W valid to BCLK (setup) 6 5 ns

44e SCn valid to BCLK (setup) 10 11 ns

45 BCLK to address SIZn, TTn, R/W, SCn invalid (hold) 2 2 ns

46 TS valid to BCLK (setup) 5 9 ns

47 BCLK to TS invalid (hold) 2 2 ns

49 BCLK to BB high impedance (68040 assumes bus mastership) 9 9 ns

51 RSTI valid to BCLK 5 4 ns

52 BCLK to RSTI invalid 2 2 ns

53 Mode select setup to RSTI negated - Note 4 20 20 ns

54 RSTI negated to mode selects invalid - Note 4 2 2 ns

Note 1 : All testing to be performed using worst-case test conditions unless otherwise specified.

Note 2 : The following pins are active low : AVEC

______, BG

___, BS

___, BR

___, CDIS

_____, CIOUT

_______, IPEND

_______, IPLO

_____, IPL1

_____, IPL2

_____, LOCK

______, LOCKE

_______,

Note 2 : MDIS

_____, MI

___, RST0

______, RSTI

_____, TA

___, TBI

____, TCI

____, TEA

____, TIP

____, TRST

______, TS

___ and W

__ of R ⁄ W

__.

Note 3 : Maximum operating junction temperature (TJ) = + 125° C. Minimum case operating temperature (TC) = – 55°C. This

Note 3 : device is not tested at TC = + 125°C. Testing is performed by setting the junction temperature TJ = + 125°C and

Note 3 : allowing the case and ambient temperatures to rise and fall as necessary so as not to exceed the maximum

Note 3 : junction temperature.

Note 4 : The levels on CDIS, MDIS, and the IPL2-IPL0 signals enable or disable the multiplexed bus mode, data latch

Note 4 : enable mode, and driver impedance selection respectively.

19/38

TS 68040

Figure 9 : Read / write timing.

Note : Transfer attribute signals UPAN, SIZN, TTN, TMN, TLNN, R/W, LOCK, LOCKE, CIOUT

Table 16 - JTAG timing application (Figures 16 - 19)

– 55°C ≤ TC ≤ TJmax

; 4.75 V

≤ VCC ≤ 5.25 V unless otherwise specified - Notes 1 and 2

Num Characteristic Min. Max. Unit

TCK frequency 010MHz

1 TCK cycle time 100 ns

2 TCK clock pulse width measured at 1.5 V 40 ns

3 TCK rise and fall times 010ns

TRST setup time to TCK falling edge 40 ns

5TRST assert time 100 ns

6 Boundary scan input data setup time 50 ns

7 Boundary scan input data hold time 50 ns

8 TCK to output data valid 050ns

9 TCK to output high impedance 0 50 ns

10 TMS, TDI data setup time 20 ns

11 TMS, TDI data hold time 5ns

12 TCK to TDO data valid 020ns

13 TCK to TDO high impedance 0 20 ns

Note 1 : All testing to be performed using worst-case test conditions unless otherwise specified.

Note 2 : Maximum operating junction temperature (TJ) = + 125°C. Minimum case operating temperature (TC) = – 55°C. This

Note 3 : device is not tested at TC = + 125°C. Testing is performed by setting the junction temperature TJ = + 125°C and

Note 3 : allowing the case and ambient temperatures to rise and fall as necessary so as not to exceed the maximum

Note 3 : junction temperature.

20/38

TS 68040

Table 17 - Boundry scan instruction codes

Bit 2 Bit 1 Bit 0 Instruction selected Test data register accessed

0 0 0 Extest Boundry scan

0 0 1 Highz Bypass

0 1 0 Sample / preload Boundry scan

0 1 1 DRVCTLT Boundry scan

1 0 0 Shutdown Bypass

1 0 1 Private Bypass

1 1 0 DRVCTLS Boundry scan

1 1 1 Bypass Bypass

5.4 - Switching test circuit and waveforms

Figure 10 : Address and data bus timing. Multiplexed bus mode.

Figure 11 : DLE timing burst access.

21/38

TS 68040

Figure 12 : Bus arbitation timing.

Figure 13 : Snoop hit timing.

22/38

TS 68040

Figure 14 : Snoop miss timing.

Figure 15 : Other signal timing.

23/38

TS 68040

Figure 16 : Clock input timing diagram.

Figure 17 : TRST

______ timing diagram.

Figure 18 : Boundry scan timing diagram.

Figure 19 : Test access port timing diagram.

24/38

TS 68040

6 - FUNCTIONAL DESCRIPTION

6.1 - Programming model

The TS 68040 integrates the functions of the integer unit, MMU, and FPU. As shown in Figure 20, the registers depicted in

the programming model provide access and control for the three units. The registers are par titioned into two levels of privilege :

user and supervisor. User programs, executing in the user mode, can only use the resources of the user model. System

software, executing in the supervisor mode, has unrestricted access to all processor resources.

The integer portion of the user programming model, consisting of 16, general-purpose, 32-bit registers and two control

registers, is the same as the user programming model of the TS 68030. The TS 68040 user programming model also incor-

porates the TS 68882 programming model consisting of eight, floating-point, 80-bit data registers, a floating-point control

The supervisor programming model is used exclusively by TS 68040 system programmers to implement operating system

functions, I/O control, and memory management subsystems. This supervisor / user distinction in the TS 68000 architecture

was carefully planned so that all application software can be written to execute in the nonprivileged user mode and migrate

to the TS 68040 from any TS 68000 platform without modification. Since system software is usually modified by system

designers when porting to a new design, the control features are properly placed in the supervisor programming model. For

example, the transparent translation registers of the TS 68040 can only be read or written by the supervisor software ; the

programming resources of user application programs are unaffected by the existence of the transparent translation registers

Registers D0-D7 ar e data registers containing operands for bit and bit field (1 to 32 bits), byte ( 8 bit), word (16 bit), long-word

(32 bit), and quad-word (64 bit) operations. Registers A0-A6 and the stack pointer registers (user, interrupt, and master) are

address registers that may be used as software stack pointers or base address registers. Register A7 is the user stack

pointer in user mode, and is either the interrupt or master stack pointer (A7’ or A7’’) in supervisor mode. In supervisor mode,

the active stack pointer (interrupt or master) is selected based on a bit in the status register (SR). The address registers

may be used for word and long-word operations, and all of the 16 general-purpose registers (D0-D7, A0-A7 in Figure 20)

may be used as index registers.

The eight, 80-bit, floating-point data registers (FP0-FP7) are analogous to the integer data registers (D0-D7) of all TS 68000

Family processors. Floating-point data registers always containt extended- precision numbers. All exter nal operands, regardless

of the data format, are converted to extended-precision values before being used in any floating-point calculation or stored

in a floating-point data register.

The program counter (PC) usually contains the address of the instruction being executed by the TS 68040. During instruction

execution and exception processing, the processor automatically increments the contents of the PC or places a new value

in the PC, as appropriate. The status register (SR in the supervisor programming model) contains the condition codes that

reflect the results of a previous operation and can be used for conditional instruction execution in a program. The lower byte

of the SR is accessible in user mode as the condition code register (CCR). Access to the upper byte of the SR is restricted

to the supervisor mode.

As part of exception processing, the vector number of the exception provides an index into the exception vector table. The

base address of the exception vector table is stored in the vector base register (VBR). The displacement of an exception

vector is added to the value in the VBR when the TS 68040 accesses the vector table during exception processing.

Alternate function code registers, SFC and DFC (source and destination), contain 3-bit function codes. Function codes can

be considered extensions of the 32-bit linear address. Function codes are automatically generated by the processor to select

address spaces for data and program accesses at the user and supervisor modes. The alternate function code registers are

used by certain instructions to explicitly specify the function codes for various operations. The cache control register (CACR)

controls enabling of the on-chip instruction and data caches of the TS 68040.

The supervisor root pointer (SRP) and user root pointer (URP) registers point to the root of the address translation table

tree to be used for supervisor mode and user mode accesses. The URP is used if FC2 of the logical address is zero, and

the SRP is used if FC2 is one.

The translation control register (TC) enables logical-to-physical address translation and selects either 4K or 8K page sizes.

As shown in Figure 20, there are four transparent translation registers - ITT0 and ITT1 for instruction accesses and DTT0

and DTT1 for data accesses. These registers allow portions of the logical address space to be transparently mapped and

accessed without the use of resident descriptors in an ATC. The MMU status register (MMUSR) contains status information

from the execution of a PTEST instruction. The PTEST instruction searches the translation tables for the logical address as

specified by this instruction’s effective address field and the DFC.

The 32-bit floating-point control register (FPCR) contains an exception enable byte that enables disables traps for each class

of floating-point exceptions and a mode byte that sets the user-selectable modes. The FPCR can be read or written to by

the user and is cleared by a hardware reset or a restore operation of the null state. When cleared, the FPCR provides the

IEEE 754 standard defaults. The floating-point status register (FPSR) contains a condition code byte, quotient bits, an ex-

ception status byte, and an accrued exception byte. All bits in the FPSR can be read or written by the user. Execution of

most floating-point instructions modifies this register.

For the subset of the FPU instructions that generate exception traps, the 32-bit floating-point instruction address register

(FPIAR) is loaded with the logical address of an instruction before the instruction is executed. This address can then be

used by a floating-point exception handler to locate a floating-point instruction that has caused an exception. The move

floating-point data register (FMOVE) instruction (to from the FPCR, FPSR, or FPIAR) and the move multiple data registers

(FMOVEN) instruction cannot generate floating-point exceptions ; therefore, these instructions do not modify the FPIAR. Thus,

the FMOVE and FMOVEM instructions can be used to read the FPIAR in the trap handler without changing the previous

value.

25/38

TS 68040

Figure 20 : Programming model.

6.2 - Data types and addressing modes

The TS 68040 supports the basic data types shown in Table 18. Some data types apply only to the integer unit, some only

to the FPU, and some to both the integer unit and the FPU. In addition, the instruction set supports operations on other

data types such as memory addresses.

Table 18 - Data types

Operand data type Size Execution unit

(IU*, FPU) Notes

Bit 1 bit IU

Bit field 1-32 bits IU Field of consecutive bits

BCD 32 bits IU Packaged : 2 digits byte

Unpacked : 1 digit byte

Byte integer 8 bits IU, FPU

Word integer 16 bits IU, FPU

Long-word integer 32 bits IU, FPU

Quad-word integer 64 bits IU Any two data registers

16 byte 128 bits IU Memory-only, aligned 16-byte boundary

Single-precision real 32 bits FPU 1-bit sign, 8-bit exponent, 23-bit mantissa

Double-precision real 64 bits FPU 1-bit sign, 11-bit exponent, 52-bit mantissa

Extended-precision real 80 bits FPU 1-bit sign, 15-bit exponent, 64-bit mantissa

* IU = Integer unit.

The three integer data formats that are common to both the integer unit and the FPU (byte, word, and long word) are the

standard twos-complement data formats defined in the TS 68000 Family architecture. Whenever an integer is used in a

floating-point operation, the integer is automatically converted by the FPU to an extended-precision floating-point number

before being used. The ability to effectively use integers in floating-point operations saves user memory because an integer

representation of a number usually requires fewer bits than the equivalent floating-point representation.

26/38

TS 68040

Single- and double-precision floating-point data formats are implemented in the FPU as defined by the IEEE standard. These

data formats are the main floating-point formats and should be used for most calculations involving real numbers.

The extended-precision data format is also in conformance with the IEEE standard, but the standard does not specify this

format to the bit level as it does for single- and double-precision. The memory format for the FPU consists of 96 bits (three

long words). Only 80 bits are actually used ; the other 16 bits are reserved for future use and for long-word alignment of

the floating-point data structures in memory. The extended-precision format has a 15-bit exponent, a 64-bit mantissa, and a

1-bit mantissa sign. Extended-precision numbers are intended for use as temporary variables, intermediate values, or where

extra precision is needed.

The TS 68040 addressing modes are shown in Table 19. The register indirect addressing modes support post-increment,

predecrement, offset, and indexing, which are particularly useful for handling data structures common to sophisticated ap-

plications and high-level languages. The program counter indirect mode also has indexing and offset capabilities ; this ad-

dressing mode is typically required to support position-independent software. In addition to these addressing modes, the

TS 68040 provides index sizing and scaling features that enhance software performance. Data formats are supported ortho-

gonally by all arithmetic operations and by all appropriate addressing modes.

Table 19 - Addressing modes

Addressing modes Syntax

Date register direct

Address register direct Dn

Address register indirect

Address register indirect with postincrement

Address register indirect with predecrement

Address register indirect with displacement

(An)

(d16, An)

Address register indirect with index (8-bit displacement)

Address register indirect with index (base displacement) (d8, An, Xn)

(bd, An, Xn)

Memory indirect

Memory indirect postincrement

Memory indirect preindexed ([bd, An], Xn, od)

([bd, An, Xn], od)

Program counter indirect with displacement (d16, PC)

Program counter indirect with index

PC indirect with index (8-bit displacement)

PC indirect with index (base displacement (d8, PC, Xn)

(bd, PC, Xn)

Program counter memory indirect

PC memory indirect postindexed

PC memory indirect preindexed ([bd, PC], Xn, od)

([bd, PC, Xn], od)

Absolute

Absolute short

Absolute long xxx.W

xxx.L

Immediate # (data)

Notes :

DN = Data register, D0-D7

AN = Address register, A0-A7

d8, d16 = A twos-complement or sign-extended displacement ; added as part of the effective address calculation ;

size is 8 (d8) or 16 (d16) bits ; when omitted, assemblers use a value of zero.

Xn = Address or data register used as an index register ; form is Xn, SIZE*SCALE, where SIZE is W or L

(indicates index register size) and SCALE is 1, 2, 4 or 8 (index register os multiplied by SCALE) ; use of

SIZE and or SCALE is optional.

bd = A twos-complement base displacement ; when present, size can be 16 or 32 bits.

od =Outer displacement added as part of effective address calculation after any memory indirection ; use is

optional with a size of 16 or 32 bits.

PC = Program counter.

(data) = Immediate value of 8, 16 or 32 bits.

( ) = Effective address.

[ ] = Used as indirect address to long-word address.

27/38

TS 68040

6.3 - Instruction set overview

The instruction provided by the TS 68040 are listed in Table 20. The instruction set has been tailored to support high-level

languages and is optimized for those instructions most commonly executed (however, all instr uctions listed are fully supported).

Many instructions operate on bytes, words, and long words, and most instructions can use any of the addressing modes of

Table 19.

Table 20 - Instruction set summary

28/38

Mnemonic Description

*ABCD

*ADD

*ADDA

*ADDI

*ADDQ

*ADDX

*AND

*ANDI

*ASL, ASR

Add decimal with extend

Add

Add address

Add immediate

Add quick

Add with extend

Logical AND

Logical AND immediate

Arithmetic shift left and right

*Bcc

*BCHG

*BCLR

*BFCHG

*BFCLR

*BFEXTS

*BFEXTU

*BFFFO

*BFINS

*BFSET

*BFTST

*BKPT

*BRA

*BSET

*BSR

*BTST

Branch conditionally

Test bit and change

Test bit and clear

Test bit field and change

Test bit field and clear

Signed bit field extract

Unsigned bit field extract

Bit field find first one

Bit field insert

Test bit field and set

Test bit field

Breakpoint

Branch

Test bit and set

Branch to subroutine

Te st b it

*CAS

*CAS2

*CHK

Compare and swap operands

Compare and swap dual operands

Check register against bounds

*CHK2 Check register against upper and

lower bounds

*CINV

*CLR

*CMP

*CMPA

*CMPI

*CMPM

Invalidate cache entries

Clear

Compare

Compare address

Compare immediate

Compare memory to memory

*CMP2 Compare register against upper and

lower bounds

*CPUSH Push then invalidate cache entries

*DBcc

*DIVS, DIVSL

*DIVU, DIVUL

Test condition, decrement and branch

Signed divide

Unsigned divide

*EOR

*EORI

*EXG

*EXT, EXTB

Logical exclusive OR

Logical exclusive OR immediate

Exchange registers

Sign extend

*ILLEGAL Take illegal instruction trap

*JMP

*JSR Jump

Jump to subroutine

*LEA

*LINK

*LSL, LSR

Load effective address

Link and allocate

Logical Shift left and right

Mnemonic Description

*MOVE

*MOVE16

*MOVEA

*MOVE CCR

*MOVE SR

*MOVE USP

*MOVEC

*MOVEM

*MOVEP

*MOVEQ

*MOVES

*MULS

*MULU

Move

16-byte block move

Move address

Move condition code register

Move status register

Move user stack pointer

Move control register

Move multiple registers

Move peripheral

Move quick

Move alternate address space

Signed multiply

Unsigned multiply

*NBCD

*NEG

*NEGX

*NOP

*NOT

Negate decimal with extend

Negate

Negate with extend

No operation

Logical complement

*OR

*ORI Logical inclusive OR

Logical inclusive OR immediate

*PACK

*PEA

*PFLUSH

*PTEST

Pack BCD

Push effective address

Flush entry(ies) in the ATCs

Test a logical address

*RESET

*ROL, ROR

*ROXL, ROXR

*RTD

*RTE

*RTR

*RTS

Reset external devices

Rotate left and right

Rotate with extend left and right

Return and deallocate

Return from exception

Return and restore codes

Return from subroutine

*SBCD

*Scc

*STOP

*SUB

*SUBA

*SUBI

*SUBQ

*SUBX

*SWAP

Substract decimal with extend

Set conditionally

Stop

Subtract

Subtract address

Subtract immediate

Subtract quick

Subtract with extend

Swap register words

*TAS

*TRAP

*TRAPcc

*TRAPV

*TST

Test operand and set

Trap

Trap conditionally

Trap on overflow

Trap operand

UNLK

UNPK Unlink

Unpack BCD

* TS 68040 additions or alterations to the TS 68030

* and TS 68881 / TS 68882 instruction sets.

TS 68040

Table 21 - Floating-point instructions

The TS 68040 floating-point instructions, a commonly used subset of the TS 68882 instruction set, are implemented in

hardware. The remaining unimplemented instructions are less frequently used and are efficiently emulated in software, main-

taining compatibility with the TS 68881 / TS 68882 floating-point coprocessors.

The TS 68040 instruction set includes MOVE16, a new user instruction that allows high-speed transfers of 16-byte blocks

between external devices such as memory to memory or coprocessor to memory.

6.4 - Instruction and data caches

Studies have shown that typical programs spend much of their execution time in a few main routines or tight loops. Earlier

members of the TS 68000 Family took advantage of this locality of reference phenomenon to varying degrees. The TS 68040

takes further advantage of cache technology with its two, independent, on-chip, physical address space caches, one for

instructions and one for data. The caches reduce the processor’s external bus activity and increase CPU throughput by

lowering the effective memory access time. For a typical system design, the large caches of the TS 68040 yield a very high

hit rate, providing a substantial increase in system performance. Additionally, the caches are automatically burstfilled from

the external bus whenever a cache miss occurs.

The autonomous nature of the caches allows instruction-stream fetches, data-stream fetches, and a third external access to

occur simultaneously with instruction execution. For example, if the TS 68040 requires both an instruction-stream access and

an external per ipheral access and if the instruction is resident in the on-chip cache, the peripheral access proceeds unimpeded

rather than being queued behind the instruction fetch. If a data operand is also required and if it is resident in the data

cache, it can also be accessed without hindering either the instruction access from its cache or the per ipheral access ex ternal

to the chip. The parallelism inherent in the TS 68040 also allows multiple instructions that do not require any external accesses

to execute concurrently while the processor is performing an external access for a previous instruction.

6.4.1 - Cache organization

The instruction and data caches are four-way set-associative with 64 sets of four, 16-byte lines for a total cache storage of

4K bytes each. As shown in Figure 21, each 16-byte line contains an address tag and state information. State information

for each entry consists of a valid flag for the entire line in both instruction and data caches and write status for each long

word in the data cache. The write status in the data cache signifies whether or not the long-word data is dirty (meaning that

the data in the cache has been modified but has not been written back to external memory) for data in copyback pages.

29/38

Mnemonic Description

*FABS

*FADD

*FBcc

*FCMP

*FDBcc

*FDIV

*FMOVE

*FMOVEM

*FMUL

Floating-point absolute value

Floating-point add

Branch on floating-point condition

Floating-point compare

Floating-point decrement and branch

Floating-point divide

Move floating-point register

Move multiple floating-point registers

Floating-point multiply

Mnemonic Description

*FNEG

*FRESTORE

*FSAVE

*FScc

**FSQRT

*FSUB

*FTRAPcc

*FTST

Floating-point negate

Restore floating-point internal state

Save floating-point internal state

Set according to floating-point condition

Floating-point Square Root

Floating-point substract

Trap on floating-point condition

Floating-point test

* TS 68040 additions or alterations to the TS 68030

* and TS 68881 / TS 68882 instruction sets.

TS 68040

Figure 21 : Cache organization overview.

The caches are accessed by physical addresses from the on-chip MMUs. The translation of the upper bits of the logical

address occurs concurrently with the accesses into the set array in the cache by the lower address bits. The output of the

ATC is compared with the tag field in the cache to determine if one of the lines in the selected set matches the translated

physical address. If the tag matches and the entry is valid, then the cache has a hit.

If the cache hits and the access is a read, the appropriate long word from the cache line is multiplexed onto the appropriate

internal bus. If the cache hits and the access is a write, the data, regardless of size, is written to the appropriate portion of

the corresponding longword entry in the cache.

When a data cache miss occurs and a previously valid cache line is needed to cache the new line, any dirty data in the

old line will be internally buffered and copied back to memory after the new cache line has been loaded.

Pushing of dirty data can be forced by the CPUSH instruction.

Cachability of data in each memory page is controlled by two bits in the page descriptor for each page. Cachable pages

may be either writethrough or copyback, with no write-allocate for misses to writethrough pages. Non-cachable pages may

also be specified as noncachable I O, forcing accesses to these pages to occur in order of instruction execution.

6.4.2 - Cache coherency

The TS 68040 has the ability to snoop the exter nal bus during accesses by other bus masters to maintain coherency between

the TS 68040’s caches and external memory systems. External write cycles are snooped by both the instruction cache and

data cache ; whereas, external read cycles are snooped only by the data cache. In addition, external cycles can be flagged

on the bus as snoopable or nonsnoopable. When an external cycle is marked as snoopable, the bus snooper checks the

caches for a coherency conflict based on the state of the corresponding cache line and the type of external cycle.

Although the internal execution units and the bus snooper circuit all have access to the on-chip caches, the snooper has

priority over the execution units to allow the snooper to resolve coherency discrepancies immediately.

30/38

TS 68040

6.4.3 - Cache instructions

The TS 68040 supports the following instructions for cache maintenance. Both instructions may selectively operate on the

data or instruction cache.

CINV : Invalidates a single line, all lines in a physical page, or the entire cache.

CPUSH : Pushes selected dirty data cache lines to memory, then invalidates all selected lines.

6.5 - Operand transfer mechanisms

The TS 68040 external synchronous bus supports multiple masters and overlaps arbitration with data transfers. The bus is

optimized to perform high-speed transfers to and from an external cache or memory. The data and address buses are each

32 bits wide.

6.5.1 - Transfer types

The TS 68040 provides two signals (TT1-TT0) that define four types of bus transfers : normal access, MOVE16 access,

alternate access, and interrupt acknowledge access. Nor mal accesses identify normal memor y references : MOVE16 accesses

are memory accesses by a MOVE16 instruction ; and alternate accesses identify accesses to the undefined address spaces

(function code values of 0, 3, 4, 7). The interrupt acknowledge access is used to fetch an interrupt vector during interrupt

exception processing.

6.5.2 - Burst transfer operation

During burst read write to cache transfers, the values on the address and transfer type signals do not change ; they are the

address of the first requested item of the cache line. When the TS 68040 request a burst read transfer of a cache line, the

address bus indicates the address of the long word in the line needed first, but the memory system is expected to provide

data in the following order (modulo 4) : 0, 1, 2, 3 (long-word offsets). The first address needed may not be from offset 0 ;

nevertheless, all four long words must be transferred. Burst writes occur in a similar manner.

6.5.3 - Bus snooping

Bus snooping ensures that data in main memory is consistent with data in the on-chip caches. If an alternate bus master

is performing a read transfer on the bus and snooping is enabled, and if the snoop logic determines that the on-chip data

cache has dirty data (data valid but not consistent with memory) for this transfer, ther memory is prevented from responding

to the read request, and the TS 68040 supplies the data directly to the master. If the alternate master is performing a write

transfer on the bus and snooping is enabled, and if the snooper determines that one of the on-chip caches has a valid line

for this request, then the snooper may either invalidate or update the line as selected by the snoop control signals.

6.6 - Exception processing

The TS 68040 provides the same extensions to the exception stacking process as the TS 68030. If the M bit in the status

register is set, the master stack pointer is used for all task-related exceptions. When a nontask-related exception occurs (i.e.,

an interrupt), the M bit is cleared, and the interrupt stack pointer is used. This feature allows a task’s stack area to be carried

within a single processor control block, and new tasks may be initiated by simply reloading the master stack pointer and

setting the M bit.

The exter nally generated exceptions are interr upts, bus errors, and reset conditions. The interrupts are requests from exter nal

devices for processor action ; whereas, the bus error and reset signals are used for access control and processor initializatio n.

The internally generated exceptions come from instructions, address errors, tracing, or breakpoints. The TRAP, TRAPcc,

TRAPVcc, FTRAPcc, CHK, CHK2, and DIV instructions can all generate exceptions as part of their instruction execution.

Tracing behaves like a ver y high-priority, inter nally generated interrupt whenever it is processed. The other inter nally generated

exceptions are caused by unimplemented floating-point instructions, illegal instructions, instruction fetches from odd addres-

ses, and privilege violations. Finally, the MMU can generate exceptions, for access violations and for when invalid descriptors

are encountered during table searches.

Exception processing for the TS 68040 occurs on the following sequence :

1 - an internal copy is made of the status register,

2 - the vector number of the exception is determined,

3 - current processor status is saved,

4 - the exception vector offset is determined by multiplying the vector number by four.

This offset is then added to the contents of the VBR to deter mine the memor y address of the exception vector. The instruction

at the address given in the exception vector is fetched, and normal instruction decoding and execition is started.

6.7 - Memory management units

The full addressing range of the TS 68040 is 4 Gbytes (4,294,967,296 bytes). However, most TS 68040 systems implement

a much smaller physical memory. Nonethless, by using virtual memory techniques, the system can be made to appear to

have a full 4 Gbytes of physical memory available to each user program. The independent instruction and data MMUs fully

support demandpaged virtual-memory operating systems with either 4K or 8K page sizes. In addition to its main function of

memory management, each MMU protects supervisor areas from accesses by user programs and also provides write pro-

tection on a page-by-page basis. For maximum efficiency, each MMU operates in parallel with other processor activities.

31/38

TS 68040

6.7.1 - Translation mechanism

Because logical-to-physical address translation is one of the most frequently executed operations of the TS 68040 MMUs,

this task has been optimized. Each MMU initiates address translation by searching for a descriptor containing the address

translation information in the ATC. If the descriptor does not reside in the ATC, then the MMU performs external bus cycles

via the bus controller to search the translation tables in physical memory. After being located, the page descriptor is loaded

into the ATC, and the address is correctly translated for the access, provided no exception conditions are encountered.

6.7.2 - Address translation cache

An integral part of the translation function previously described is the dual cache memory that stores recently used logical-

to-physical address translation information (page descriptors) for instruction and date accesses. These caches are 64-entry,

four-way, set associative. Each ATC compare the logical address of the incoming access against its entries. If one of the

entries matches, there is a hit, and the ATC sends the physical address to the bus controller, which then starts the external

bus cycle (provided there was no hit in the corresponding cache for the access).

6.7.3 - Translation tables

The translation tables of the TS 68040 have a threelevel tree structure and reside in main memory. Since only a portion of

the complete tree needs to exist at any one time, the tree structure minimizes the amount of memory necessary to set up

the tables for most programs. As shown in Figure 20, either the user root pointer or the supervisor root pointer points to

the first level table, depending on the values of the function code for an access. Table entries at the second level of the tree

(pointer tables) contain pointers to the third level (page tables). Entries in the page tables contain either page descriptors

or indirect pointers to page descriptors. The mechanism for performing table search operations uses portions of the logical

address (as indices) at each level of the search. All addresses in the translation table entries are physical addresses.

Figure 22 : Translation table structure.

There are two variations of table searches for both 4K and 8K page sizes : normal searches and indirect searches. An

indirect search differs in that the entry in the third level page table contains a pointer to a page descriptor rather than the

page descriptor itself.

Entries in the translation tables contain control and status information on addition to the physical address information. Contr ol

bits specify write protection, limit access to supervisor only, and determine cachability of data in each memory page. Each

page descriptor also has two user-programmable bits that appear on the UPA0 and UPA1 signals during an external access

for use as address modifier bits.

A global bit can be set in each page descriptor to pr event flushing of the ATC entr y for that page by some PFLUSH instr uction

variants, allowing system ATC entries to remain resident during task swaps. If these special PFLUSH instructions are not

used, this bit can be user defined. The MMUs automatically maintain access history information for the pages by updating

the used (U) and modified (M) status bits.

6.7.4 - MMU instructions

The MMU instructions supported by the TS 68040 are as follows :

PFLUSH : Allows flushing of either selected ATC entries by function code and logical address or the entire ATCs.

PTEST : Takes an address and function code and searches the translation tables for the corresponding entry, which is then

loaded into the ATC. The results of the search are available in the MMU status register and are often useful in determining

the cause of a fault.

All of the TS 68040 MMU instructions are privileged and can only be executed from the supervisor mode.

32/38

TS 68040

6.7.5 - Transparent translation

Four transparent translation registers, two each for instruction and data accesses, have been provided on the TS 68040

MMU to allow portions of the logical address space to be transparently mapped and accessed without the need for corre-

ponding entries resident in the ATC. Each register can be used to define a range of logical addresses from 16 Mbytes to

4 Gbytes with a base address and a mask. All addresses within these ranges are not mapped, and are optionally protected

against user or supervisor accesses and write accesses. Logical addresses in these areas become the physical addresses

for memory access. The transparent translation feature allows rapid movement of large blocks of data in memory or I/O

space without disturbing the context of the on-chip ATCs or incurring delays associated with translation table searches.

7 - PREPARATION FOR DELIVERY

7.1 - Packaging

Microcircuits are prepared for delivery in accordance with MIL-M-38510 or TCS standard.

7.2 - Certificate of compliance

TCS offers a certificate of compliances with each shipment of parts, affirming the products are in compliance either with

MIL-STD-883 or TCS standard and guarantying the parameters not tested at temperature extremes for the entire temperature

range.

8 - HANDLING

MOS devices must be handled with cer tain precautions to avoid damage due to accumulation of static charge. Input protection

devices have been designed in the chip to minimize the effect of this static buildup. However, the following handling practices

are recommended :

a) Devices should be handled on benches with conductive and grounded surfaces.

b) Ground test equipment, tools and operator.

c) Do not handle devices by the leads.

d) Store devices in conductive foam or carriers.

e) Avoid use of plastic, rubber, or silk in MOS areas.

f) Maintain relative humidity above 50 percent if practical.

9 - PACKAGE MECHANICAL DATA

9.1 - 179 pins - PGA

Dim Millimeters Inches

Min Max Min Max

A 46.863 47.625 1.845 1.875

B 46.863 47.625 1.845 1.875

C 2.3876 1.875 0.094 0.116

D 4.318 4.826 0.170 0.190

E 1.143 1.4 0.045 0.055

F 1.143 1.4 0.045 0.055

G 2.54 BSC 0.100 BSC

H* 0.432 0.483 0.017 0.019

* For untinned leads (gold).

33/38

TS 68040

9.2 - 196 pins - Tie bar CQFP cavity up (on request)

Dim Millimeters Inches

A 3.30 max 0.130 max

B0.23 – 0.038

+ 0.05 .009 – .015

+ .002

C 0.635 typ. .025 typ.

D1 33.91 ± 0.25 1.335 ± .01

J0.89 ± 0.13 .035 ± .005

L63.5 ± 0.51 2.5 ± .02

34/38

TS 68040

9.3 - 196 pins - Gullwing CQFP cavity up

Symbol Millimeters Inches

A 4.19 max 0.165 max

A1 0.673 ± 0.2 .0265 ± .008

b0.23 – 0.038

+ 0.05 .009 – .0015

+ .002

c0.127 – 0.025

+ 0.05 .005 – .001

+ .002

D/E 33.91 ± 0.25 1.335 ± .01

e 0.635 BSC .025 BSC

e1 30.48 ± 0.13 1.2 ± .005

HD/HE 38.8 ± 0.18 1.528 ± .007

L0.813 ± 0.2 .032 ± .008

N 196 196

R0.55 ± 0.25 .022 ± .01

R1 0.23 min .009 min

35/38

* Reduced pin count shown for clarity, 49 pins per side

TS 68040

10 - ORDERING INFORMATION

10.1 - MIL-STD-883 C and internal standard

Note 1 : THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES.

Note 2 : On request.

Note 3 : Standard process.

Note 4 : On request for small quantity.

10.2 - DESC Drawing 5962-93143

Note 1 : THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES.

36/38

76  0 5  %& 

2SHUDWLQJ IUHTXHQF\ 





6FUHHQLQJ OHYHO 

%&

'7

87

/HDG ILQLVK 

  +RW VROGHU GLS 1RWH 

  *ROG 1RWH 

0+]

0+]

 0,/67' FODVV %

 ,QWHUQDO VWDQGDUG ZLWK EXUQ LQ

8SVFUHHQLQJ

 8SVFUHHQLQJ  EXUQLQ

 ,QWHUQDO VWDQGDUG

'HYLFH

7&6 SUHIL[ 1RWH 

7HPSHUDWXUH UDQJH 

7F  7M &

7F  7M &



3DFNDJH 

)

6WDQGDUG OHDG ILQLVK

 &4)3  *XOOZLQJ OHDGV

 3*$

 &4)3 )ODW WLHEDU 1RWH 

*ROG

TS 68040

10.3 - Detailed TS 68040 part list

10.3.1 - Hi-REL product

Commercial TCS

part number

(see Note) Norms Package Temperature range

(°C) Frequency

(MHz) Drawing number

TS68040MRB/C25 MIL-STD-883 PGA 179 TC = – 55 / + TJ = + 125 25 TCS data sheet

TS68040MRB/C33 MIL-STD-883 PGA 179 TC = – 55 / + TJ = + 125 33 TCS data sheet

TS68040MFB/C25 MIL-STD-883 CQFP 196 TC = – 55 / + TJ = + 125 25 TCS data sheet

TS68040MFB/C33 MIL-STD-883 CQFP 196 TC = – 55 / + TJ = + 125 33 TCS data sheet

TS68040DESC01XA DESC PGA 179 tin TC = – 55 / + TJ = + 125 25 5962-9314301MXA

TS68040DESC02XA DESC PGA 179 tin TC = – 55 / + TJ = + 125 33 5962-9314302MXA

TS68040DESC01XC DESC PGA 179 gold TC = – 55 / + TJ = + 125 25 5962-9314301MXC

TS68040DESC02XC DESC PGA 179 gold TC = – 55 / + TJ = + 125 33 5962-9314302MXC

TS68040DESC01YC DESC CQFP 196

tie bar gold TC = – 55 / + TJ = + 125 25 5962-9314301MYC

TS68040DESC02YC DESC CQFP 196

tie bar gold TC = – 55 / + TJ = + 125 33 5962-9314302MYC

TS68040DESC01ZA DESC CQFP 196

gullwing tin TC = – 55 / + TJ = + 125 25 5962-9314301MZA

TS68040DESC01ZC DESC CQFP 196

gullwing gold TC = – 55 / + TJ = + 125 25 5962-9314301MZC

TS68040DESC02ZA DESC CQFP 196

gullwing tin TC = – 55 / + TJ = + 125 33 5962-9314302MZA

TS68040DESC02ZC DESC CQFP 196

gullwing gold TC = – 55 / + TJ = + 125 33 5962-9314302MZC

TS68040MFB/C25 MIL-STD-883 CQFP 196 TC = – 55 / + TJ = + 125 25 TCS data sheet

TS68040MFB/C33 MIL-STD-883 CQFP 196 TC = – 55 / + TJ = + 125 33 TCS data sheet

TS68040MRD/T25 BURN IN PGA 179 TC = – 55 / + TJ = + 125 25 TCS data sheet

TS68040MRD/T33 BURN IN PGA 179 TC = – 55 / + TJ = + 125 33 TCS data sheet

TS68040MFD/T25 BURN IN CQFP 196 TC = – 55 / + TJ = + 125 25 TCS data sheet

TS68040MFD/T33 BURN IN CQFP 196 TC = – 55 / + TJ = + 125 33 TCS data sheet

Note : THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES.

10.3.2 - Standard product

Commercial TCS

part number

(see Note) Norms Package Temperature range

(°C) Frequency

(MHz) Drawing number

TS68040VR25 TCS standard PGA 179 TC = – 40 / + TJ = + 110 25 TCS data sheet

TS68040VR33 TCS standard PGA 179 TC = – 40 / + TJ = + 110 33 TCS data sheet

TS68040MR25 TCS standard PGA 179 TC = – 55 / + TJ = + 125 25 TCS data sheet

TS68040MR33 TCS standard PGA 179 TC = – 55 / + TJ = + 125 33 TCS data sheet

TS68040VF25 TCS standard CQFP 196 TC = – 40 / + TJ = + 110 25 TCS data sheet

TS68040VF33 TCS standard CQFP 196 TC = – 40 / + TJ = + 110 33 TCS data sheet

TS68040MF25 TCS standard CQFP 196 TC = – 55 / + TJ = + 125 25 TCS data sheet

TS68040MF33 TCS standard CQFP 196 TC = – 55 / + TJ = + 125 33 TCS data sheet

Note : THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES.

Note : FT : available on request.

37/38

TS 68040

Information furnished is believed to be accurate and reliable. However THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES

assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of

third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent

rights of THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES. Specifications mentioned in this publication are subject to

change without notice. This publication supersedes and replaces all information previously supplied. THOMSON-CSF

SEMICONDUCTEURS SPECIFIQUES products are not authorized for use as critical components in life support devices or

systems without express written approval from THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES.  1998 THOMSON-CSF

This product is manufactured by THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES - 38521 SAINT-EGREVE / FRANCE.

For fur ther information please contact : THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES - Route Dépar tementale 128 -

B.P. 46 - 91401 ORSAY Cedex / FRANCE - Tél. : (33)(0) 1.69.33.00.00 / Téléfax : (33)(0) 1.69.33.03.21.

E-mail : lafrique@tcs.thomson.fr

38/38

ORDER CODE : DSTS68040T/0298 Créé / réalisé par Graphic Express - Tél. : 01.46.55.27.24 - 10233 - 02/98

TS 68040