_.. __.. General Description The MAX173 is a complete, 10-bit linear analog-to- digital converter (ADC) that combines high speed, low power consumption, and an on-chip voltage reference. The conversion time is 54s. The buried zener reference provides low drift and low noise performance. External component requirements are limited to only decoupling capacitors for the power supply and refer- ence voltages. On-chip clock circuitry is also included which can either be driven from an external source, or in stand-alone applications, from a crystal. The MAX 173 uses a standard microprocessor interlace architecture. Three-state data_outputs are controlted by Read (RD) and Chip Select (CS) inputs. Data access and bus release times of 90ns and 75ns respectively ensure compatibility with most popular microproces- sors without resorting to wait states. ____ Applications Digital Signal Processing (DSP) High Accuracy Process Contral High Speed Data Acquisition Electro-Mechanical Systems Functional Diagram AGN Yate AW [se [1 SUI A AL/VI Complete 5us CMOS 10-Bit A/D Converter Features # 12-Bit Resolution and 10-Bit Linearity @ 5s Conversion Time @ On-Chip +40ppm/C Voltage Reference # 90ns Access Time @ 215mW (Max) Power Consumption @ 24-Lead Narrow DIP and Wide $0 Packages _ Ordering Information PART TEMP. RANGE PACKAGE* MAX173CNG 0C ta +70C Plastic DIP MAX173CWG _ __ C to +70 Cc Wide 50 MAX173C/D oc to +70C Dice** MAX173ENG -40 G to +85G Plastic DIP MAX173EWG -40G to +86C Wide SO MAX173MRG -55C to +125C CERDIP * All davices 24 lead packages ** Consult factory for dice specifications Pin Configurations Top View 2 anol * fw REFERENCE 2 Veer Ee 23] Vgs SUCCESSIVE = ves aRy AAAKIAA APPROXIMATION * AGND Ey Pz] Busy MAXKI73 C REGISTER Loy OW EA rr] ts . 00 fo] AD a 0p ey 191 en POMTROL L 12 s 08 MAX173 Pe] CLK OUT 2 Te ve 7] CLOCK IW MULIIPLEXER 7 etH 06 Gy fe] 00/8 THREE- sf | t 1" 05 =] 1g STATE | H coe out autruT THREE STATE cock Fy, 4 Pa] 02/10 DRIVERS a ERS gscuitamon ry CLR IN DGND [2] rs) 03/11 T T JT JT |: -} le qe 2 [ia] on oa Oo? 04 Oa Oor8 nono Axi uel #VIAXAI VI Maxim Integrated Products | Maxim is a registered trademark of Maxim Integrated Products ELLXVI MAX173 Complete 5us CMOS 10-Bit A/D Converter ABSOLUTE MAXIMUM RATINGS Vop ta DGND Vss to DGND AGND tc DGND AIN to AGND Digital Input Voltage to OGND (Pins 17, 19-21) Digita} Output Voltage to DGND (Pins 4-11, 13-16, 18, 22) -O0.3V, Vpp + 0.3V -O.3V, Voo + O.4V -0,3V to +7V Operating Temperature Ranges +0.3V ta -17V MAXAT3IXS ieee ee eee -0 3V, Von + 0.3V MAXI7OXE 20... ee eee ee ee -15V to +15V MAXI73KM ....... Derates Above +75C by Storage Temperature Range eee nee Power Dissipation (any Package) to +75C Lead Temperature (Soldering 10 seconds) orc to +70C .. 40C to +BSC . 35C ta +125C . 65C to + 160C 1000mWw Stresses above thase listed under "Absolute Maximum Ratings" may cause permanent damage to the davica. These are stress ratings only, and functional operation of the device af these or any other conditions abova those indicatad in the operational sections of the specifications ts not implied. Exposure to absolute maximum rating conditions for extended periods may affect device rehabulity. ELECTRICAL CHARACTERISTICS (Vpp = +5 + 5%, Ves = -12V or -15V + 5%: Slow Memory Mode; Ta = Twin to Taax unless otherwise noted, foi = 2-5MHz.) PARAMETER | symBo1 | CONDITIONS MIN TYP MAX | UNITS ACCURACY , Resolution 12 Bits No Missing Code Resclution 10 Bits Integral Non-Lingarity INL a +005 | %FSR Offset Error (Note 1) +5 mv Full Scale Error (Note 2) 04 % Full Scale Tempco (Notes 3, 4} {45 Ippm/c ANALOG INPUT : Input Voltage Range 0 5 | Vv Input Current AIN = OV to +5V : 35 | mA " INTERNAL REFERENCE Veer Output Voltage Ta = 25C 52 625 -53 v Vaer Output Tempca (Note 5) ~ +40 pom/?c Output Gurrent Sink Gapability (Note 6) - 5 mA LOGIC INPUTS ; Input Low Vollage Vic CS, RD, HBEN, CLKIN 0.8 Input High Voltage Viq__ |CS, AD, HBEN, CLKIN 24 input Capacitance (Nete 7} Cm |CSRD, HBEN, CLKIN 10 | pF Ci Input Current ling its HBEN VIN = 0 to Von te uA | LOGIC OUTPUTS _ | | Output Low Voltage Vo. | D11-Dov8, BUSY, CLKOUT Isinx = 1.6 mA 0.4 vo Output High Voltage Von | D11-D0/a, BUSY CLKOUT Isounce - 20004 4 Vv Foaling State Leakage lag | D11-DO/8. Vaur = OV to Vpp =10 | WA Co encttance (Note 7) Cour pF | CONVERSION TIME 7 MAX173 tcony Reyne hvonout {i te 1B cltek evctes} 4.8 52 us 2 CO AMA KL SI Complete 5us CMOS 10-Bit A/D Converter ELECTRICAL CHARACTERISTICS (continued) = (Vpp = +5V + 5%, Vs = -12V or -15V 4 5%; Slow Memory Made; Ts - Twin to Tax unless otherwise noted, fo.w = 2.5MHz.) PARAMETER | SYMBOL | CONDITIONS | MIN TYP MAX [UNITS > POWER SUPPLY REJECTION Vop Only FS Change, Vsg = -15V, Vpp = 4.75V to 5.25 +0.01 % Ni Vag Only FS Change, Von = 5, Vsg = -5% ta +5% +001 % w POWER REQUIREMENTS Von +5% for Specified Performance 5 Ves (Note 8} +5% for Specified Performance -12 of -15 In CS RD = Vpo, AIN=5V : 5 7 mA Iss GS =AD=Voo, AIN 5V 8 12 mA Power Dissipation Vop = +5, Vas = -15V 145 215 mw Note 1: Typical change over temp is + 1.2mvV. Note 2: Voo = +5V, Vss = -15V, FS +5.000V. Ideal last code transition = FS - 1.8mv. Note 3: Full Scale TC = AFS/AT, where AFS is full scale change from Ta = 26C to Tain OF Tmax. Note 4: Includes internal reference drift. Note 5: Vace TG = AVeer/AT, where AVurer is reference voltage change from Ta = 25C to Twin or Taax Note 6: Output current should not change during conversion. Note 7: Guaranteed by design, not subject to test. Note 8: Functional operation at Vgs = -12V 4 5% is guaranteed by testing offset error and full scale error TIMING CHARACTERISTICS (Note 9) (See MAX162 data sheet for ty-t,9 description) (Von tSV, Vg5 = -12V or -18V: Ta = Twin tO Tmax, Specifications in bold type are 100% tested, athers are quaranteed by design, unless otherwise noted.) i T,= 25C MAXI73C/E | MAXI73M PARAMETER SYMBOL | CONDITIONS TYP MAX MIN Max | MIM MAK UNITS TStoRDSetup time t 0 0 G ns AD to BUSY Delay (Note 12) b CL = 50pF 9 190 230 270 | ns ) Data Access Time (Note 10} ts Ci = 20pF 60 90 110 120 ns Data Access Time (Notes 10, 12) i C, = 100pF 70 125 , 150 170 ns AD Pulse Width tu tb ty ty CS to RD Hold Time ts | 0 0 0 ns (Notes 10.12) After BUSY te 8D 105 420 | ns Bus Relinquish Time (Notes 11, 12) ty T5 35 90 ns HBEN to RD Setup Time ta rh) 0 a ns HBEN to AD Hold Time ty 9 0 0 ns Delay Between Read Operations to : 200 200 200 ns Note 9: Al! input control signals are specified with t; = t, = Sms (10% to 90% of +5) and timed from a voltage level of +1 6V Note 10: t; and tgare measured with the load circuits of Figure 1 (see MAX 162 data sheet) and defined as the time required far an output to cross 0.8V or 2.4V. Note 11: 7 is defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2 {see MAX162 data sheet). Note 12: This specification is 100% production tested. For additional information on using the MAX173 please refer to MAX162 data sheet. SIA AISEL a ee 8 Complete 5us CMOS 10-Bit A/D Converter 6 =O Chip Topography IN Na 0.128" < + 820m = AGNO Vaee AIN Vou ss BUSY | i on naa BO ; | CLKOUT | or nai , an aa a eae 0.120" na el i Til | (3.05mm| | , O31 O20 O19 Bove OGND 05 04 Maxis cannot assume responsibility for use of any corcintry other ther circuitry entirely embodtad ina Maxim product. Ne circul! patent Heenses are imphed Mavie reserves the nga! to change the circurtry and specifications without! notes at any time. * VIA AI /I 4