1 kV RMS Six-Channel Digital Isolators
Data Sheet ADuM7640/ADuM7641/ADuM7642/ADuM7643
Rev. 0 Document Feedbac
k
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FEATURES
Small 20-lead QSOP
1000 V rms isolation rating
Safety and regulatory approvals (pending):
UL recognition (pending)
1000 V rms for 1 minute per UL 1577
Low power operation
3.3 V operation
1.6 mA per channel maximum at 0 Mbps to 1 Mbps
7.8 mA per channel maximum at 25 Mbps
5 V operation
2.2 mA per channel maximum at 0 Mbps to 1 Mbps
11.2 mA per channel maximum at 25 Mbps
Bidirectional communication
Up to 25 Mbps data rate (NRZ)
3 V/5 V level translation
High temperature operation: 105°C
High common-mode transient immunity: >15 kV/μs
APPLICATIONS
General-purpose, multichannel isolation
SPI interface/data converter isolation
RS-232/RS-422/RS-485 transceivers
Industrial field bus isolation
GENERAL DESCRIPTION
The ADuM7640/ADuM7641/ADuM7642/ADuM76431 are
6-channel digital isolators based on the Analog Devices, Inc.,
iCoupler® technology. These 1 kV digital isolation devices are
packaged in a small 20-lead QSOP. They offer space savings and
a lower price than 2.5 kV or 5 kV isolation solutions when only
functional isolation is needed.
This family, like many Analog Devices isolators, offers very low
power consumption, using one-tenth to one-sixth the power of
other digital isolators, with the supply voltage on either side
ranging from 3.0 V to 5.5 V. Despite their low power consumption,
the ADuM7640/ADuM7641/ADuM7642/ADuM7643 provide
low pulse width distortion (< 6 ns for C grade) and a channel-
by-channel glitch filter to protect the device against extraneous
noise disturbances. Four channel direction combinations are
available with a maximum data rate of 1 Mbps or 25 Mbps. All
products have a default output high logic state in the absence of
input power.
FUNCTIONAL BLOCK DIAGRAMS
V
DD1A
V
DD2A
120
GND
1
GND
2
219
V
IA
V
OA
318
ENCODE DECODE
V
IB
V
OB
417
ENCODE DECODE
V
IC
V
OC
516
ENCODE DECODE
V
ID
V
OD
615
ENCODE DECODE
V
DD1B
V
DD2B
714
V
IE
V
OE
813
ENCODE DECODE
V
IF
V
OF
912
ENCODE DECODE
GND
1
GND
2
10 11
ADuM7640
10448-001
Figure 1. ADuM7640
V
DD1A
V
DD2A
120
GND
1
GND
2
219
V
IA
V
OA
318
ENCODE DECODE
V
IB
V
OB
417
ENCODE DECODE
V
IC
V
OC
516
ENCODE DECODE
V
ID
V
OD
615
ENCODE DECODE
V
DD1B
V
DD2B
714
V
OE
V
IE
813
DECODE ENCODE
V
IF
V
OF
912
ENCODE DECODE
GND
1
GND
2
10 11
ADuM7641
10448-002
Figure 2. ADuM7641
V
DD1A
V
DD2A
120
GND
1
GND
2
219
V
IA
V
OA
318
ENCODE DECODE
V
IB
V
OB
417
ENCODE DECODE
V
IC
V
OC
516
ENCODE DECODE
V
OD
V
ID
615
DECODE ENCODE
V
DD1B
V
DD2B
714
V
OE
V
IE
813
DECODE ENCODE
V
IF
V
OF
912
ENCODE DECODE
GND
1
GND
2
10 11
ADuM7642
10448-003
Figure 3. ADuM7642
VDD1A VDD2A
120
GND1GND2
219
VIA VOA
318
ENCODE DECODE
VIB VOB
417
ENCODE DECODE
VOC VIC
516
DECODE ENCODE
VOD VID
615
DECODE ENCODE
VDD1B VDD2B
714
VOE VIE
813
DECODE ENCODE
VIF VOF
912
ENCODE DECODE
GND1GND2
10 11
ADuM7643
10448-004
Figure 4. ADuM7643
1 Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329. Other patents pending.
ADuM7640/ADuM7641/ADuM7642/ADuM7643 Data Sheet
Rev. 0 | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics—5 V Operation................................ 3
Electrical Characteristics—3.3 V Operation ............................ 5
Electrical Characteristics—Mixed 5 V/3.3 V Operation ........ 7
Electrical Characteristics—Mixed 3.3 V/5 V Operation ........ 8
Package Characteristics ............................................................... 9
Regulatory Information ............................................................... 9
Insulation and Safety Related Specifications ............................ 9
Recommended Operating Conditions ...................................... 9
Absolute Maximum Ratings ......................................................... 10
ESD Caution................................................................................ 10
Pin Configurations and Function Descriptions ......................... 11
Typical Performance Characteristics ........................................... 15
Applications Information .............................................................. 17
Printed Circuit Board Layout ................................................... 17
Propagation Delay-Related Parameters ................................... 17
DC Correctness ............................................................................ 17
Magnetic Field Immunity ............................................................. 18
Power Consumption .................................................................. 19
Insulation Lifetime ..................................................................... 19
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 20
REVISION HISTORY
9/12—Revision 0: Initial Version
Data Sheet ADuM7640/ADuM7641/ADuM7642/ADuM7643
Rev. 0 | Page 3 of 20
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. Minimum/maximum specifications apply over the entire recommended operation
range of 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications are tested
with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 1.
A Grade
C Grade
Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width PW 250 40 ns Within PWD limit
Data Rate 1 25 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 75 28 40 50 ns 50% input to 50% output
Pulse Width Distortion PWD 25 2 6 ns |tPLH − tPHL|
Change vs. Temperature
3
ps/°C
Propagation Delay Skew1 tPSK 20 14 ns
Channel Matching
Codirectional2 tPSKCD 25 6 12 ns
Opposing Directional3 tPSKOD 30 7 12 ns
Jitter 2 2 ns
1 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
2 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.
3 Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposite sides of the
isolation barrier.
Table 2.
1 Mbps—A and C Grades 25 Mbps—C Grade
Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions/Comments
SUPPLY CURRENT No load
ADuM7640 IDD1 5.7 7.0 44 54 mA
IDD2 4.4 5.9 11 13 mA
ADuM7641 IDD1 5.5 6.8 38 46 mA
I
DD2
4.6
5.7
15
19
mA
ADuM7642 IDD1 5.2 6.3 31 38 mA
IDD2 4.8 6.0 19 24 mA
ADuM7643 IDD1 4.8 6.0 24 30 mA
IDD2 5.0 6.3 22 29 mA
ADuM7640/ADuM7641/ADuM7642/ADuM7643 Data Sheet
Rev. 0 | Page 4 of 20
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC SPECIFICATIONS
Input Voltage Threshold
Logic High VIH 0.7 VDDx V
Logic Low VIL 0.3 VDDx V
Output Voltages
Logic High VOH VDDx − 0.1 5.0 V IOx = −20 µA, VIx = VIxH
VDDx − 0.4 4.8 V IOx = −4 mA, VIx = VIxH
Logic Low VOL 0.0 0.1 V IOx = 20 µA, VIx = VIxL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
Input Current per Channel
I
I
−10
+0.01
+10
µA
0 V ≤ V
Ix
≤ V
DDx
Supply Current per Channel
Quiescent Supply Current
Input IDDI (Q) 0.95 1.16 mA
Output IDDO (Q) 0.73 0.98 mA
Dynamic Supply Current
Input
I
DDI (D)
0.26
mA/Mbps
Output IDDO (D) 0.04 mA/Mbps
AC SPECIFICATIONS
Output Rise/Fall Time
t
R
/t
F
2.0
ns
10% to 90%
Common-Mode Transient Immunity1 |CM| 15 25 kV/µs VIx = VDDx, VCM = 1000 V, transient
magnitude = 800 V
Refresh Rate fr 600 kHz DC data inputs
1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOL < 0.8 × VDDLx or VOH > 0.7 × VDDIx. The common-mode voltage slew
rates apply to both rising and falling common-mode voltage edges.
Data Sheet ADuM7640/ADuM7641/ADuM7642/ADuM7643
Rev. 0 | Page 5 of 20
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. Minimum/maximum specifications apply over the entire recommended
operation range of 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 4.
A Grade C Grade
Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width PW 250 40 ns Within PWD limit
Data Rate
1
25
Mbps
Within PWD limit
Propagation Delay tPHL, tPLH 85 33 49 66 ns 50% input to 50% output
Pulse Width Distortion PWD 25 2 6 ns |tPLH − tPHL|
Change vs. Temperature 5 3 ps/°C
Propagation Delay Skew1 tPSK 20 14 ns
Channel Matching
Codirectional2 tPSKCD 25 6 12 ns
Opposing Directional3 tPSKOD 30 6 15 ns
Jitter 2 2 ns
1 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
2 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.
3 Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposite sides of the
isolation barrier.
Table 5.
1 Mbps—A and C Grades
25 Mbps—C Grade
Parameter
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
Test Conditions/Comments
SUPPLY CURRENT No load
ADuM7640
I
DD1
4.1
5.2
32
38
mA
IDD2 3.3 4.3 7.2 8.7 mA
ADuM7641 IDD1 3.9 4.9 27 33 mA
IDD2 3.4 4.2 11 13 mA
ADuM7642 IDD1 3.7 4.7 23 27 mA
IDD2 3.5 4.4 14 16 mA
ADuM7643 IDD1 3.5 4.4 18 21 mA
IDD2 3.6 4.5 16 20 mA
ADuM7640/ADuM7641/ADuM7642/ADuM7643 Data Sheet
Rev. 0 | Page 6 of 20
Table 6.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC SPECIFICATIONS
Input Voltage Threshold
Logic High VIH 0.7 VDDx V
Logic Low VIL 0.3 VDDx V
Output Voltages
Logic High VOH VDDx − 0.2 3.3 V IOx = −20 µA, VIx = VIxH
VDDx − 0.5 3.1 V IOx = −4 mA, VIx = VIxH
Logic Low VOL 0.0 0.1 V IOx = 20 µA, VIx = VIxL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
Input Current per Channel
I
I
−10
+0.01
+10
µA
0 V ≤ V
Ix
≤ V
DDx
Supply Current per Channel
Quiescent Supply Current
Input IDDI (Q) 0.68 0.87 mA
Output IDDO (Q) 0.55 0.72 mA
Dynamic Supply Current
Input
I
DDI (D)
0.19
mA/Mbps
Output IDDO (D) 0.03 mA/Mbps
AC SPECIFICATIONS
Output Rise/Fall Time
t
R
/t
F
2.8
ns
10% to 90%
Common-Mode Transient Immunity1 |CM| 15 20 kV/µs VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate fr 550 kHz DC data inputs
1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOL < 0.8 VDDLx or VOH > 0.7 × VDDIx. The common-mode voltage slew
rates apply to both rising and falling common-mode voltage edges.
Data Sheet ADuM7640/ADuM7641/ADuM7642/ADuM7643
Rev. 0 | Page 7 of 20
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3.3 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = 5 V, V DD2 = 3.3 V. Minimum/maximum specifications apply over the entire recom-
mended operation range of 4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching
specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 7.
A Grade
C Grade
Parameter Symbol
Min
Typ
Max
Min
Typ
Max
Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width PW 250 40 ns Within PWD limit
Data Rate
1
25
Mbps
Within PWD limit
Propagation Delay tPHL, tPLH 80 30 42 58 ns 50% input to 50% output
Pulse Width Distortion PWD 25 2 6 ns |tPLH − tPHL|
Change vs. Temperature 5 3 ps/°C
Propagation Delay Skew1 tPSK 20 14 ns
Channel Matching
Codirectional2 tPSKCD 25 5 15 ns
Opposing Directional3 tPSKOD 30 8 15 ns
Jitter 2 2 ns
1 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
2 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.
3 Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposite sides of the
isolation barrier.
Table 8.
1 Mbps—A, C Grades 25 Mbps—C Grade
Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions/Comments
SUPPLY CURRENT No load
ADuM7640
I
DD1
5.7
7.0
44
54
mA
IDD2 3.3 4.1 7.5 8.7 mA
ADuM7641 IDD1 5.4 6.8 38 46 mA
IDD2 3.4 4.0 11 13 mA
ADuM7642 IDD1 5.1 6.3 31 38 mA
IDD2 3.5 4.3 14 16 mA
ADuM7643 IDD1 4.8 6.0 24 30 mA
IDD2 3.6 4.3 16 20 mA
Table 9.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC SPECIFICATIONS
Input Voltage Threshold
Logic High VIH 0.7 VDDx V
Logic Low VIL 0.3 VDDx V
Output Voltages
Logic High
V
OH
V
DDx
− 0.1
V
DDx
V
I
Ox
= −20 µA, V
Ix
= V
IxH
VDDx − 0.5 VDDx − 0.2 V IOx = −4 mA, VIx = VIxH
Logic Low VOL 0.0 0.1 V IOx = 20 µA, VIx = VIxL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
Input Current per Channel II −10 +0.01 +10 µA 0 V ≤ VIx ≤ VDDx
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient Immunity1 |CM| 15 20 kV/µs VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate fr 600 kHz DC data inputs
1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOL < 0.8 VDDLx or VOH > 0.7 × VDDIx. The common-mode voltage slew
rates apply to both rising and falling common-mode voltage edges.
ADuM7640/ADuM7641/ADuM7642/ADuM7643 Data Sheet
Rev. 0 | Page 8 of 20
ELECTRICAL CHARACTERISTICS—MIXED 3.3 V/5 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = 3.3 V, VDD2 = 5 V. Minimum/maximum specifications apply over the entire recom-
mended operation range of 3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching
specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 10.
A Grade C Grade
Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width PW 250 40 ns Within PWD limit
Data Rate 1 25 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 80 29 46 60 ns 50% input to 50% output
Pulse Width Distortion PWD 25 2 6 ns |tPLH − tPHL|
Change vs. Temperature 5 3 ps/°C
Propagation Delay Skew1 tPSK 20 14 ns
Channel Matching
Codirectional2 tPSKCD 25 6 13 ns
Opposing Directional3 tPSKOD 30 9 18 ns
Jitter 2 2 ns
1 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
2 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.
3 Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposite sides of the
isolation barrier.
Table 11.
1 Mbps—A, C Grades 25 Mbps—C Grade
Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions/Comments
SUPPLY CURRENT No load
ADuM7640
I
DD1
4.1
4.9
32
38
mA
IDD2 4.5 5.9 11 13 mA
ADuM7641 IDD1 3.9 4.7 27 33 mA
IDD2 4.6 5.7 15 19 mA
ADuM7642 IDD1 3.7 4.4 23 27 mA
IDD2 4.8 6.0 19 24 mA
ADuM7643 IDD1 3.5 4.2 18 21 mA
IDD2 5.0 6.2 22 29 mA
Table 12.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC SPECIFICATIONS
Input Voltage Threshold
Logic High VIH 0.7 VDDx V
Logic Low VIL 0.3 VDDx V
Output Voltages
Logic High
V
OH
V
DDx
− 0.1
V
DDx
V
I
Ox
= −20 µA, V
Ix
= V
IxH
VDDx − 0.5 VDDx − 0.2 V IOx = −4 mA, VIx = VIxH
Logic Low VOL 0.0 0.1 V IOx = 20 µA, VIx = VIxL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
Input Current per Channel II −10 +0.01 +10 µA 0 V ≤ VIx ≤ VDDx
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient Immunity1 |CM| 15 20 kV/µs VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate fr 550 kHz DC data inputs
1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOL < 0.8 VDDLx or VOH > 0.7 × VDDIx. The common-mode voltage
slew rates apply to both rising and falling common-mode voltage edges.
Data Sheet ADuM7640/ADuM7641/ADuM7642/ADuM7643
Rev. 0 | Page 9 of 20
PACKAGE CHARACTERISTICS
Table 13.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Resistance (Input to Output)1
R
I-O
1013
Ω
Capacitance (Input to Output)1 CI-O 2 pF f = 1 MHz
Input Capacitance2 CI 4.0 pF
IC Junction-to-Ambient Thermal Resistance θJA 76 °C/W Thermocouple located at
center of package underside
1 The device is considered a 2-terminal device: Pin 1 through Pin 10 are shorted together, and Pin 11 through Pin 20 are shorted together.
2 Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM7640/ADuM7641/ADuM7642/ADuM7643 are approved by the organizations listed in Table 14. See Table 18 and the
Insulation Lifetime section for recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.
Table 14.
UL (Pending)
Recognized Under UL 1577 Component Recognition Program1
Single Protection,1000 V rms Isolation Voltage
File E274400
1 In accordance with UL 1577, each ADuM7640/ADuM7641/ADuM7642/ADuM7643 is proof tested by applying an insulation test voltage ≥ 1200 V rms for 1 sec (current
leakage detection limit = 5 µA).
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 15.
Parameter Symbol Value Unit Test Conditions/Comments
Rated Dielectric Insulation Voltage 1000 V rms 1 minute duration
Minimum External Air Gap (Clearance) L(I01) 3.8 mm min Measured from input terminals to output
terminals, shortest distance through air
Minimum External Tracking (Creepage) L(I02) 2.8 mm min Measured from input terminals to output
terminals, shortest distance path along body
Minimum Internal Gap (Internal Clearance) 2.6 μm min Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303 Part 1
Isolation Group II Material Group (DIN VDE 0110, 1/89, Table 1)
CASE TEMPERATURE (°C)
SAF E TY-LI M ITING CURRE NT (mA)
0
0
350
300
250
200
150
100
50
50 100 150 200
10448-005
Figure 5. Thermal Derating Curve, Dependence of Safety-Limiting Values on
Case Temperature per DIN V VDE V 0884-10
RECOMMENDED OPERATING CONDITIONS
Table 16.
Parameter
Symbol
Min
Max
Unit
Operating Temperature TA −40 +105 °C
Supply Voltages
1
V
DD1
, V
DD2
3.0
5.5
V
Input Signal Rise and Fall
Times
1.0 ms
1 All voltages are relative to their respective grounds. See the DC Correctness
section for information about immunity to external magnetic fields.
ADuM7640/ADuM7641/ADuM7642/ADuM7643 Data Sheet
Rev. 0 | Page 10 of 20
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 17.
Parameter Rating
Storage Temperature (TST) Range −65°C to +150°C
Ambient Operating Temperature (TA) −40°C to +105°C
Supply Voltages (VDD1, VDD2) −0.5 V to +7.0 V
Input Voltages (VIA, VIB, VIC, VID, VIE, VIF)1, 2 −0.5 V to VDDI + 0.5 V
Output Voltages (VOA, VOB, VOC, VOD, VIE,
VIF)1, 2
−0.5 V to VDDO + 0.5 V
Average Output Current per Pin3
Side 1 (IO1) −10 mA to +10 mA
Side 2 (IO2) −10 mA to +10 mA
Common-Mode Transients3 −100 kV/µs to +100 kV/µs
1 VDDI and VDDO refer to the supply voltages on the input and output sides of a
given channel, respectively. See the Printed Circuit Board Layout section.
2 See Figure 5 for maximum rated current values for various temperatures.
3 Refers to common-mode transients across the insulation barrier. Common-
mode transients exceeding the absolute maximum ratings may cause
latch-up or permanent damage.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating
only; functional operation of the device at these or any other
conditions above those indicated in the operational section of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
ESD CAUTION
Table 18. Maximum Continuous Working Voltage1
Parameter Max Unit Constraint
AC Voltage, Bipolar Waveform 420 V peak 50-year minimum lifetime
AC Voltage, Unipolar Waveform
Basic Insulation 420 V peak 50-year minimum lifetime
DC Voltage
Basic Insulation 420 V peak 50-year minimum lifetime
1 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more information.
Table 19. Truth Table (Positive Logic)
VIx Input1 VDDI State2 VDDO State3 VOxOutput1 Description
H Powered Powered H Normal operation; data is high.
L Powered Powered L Normal operation; data is low.
X Unpowered Powered H Input unpowered. Output pins are in the default high state. Outputs
return to input state within 1.6 µs of VDDI power restoration. See the pin
function descriptions (Table 20 through Table 23) for more information.
X Powered Unpowered Z Output unpowered. Output pins are in high impedance state. Outputs
return to input state within 1.6 µs of VDDO power restoration. See the pin
function descriptions (Table 20 through Table 23Table 22) for more
information.
1 VIx and VOx refer to the input and output signals of a given channel (A, B, C, D, E or F).
2 VDDI refers to the supply voltage on the input side of a given channel (A, B, C, D, E or F).
3 VDDO refers to the supply voltage on the output side of a given channel (A, B, C, D, E or F).
Data Sheet ADuM7640/ADuM7641/ADuM7642/ADuM7643
Rev. 0 | Page 11 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
*PI N 2 AND P IN 10 ARE I NTERNALLY CONNECTED.
CONNE CTING BO TH PI NS TO P CB S IDE 1 GROUND
IS RE COMME NDE D. PIN 11 AND PI N 19 ARE
INTERNAL LY CONNECT E D. CO NNE CTI NG BOTH
PI NS TO P CB S IDE 2 GROUND IS RE COMM E NDE D.
1
2
3
4
20
19
18
17
516
615
714
912
10 11
813
ADuM7640
TOP VI EW
(No t t o Scal e)
V
DD1A
GND
1
*
V
IA
V
IB
V
IC
V
ID
V
DD1B
V
IE
V
IF
GND
1
*
V
DD2A
GND
2
*
V
OA
V
OB
V
OC
V
OD
V
DD2B
V
OE
V
OF
GND
2
*
10448-006
Figure 6. ADuM7640 Pin Configuration
Table 20. ADuM7640 Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD1A Supply Voltage A for Isolator Side 1 (3.0 V to 5.5 V). Pin 1 must be connected externally to Pin 7. Connect a 0.01 µF to
0.1 µF between VDD1A (Pin 1) and GND1 (Pin 2).
2 GND1 Ground Reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both pins to the
PCB ground plane is recommended.
3 VIA Logic Input A.
4 VIB Logic Input B.
5 VIC Logic Input C.
6 VID Logic Input D.
7 VDD1B Supply Voltage B for Isolator Side 1 (3.0 V to 5.5 V). Pin 7 must be connected externally to Pin 1. Connect a 0.01 µF to
0.1 µF between VDD1B (Pin 7) and GND1 (Pin 10).
8
V
IE
Logic Input E.
9 VIF Logic Input F.
10 GND1 Ground Reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both pins to the PCB
ground plane is recommended.
11 GND2 Ground Reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both pins to the PCB
ground plane is recommended.
12
V
OF
Logic Output F.
13 VOE Logic Output E.
14 VDD2B Supply Voltage B for Isolator Side 2 (3.0 V to 5.5 V). Pin 14 must be connected externally to Pin 20. Connect a 0.01 µF
to 0.1 µF between VDD2B (Pin 14) and GND2 (Pin 11).
15 VOD Logic Output D.
16 VOC Logic Output C.
17 VOB Logic Output B.
18 VOA Logic Output A.
19 GND2 Ground Reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both pins to the PCB
ground plane is recommended.
20 VDD2A Supply Voltage A for Isolator Side 2 (3.0 V to 5.5 V). Pin 20 must be connected externally to Pin 14. Connect a 0.01 µF
to 0.1 µF between VDD2A (Pin 20) and GND2 (Pin 19).
Reference the AN-1109 Application Note for specific layout guidelines.
ADuM7640/ADuM7641/ADuM7642/ADuM7643 Data Sheet
Rev. 0 | Page 12 of 20
*PI N 2 AND P IN 10 ARE I NTERNALLY CONNECTED.
CONNE CTING BO TH PI NS TO P CB S IDE 1 GROUND
IS RE COMME NDE D. PIN 11 AND PI N 19 ARE
INTERNAL LY CONNECT E D. CO NNE CTI NG BOTH
PI NS TO P CB S IDE 2 GROUND IS RE COMM E NDE D.
1
2
3
4
20
19
18
17
516
615
714
912
10 11
813
ADuM7641
TOP VI EW
(No t t o Scal e)
VDD1A
GND1*
VIA
VIB
VIC
VID
VDD1B
VOE
VIF
GND1*
VDD2A
GND2*
VOA
VOB
VOC
VOD
VDD2B
VIE
VOF
GND2*
10448-007
Figure 7. ADuM7641 Pin Configuration
Table 21. ADuM7641 Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD1A Supply Voltage A for Isolator Side 1 (3.0 V to 5.5 V). Pin 1 must be connected externally to Pin 7. Connect a 0.01 µF to
0.1 µF between VDD1A (Pin 1) and GND1 (Pin 2).
2
GND
1 Ground Reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both pins to the PCB
ground plane is recommended.
3 VIA Logic Input A.
4 VIB Logic Input B.
5 VIC Logic Input C.
6 VID Logic Input D.
7 VDD1B Supply Voltage B for Isolator Side 1 (3.0 V to 5.5 V). Pin 7 must be connected externally to Pin 1. Connect a 0.01 µF to
0.1 µF between VDD1B (Pin 7) and GND1 (Pin 10).
8 VOE Logic Output E.
9 VIF Logic Input F.
10 GND1 Ground Reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both pins to the PCB
ground plane is recommended.
11 GND2 Ground Reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both pins to the PCB
ground plane is recommended.
12 VOF Logic Output F.
13 VIE Logic Input E.
14 VDD2B Supply Voltage B for Isolator Side 2 (3.0 V to 5.5 V). Pin 14 must be connected externally to Pin 20. Connect a 0.01 µF
to 0.1 µF between VDD2B (Pin 14) and GND2 (Pin 11).
15 VOD Logic Output D.
16 VOC Logic Output C.
17 VOB Logic Output B.
18 VOA Logic Output A.
19 GND2 Ground Reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both pins to the PCB
ground plane is recommended.
20 VDD2A Supply Voltage A for Isolator Side 2 (3.0 V to 5.5 V). Pin 20 must be connected externally to Pin 14. Connect a 0.01 µF
to 0.1 µF between VDD2A (Pin 20) and GND2 (Pin 19).
Reference the AN-1109 Application Note for specific layout guidelines.
Data Sheet ADuM7640/ADuM7641/ADuM7642/ADuM7643
Rev. 0 | Page 13 of 20
*PI N 2 AND P IN 10 ARE I NTERNALLY CONNECTED.
CONNE CTING BO TH PI NS TO P CB S IDE 1 GROUND
IS RE COMME NDE D. PIN 11 AND PI N 19 ARE
INTERNAL LY CONNECT E D. CO NNE CTI NG BOTH
PI NS TO P CB S IDE 2 GROUND IS RE COMM E NDE D.
1
2
3
4
20
19
18
17
516
615
714
912
10 11
813
ADuM7642
TOP VI EW
(No t t o Scal e)
VDD1A
GND1*
VIA
VIB
VIC
VOD
VDD1B
VOE
VIF
GND1*
VDD2A
GND2*
VOA
VOB
VOC
VID
VDD2B
VIE
VOF
GND2*
10448-008
Figure 8. ADuM7642 Pin Configuration
Table 22. ADuM7642 Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD1A Supply Voltage A for Isolator Side 1 (3.0 V to 5.5 V). Pin 1 must be connected externally to Pin 7. Connect a 0.01 µF to
0.1 µF between VDD1A (Pin 1) and GND1 (Pin 2).
2
GND
1 Ground Reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both pins to the PCB
ground plane is recommended.
3 VIA Logic Input A.
4 VIB Logic Input B.
5 VIC Logic Input C.
6 VOD Logic Output D.
7 VDD1B Supply Voltage B for Isolator Side 1 (3.0 V to 5.5 V). Pin 7 must be connected externally to Pin 1. Connect a 0.01 µF to
0.1 µF between VDD1B (Pin 7) and GND1 (Pin 10).
8 VOE Logic Output E.
9 VIF Logic Input F.
10 GND1 Ground Reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both pins to the PCB
ground plane is recommended.
11 GND2 Ground Reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both pins to the PCB
ground plane is recommended.
12 VOF Logic Output F.
13 VIE Logic Input E.
14 VDD2B Supply Voltage B for Isolator Side 2 (3.0 V to 5.5 V). Pin 14 must be connected externally to Pin 20. Connect a 0.01 µF
to 0.1 µF between VDD2B (Pin 14) and GND2 (Pin 11).
15 VID Logic Input D.
16 VOC Logic Output C.
17 VOB Logic Output B.
18 VOA Logic Output A.
19 GND2 Ground Reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both pins to the PCB
ground plane is recommended.
20 VDD2A Supply Voltage A for Isolator Side 2 (3.0 V to 5.5 V). Pin 20 must be connected externally to Pin 14. Connect a 0.01 µF
to 0.1 µF between VDD2A (Pin 20) and GND2 (Pin 19).
Reference the AN-1109 Application Note for specific layout guidelines.
ADuM7640/ADuM7641/ADuM7642/ADuM7643 Data Sheet
Rev. 0 | Page 14 of 20
*PI N 2 AND P IN 10 ARE I NTERNALLY CONNECTED.
CONNE CTING BO TH PI NS TO P CB S IDE 1 GROUND
IS RE COMME NDE D. PIN 11 AND PI N 19 ARE
INTERNAL LY CONNECT E D. CO NNE CTI NG BOTH
PI NS TO P CB S IDE 2 GROUND IS RE COMM E NDE D.
1
2
3
4
20
19
18
17
516
615
714
912
10 11
813
ADuM7643
TOP VI EW
(No t t o Scal e)
VDD1A
GND1*
VIA
VIB
VOC
VOD
VDD1B
VOE
VIF
GND1*
VDD2A
GND2*
VOA
VOB
VIC
VID
VDD2B
VIE
VOF
GND2*
10448-009
Figure 9. ADuM7643 Pin Configuration
Table 23. ADuM7643 Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD1A Supply Voltage A for Isolator Side 1 (3.0 V to 5.5 V). Pin 1 must be connected externally to Pin 7. Connect a 0.01 µF to
0.1 µF between VDD1A (Pin 1) and GND1 (Pin 2).
2
GND
1 Ground Reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both pins to the PCB
ground plane is recommended.
3 VIA Logic Input A.
4 VIB Logic Input B.
5 VOC Logic Output C.
6 VOD Logic Output D.
7 VDD1B Supply Voltage B for Isolator Side 1 (3.0 V to 5.5 V). Pin 7 must be connected externally to Pin 1. Connect a 0.01 µF to
0.1 µF between VDD1B (Pin 7) and GND1 (Pin 10).
8 VOE Logic Output E.
9 VIF Logic Input F.
10 GND1 Ground Reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both pins to the PCB
ground plane is recommended.
11 GND2 Ground Reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both pins to the PCB
ground plane is recommended.
12 VOF Logic Output F.
13 VIE Logic Input E.
14 VDD2B Supply Voltage B for Isolator Side 2 (3.0 V to 5.5 V). Pin 14 must be connected externally to Pin 20. Connect a 0.01 µF
to 0.1 µF between VDD2B (Pin 14) and GND2 (Pin 11).
15 VID Logic Input D.
16 VIC Logic Input C.
17 VOB Logic Output B.
18 VOA Logic Output A.
19 GND2 Ground Reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both pins to the PCB
ground plane is recommended.
20 VDD2A Supply Voltage A for Isolator Side 2 (3.0 V to 5.5 V). Pin 20 must be connected externally to Pin 14. Connect a 0.01 µF
to 0.1 µF between VDD2A (Pin 20) and GND2 (Pin 19).
Reference the AN-1109 Application Note for specific layout guidelines.
Data Sheet ADuM7640/ADuM7641/ADuM7642/ADuM7643
Rev. 0 | Page 15 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
0 5 10 15 20 25 30
DATA RATE (M bp s)
3.3V
5V
10
8
6
4
2
0
CURRENT ( mA)
10448-010
Figure 10. Typical Supply Current per Input Channel vs. Data Rate
for 5 V and 3.3 V Operation
0 5 10 15 20 25 30
DATA RATE (M bp s)
4
3
2
1
0
CURRENT ( mA)
10448-011
5V
3.3V
Figure 11. Typical Supply Current per Output Channel vs. Data Rate
for 5 V and 3.3 V Operation (No Output Load)
0 5 10 15 20 25 30
DATA RATE (M bp s)
4
3
2
1
0
CURRENT ( mA)
10448-012
5V
3.3V
Figure 12. Typical Supply Current per Output Channel vs. Data Rate
for 5 V and 3.3 V Operation (15 pF Output Load)
0 5 10 15 20 25
DATA RATE (M bp s)
45
40
35
30
25
20
15
10
5
0
I
DD1
CURRENT ( mA)
10448-013
5V
3.3V
Figure 13. Typical ADuM7640 VDD1 Supply Current vs. Data Rate
for 5 V and 3.3 V Operation
0 5 10 15 20 25
DATA RATE (M bp s)
12
10
8
6
4
2
0
I
DD2
CURRENT ( mA)
10448-014
5V
3.3V
Figure 14. Typical ADuM7640 VDD2 Supply Current vs. Data Rate
for 5 V and 3.3 V Operation
0 5 10 15 20 25
DATA RATE (M bp s)
40
35
30
25
20
15
10
5
0
I
DD1
CURRENT ( mA)
10448-015
5V
3.3V
Figure 15. Typical ADuM7641 VDD1 Supply Current vs. Data Rate
for 5 V and 3.3 V Operation
ADuM7640/ADuM7641/ADuM7642/ADuM7643 Data Sheet
Rev. 0 | Page 16 of 20
0 5 10 15 20 25
DATA RATE (M bp s)
18
14
16
12
10
8
6
4
2
0
I
DD2
CURRENT ( mA)
10448-016
5V
3.3V
Figure 16. Typical ADuM7641 VDD2 Supply Current vs. Data Rate
for 5 V and 3.3 V Operation
0 5 10 15 20 25
DATA RATE (M bp s)
35
25
30
20
15
10
5
0
I
DD1
CURRENT ( mA)
10448-017
5V
3.3V
Figure 17. Typical ADuM7642 VDD1 Supply Current vs.
Data Rate for 5 V and 3.3 V Operation
0510 15 20 25
DATA RATE (M bp s)
25
20
15
10
5
0
I
DD2
CURRENT ( mA)
10448-018
5V
3.3V
Figure 18. Typical ADuM7642 VDD2 Supply Current vs.
Data Rate for 5 V and 3.3 V Operation
0 5 10 15 20 25
DATA RATE (M bp s)
30
25
20
15
10
5
0
I
DD1
CURRENT ( mA)
10448-019
5V
3.3V
Figure 19. Typical ADuM7643 VDD1 or VDD2 Supply Current vs.
Data Rate for 5 V and 3.3 V Operation
Data Sheet ADuM7640/ADuM7641/ADuM7642/ADuM7643
Rev. 0 | Page 17 of 20
APPLICATIONS INFORMATION
PRINTED CIRCUIT BOARD LAYOUT
The ADuM7640/ADuM7641/ADuM7642/ADuM7643 digital
isolators require no external interface circuitry for the logic
interfaces. Power supply bypassing is strongly recommended at the
input and output supply pins (see Figure 20). Connect four bypass
capacitors between Pin 1 and Pin 2 for VDD1A, between Pin 7 and
Pin 10 for VDD1B, between Pin 11 and Pin 14 for VDD2B, and between
Pin 19 and Pin 20 for VDD2A. Connect the VDD1A supply pin and the
VDD1B supply pin together, and connect the VDD2B supply pin and
VDD2A supply pin together. The capacitor values should be from
0.01 µF to 0.1 µF. The total lead length between both ends of the
capacitor and the power supply pin should not exceed 20 mm.
V
DD1A
GND
1
V
IA
V
IB
V
IC
/V
OC
V
ID
/V
OD
V
DD1B
V
IE
/V
OE
V
IF
GND
1
V
DD2A
GND
2
V
OA
V
OB
V
OC
/V
IC
V
OD
/V
ID
V
DD2B
V
OE
/V
IE
V
OF
GND
2
10448-020
Figure 20. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, it is
important to minimize board coupling across the isolation barrier.
Furthermore, users should design the board layout so that any
coupling that occurs affects all pins equally on a given component
side. Failure to follow this design guideline can cause voltage
differentials between pins that exceed the absolute maximum
ratings of the device, which can lead to latch-up or permanent
damage.
With proper PCB design choices, the ADuM7640/ADuM7641/
ADuM7642/ADuM7643 can readily meet CISPR 22 Class A
(and FCC Class A) emissions standards, as well as the more
stringent CISPR 22 Class B (and FCC Class B) standards in
an unshielded environment. For PCB-related EMI mitigation
techniques, including board layout and stack-up issues, see the
AN-1109 Application Note.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The input-to-
output propagation delay time for a high-to-low transition may
differ from the propagation delay time for a low-to-high transition.
INPUT (VIx)
OUTPUT (VOx)
tPLH tPHL
50%
50%
10448-021
Figure 21. Propagation Delay Parameters
Pulse width distortion is the maximum difference between these
two propagation delay values and is an indication of how accurately
the timing of the input signal is preserved.
Channel-to-channel matching refers to the maximum amount
of time that the propagation delay differs between channels
within a single ADuM7640/ADuM7641/ADuM7642/ADuM7643
component.
Propagation delay skew refers to the maximum amount of time
that the propagation delay differs between multiple ADuM7640/
ADuM7641/ADuM7642/ADuM7643 components operating
under the same conditions.
DC CORRECTNESS
Positive and negative logic transitions at the isolator input
cause narrow (~1 ns) pulses to be sent to the decoder using the
transformer. The decoder is bistable and is, therefore, either set
or reset by the pulses, indicating input logic transitions. In the
absence of logic transitions at the input for more than ~1 µs, a
periodic set of refresh pulses indicative of the correct input state
is sent to ensure dc correctness at the output. If the decoder receives
no internal pulses for more than approximately 5 µs, the input side
is assumed to be unpowered or nonfunctional, in which case the
isolator output is forced to a default high state by the watchdog
timer circuit.
ADuM7640/ADuM7641/ADuM7642/ADuM7643 Data Sheet
Rev. 0 | Page 18 of 20
MAGNETIC FIELD IMMUNITY
The magnetic field immunity of the ADuM7640/ADuM7641/
ADuM7642/ADuM7643 is determined by the changing magnetic
field, which induces a voltage in the transformer receiving coil
large enough to either falsely set or reset the decoder. The following
analysis defines the conditions under which this can occur. The
3 V operating condition of the ADuM7640/ADuM7641/
ADuM7642/ADuM7643 is examined because it represents the
most susceptible mode of operation.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at approximately
0.5 V, thus establishing a 0.5 V margin in which induced voltages
can be tolerated. The voltage induced across the receiving coil is
given by
V = (−dβ/dt) ∑ π rn2; n = 1, 2, … , N
where:
β is magnetic flux density (gauss).
rn is the radius of the nth turn in the receiving coil (cm).
N is the total number of turns in the receiving coil.
Given the geometry of the receiving coil in the ADuM7640/
ADuM7641/ADuM7642/ADuM7643 and an imposed
requirement that the induced voltage be, at most, 50% of the 0.5 V
margin at the decoder, a maximum allowable magnetic field at a
given frequency can be calculated. The result is shown in Figure 22.
1000
100
10
1
0.1
0.01
0.0011k 100M10k
MAXIMUM ALL OWABLE M AGNETIC FL UX ( kgauss)
100k 1M 10M
MAG NE TIC FI E LD FRE QUENCY ( Hz )
10448-022
Figure 22. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the maximum
allowable magnetic field of 0.5 kgauss induces a voltage of 0.25 V at
the receiving coil. This voltage is approximately 50% of the sensing
threshold and does not cause a faulty output transition. Similarly, if
such an event occurs during a transmitted pulse and is of the
worst-case polarity, it reduces the received pulse from >1.0 V to
0.75 V, still well above the 0.5 V sensing threshold of the decoder.
The preceding magnetic flux density values correspond to specific
current magnitudes at given distances from the ADuM7640/
ADuM7641/ADuM7642/ADuM7643 transformers. Figure 23
shows these allowable current magnitudes as a function of
frequency for selected distances. As shown in Figure 23, the
ADuM7640/ ADuM7641/ADuM7642/ADuM7643 are extremely
immune and can be affected only by extremely large currents
operated at high frequency very close to the component. For the
1 MHz example noted previously, a 1.2 kA current would have
to be placed 5 mm away from the ADuM7640/ADuM7641/
ADuM7642/ADuM7643 to affect the operation of the component.
1000
100
10
1
0.1
0.011k 100M
10k
MAXIMUM ALL OWABLE CURRE NT (kA)
100k 1M 10M
MAG NE TIC FI E LD FRE QUENCY ( Hz )
DIS TANCE = 5mm
DIS TANCE = 1m
DIS TANCE = 100mm
10448-023
Figure 23. Maximum Allowable Current for Various
Current-to-ADuM7640/ADuM7641/ADuM7642/ADuM7643 Spacings
Note that at combinations of strong magnetic field and high
frequency, any loops formed by printed circuit board traces can
induce error voltages sufficiently large to trigger the thresholds
of succeeding circuitry. Take care in the layout of such traces to
avoid this possibility.
Data Sheet ADuM7640/ADuM7641/ADuM7642/ADuM7643
Rev. 0 | Page 19 of 20
POWER CONSUMPTION
The supply current at a given channel of the ADuM7640/
ADuM7641/ADuM7642/ADuM7643 isolator is a function of
the supply voltage, the data rate of the channel, and the output
load of the channel.
For each input channel, the supply current is given by
IDDI = IDDI (Q) f ≤ 0.5 fr
IDDI = IDDI (D) × (2f − fr) + IDDI (Q) f > 0.5 fr
For each output channel, the supply current is given by
IDDO = IDDO (Q) f ≤ 0.5 fr
IDDO = (IDDO (D) + (0.5 × 10−3) × CL × VDDO) × (2f − fr) + IDDO (Q)
f > 0.5 fr
where:
IDDI (D), IDDO (D) are the input and output dynamic supply currents
per channel (mA/Mbps).
IDDI (Q), IDDO (Q) are the specified input and output quiescent
supply currents (mA).
f is the input logic signal frequency (MHz); it is half the input
data rate, expressed in units of Mbps.
fr is the input stage refresh rate (Mbps).
CL is the output load capacitance (pF).
VDDO is the output supply voltage (V).
To calculate the total VDD1 and VDD2 supply current, the supply
currents for each input and output channel corresponding to
VDD1 and VDD2 are calculated and totaled. Figure 10 and Figure 11
show per-channel supply currents as a function of data rate for
an unloaded output condition. Figure 12 shows the per-channel
supply current as a function of data rate for a 15 pF output
condition. Figure 13 through Figure 17 show the total VDD1 and
VDD2 supply current as a function of data rate for ADuM7640/
ADuM7641/ADuM7642/ADuM7643 channel configurations.
INSULATION LIFETIME
All insulation structures eventually break down when subjected to
voltage stress over a sufficiently long period. The rate of insulation
degradation depends on the characteristics of the voltage waveform
applied across the insulation. In addition to the testing performed
by the regulatory agencies, Analog Devices carries out an extensive
set of evaluations to determine the lifetime of the insulation
structure within the ADuM7640/ADuM7641/ADuM7642/
ADuM7643 components.
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage. Accel-
eration factors for several operating conditions are determined.
These factors allow calculation of the time to failure at the actual
working voltage. The values shown in Table 18 summarize the peak
voltage for 50 years of service life for a bipolar ac operating
condition and the maximum working voltages. In many cases,
the approved working voltage is higher than the 50-year service life
voltage. Operation at these high working voltages can lead to
shortened insulation life in some cases.
The insulation lifetime of the ADuM7640/ADuM7641/
ADuM7642/ADuM7643 depends on the voltage waveform type
imposed across the isolation barrier. The iCoupler insulation
structure degrades at different rates depending on whether the
waveform is bipolar ac, unipolar ac, or dc. Figure 24, Figure 25,
and Figure 26 illustrate these different isolation voltage
waveforms.
Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime under the bipolar ac condition
determines the Analog Devices recommended maximum
working voltage.
In the case of unipolar ac or dc voltage, the stress on the insulation
is significantly lower. This allows operation at higher working
voltages while still achieving a 50-year service life. The working
voltages listed in Table 18 can be applied while maintaining the
50-year minimum lifetime, provided that the voltage conforms to
either the unipolar ac or dc voltage case. Any cross-insulation
voltage waveform that does not conform to Figure 25 or Figure 26
should be treated as a bipolar ac waveform, and its peak voltage
should be limited to the 50-year lifetime voltage value listed in
Table 18.
The voltage presented in Figure 25 is shown as sinusoidal for
illustration purposes only. It is meant to represent any voltage
waveform varying between 0 V and some limiting value. The
limiting value can be positive or negative, but the voltage cannot
cross 0 V.
0V
RATED P E AK V OL TAG E
10448-024
Figure 24. Bipolar AC Waveform
0V
RATED P E AK V OL TAG E
10448-025
Figure 25. Unipolar AC Waveform
0V
RATED P E AK V OL TAG E
10448-026
Figure 26. DC Waveform
ADuM7640/ADuM7641/ADuM7642/ADuM7643 Data Sheet
Rev. 0 | Page 20 of 20
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-137-AD
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
20 11
101
SEATING
PLANE
0.010 (0.25)
0.004 (0.10)
0.012 (0.30)
0.008 (0.20)
0.025 (0.64)
BSC
0.041 (1.04)
REF
0.010(0.25)
0.006 (0.15)
0.050 (1.27)
0.016 (0.41)
0.020 (0.51)
0.010 (0.25)
8°
0°
COPLANARITY
0.004 (0.10)
0.065 (1.65)
0.049 (1.25) 0.069 (1.75)
0.053 (1.35)
0.345 (8.76)
0.341 (8.66)
0.337 (8.55)
0.158 (4.01)
0.154 (3.91)
0.150 (3.81) 0.244 (6.20)
0.236 (5.99)
0.228 (5.79)
08-19-2008-A
Figure 27. 20-Lead Shrink Small Outline Package [QSOP]
(RQ-20)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model1
Number
of Inputs,
VDD1 Side
Number
of Inputs,
VDD2 Side
Maximum
Data Rate
Maximum
Propagation
Delay, 5 V
Maximum
Pulse Width
Distortion
Temperature
Range
Package
Description
Package
Option
ADuM7640ARQZ 6 0 1 Mbps 20 ns 75 ns −40°C to +105°C 20-Lead QSOP RQ-20
ADuM7640ARQZ-RL7 6 0 1 Mbps 20 ns 75 ns −40°C to +105°C 20-Lead QSOP,
7” Tape and Reel
RQ-20
ADuM7640CRQZ 6 0 25 Mbps 14 ns 50 ns −40°C to +105°C 20-Lead QSOP RQ-20
ADuM7640CRQZ-RL7 6 0 25 Mbps 14 ns 50 ns −40°C to +105°C 20-Lead QSOP,
7” Tape and Reel
RQ-20
ADuM7641ARQZ 5 1 1 Mbps 20 ns 75 ns −40°C to +105°C 20-Lead QSOP RQ-20
ADuM7641ARQZ-RL7 5 1 1 Mbps 20 ns 75 ns −40°C to +105°C 20-Lead QSOP,
7” Tape and Reel
RQ-20
ADuM7641CRQZ 5 1 25 Mbps 14 ns 50 ns −40°C to +105°C 20-Lead QSOP RQ-20
ADuM7641CRQZ-RL7 5 1 25 Mbps 14 ns 50 ns −40°C to +105°C 20-Lead QSOP,
7” Tape and Reel
RQ-20
ADuM7642ARQZ 4 2 1 Mbps 20 ns 75 ns −40°C to +105°C 20-Lead QSOP RQ-20
ADuM7642ARQZ-RL7 4 2 1 Mbps 20 ns 75 ns −40°C to +105°C 20-Lead QSOP,
7” Tape and Reel
RQ-20
ADuM7642CRQZ 4 2 25 Mbps 14 ns 50 ns −40°C to +105°C 20-Lead QSOP RQ-20
ADuM7642CRQZ-RL7 4 2 25 Mbps 14 ns 50 ns −40°C to +105°C 20-Lead QSOP,
7” Tape and Reel
RQ-20
ADuM7643ARQZ 3 3 1 Mbps 20 ns 75 ns −40°C to +105°C 20-Lead QSOP RQ-20
ADuM7643ARQZ-RL7 3 3 1 Mbps 20 ns 75 ns −40°C to +105°C 20-Lead QSOP,
7” Tape and Reel
RQ-20
ADuM7643CRQZ 3 3 25 Mbps 14 ns 50 ns −40°C to +105°C 20-Lead QSOP RQ-20
ADuM7643CRQZ-RL7 3 3 25 Mbps 14 ns 50 ns −40°C to +105°C 20-Lead QSOP,
7” Tape and Reel
RQ-20
1 Z = RoHS Compliant Part.
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D10448-0-9/12(0)
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ADUM7642CRQZ-RL7 ADUM7641ARQZ ADUM7640CRQZ ADUM7641ARQZ-RL7 ADUM7643CRQZ-RL7
ADUM7640ARQZ-RL7 ADUM7642ARQZ ADUM7640CRQZ-RL7 ADUM7641CRQZ ADUM7642ARQZ-RL7
ADUM7643CRQZ ADUM7643ARQZ-RL7 ADUM7643ARQZ ADUM7641CRQZ-RL7 ADUM7642CRQZ
ADUM7640ARQZ EVAL-ADUM7643EBZ