Gennum Fall 2009 Product Guide
•
Broadcast
V
ideo
VCXO
High-End
FPGA
R
e
c
e
i
ve
r
P
r
op
r
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t
a
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y
C
u
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m
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L
og
i
c
T
r
a
n
s
m
i
tt
e
r
D
i
g
i
t
a
l
S
M
P
T
E
p
r
o
c
e
ss
i
ng
Choosing
t
h
e
Right
S
e
r
D
e
s
For Your
S
y
s
te
m
As a designer, you have the choice of
selecting
components from different vendors. But when it comes to designs with serializers
and
deserializers,
you first have to choose an architecture. In implementing a design with a serializer and/or
deserializer,
you have
3 architectural choices at your
disposal: G
e
nn
um
’
s
complete transmitter/receiver solution architecture, an
i
nt
e
g
r
a
t
e
d-
t
r
a
n
scei
v
e
r
FPGA architecture and an FPGA-helper architecture.
L
e
t
’
s
explore these three options with an assessment of the
following
key
p
a
r
a
me
t
e
r
s
:
jitter, power consumption, integration (component/features), time-to-market, system
size
and cost.
Gennum’s
c
o
m
p
l
e
t
e s
o
l
u
t
i
o
n
a
r
c
h
i
t
e
c
t
u
r
e
Leveraging
its expertise in signal integrity and deep understanding of broadcast video technologies,
G
e
nn
um
’
s
offering
encapsulates all the analog components
(SerDes,
VCO, CD, EQ,
Reclocker)
as
well
as the digital
SMPTE
video and audio
processing required to transmit and
receive
SDI video into one optimized,
cost-effective
and power
efficient ASIC i
mp
l
e
me
nt
a
t
i
o
n
that lets you focus on customer value-add processing for quicker time-to-market.
All
of this integration into one package
reduces the system
PCB
footprint required to implement SDI transmit/receive, at no compromise to
G
e
nn
um
’
s
superior
j
i
tt
e
r
performance. Only Gennum
offers
a solution that scores high for each evaluation
p
a
r
a
me
t
e
r
.
Gennum: Complete Solution
Transmitter/Receive
r
SDI
I
npu
t
C
o
m
p
l
e
t
e
E
Q
+
R
e
c
eiver
Low-End
FP
G
A
S
par
t
an
3A,
Cyclone
III
P
r
op
r
i
e
t
a
r
y
C
u
s
t
o
m
e
r
C
o
m
p
l
e
t
e
T
ran
s
mi
tt
er
w
/
C
D
SDI
O
u
t
pu
t
EQ
Receiver
11
E
Q Logic 11
i
n
t
e
G
r
a
t
e
d
-
t
r
a
n
s
c
ei
v
e
r
f
p
G
a
a
r
c
h
i
t
e
c
t
u
r
e
Integrated-transceiver
FPGAs typically offer
the worst
specifications
in terms of jitter. Maximum output jitter and input
j
i
tt
e
r
tolerance (IJT) are
typically
at the limit of the
SMPTE
standards, and, in some
cases, actually
in violation of industry
n
o
r
m
s
.
Th
a
t
is why extra components, namely a
VCXO
and
reclockers,
are required to get the system jitter performance to an acceptable
level,
but at the penalty of higher power consumption, system footprint
size
and cost.
Because
of all the fine tuning required
t
o
g
e
t
this
architecture to work, and because of the IP licensing/development required for the digital
SMPTE
video processing,
t
h
is
architecture unnecessarily prolongs time-to-market.
Finally,
while
FPGAs
integrate transceivers, they do not integrate
r
o
u
t
i
n
g
components like cable drivers and equalizers.
Integrated
Transceiver FPGAs
SDI
I
npu
t
E
Q
R
e
c
lo
c
ker
SDI
O
u
t
pu
t
CD