Programmable Controller CPU 945-7UA1.l-7UA2. Manual This manual has the order number: 6ES5998-3UF21 EWA 4NEB 811 6150-02e Edition 06 Preface lntroduction System Overview Installation Guidelines Testing and Loading the Control Program and Starting Up a System Error Diagnostics Addressing/Address Assignment lntroduction to STEP 5 STEP 5 Operations Interrupt Processing Parameterisation of CPU 945 with DB1 Real-Time Clock Reliability, Availability and Safety of Electronic Control Equipment List of Abbreviations - Index EWA 4NEB 81 l 6150-O2d EWA 4NEB 81 1 61 50-O2d CPU 945 Manual Summary Summary Page Preface ............................................................. xv introduction ................................................................. xvii 1 2 System Overview ........................................................ 1. 1 ..................................................... 1. 1 1.1 Application 1.2 1.2.1 1.2.2 1.2.3 1.2.4 1.2.5 Systemcomponents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... . Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Central Processing Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input and Output Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Intelligent Input/Output Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Communications Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111111- 1.3 1.3.1 1.3.2 Expansion Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Centralized Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Distributed Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 4 l. 5 1. 5 1.4 Communications Systems for the S5-115U 1.5 Operator Control and Monitoring and Programming Technical Description 2 2 3 3 4 4 . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 5 ............... .................................................... .................................................. 1. 6 2. 1 2.1 Modular Design 2.2 Power Supply Modules 2.3 2.3.1 2.3.2 2.3.3 CPU945 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Units o f t h e CPU 945 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features of the CPU 945 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operator Functions of the CPU 945 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Overview o f the CPU 945 Operating Modes 2.5 STOP mode 2.6 2.6.1 2.6.2 Restart Characteristics of the CPU 945 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 16 Cold Restart Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 16 RESTART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 19 EWA 4NEB 81 1 61 50-02d 2- 1 ............................................ 2. 3 ......................... ...................................................... 222. 2. 4 4 8 9 2 . 12 2 . 16 CPU 945 Manual Summary Page 2.7 3 RUN Mode ...................................................... 2 - 22 Program Execution Levels o f the CPU 945 . . . . . . . . . . . . . . . . . . . . . . . . . . Overview o f the Program Execution Levels of the CPU 945 . . . . . . . . . . . Cyclic Program Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Time-Controlled Program Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . Interrupt-Driven Program Processing . . . . . . . . . . . . . . . . . . . . . Timed-Interrupt-Driven Program Processing . . . . . . . . . . . . . . . . . . . . . . . System Error Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Handling Programming Errors and PLC Malfunctions . . . . . . . . . . . . . . . 2 . 23 2 . 23 2 . 25 2 . 28 2 . 30 2 . 34 2 . 35 2 . 37 2.9 2.9.1 2.9.2 2.9.3 2.9.4 2.9.5 Scan times of the CPU 945 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Response Time in the Case of Exclusive~y Cyclic Program Execution . . . Estimating the Scan Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basis for Calculating the Scan Time ................................ Measuring the Scan Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting the Scan Monitoring Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 39 2 .40 2 .42 2 .43 2 - 46 2 .47 2.1 0 Operating System Services in OB250 ............................... 2 . 49 Further CPU 945 Functions in Integral Blocks . . . . . . . . . . . . . . . . . . . . . . . Compressing the Program Memory with FB238 "COMPR" . . . . . . . . . . . Deleting a Block with FB239 "DELETE" . . . . . . . . . . . . . . . . . . . . . . . . . . . . Generating STEP 5 Blocks: OB 125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Variable Time Loop with OB160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Copying Data Area: OB 182 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Duplicating DX or DB Blocks: OB 183 and OB 184 . . . . . . . . . . . . . . . . . . . Transferring Flags t o Data Blocks: OB 190 and OB 192 . . . . . . . . . . . . . . . Transferring Data Blocksto Flag Area: OB 191 and OB 193 . . . . . . . . . . . Extension for Sign: OB 220 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reading the Digital Inputs Into the Process lmage o f the Inputs with 0B254 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sending the Process lmage of the Outputs t o the Digital Outputs with 0 B 2 5 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PID Control Algorithm: OB 251 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 60 2 . 61 2 . 62 2 . 63 2 . 65 2 . 66 2 . 68 2 . 69 2 - 71 2 .76 ................................................... 3. 1 Installation Guidelines 2 . 76 2 .77 2 . 78 3.1 3.1 .1 3.1.2 Mounting Racks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 1 Central Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . 2 Expansion Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 4 3.2 3.2.1 3.2.2 3- 7 Mechanicallnstallation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Installing the Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . 7 Installing Fans . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 10 CPU 945 Manual Summary Page 3.3 3.3.1 3.3.2 3.3.3 Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .............. Centralized Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . Distributed Configurations . . . . . . . . . . . . . . . . . . . . .. Connection Possibilities with Other SlMATlC S5 Systems . . . . . . . . . . . . . 3 . 11 3 . 12 3 . 14 3 . 20 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 WiringtheModules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connecting the PS 951 Power Supply Module . . . . . . . . . . . . . . . . . . . . . . Connecting Digital Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connecting Analog Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Front Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 21 3 . 21 3 . 22 3 . 22 3 - 23 3 - 24 Guidelines for Interference-Free Design of the PLC . . . . . . . . . . . . . . . . . Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Installation with Field Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . Connecting Nonfloating and Floating Modules . . . . . . . . . . . . . . . . . . . . . Running Cables Inside a Cabinet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Running Lines Outside Buildings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Taking Measures Against Interference Voltage . . . . . . . . . . . . . . . . . . . . . Shielding Devices and Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Equipotential Bonding in the Case o f Distributed Configurations .... Special Measures for Interference-Free Operation . . . . . . . . . . . . . . . . . . 3 - 25 3 . 25 3 . 27 3 - 32 3 . 34 3 . 35 3 . 35 3 . 36 3 . 38 3 . 38 3.6 4 Safety Measures and Monitoring Facilities ......................... Testing and Loading the Control Program and Starting Up a System .......... 3 .40 4- 1 ............................... 4- 1 4.1 Prerequisites for Starting Up the PLC 4.2 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 Testing the Control Program ....................................... Testing the Control Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "Program Test" Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STATUSISTATUS VAR Test Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FORCE Outputs and Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Points t o Note When Using the 2nd lnterface as a Programmer Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44444- 1 1 2 3 4 4. 5 4.3 4.3.1 4.3.2 4.3.3 4.3.4 Loading the Control Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 . 5 OverallReset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 5 Transferring the Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 . 7 Activating Software Protection .................................... 4 . 9 Determining the Retentive Feature of Timers, Counters. Flags and S Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 . 10 4.4 Starting the Control Program ...................................... 4 - 11 4.5 4.5.1 4.5.2 4.5.3 4.5.4 System Configuration and Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Notes on Configuring and Installing a System . . . . . . . . . . . . . . . . . . . . . . . Notes on the Use of InputIOutput Modules . . . . . . . . . . . . . . . . . . . . . . . . . System Startup Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Active and Passive Faults in Automation Equipment .................. 4 . 12 4 - 12 4 . 13 4 - 14 4 . 16 vii Summary CPU 945 Manual Page 5 6 7 Error Diagnostics ................... . . . ................................. ............................................. 5. 1 5.1 LED Error Signalling 5.2 5.2.1 5.2.2 Interrupt Analysis with the Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 . 3 "ISTACK" Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 . 3 Meaning o f the ISTACK Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 . 6 5.3 Error Messages When Using Memory Submodules . . . . . . . . . . . . . . . . . . 5.4 5.4.1 5.4.2 ProgramErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 9 Determining the Error Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 . 10 Program Trace with the Block Stack ("BSTACK") Function . . . . . . . . . . . 5 . 11 5.5 Other Causes o f Malfunction 5.6 System Parameters ..................................... .............................................. AddressingIAddress Assignments ......................................... 5- 2 5. 9 5 . 12 5 - 12 6. 1 6.1 6.1 .1 6.1.2 Address Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Module Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Module Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6. 1 6. 1 6. 1 6.2 6.2.1 6.2.2 6.2.3 Slot Address Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fixed Slot Address Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Variable Slot Address Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Addressing in the OArea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6. 6. 6. 6- 6.3 6.3.1 6.3.2 6.3.3 Handling the Process Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accessing the Pll ................................................ Accessing the PlQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DirectAccess . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6- 6.4 Address Allocation on the CPU Introduction t o STEP 5 .................................... 1 2 3 6 7 8 6- 9 6 - 10 6- 6 . 11 ................................................... 7. 1 ..................................... 7. 2 7.1 The Registers o f the CPU 945 7.2 7.2.1 7.2.2 Generating a Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 . 5 Methods of Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 . 6 Operands and Blocks ............................................ 7 . 7 7.3 7.3.1 7.3.2 ProgramStructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Linear Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Structured Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 8 8 8 CPU 945 Manual Summary Page 8 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 Block Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 . l 0 Organization Blocks (OBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 . 11 Program Blocks (PB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 . 13 Sequence Blocks (SBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7.. 13 Function Blocks (FBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 . 43 Data Blocks (DBsIDXs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 . 18 7.5 7.5.1 7.5.2 7.5.3 Processing Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 . 19 Modifying the Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7. -. .20 . Modifying Blocks . . . ., . . . . ,. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 - 20 Compressing t h e Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 20 7.6 Number Representation STEP 5 Operations ........................... . . .. . . . . . . . . . . 7 . 21 ..................................... .................. 8. 1 Basic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 . 1 Boolean Logic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 2 SetIReset Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 . 3 Load and Transfer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 . 4 Timeroperations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 8 Counter Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 . 14 Comparison Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 . 18 Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 . 20 Block Call Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 . 22 Other Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 . 28 Supplementary Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Load Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enable Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Test Operations and Bit Setting Operations . . . . . . . . . . . . . . . . . . . . . . Digital Logic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shift Operations and Rotate Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conversion Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrementllncrement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DisableIEnable Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Processing Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Jumpoperations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Substitution Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 . 29 8 . 29 8 . 30 8 . 31 8 . 33 8 . 36 8 . 41 8 . 45 8 .46 8 . 48 8 - 51 8 . 54 8.3 8.3.1 8.3.2 8.3.3 System Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Load and Transfer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Other Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 . 61 8 . 61 8 . 67 8 . 68 8.4 Condition Code Generation EWA 4NEB 81 1 61 50-02d ....................................... 8 . 69 Summary CPU 945 Manual Page 9 10 Interrupt Processing ................................................... 9. 1 9.1 9.1.1 Programming Interrupt Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Usable Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9. 1 9- 1 9.2 9.2.1 9.2.2 9.2.3 9.2.4 9.2.5 Process Interrupt Generation with the 434-7 Digital Input Module . . . Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization in Restart OBs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reading in the Process Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming Example for interrupt Processing . . . . . . . . . . . . . . . . . . . . 9. 9. 999. 9. Analog Value Processing ................................................ .......................................... 2 2 2 3 4 5 10 . 1 10.1 Analog Input Modules 10.2 10.2.1 10.2.2 Analog Input Module 460-7LA12 ................................ Connecting Transducerstothe 460-7LA12Analog Input Module . . . . Startup of Analog Module 460-7LA12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 460-7LA13 Analog Input Module 10.4 10.4.1 10.4.2 Analog Input Module 465-7LA13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10- 18 Connecting Transducers t o the 465-7LA13 Analog Input Module . . . . 10 . 19 Startup of the 465-7LA13 Analog Input Module . . . . . . . . . . . . . . . . . . . 10 . 23 10.5 10.5.1 10.5.2 463.4UA.J.4UB .. Analog Input Module . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 . 26 Connection of Measuring Transducers t o the 463.4UA.J.4UB .. Analog Input Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 . 27 Startup of the 463.4UA../.4UB .. Analog Input Module . . . . . . . . . . . . . 10- 29 10.6 10.6.1 10.6.2 466-3LA11 Analog Input Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 . 32 Connecting Transducers t o the 466-3LA11 Analog Input Module .... 10- 33 Startup of the 466-3LA11 Analog input Module . . . . . . . . . . . . . . . . . . . 10 . 37 10.7 10.7.1 Representation o f the Digital Input Value . . . . . . . . . . . . . . . . . . . . . . . . Types of Representation of the Digital lnput Value for the 460 and 465 Analog Input Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Types o f Representation of the Digital lnput Value for the 463 Analog Input Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Forms of Representation of the Digital Input Values for the 466 Analog Input Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7.2 10.7.3 ................................ ......... 10- 1 10 . 3 10- 4 10- 12 10 . 15 10- 45 10 . 46 10 . 53 10- 55 10.8 Wirebreak Signal and Sampling for Analog Input Modules 10.9 10.9.1 10.9.2 Analog Output Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 . 61 Connecting Loads t o Analog Output Modules . . . . . . . . . . . . . . . . . . . . . 10- 63 Digital Representation of an Analog Value . . . . . . . . . . . . . . . . . . . . . . . 10 . 65 10- 58 CPU 945 Manual Summary Page 10.10 Analog Value Matching Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.10.1 FB25O-Reading and Scaling Analog Values of the 460 and 465 Analog Input Modules . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 10.10.2 FB241-Readingand Scaling Analog Values of the 463 Analog Input Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.10.3 FB242-Readingand Scaling Analog Values o f the 464-8Mxxx Analog Input Module ................................ 10.10.4 FB243-Readingand Scaling Analog Values o f the 466 Analog Input Module ....................................... 10.10.5 Outputting an Analog Value -FB251- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.10.6 Extended Error Diagnosticsw i t h the Analog Value Matching Blocks ....................................................... 10.11 11 12 10 . 68 10 . 70 10 . 71 10- 72 10- 73 10- 74 ............................. 10- 75 ................................... 11 . 1 Example of Analog Value Processing Parameterization of CPU 945 w i t h DBI 10 . 67 11.1 Configuration and Default Settings for DBI ....................... 11 . 1 11.2 Setting the Addresses for the Parameter Error Code in DBI (An example of how t o set the parameters correctly) . . . . . . . . . . . . . . . 11 . 2 ................................ 11 . 3 .............................. 11 . 4 ................... 11 . 5 11.3 How t o Assign Parameters in DBI 11.4 Rules for Setting Parameters in DBI 11.5 How t o Recognize and Correct Parameter Errors 11.6 Transferring the DB1 Parameterst o the PLC 11.7 Reference Table for Initializing DBI 11.8 DB1 Programming Example Communications Capabilities . . . . . . . . . . . . . . . . . . . . . . . 11 . 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 . 10 ..................................... ............................................ 11 . 15 12 . 1 12.1 Overview o f the Communications Capabilities Offered by the CPU 945 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 . 1 12.2 Data lnterchange over the S5 Backplane Bus o f the Programmable Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Interchange over lnterprocessor Communication Flags . . . . . . . . Data Interchange over the I10 Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Interchange over Data Handling Blocks FB244 t o FB249 . . . . . . . 12.2.1 12.2.2 12.2.3 12.3.1 12.3.2 12.3.3 12 . 5 12 . 5 12 . 12 12 . 12 Connection of the 55-1 15U PLC t o the L1 Bus Cable . . . . . . . . . . . . . . . . 12 .40 Coordinating Data lnterchange by Connecting the CPU 945 t o the SINEC L1 Bus via One of Its Serial Interfaces . . . . . . . . . 12 . 41 Assigning Parameters t o the 55-115U for Data lnterchange via SINECLI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12- 45 EWA 4NEB 81 1 61 50-02d CPU 945 Manual Summary Page 12.4 12.4.1 12.4.2 ASCll Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Traffic via the ASCll Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coordination Bytes of the ASCll Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifying the Type o f Data Traffic by Means of Mode Numbers . . . . ASCll Parameter Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Assigning Parameters t o the ASCll Driver . . . . . . . . . . . . . . . . . . . . . . . . . Program Example for ASCII Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ASCll Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 . 54 12 . 55 12 . 56 12 . 58 12 . 60 12 .63 12 .65 12 . 74 12 . 75 12 .77 12.6.3 12.6.4 12.6.5 12.6.6 Computer Link with 3964(R) Transmission Protocol . . . . . . . . . . . . . . . . 3964(R) Transmission Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Interchange over the S1 2 lnterface with 3964(R) Transmission Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coordination Bytes of the 3964(R) Driver . . . . . . . . . . . . . . . . . . . . . . . . . Parameter Set of the 3964(R) Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Assigning Parameters t o the 3964(R) Driver . . . . . . . . . . . . . . . . . . . . . . . Program Example for Transmitting Data . . . . . . . . . . . . . . . . . . . . . . . . . . 12.7 12.7.1 12.7.2 12.7.3 12.7.4 12.7.5 12.7.5 Interface Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ProgrammerModule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V.24 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TTY Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RS422-Al485-Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SINEC L1 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technical Specifications o f the Interface Modules . . . . . . . . . . . . . . . . . . 12 .97 12-98 12 -103 12-108 12 -1 13 12-117 12 -120 12.6 12.6.1 12.6.2 13 14 Point-To-Point Connection with SINEC L1 Protocol . . . . . . . . . . . . . . . . . 12 . 51 Point-To-Point Connection o f a Communications Partner . . . . . . . . . . . 12 . 51 Parameter Assignment and Operation of the Point-To-Point Connection ...................................... 12 . 51 Real-Time Clock ........................................................ 13 . 1 ................................. 13 . 6 .................................... 13 . l 0 Parameterizing the Real-Time Clock 13.2 Structure of the Clock Data Area 13.3 Structure of the Status Word 13.4 Backup o f the Clock 13.5 Programming the Clock ........................................ 13 . 12 ......................................... 13 . 13 Reliability. Availability and Safety o f Electronic Control Equipment 14.1.3 13- l .............................. 13.1 14.1 14.1 .1 14.1.2 12 . 84 12 . 86 12 . 88 12 . 91 12 . 93 ......... Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Failure Characteristics o f Electronic Devices . . . . . . . . . . . . . . . . . . . . . . . Reliability of SIMATIC S5 Programmable Controllers and Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Failure Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14- 1 14- 1 14 . 2 14- 2 14- 3 1 Summary CPU 945 Manual Page 15 .................................................... 14.2 Availability 44- 4 14.3 14.3.1 14.3.2 .. . . . . . . . . . . . . . . . . . . . . . . . . . 14- 5 Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . TypesofFailures ............................................... 14- 5 Safety Measures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14- 6 14.4 Summary .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14- Technical Specifications 15.1 ................................................. 15 . 1 ................................. 15 . 1 Description o f Modules ......................................... Mounting Racks (CRs. ERs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Central Processing Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Input Modules .......................................... Digital Output Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Input/Output Module .................................... Analog Input Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Output Modules ........................................ Signal Preprocessing Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Communications Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interface Modules .............................................. The 313 Watchdog Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 . 5 15 . 5 15 . 10 15 . 15 15 . 16 15 . 26 15 . 39 15 . 40 15 . 45 15 . 51 15 . 52 15 . 53 15 . 55 General Technical Specifications 15.3 7 Accessories .................................................... 15 . 56 Appendices A Dimension Drawings .................................................... A ....................................... A- 1 .............................. A- 2 ....................... A- 3 A.l Dimensions of the Modules A.2 Dimension Drawings o f the Subracks A.3 Dimension Drawings for Cabinet Installation EWA 4NEB 81 1 61 50-02d 1 Xiii CPU 945 Manual Summary Page B C Maintenance xiv ................................................ B.l Changing Fuses B.2 B.2.1 B.2.2 B.2.3 Installing or Changing Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Removing the Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Installing the Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Battery Disposal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.3 Changing t h e Fan Filter B.4 Replacing the Fan Motor B- 1 B. 1 B. B. B. B. 1 2 2 3 ........................................... B. 3 ......................................... B. 4 Guidelines f o r Handling Electrostatic Sensitive Devices (ESD) List o f Abbreviations Index ....................... .................................. ................ C. 1 CPU 945 Manual Preface Preface The 55-115U is a programmable controller for the lower and mid performance ranges. It meets all the demands made o f a modern programmable controller. The performance capability of the 55-115U has been subject t o constant enhancement. You now have at your disposal the most powerful CPU for the 55-115U in the shape of the CPU 945. To make optimum use of the CPU 945 in the S5-115U, you require a certain amount of detailed information. This manual presents all this information in an organized manner. A proforma for corrections and improvement suggestions is included at the end o f the manual. You can use these t o help us improve the next edition. Important differences between the CPU 945 and the CPUs 941 t o 944 New CPU architecture Extremely fast operation execution times Expanded STEP 5 operation set Floating-point arithmetic 32-bit accumulators and expanded register set Larger address area Additional flag area Additional system data area Improved execution level system Additional organization blocks Additional integral FBs for analog value processing Integral OB 250 for invoking and parameterizing operating system services Additional blocks (FX, DX) New memory submodules Various interface modules can be used as a 2nd interface Expanded DB 1 -Parameterization o f ASCll driver -Parameterization o f computer interface You require a PG 7xx programmer with 55-DOS from Stage V6.1 for programming the CPU 945. Compatibility of the CPU 945 w i t h the CPUs 941 t o 944 Programs written for the CPUs 941 t o 944 must be adapted in the following cases: If waiting times have been implemented over operation run time loops or If the programs contain absolute address accesses Please also note that Assembler blocks cannot execute on the CPU 945 For programs containing data handling block calls (SEND, RECEIVE) in quick succession, additional wait times must be programmed for slow communications partners, such as the CP 524 and CP 525. For these reasons, new standard function blocks are required when using most intelligent I10 modules and some CPs. Preface CPU 945 Manual You require operating system services for the CPU 945 for assigning some operating system parameters. These are the operating system services for: Interrupt response after timeout (OB6) Time-controlled program processing (OB10 t o 13) Manipulation of the process l10 image transfer Regeneration o f the block address l i s t Generating a data block (DBIDX) without TRAF I10 accesses and page accesses without QVZ Disabling and enabling the output modules (setting and resetting BASP) FBs 240 t o 243, which were previously integrated in the CPUs 941 t o 944 are no longer required in the CPU 945 due t o the larger operation set. They have been replaced by the following additional FBs for analog value processing: FB241 Reading in analog value from the 463 analog input module FB242 Reading in analog value from the 464 analog input module FB243 Reading in analog value from the 466 analog input module Modification t o parameterization of FB2501251: Analog values represented in floating-point format Account is taken o f the P, 0, IM3 and IM4 peripheral areas Changes i n the n e w manual compared t o the manual for the CPUs 941 t o 944 The 460-7LA13 and 463-4UA13 analog input modules have been included in the chapter on "Analog Value Processing". From CPU 945 firmware version Z 02 This manual describes the CPU 945 from firmware version Z 02. From firmware version Z 02, the CPU 945 has the following new functions: Organization Blocks o f the CPU 945 for Special Functions Copying Data Area: OB 182 Duplicating DX or DB Blocks: OB 183 and OB 184 Transferring Flags t o Data Blocks: OB 190 and OB 192 Transferring Data Blocks t o Flag Area: OB 191 and OB 193 Extension for Sign: OB 220 PID Control Algorithm: OB 251 New Operating System Services of the OB 250 - Access t o DBS and DBL Registers - Indexed Access t o DX lFX - Cancelling a Block in the Block Address List - Changing the Block Identifier Generating STEP 5 Blocks: OB 125 Not all problemsthat might occur in the many and varied applications can be handled in detail in a manual. If you have a problem that is not discussed in the manual, contact your nearest SIEMENS office or representative. EWA 4NEB 81 1 61 50-02d CPU 945 Manual Introduction Introduction The following pages contain information t o help you familiarize yourself with the manual. Description of contents The contents of the manual can be broken down subject-wise into a number of blocks: Description (System overview, technical description) Installation and operation (Installation guidelines, program test and startup, fault diagnostics, addressing) Programming instructions (Introduction t o STEP 5, STEP 5 operations) Special capabilities (Interrupt processing, analog value processing, parameterizing the CPU with DBI, communications) Technical specifications overview You will find additional information in tabular form in the appendices. A pocket guide for the STEP 5 operation set of the CPU 945 i s t an integral part of the manual. Please use the forms at the back o f the manual for any suggestions or corrections you may have and return the forms t o us. This will help us t o make the necessary improvements in the next edition. Training courses Siemens offer comprehensive training facilities for users of SIMATIC 55. Details can be obtained from your nearest Siemens office or representative. Reference literature The manual contains a comprehensive description of the S5-115U. Subjects that are not specially related t o the 55-11 5U have only been treated in brief, however. More detailed information is available in the following literature: Programmable controls Volume 1: Logic and sequence controls; from the control problem t o the control program Gunter Wellenreuther, Dieter Zastrow Brunswick l987 Contents: Theory of operation o f a programmable control system - Theory o f logic control technology using the STEP 5 programming language for SIMATIC S5 programmable controllers. - Order No.: ISBN 3-528-04464-0 EWA 4NEB 81 1 61 50-02d Introduction CPU 945 Manual Automating with the 55-115U SIMATIC S5 Programmable Controllers Hans Berger Siemens AG, Berlin and Munich 1989 Contents: STEP 5 programming language Program scanning Integral software blocks I10 interfaces - Order No.: ISBN 3-89578-022-7 Information on the programmable controller hardware is t o be found in the following catalogues: ST 52.3 ST 57 ST 59 ET 1.1 MP 11 "55-1 15U Programmable Controller" "Standard Function Blocks and Driver Software for Programmable Controllers of theURangeW "Programmers" "ES 902 C Modular 19 in. Packaging System" "Thermocouples; compensating boxes" The relevant manuals are available for other components and modules (e.g. CPs and SINEC LI). Reference is made t o these sources of information at various points in the manual. The 55-115U programmable controller is designed t o VDE 0160. The corresponding IEC and VDE (Association of German Electrical Engineers) standards are referred t o in the text. Conventions Structure of the manual In order t o improve readability o f the manual, a menu-styled breakdown was used, i.e.: The individual chapters can be quickly located by means o f a thumb register. There is an overview containing the headings o f the individual chapters at the beginning of the manual. Each chapter is preceeded by a breakdown t o i t s subject matter. The individual chapters are subdivided into sections. Boldface type is used for further subdivisions. Figures and tables are numbered separately in each chapter. The page following the chapter breakdown contains a list of the figures and tables appearing in that particular chapter. EWA 4NEB 81 1 61 50-O2d CPU 945 Manual Introduction Certain conventions were observed when writing t h e manual. These are explained below. m m l m m m m A number o f abbreviations have been used. Example: Programmer (PG) Footnotes are identified by superscripts consisting o f a small digit (e.g. "1 ") or "*". The actual footnote is generally at the bottom left o f t h e page or below the relevant table or figure. Lists are indicated by a black d o t (m), as i n this l i s t for example, o r w i t h a dash (-). Instructions f o r operator actions are indicated by black triangles 0 ) . Cross references are shown as follows: "(+Section 7.3.2)" refers t o Section 7.3.2. No references are made t o individual pages. All dimensions i n drawings etc. are given i n millimetres followed by inches i n brackets. Example: 187 (7.29). Values may b e represented as binary, decimal or hexadecimal numbers. The hexadecimal number system is indicated w i t h a subscript (example FOOOH) Information o f special importance is enclosed in black-edged boxes: /1\ Warning See t h e "Safety-Related Guidelines" f o r definitions o f the terms "Warning", "Danger", "Caution" and "Note". Manuals can only describe t h e current version o f t h e programmer. Should modifications or supplements become necessary in t h e course o f time, a supplement will be prepared and included in the manual t h e next time it is revised. Introduction 55-1 15UCPU 945 Manual Safety-Related Guidelines for the User This document provides the information required for the intended use of the particular product. The documentation is written for technically qualified personnel. Qualified personnel as referred t o in the safety guidelines in this document as well as on the product itself are defined as follows. System planning and design engineers who are familiar with the safety concepts of automation equipment. m Operating personnel who have been trained t o work with automation equipment and are conversant with the contents of the document in as far as it is connected with the actual operation o f the plant. Commissioning and service personnel who are trained t o repair such automation equipment and who are authorized t o energize, de-energize, clear, ground, and tag circuits, equipment, and systems in accordance with established safety practice. Danger Notices The notices and guidelines that follow are intended t o ensure personal safety, as well as protect the products and connected equipment against damage. The safety notices and warnings for protection against loss of life (the users or service personnel) or for protection against damage t o property are highlighted in this document by the terms and pictograms defined here. The terms used in this document and marked on the equipment itself have the following significance. m Danger indicates that death, severe personal injury or substantial property damage will result if proper precautions are not taken. Ezl Warning indicates that death, severe personal injury or substantial property damage result if proper precautions are not taken. U Caution indicates that minor personal injury or property damage can result if proper precautions are not taken. contains important information about the product, i t s operation or a part of the document t o which special attention is drawn. Proper Usage /i\ Warning The equipmentlsystem or the system components may only be used for the applications described in the catalog or the technical description, and only in combination w i t h the equipment, components, and devices of other manufacturers as far as this is recommended or permitted by Siemens. The product will function correctly and safely only if it is transported, stored, set up, and installed as intended, and operated and maintained with care. EWA 4NEB 81 1 61 50-02d 1.2 1.2.1 1.2.2 1.2.3 1.2.4 1.2.5 System Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Central Processing Units . . . . . . . . . . . . . . . . . . . . . . ...... . . ...... lnputand Output Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Intelligent InputIOutput Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Communications Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 1 1 1 1 1.3 1.3.1 1.3.2 Expansion Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Centralized Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Distributed Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 . 4 1 . 5 1 . 5 1.4 Communications Systems for the 55-1 15U 1.5 Operator Control and Monitoring and Programming EWA 4NEB 81 1 61 50-02d . . . . . . 2 2 3 3 4 4 ...................... 1 . 5 ............ 1 . 6 1.1 55-115U Components . . .. .... .. . . . . . . . . . ... .. .. . ... . . . . . . . . . . . .. . . . . 1 - 2 EWA 4NEB 81 1 61 50-O2d CPU 945 Manual System Overview System Overview The SIMATICm55-1 15U programmable controller is used worldwide in almost all fields in a wide range of applications. Each of i t s modular components handles a specific task. Therefore, you can expand the system according t o your needs. The most powerful 55-115U configuration is implemented with the CPU 945. The 55-115U system provides operator panels, monitoring devices, and various programmers t o suit your needs. The STEP 5 programming language and an extensive software catalog make programming easy. 1.l Application Many different industries use the 55-1 15U. Even though each automation task is different, the 55-115U adapts optimally t o the most varied jobs, whether they involve simple open-loop control or complex closed-loop control. Present areas o f application include the following: Automobile lndustry Automatic drill, assembly and test equipment, painting facilities, shock absorber test bays Plastics Industry Blow, injection, and thermal molding machines, synthetics production systems Heavy lndustry Molding equipment, industrial furnaces, rolling mills, automatic p i t shaft temperature control systems Chemical lndustry Proportioning and mixing systems Food and Beverages Industry Brewery systems, centrifuges Machinery Packing, woodworking, and custom-made machines, machine controls, machine tools, drilling mills, fault alarm centers, welding technology Building Services Elevator technology, climate control, ventilation, lighting Transport Systems Transport and sorting equipment, high-bay warehouses, conveyor and crane systems Energy, Gas, Water, Air Pressure booster stations, standby power supply, pump control, water and air treatment, filtering and gas recovery systems EWA 4NEB 81 1 61 50-O2d System Overview 1.2 CPU 945 Manual System Components The 55-115U system is made up o f various modular components, as pictured in Figure 1-1. These components include the following: Power supply module (PS) Central processing unit (CPU) Input and output modules (110s) Intelligent inputloutput modules (IPs, WFs) Communications processors (CPs) Figure 7-1 55-1 75U Components 1.2.1 Power Supply The power supply module (PS) converts the external power supply t o the internal operating voltage. Supply voltages for the 55-115U include 24 V DC, 115 VAC, and 230 VAC. Screw-type terminals connect the power supply lines t o the bottom of the PS. Three maximum output currents are available. Choose 3 A, 7 A, or 15 A according t o the number o f modules you have or according t o their power consumption. A fan is not necessary for output currents up t o 7 A. CPU 945 Manual System Overview A lithium battery backs up the program memory and the internal retentive flags, timers and counters in the event of a power failure. An LED signals battery failure. If you change the battery when the power is shut off, connect a back-up voltage from an outside source t o the sockets provided for this purpose on the power supply module. 1.2.2 Central Processing Units The central processing unit (CPU) is the "brain" of the programmable controller. It executes the control program. As well as the CPU 945, the most powerful o f the CPUs, you can also use the following four CPUs in the 55-115U: CPU 941, CPU 942, CPU 943, CPU 944. These CPUs offer a varied performance range and are described in a separate manual (Order No.: 6ES5 998-OUF.3). The CPU 945 allows you t o implement the fastest execution times of your control programs. The CPU 945 has the largest STEP 5 operation set and the largest program memory. A new feature o f the CPU 945 is i t s ability t o implement FUZZY control (see Catalog ST 57). The new FUZZY control block replaces the OB251 (PID control algorithm) integrated in the CPUs 941 t o 944. 1.2.3 lnput and Output Modules lnput and output modules are the interfaces t o the sensors and actuators of a machine or controlled system. The following features make 55-1 15U modules easyto handle: Fast installation Mechanical coding Large labeling areas Digital Modules Digital modules conform t o the voltage and current levels of your machine. You do not have t o adapt the existing level t o the programmable controller. The 55-115U adapts itself t o your machine. Digital modules have the following convenient features: connection o f signal lines via front connectors a choice o f screw-type or crimp snap-in connections Analog Modules As a programmable controller's degree of performance increases, so does the significance o f i t s analog value processing. The significance o f the analog input and output modules increases accordingly. Analog modules handle mainly closed-loop control tasks, such as automatic level, temperature, or speed control. EWA 4 N E B 81 1 61 50-O2d System Overview CPU 945 Manual The 55-115U offers floating and non-floating analog input modules. They use one range card for every four channels t o adapt the desired signal level. This feature allows you t o do the following: Have up t o four different measuring ranges on one module, depending on the number of channels a module has Change the measuring ranges simply by exchanging range cards Three analog output modules cover the various voltage or current ranges of analog actuators. 1.2.4 Intelligent InputIOutput Modules Counting rapid pulse trains, detecting and processing position increments, measuring time and speed, closed-loop control, and positioning are just a few of many time-critical jobs. The central processor of a programmable controller usually cannot execute such jobs fast enough in addition t o i t s actual control task. The 55-115U provides intelligent inputloutput modules (IPs) t o handle these time-critical jobs. Use these modules t o handle measuring, closed-loop control, and openloop control tasks rapidly in parallel t o the program. Most o f the modules have their own processor t o handle tasks independently. All these modules have a high processing speed and are easy t o handle. Standard software puts them into operation. 1.2.5 Communications Processors The 55-1 15U offers a number o f special communications processors (CPs) t o make communication easier between man and machine or machine and machine. These are divided into the following three main groups: CPs for bus systems (e.g. CP 530,143,5430) CPsfor linking, reporting and listing (e.g. CP 523, 524, 525) Operator control and monitoring (e.g. 526,527,528,552) 1.3 Expansion Capability If the connection capability of one central controller (CC) is no longer sufficient for your machine or system, increase the capacity with expansion units (EUs). Interface modules connect a CC t o EUs and connect EUs t o each other. Choose an interface module suitable t o the controller configuration you need. EWA 4NEB 81 1 61 50-02d CPU 945 Manual 1.3.1 System Overview Centralized Configuration A centralized configuration allows you t o connect up t o three expansion units t o one CC. The interface modules for this purpose connect bus lines and supply voltage t o the expansion units. The expansion units in such configurations therefore need no power supplies of their own. The cables between the individual controllers have a total maximum length of 2.5 m (8.2 ft.). 1.3.2 Distributed Configuration A distributed configuration allows you t o relocate expansion units nearer t o the sensors and actuators o f your machine. Distributed configurations reduce cabling costs for these devices. 1.4 Communications Systems for the S5-115U Controller flexibility is critical t o manufacturing productivity. Complex control tasks can be divided and distributed over several controllers t o achieve the greatest flexibility possible. Distribution offers the following advantages: Small units that are easier t o manage. You can plan, start up, diagnose, modify, and operate your system more easily, and observe the entire process more easily Enhanced system availability because, if one unit fails, the rest of the system continues t o function Information must flow between distributed controllers t o ensure the following: Data exchange between programmable controllers Central monitoring, operation, and control of manufacturing systems Collection o f management information such as production and warehousing data For this reason, we offer the following communications facilities for the 55-115U programmable controller: Point-to-point connection with the CP 524 and CP 525 communications processors Local area network communications via the SINEC L1 network SINEC H1 SlNEC L2 Point-to-point connection with the CPUs 943,944 and 945 ASCII interface for connecting printer, keyboard, etc. in the case of the CPU 943,944 and 945 Computer connection with 396413964R protocol in the case of the CPU 944 and CPU 945 The CPU 945 provides a wide variety of communications possibilities thanks t o different interface modules which can be connected t o 512. System Overview 1.5 CPU 945 Manual Operator Control and Monitoring and Programming SIMATIC offers you a range o f operator control and monitoring devices graded according t o price and performance. These devices provide you w i t h a user-friendly means o f selectively following and, i f necessary, intervening i n processes. There is a meaningfully graded and compatible range o f programmers available: PG710 PG730 PG750 PG770 All t h e programmers feature high performance, simple handling, user-friendly operator prompting, and t h e standard, easily learned STEP 5 programming language. ....................................... 2.2 Power Supply Modules 2.3 2.3.1 2.3.2 2.3.3 CPU945 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Units o f t h e CPU 945 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features o f t h e CPU 945 . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . Operator Functions o f t h e CPU 945 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 4 2 . 4 2 . 8 2 . 9 2.4 Overview o f t h e CPU 945 Operating Modes . . . . . . . . . . . . . . . . . . . . . 2 .12 2.5 STOP mode 2.6 2.6.1 2.6.2 2 .16 Restart Characteristics o f t h e CPU 945 . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 16 Cold Restart Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RESTART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 .19 2.7 RUN M o d e 2.8 2.8.1 2.8.2 2.8.3 2.8.4 2.8.5 2.8.6 2.8.7 Program Execution Levels o f t h e CPU 945 . . . . . . . . . . . . . . . . . . . . . . Overview o f t h e Program Execution Levels o f t h e CPU 945 . . . . . . . Cyclic Program Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Time-ControlledProgramExecution ........................... Interrupt-Driven Program Processing . . . . . . . . . . . . . . . . . . . . . . . . . . Timed-Interrupt-DrivenProgramProcessing . . . . . . . . . . . . . . . . . . . . System Error Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Handling Programming Errors and PLC Malfunctions . . . . . . . . . . . . 2 2 2 2 2 2 2 2 .23 .23 .25 -28 .30 -34 .35 .37 2.9 2.9.1 2.9.2 2.9.3 2.9.4 2.9.5 Scan times o f t h e CPU 945 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Response Time i n t h e Case o f Exclusively Cyclic Program Execution Estimating t h e Scan Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basis f o r Calculating t h e Scan Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . Measuring t h e Scan Time ..................................... Setting t h e Scan Monitoring Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 2 2 2 2 .39 .40 .42 .43 .46 .47 2.10 Operating System Services in OB250 2.1 1 2.1 1.1 2.1 1.2 2.1 1.3 2.1 1.4 2.1 1.5 2.11.6 2.1 1.7 Further CPU 945 Functions i n Integral Blocks . . . . . . . . . . . . . . . . . . . . Compressing t h e Program Memory w i t h FB238 "COMPR" . . . . . . . . Deleting a B l o c k w i t h FB239 "DELETE" . . . . . . . . . . . . . . . . . . . . . . . . . Generating STEP 5 Blocks: OB 125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Variable Time Loop w i t h OB160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Copying Data Area: OB 182 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Duplicating D X o r DB Blocks: OB 183 and OB 184 . . . . . . . . . . . . . . . Transferring Flags t o Data Blocks: OB 190 and OB 192 . . . . . . . . . . . ................................................. .................................................. ........................... 2 . 3 2 . 16 2 .22 2 .49 2 .60 2 .61 2 .62 2 .63 2 .65 2 .66 2 .68 2 .69 2.1 1.9 Extension for Sign: OB 220 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 1. l 0 Reading the Digital Inputs Into the Process Image . . ... . . .. .... . of the Inputs with OB254 . . . . . . . . . . . . . . . . . . . . . 2.1 1.1 1 Sending the Process Image of the Outputs to the Digital Outputs with 0B255 . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 2 - 76 2 - 76 2 - 77 EWA 4NEB 81 1 61 50-02d 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.1 0 2.1 1 2.1 2 2.1 3 2.14 2.1 5 2.1 6 2.17 2.1 8 2.19 2.20 2.21 2.22 2.23 2.24 Schematicof the 55-115U . . . . . . . . . . . . . . . . . . . . . .... .. . . . . . . . . . . . . . . . . Schematicofthe CPU 945 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Front View o f t h e CPU 945 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Panel o f t h e Different CPUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Restart Characteristics o f the CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conditions f o r Changing the Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . Cold Restart Characteristics After Power Restore . . . . . . . . . . . . . . . . . . . . . . . Data Flow i n the Case o f Process I10 Image Transfer . . . . . . . . . . . . . . . . . . . . Sequential and Parallel Transfer o f t h e Process I10 Image . . . . . . . . . . . . . . . Program for Interrupt OB (Principle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Response Time i n the Case o f Sequential Process 110 Image Transfer . . . . . Response Time i n the Case o f Parallel Process I10 Image Transfer . . . . . . . . Breakdown o f the Scan Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Response Times i n t h e Case o f Parallel and Sequential Process I10 Image Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . Assignment o f t h e ACCUs when Inputting and . Outputting Operating System Service Parameters . . . . . . . . . . . . . . . . . . . . . Byte-By-Byte (OB 190) and Word-By-Word (OB 192) Transfer . . . . . . . . . . . . Byte-By-Byte (OB 191) and Word-By-Word (OB 193) Transfer . . . . . . . . . . . . Saving Flag Areas when Changing the Program Execution Level . . . . . . . . . Exchanging High-Order Byte and Low-Order Byte i n a DB Using OB 193/0B190 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram o f t h e PID Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Estimating t h e Dominant System Time Constant (TRKdom). . . . . . . . . . . . . . . Process Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EWA 4NEB 81 1 61 50-02d 2 2 2 2 2 2 2 2 2 2 2 2 2 . 4 . 7 . 9 . 10 .13 . 14 .15 .25 .26 .32 .40 .41 .42 2 .45 2 2 2 2 .49 .70 .72 .74 2 2 2 2 .75 .78 .84 .85 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.1 0 2.1 1 2.1 2 2.1 3 2.14 2.1 5 2.1 6 2.17 2.1 8 2.1 9 2.20 2.21 2.22 2.23 2.24 2.25 2.26 2.27 2.28 2.29 2.30 2.31 2.32 Features o f t h e CPU 945 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . ...... . . . . . . . Operating Mode LEDs ................... . System Data Area; List o f All Addressable I10 Words (DI= Digital Input Byte. DQ= Digital Output Byte. AI =Analog Input Byte. AQ=Analog Output Byte) . . . . . . . . . . . . . . . . . . . . . Program Execution Levels of the CPU 945 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parameter Block for Timed-Interrupt OBs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............. ... . Additional Response Times . . . . . . . . . . . . . . . . . . . . . . . . Errors Handled in OB33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Errors Handled in OB35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Breakdown o f the Scan Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ready Delays of the Different I10 Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating System Service for Activating OB6 .......................... Operating System Services for Time-Controlled Program Execution . . . . . . Operating System Services for Changing the Process 110 Image Transfer . . Operating System Services for Generating a DBIDX Without TRAF . . . . . . . Operating System Services for Regenerating the Block Address List . . . . . . Operating System Services for I f 0 Accesses and Page Accesses Without QV2 Operating System Service for Disabling Digital Outputs . . . . . . . . . . . . . . . . . Operating System Services for Access t o DBS and DBL Registers . . . . . . . . . . Operating System Utilities for Indexed Access t o DX .................... Operating System Utilities for Indexed Access t o FX . . . . . . . . . . . . . . . . . . . . . Operating System Services for Cancelling a Block in the Block Address List Operating System Services for Changing Block Identifiers . . . . . . . . . . . . . . . FB238 Flags ......................................................... Error Bits Set by FB239 (ERR Parameter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Permissible Types and Numbers o f Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Condition Codes o f OB 125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Condition Codes of the OB 125 in ACCU 1-LL . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Identifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Possible Errors ...................................................... Description of the Control Bits in Control Word STEU ................... Possible Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Format o f the Controller DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 8 2 . 11 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 . 18 .24 .29 .33 .36 .36 .43 .44 .50 . 50 .51 .52 . 52 .53 . 54 .55 .56 .56 .57 .58 .61 .62 .63 .64 .65 .67 .68 .80 .82 .82 CPU 945 Manual 2 Technical Description Technical Description This chapter describes the design of an 55-115U with the CPU 945, giving an overview of the following: The modular design o f the PLC The power supply modules The features of the CPU 945 and i t s various operating modes Ways in which you can influence the scan time of your PLC The new operating system services o f the CPU 945 Further functions provided by the CPU 945 over integral blocks. 2.1 Modular Design The 55-1 15U consists of various functional units that can be combined t o suit the particular problem. Figure 2- I The 55-1 15U PLC with the CPU 945 (Central Controller) The numbered information below briefly describes the most important components of the 55-1 15U. O Power Supply Module (PS 951) The PS951 power supply module generates the operating voltage for the PLC from the 115 V A C l 2 3 0 V A C or 2 4 V DC power system voltages. This module uses a battery or an external power supply t o back up the RAM. The PS 951 power supply module also performs monitoring and signalling functions. Technical Description CPU 945 Manual O Central Processing Unit (CPU) The central processing unit reads in input signal states, processes the control program, and controls outputs. In addition t o program scanning functions, the CPU provides internal flags, timers and counters. You can preset the restart procedure and diagnose errors using the CPU's LEDs. Use the Overall Reset switch on the CPU t o delete the RAM contents. Use a programmer or a memorysubmodule t o transfer the control program t o the CPU. O Communications Processors (CP) Communications processors can be used in the 55-115U for communication between man and machine and between machines. Communications processors perform the following functions: Operator monitoring and control of machine functions or process sequences Reporting and listing of machine and process states You can connect various peripheral devices t o these processors, e.g. printers, keyboards, CRTs and monitors as well as other controllers and computers. C9 Input/Output Modules (110s) Digital input modules adapt digital signals, e.g. from pressure switches or BERO@proximity switches, t o the internal signal level of the 55-115U. Digital output modules convert the internal signal level of the 55-115U into digital process signals, e.g. for relays or solenoid valves. Analog input modules adapt analog process signals, e.g. from transducers or resistance thermometers, t o the 55-115U, which functions digitally. Analog output modules convert internal digital values of the 55-115U t o analog process signals, e.g. for speed controllers. C3 lnterface Modules (IM) The 55-115U is installed on mounting racks with a specific number o f mounting locations (slots). A configuration comprising power supply, CPU, and inputloutput modules is called a central controller. If the slots on the central controller's mounting rack are insufficient, you can install expansion units (systems without CPUs) on additional mounting racks. lnterface modules connect an expansion unit t o a central controller. C 3 Mounting Racks A mounting rack consists o f an aluminium rail t o which all the modules are fastened mechanically. It has one or t w o backplanes that connect the modules t o each other electrically. Not represented in Figure 1-1: Intelligent InputIOutput Modules (IPs) Intelligent inputloutput modules are available for handling the following special tasks: Counting rapid pulse trains Measuring and processing positioning increments Measuring speed and time Controlling temperatures and drives, and so on. lntelligent inputloutput modules generally have their own processor and thus off-load the CPU. Consequently, they can process measuring and open- and closed-loop control tasks quickly while the CPU handles other jobs. EWA 4NEB 81 1 61 50-02d CPU 945 Manual Technical Description Power Supply Modules 2.2 Power supply modules generate the operational voltages for the PLC from t h e 1201230 V AC or 24 V DC mains supply and they provide backup for the RAM w i t h a battery or an external power supply. Power supply modules also execute monitoring and signalling functions. You can set t h e following switches o n t h e PS 951 power supply module: The Voltage Selector switch sets t h e line voltage a t either 120 VAC or 230VAC for AC modules. The PS 951 can also be operated w i t h a 24 V DC power supply. The ONIOFF switch turns the operating voltages on or off. The RESET switch acknowledges a battery failure indication. O Battery compartment O Sockets f o r external 3, 4 t o 9 V DC f o r backup (when battery is changed and power supply is shut off) C 3 Battery failure indicator The LED lights up under the following conditions: There is no battery. The battery has been installed incorrectly. The battery voltage has dropped below 2.8 V. If t h e LED lights up, t h e "BAU" signal is sent t o the CPU. 0 0 C9 RESET switch Use this switch t o acknowledge a battery failure signal after you have installed a new battery. If you are operating t h e PS 951 power supply module without a battery, activate this switch t o suppress the "BAU" signal. 0 C9 0 O Operating voltage displays 24V DC INT DC ,, < ) g-j I +5 V + 5.2 V 0 I 0 VOLTAGE SE LECTOR +24 V 0 N 8e supply voltage for t h e inputloutput modules supply voltage for PG 605U or PG 61 5, OPs, BT777 bus terminal f o r serial interface (20 m A current loop interface). O ONIOFF switch (I=ON, O=OFF) When t h e switch is in t h e "OFF" position, t h e operat i n g voltages are disabled w i t h o u t interrupting t h e connected line voltage. 120123ov O 120 V ACl230 V A C voltage selector switch w i t h transparent cover 0 Screw-type terminals f o r connecting t h e line voltage Figure 2-2 Power Supply Module Control Panel Technical Description 2.3 CPU 945 Manual CPU 945 This chapter describes the CPU 945. The following are the most important differences between t h e CPU 945 and the CPUs 941 t o 944: New CPU architecture Extremely fast operation execution times Expanded STEP 5 operation set; e.g. floating-point arithmetic 32-bit accumulators and expanded register set Larger program memory Expanded address area; 0 area Additional flag area (S flags) Additional system data area (RT), which is n o t deleted a t Overall Reset Improved program execution on the different program execution levels Call interval o f t h e timer OBs (l ms) Additional organization blocks (OBs) Firmware update onsite using programmer or memorysubmodule New memory submodules 2nd interface i n the form o f an interface module 2.3.1 Functional Units of the CPU 945 rlmlllLllmll 1 CPU 945 I I I I I I I Timers, I counters, I flags I 1 Internal program memory (RAM) - I I I ' I I Memory submodule (Flash EPROM) Serial interface I Processor I interface module Lmm---- l Figure 2-3 Schematic of the 55- 115U EWA 4NEB 81 1 61 50-02d CPU 945 Manual Technical Description Program memory (internal program memory, memory submodule) The control program can be stored on a memory submodule or i t is stored by the programmer in RAM. The CPU 945 always copies the entire control program from the memory submodule into internal program memory (RAM) from where it is processed. As security against powerfails, the control program is also stored on the flash EPROM external t o the PLC. The internal RAM has the following characteristics in contrast t o the external flash EPROM : The memory contents can be changed quickly. User data can be stored and changed. If memory contents are t o be retained on powerfail, the RAM must be provided with battery backup. Note: The memory submodule may be plugged in and removed in the POWER OFF state only! Process Images (PII, PIQ) Signal states o f the digital input and output modules are stored in the CPU in "process images." Process images are reserved areas in CPU RAM. Input and output modules have separate images as follows: Process input image (PII) and Process output image (PIQ) Interfaces The CPU 945 is equipped with the following: A serial interface A slot for interface modules You can connect the following t o serial interface 1 A programmer An OP 393 operator panel The SINEC L1 local area network There are various interface modules available for different connections: Programmer interface module (1 5-pin) TTY interface module (25-pin) RS 232C (V.24) interface module (25-pin) RS 422-AI485 interface module (15-pin) SINEC L1 interface module (15-pin) CPU 945 Manual Technical Description Timers, Counters and Flags Each CPU provides the control program with internal timers, counters and flags. Flags are memory locations for storing signal states. Timers, counters and flags can each be set as "retentive'yby area), i.e. their contents are not lost at POWER OFF. Memory areas whose contents are reset at POWER OFF are "non-retentive". Processor The processor calls statements in the program memory in sequence and executes them in accordance w i t h the control program. I t processes the information from the PII and takes into consideration the values of internal timers and counters as well as the signal states of internal flags. The processor contains the accumulators (shortened t o "ACCUs") and further registers. The ACCUs are arithmetic registers, over which the values of, for example, the internal timers and counters are loaded. In addition, comparison operations, arithmetic operations and conversion operations are executed in the ACCUs. The CPU 945 also provides a range o f additional registers, e.g. the BR (basic address register) and DBS (data block start register) (see Section 7.1). I10 Bus The I10 bus establishes the electrical connection for all signals that are exchanged between the CPU and the other modules in a central controller or an expansion unit. Memory submodules Memory submodules (flash EPROMs) are available for storing the control program or for transferring programs t o the PLC. These memory submodules are SIMATIC S5 memory cards with a capacity o f 128,256 and 512 Kbytes. * ** 128 Kbytes 6ES5 374-1FG11 Byte 256 Kbytes 6ES5 374-1FHI 1 Byte 512 Kbytes* 6ES5 374-1FJ21 WOrd 128 Kbytes 6ES5 374-1KG11** Byte 256 Kbytes 6ES5 374-1KH21** WOrd 512 Kbytes 6ES5 374-1KJI 1** Byte 1 MB 6ES5 374-1KK21** WOrd Only 256/384 Kbytes can be used Programmer Software level 6.6 and higher 500 500 CPU 945 Manual Technical Description Overview of the CPU 945 The CPU 945 has a new CPU architecture compared t o the CPUs 941 t o 944. The CPU 945 contains the following: A STEP 5 processor (SP 90) A floating-point coprocessor (CP 90) 0 A bus controller (AMBUS) A microcontroller (Motorola 68302) The new CPU architecture results in the following advantages: Coprocessor execution o f STEP 5 operations with SP 90 and CP 90 Control program less burdened by communications thanks t o internal multiprocessor architecture. The operating system is located on a flash EPROM. This makes it possible t o update the operating system onsite using a programmer or via the memory submodule. The microcontroller manages all functions implemented over both serial interfaces. This includes all programmer functions and SINEC L1 connection at serial interface 1. Various interface modules can be plugged in t o constitute interface 2 (see Section 12.7). The bus controller controls data interchange between the individual processors and the S5 bus. The CPU has an internal RAM from which the control program can be executed. The control program is always copied from the memorysubmodule into internal RAM. iI Control side 1i OperaSTEP 5 processor panel floating-point coprocessor bus A A A Ak v v v i controller I Flash EPROM submodule Motorola 68302 I e.g. SINEC L1 RAM microcon- Serial Programmer Clock f) interface EPROM I - i i i Interface module I I Communication side Figure 2-4 Schematic of the CPU 945 EWA 4NEB 81 1 61 50-O2d Operating system flash i bus Technical Description CPU 945 Manual 2.3.2 Features of the CPU 945 The f o l l o w i n g t a b l e shows t h e most important features o f t h e CPU 945. Table 2-1 Features of t h e CPU 945 approx. l00 y s see Pocket Guide for Address range, max. (digital inputs, analog inputs) P area 256 bytes 0 t o 127 i n process I10 image 128 t o 255 w i t h o u t process l10 image 0 area 256 bytes IM 3 area 256 bytes IM 4 area 256 bytes Flags 2048 bits, optionally all retentive half retentive all non-retentive S flags 32768 bits, optionally all retentive half retentive all non-retentive 256 bits, optionally all retentive T 0 t o 63 retentive all non-retentive 256 bits, optionally all retentive C 0 t o 63 retentive all non-retentive Timers Counters Time range Counting range Operation set 0.01 t o 9990 s 0 t o 999 Approx. 250 operations CPU 945 Manual Technical Description 2.3.3 Operator Functions of the CPU 945 The following operator functions are possible on the front panel of the CPUs: Plug in a memory submodule Connect a programmer (PG) or an operator panel (OP) Connect SlNEC L1 Connect PLCs or devices o f other manufacture - Connection with ASCll driver - Point-to-point connection (master function) - Computer interface (3964(R) procedure) Set the operating mode Preset retentive feature Perform Overall Reset 0 LEDs indicate the current CPU status. View of CPU 945 O C9 O O Receptacle for memory submodule Control panel Slot for interface module (see Section 12.7) Connection sockets for PG, OP or SINEC L1 LAN Figure 2-5 Front View of the CPU 945 Technical Description CPU 945 Manual The CPU controls are arranged i n a panel. Figure 2-8 shows the control panel o f t h e different CPUs. STOP 0 RUN 0 STOP Qvz c3 ZYK BASP 0 NR RE 0R O Mode selector STOPIRUN O O 0 RUNLED @ STOP LED C3 P P P P Error LEDs (QVZ, ZYK) BASP (output disable); outputs o f t h e output modules are n o t enabled Switch f o r t h e following RESTART settings: nonretentive presetting (NR) retentive presetting (RE) overall reset (OR) - Figure 2-6 Control Panel of the Different CPUs CPU 945 Manual Technical Description Meaning of the LEDs Two LEDs on t h e control panel o f the CPU indicate the operating status o f the CPU (G3 and O in Figure 2-8). Table 2-3 lists the possible indications. Aflashing or flickering red LED indicates PLC malfunctions (see Chapter 5). Table 2-2 Operating Mode LEDs CPU is in cold restart routine or in RESTART mode STOP mode RUN mode - Program check running or CPU is i n RESET - Overall Reset active \I/ -0- /I\ Request Overall Reset Flashing -\ *I //l\ Flickering Hardware fault Technical Description 2.4 CPU 945 Manual Overview of the CPU 945 Operating Modes Use the mode selectorto set t h e STOP (ST) or RUN (RN) mode. Everything t h a t takes place between m a STOP-, RUN transition (manual cold restart) m a POWER UP+ RUN transition (automatic cold restart after power up) or m a POWER UP+ STOP transition is referred t o as "restart characteristics". Two phases can be distinguished during restart: The cold restart routine (PLC cannot be directly influenced) The RESTART control program (PLC characteristics can be controlled in RESTART OBs (OB21 and OB22)). The following figure gives a clear breakdown o f the restart characteristics o f t h e CPU and cyclic operation (see Section 2.7). Figure 2-8 shows the possible causes o f operating status change. Figure 2-9 shows h o w restart characteristics depend o n t h e following m The status o f t h e backup battery Errors The operating status before POWER OFF and The position o f t h e mode selector. CPU 945 Manual Technical Description Mode selector STOP + RUN PG command RUN Power restoration 1 * + CPU selftest v Process 110 image (PI1 and PIQ) is deleted; Non-retentive timers, counters and flags are deleted; Stored start events for timer OBs, interrupts OBs and system error OBs are deleted; Digital outputs are overwritten with Process I10 image (PI1 and PIQ) is deleted; Non-retentive timers, counters and flags are deleted; Stored start events for timer and interrupt OBs are deleted; Digital outputs are overwritten with "0"; "0"; Configuration o f I10 modules is determined and stored; Address l i s t for the control program is constructed; DB 1 is interpreted (see Chapter 1 l ) S5 timers enabled Cold restart routine is delayed (delay time in SD 126); Configuration o f I10 modules is determined and stored; Control program is copied from memory submodule into interval program memory; Address l i s t for the control program is constructed; DBI is interpreted (see Chapter 11) S5 timers enabled In addition, the battery, memory submodule and status before POWER OFF are evaluated (see Figure 2-9) 4 4 Processing of OB21 * Processing o f OB22 * I I I Outputs enabled (BASP signal revoked) PI1 read in + + Processing of OB1 PIQ output I 1 * If the PLC was in RUN at POWER OFF. If 0821 or 0822 containsthe RA(enable interrupt) 0peration.a central process interrupt is possiblefrorn this point. If this operation has not been used in the RESTART 00, interrupt and timed-interrupt 00s can only become effective after the RESTART OB has been processed. Figure 2-7 Restart Characteristics of the CPU EWA 4NEB 81 1 61 50-02d Technical Description CPU 945 Manual Changing the Operating Mode - - After power restoration 4 The mode selector is set from STOP t o RUN RUN is selected o n a programmer 'Oldroutine restart - - C_ If PLC was a t RUN or RESTART before power restore - 1- ( RUN I f PLC was a t STOP before power restore The control program is destroyed (e.g. RAM is erased after battery fails) The ma~ d selece t o r is set from RUN t o STOP Causes of interrupts (see Chapter 5) The mode selector is set from RUN t o STOP Causesof interrupts (see Chapter 5) The restart block is processed 1 Figure 2-8 Conditions for Changing the Operating Mode - The mode selector is set from RUN t o STOP STOP is selected o n a programmer Causes of interrupts (see Chapter 5) CPU 945 Manual Technical Description Cold restart characteristics after power restore The following figure shows the cold restart characteristics after power restore depending on battery status, possible faults, the status before POWER OFF and the mode selector. 7 I Power ON CPU selftest Program storage No Cold restart routine Cold restart routine* Yes STOP RUN RUN RESTART RESTART J. RUN * v v STOP RUN Restart delay set t o default of approx. 1 second Figure 2-9 Cold Restart CharacteristicsAfter Power Restore v STOP Technical Description 2.5 CPU 945 Manual STOPMode BASP (command output disable) is active The control program is not executed The process 110 image and the interprocessor communication flags are not processed The values o f timers, counters, flags and process 110 images current at the point of transition t o STOP are retained S5 timers are not processed Interrupts are not stored 2.6 Restart Characteristics of the CPU 945 Everything that takes place between a STOP* RUN transition (manual cold restart) a POWER UP+ RUN transition (automatic cold restart after power up) or a POWER UP+ STOP transition is referred t o as "restart characteristics". Two phases can be distinguished during restart: The cold restart routine (PLC cannot be directly influenced) The RESTART control program in which PLC characteristics can be controlled in restart OBs (OB21 and OB22). 2.6.1 Cold Restart Routine The following takes place during the cold restart routine The "BASP" LED lights up and the "BASP" signal is active - Error flags are deleted in the case of manual cold restart - All fault LEDs light up briefly in the case o f automatic cold restart after power restore The control program is copied from the memory submodule into internal program memory (RAM) (not in the case of STOP + RUN) The address l i s t o f the blocks is re-constructed The start events stored for timer, interrupt and system error OBs are deleted Non-retentive timers, counters, flags and S flags are deleted Digital outputs take signal "0"if all output modules are disabled All inputs and outputs take signal "0"in the process I/O image Scan time monitoring is inactive DBI is interpreted The configuration of 110 modules is determined and stored. This procedure is described on the next page. EWA 4NEB 81 1 61 50-O2d CPU 945 Manual Technical Description To establish t h e configuration o f the I10 modules, t h e control processor checks the f u l l address area o f t h e inputloutput modules word by word. If it addresses a module over an I10 byte, the processor "notes" this byte by setting a b i t allocated t o it i n a special memory area called t h e system data area. This b i t is only set by the processor i f both l10 bytes o f an I10 word are addressable. The processor uses one system data word (RS) t o check 16 110 bytes. Using this method, t h e processor determines t h e bytes o f the process I10 image t o be updated during process I10 image transfer. Table 2-3 lists all relevant system data words i n the system data area. If, f o r instance, l10 byte 13 canberead,bit5issetinsystemdataword(RS)128; canbewrittento,bit5issetinsystemdata~ord(RS)136; EWA 4NEB 81 1 61 50-O2d Technical Description CPU 945 Manual Table 2-3 System Data Area; List of All Addressable 110 Words (DI= Digital lnput Byte, DQ= Digital Output Byte, Ai=Analog lnput Byte, AQ=Analog Output Byte) Note These bits are flag bits, i.e. manipulation o f these bits by the control program has no effect on update o f the process I10 image. Changes t o the determined module configuration affecting updating o f the process I10 image can only be made over operating system service No. 6 (see Section 2.1 0). EWA 4 N E B 81 1 61 50-02d CPU 945 Manual 2.6.2 Technical Description RESTART While t h e CPU is in RESTART, the following applies: The fault LEDs are dark; the RUN, STOP and BASP LEDs light up All output modules are disabled (outputs show signal "0") The PI1 is n o t yet updated; evaluation o f t h e inputs is only possible w i t h direct I10 access (L PY../L PW..) L PW o Example: T IW 0 A I 0.0 Scan time monitoring is inactive The relevant RESTART OB is processed (in the case o f manual cold restart o f OB21, in the case o f automatic cold restart o f OB22 - if t h e mode selector is a t RUN) Timers are processed Interrupt OBs (OB2 t o OB6) and timed-interrupt OBs (OB10 t o OB13) are only processed if the interrupts are explicitly enabled (RA operation). RESTART program execution During RESTART, i.e. after a STOP+ RUN transition (manual cold restart) and after a POWER OFF += POWER UP transition (automatic cold restart after power restore i f t h e CPU was previously in t h e RUN mode), t h e CPU operating system automatically invokes a RESTART OB, provided one has been programmed: OB2l (in t h e case o f manual cold restart) or OB22 (in t h e case o f automatic cold restart after power restore i f the CPU was previously in RUN). If you have programmed these blocks, this program w i l l be executed before cyclic program execution; this makes it suitable for, e.g. (one-off) setting o f specific system data or carrying o u t parameterization f o r t h e process t o b e automated. If the relevant RESTART OB has n o t been programmed, t h e CPU branches direct t o RUN (cyclic program execution, OB 1). A t this point, w e have an example o f h o w a RESTART OB can be programmed. Technical Description CPU 945 Manual Example l: Programming OB 22 A check is t o be made after power restore t o ensure that all input/output modules are ready for operation. If one or more modules cannot be accessed (not plugged in or faulty), the PLC must branch t o STOP. ...................................................................................................................... ....................................... .................... ..... G:.::::::::::::::::::.jiiii....... ...:.:.:.:.:::...:.:.:.:.:.::::::::::::;C:;=: :.:.:.:...................m.y.-'.............. ............ ::::::::::::.::::::::::::::1;:~j~;~222;~:;:;~@&~~&@&~~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . :........................... . . . . . . . . ::::............................ j;:;:;::::;~E:;~222;;2~~2<2222;;j;;;;jj$2~2;~$;;;j;jj;jjg;2;;;2~22;;;;;: C ........ :L KBO :T PW jC~~:g~~JgIjjj$:j:i:i:;:~zjjjl22;2jijj<:::::2:j:;:~;:;:~8j:Zjf:;2j~:jlJ2222ji2;jj;E 3;:i::::::i:jsm~~jiiiJjjjlJIIjjJ;;j~~~m~~IIjjIIjjjjjjjjIIIIIIIIjjjjjjjjj~jj~jjjjjlIIliJ;jj;jljj~;jgg~~~ijggg~~g~ggI;;~;~;~j~;IIIj~~IIIIIl;i;j;i;i;i;j;i;~ $ ~ ~ ; ~ r i j i i g j j j j j j :.:.:.:.: ; j ~........................................................ ~ ~ ~ ~ # ~ f & ~ & ~ f I : ~ @.................... $ i i :.i:.:.i:.:.:;.:.:$., ........... ;~~;~$$;iii;i;i;i;i;ii p :.: - Output words 0, 2 and 4 are set to " 0 " 0 :T PW 2 :T PW 4 :L PW 6 The information in input words 6 , 8 and 10 is :L PW 8 loaded consecutively into ACClJ 1. :L PW 10 :BE If an input or output module cannot be accessed with the statement L PW or T PW, the CPU enters STOP at this statement and the QV2 (timeout) interrupt bit is set in the ISTACK (see Chapter 5 ) i f OB23 has not been programmed t o respond t o a QVZ (see Section 2.8.7). CPU 945 Manual Technical Description Example 2: Programming OB 21 and FB 1 After cold restart using t h e mode selector, flag bytes 0 t o 99 are t o b e preset w i t h " O M , flag bytes 100 t o 127 are t o b e retained since they contain important machine data. Retentive switch a t retentive position (RE). Prerequisite: Flag word 2 0 0 is preset with " O M :L KBO :T FW L KBO :B FW FW 200 current flag word. :T 0 T h e current flag word is set to " 0 " :L FW 200 :I 2 :T FW 200 L KF +l00 :J C =M10 T h e value " 0 " 200 is stored in ACCU 1 The contents of FW 2 0 0 specify the T h e contents of FW 2 0 0 are incremented by 2 . T h e comparison value " 1 0 0 " is loaded into ACCU 1 As long as contents of FW 2 0 0 < 1 0 0 , I jump to marker 1 0 . The bytes FY 0 to 99 are set to " 0 " . I I Technical Description CPU 945 Manual Programmable Restart Delay a t Cold Restart and After Power Restore If you want t o delay checking t h e module configuration because, for example, switching t h e voltage t o a remotely connected expansion unit is delayed, you must modify system data w o r d 126 (E IOFC,) i n one o f the following ways: With t h e "Display memory contents" programmer function (only permissible when the CPU is in t h e STOP mode!) W i t h STEP 5 operations i n the control program (only i n FBs). In any event, t h e restart delay w i l l only become effective after t h e next POWER OFF + POWER ON transition and remains effective until t h e next modification t o this system data word. After Overall Reset, t h e default applies (OOOO,, i.e. no delay). One unit in system data w o r d 126 corresponds t o a restart delay o f 1 ms; t h e longest possible delay is 65535 ms (FFFF,). Programming a restart delay o f approximately one minute Example: : L K H EA60 :T RS 1 2 6 : BE Restart d e l a y of 6 0 , 0 0 0 rns (1 m i n u t e ) Note If no backup battery has been inserted i n t h e power supply module (or if the inserted battery is defective) and t h e control program is stored on a flash EPROM submodule, t h e restart w i l l be delayed by approximately one second. 2.7 RUN Mode After t h e CPU operating system has run the restart program, it starts cyclic program execution (see Section 2.8.2). Cyclic program execution means t h e following: The process I10 image and t h e interprocessor communication flags are processed cyclically (see Section 2.8.2) The control program is processed cyclically (OBI) (see Section 2.8.2) The time-controlled, interrupt-driven and timed-interrupt-driven program execution levels and t h e system fault level are enabled f o r processing. In addition, scan t i m e monitoring is active (see Section 2.9.5). EWA 4NEB 81 1 61 50-02d CPU 945 Manual Technical Description 2.8 Program Execution Levels of the CPU 945 2.8.1 Overview of the Program Execution Levels of the CPU 945 In RUN mode, wedistinguish between 5 types o f program execution: Cyclic program execution Time-controlled program execution Interrupt-driven program execution Timed-interrupt-driven program execution System error handling Programs are executed on different program execution levels. The program execution levels are invoked by the operating system over organization blocks (OBs). The various program execution levels have different priorities for program processing. The interrupt characteristics o f each program execution level depend on the priority o f t h a t level. It is a basic rule o f interrupt behaviour that: A higher-priority level can interrupt a lower-priority level after every STEP 5 statement. You must note t h e following w i t h regard t o interrupts: The operations DO DWIDO F W a n d t h e next operation count as one operation. The operations TNBITNW cannot be interrupted. There are restrictions as t o t h e STEP 5 statements after which integral blocks can be interrupted. If a level is interrupted by a higher-priority level, program execution is continued a t the interrupt point after t h e higher-priority level has been executed. The following table gives an overview o f t h e various program execution levels and their interrupt characteristics. EWA 4NEB 81 1 61 50-02d CPU 945 Manual Technical Description Table 2-4 Program Execution Levels o f the CPU 945 Cyclic level OB1 The cyclic level can be interrupted by all time levels all interrupt levels the timed-interrupt level the system error level The cyclic level cannot interrupt any other level Time level 3 Time level 2 Time level 1 Time level 0 OBlO OBl l OB12 OB13 A t i m e level can be interrupted by a higher-priority time level all interrupt levels the timed-interrupt level the system error level A time level can interrupt t h e following the cyclic level - i n the control program - i n the operating system lower-priority time levels Interr. level D Interr. level C Interr. level B Interr. level A A n interrupt level can be interrupted by a higher-priority interrupt level t h e timed-interrupt level t h e system error level An interrupt level can interrupt t h e following the cyclic level - i n the control program - i n t h e operating system all time levels lower-priority interrupt levels Timedinterrupt level The timed-interrupt level can only be interrupted by t h e system error level The timed-interrupt level can interrupt t h e following t h e cyclic level - i n the control program - i n t h e operating system all time levels all interrupt levels System error level - Scan time monitoring - Collision o f t w o timed interrupts - IIOerror The system error level cannot be interrupted by any other level and cannot even interrupt itself. The system error level can interrupt all other levels. CPU 945 Manual 2.8.2 Technical Description Cyclic Program Execution After the operating system of the CPU has run the restart program, i t starts cyclic program execution. The maximum duration o f the cyclic program is defined by the scan monitoring time (see Section 2.9.5). Cyclic program execution means the following O Scanning the input signals at the input modules and representing them in the PI1 O Updating the input interprocessor communication flags (see Section 12.2.1) O Excuting OBl (running the control program; results are written into the PIQ or, e.g. stored in flags or DBs) O Transferring data from the PIQ t o the output modules O Transferring output interprocessor communication flags t o the CPs. Transfer of the process I10 image In contrast t o the CPUs 941 t o 944, process I10 image is transferred in t w o steps in the CPU 945: The bus controller (AMBUS) updates the PII' in accordance with the determined module configuration. The control processor fetches the updated PII' from the bus controller and transfers it into the PI1 for further processing. Output of the process I10 image t o the digital output modules is executed in the same t w o steps. Figure 2-10 shows the t w o steps o f process I10 image transfer. Note Unused inputs (I x.y, IB X, IW X, ID X) cannot be used as additional flag areas since they are overwritten with " 0 " every time the process input image is transferred (I' transfer). Control processor Bus controller (AMBUS) S5 backplane bus Digital I10 PI1 PIQ I' I Q' configuration Figure 2-10 Data Flow in the Case of Process I/O Image Transfer Technical Description CPU 945 Manual There are t w o different types of process 110 image transfer: Sequential Parallel There are t w o methods of setting the type o f process I10 image transfer: In DBI with the PPlT parameter (see Chapter 11) With system data bit 120 (E IOFO,); parallel transfer o f the process I10 image is set by setting bit No. 7 = " 1 " . Sequential process I10 image transfer In sequential process I10 image transfer, the PI1 is transferred before the control program. The new signal states resulting from the control program are transferred from the PIQ t o the output modules. All sequential process I10 image transfer times are accommodated fully in the scan time (see Figure 2-1 1). Parallel transfer o f the process I10 image Here, the process I10 image is transferred in t w o independent procedures (see Figure 2-11) A t the beginning and end o f the control program between the control processor and the bus controller Parallel t o the control program between the bus controller and the 110. Sequential transfer of the process I10 image Parallel transfer o f the process I10 image Control processor m ., --- I I ,rTI,,1 1X-lp-l Bus controller AMBUS Reading the digital input modules into the PI1 of the bus controller Legend: I ... I' ... Transfer o f the PI1from the bus controller into the PI1 of the control processor IPCl ... Reading in the interprocessor communication flags B ... Control program Q' ... Transferof thePIQ from the control processor into the PIQ of the bus controller Q ... Output of the PIQ from the bus controller t o the digital output modules IPCQ ... Outputting the interprocessor communication flags SCP... Scan control point Figure 2-1 l Seguentialand Parallel Transfer of the Process I/O Image EWA 4 N E B 81 1 61 50-O2d CPU 945 Manual Technical Description Reducing PIQ transfer The CPU 945 offers the possibility o f executing PIQ transfer in a reduced form. For this purpose there is a memory area for the digital outputs in addition t o the memory area containing the determined module configuration (see Section 2.6.1). This additional memory area contains the output bytes which have changed in the current scan compared t o the previous scan. If the reduced PIQ transfer is active, only those output bytes which have actually changed are transferred t o the output modules. Failure of an output module is not detected during reduced PIQ transfer if the modules output bytes only change infrequently. To prevent this, ail available output bytes mut be output after a specific number o f scans. You can program the number of scans with reduced PIQ transfer as follows: With the DBI RPlC parameter (Reduced Process Image Output Counter) (see Chapter 11) or With operating system service No. 7 "Reduction o f PIQ transfer" (see Section 2.10). The programmed number of scans with reduced PIQ transfer is followed by one scan with a complete PIQ transfer. The RPlC parameter can be set in the range 1 t o 255. If a default value of RPlC = 0 is set, reduced PIQ transfer is switched off, i.e. a complete PIQ transfer takes place after each scan. Note Defective modules are only detected after one or several scans, since usually not all connected output modules are addressed within one scan. Scope for fast responses t o signal changes Even during cyclic program execution there is scope for fast responses t o signal changes by, for example programming organization blocks for interrupt processing and using interrupt modules using operations with direct I f 0 access (e.g. L PW, T PY) multiple programming o f direct I10 scans in the control program. CPU 945 Manual Technical Description 2.8.3 Time-Controlled Program Execution OBs 10 t o 13 are available for time-controlled program execution. The time OBs are called by the operating system at fixed intervals. You can set the call intervals for the time OBs in different ways: In DBI (see Chapter 11) Over the operating system services in 08250 (see Section 2.10). The call interval can be set in the range from 1 ms t o 1 min (range 0 t o FFFFH; see Table 2-5). You can also change the call interval using the operating system services. A call interval o f 100 ms is the default for OB13. Time OBs interrupt the cyclic program after each STEP5 operation. Time OBs cannot interrupt the following: Higher-priority time OBs OB6 Process interrupts (OB2 t o OB5) The system error OBs 26,33,35 Time OBs can be interrupted by the following: A higher-priority time OBs OB6 Process interrupts (OB2 t o OB5) System error OBs. The order o f priority for the time OBs is as follows: Highest priority: Lowest priority: OB13 OB12 OBl l OB10. Please note also: You can disable invocation o f all time OBs with the "IA" operation. You can then enable invocation o f all time OBs agian with the "RA" operation. You can use the "SIM" operation t o disable one or several time OBs (see section 8.2.8). Disabling invocation o f time OBs is needed if integral handling blocks are used in the cyclic and time-controlled program and if they access the same page number in doing so. The interrupts must be disabled and then re-enabled before every invocation o f an integral data handling block in the lower-priority program. CPU 945 Manual Technical Description During an interrupt disable or while a time OB is executing, one call request per time OB is stored. I f a second call request occurs f o r the same time OB, the CPU signals "collision o f t w o timed interrupts". If time OBs are t o be processed in the RESTART OB (OB21,OB22), you must enable interrupts i n t h e RESTART OB w i t h "RA". The block nesting level o f 50 levels applies also when processing a time-controlled OB and must n o t be exceeded. If a time-controlled OB uses "scratch flags" which are also being used i n t h e cyclic control program or in a lower-priority time-controlled program, these flags must be saved i n a data block during processing o f t h e timed-interrupt OB. Invocation o f the timed-interrupt OBs can be delayed in the following cases (see Table 2-6) If integral blocks are used If t h e clock has been parameterized I f programmer1OP functions are active If SlNEC L1 is connected I f t h e computer interface or ASCII driver are active I f t h e S5 bus is accessed direct by the [P 252 If higher-priority execution levels are active or if interrupts are disabled - The values in system data words RS 97 t o RS 100 are only flags f o r t h e set intervals. Changing system data words RS 97 t o RS 100 does n o t effect any change i n t h e call intervals. The call intervals can only be changed over operating system services No. 2 t o 5 (see Section 2.1 0). t Table 2-5 Parameter Block for T i m e d - l n t e r r u ~OBs RS 97 E 10C2 Interval for OB13 (0 t o FFFFH) 100(=100ms) 5 RS 98 E 10C4 Interval for OB12 (0 t o FFFFH) 0 ( = n o call) 4 RS 99 E 10C6 Interval for OB11 (0 t o FFFFH) 0 (=no call) 3 RS l 0 0 E 10C8 Interval for OB10 (0 t o FFFFH) 0 (=no call) 2 Example Setting an interval f o r 1 s f o r OB13 w i t h operating system service No. 5 S e t OB13 i n t e r v a l :L KF+1000 Load i n t e r v a l ( 1 S) :L KB5 Load o p e r a t i n g s y s t e m s e r v i c e f u n c t i o n number : J U OB 2 5 0 f o r OB13 Call operating system service :BE EWA 4NEB 81 1 61 50-02d CPU 945 Manual Technical Description 2.8.4 Interrupt-Driven Program Processing OBs 2 t o 5 are invoked automatically by the operating system if a (process) interrupt (interrupt A, B, C or D) occurs. Programming interrupt blocks You can use interrupt-initiating modules in the 55-115U (e.g. intelligent I10 modules, the 434-7 digitial input module or the 485-7 digital inputloutput module (see Chapter 9)). These modules activate the CPU over an interrupt line in the I10 bus (S5 backplane bus). The CPU distinguishes between A, B, C or D interrupts depending on which interrupt line has been activated. Each o f these interrupts causes the operating system of the CPU t o interrupt the cyclic or timecontrolled program and t o call an interrupt OB: OB2 in the case of interrupt A (interrupt A is triggered by the 434-7 DI module (see Chapter g), 485-7 DIJDQ, by some CPs or by IPs) OB3 in the case o f interrupt B (interrupt B is triggered by some CPs or by IPs) OB4 in the case of interrupt C (interrupt C is triggered by some CPs or by IPs) OB5 in the case of interrupt D (interrupt D is triggered by some CPs or by IPs) What interrupts what and where? The following execution levels can be interrupted The cyclic program (OBI) The time-controlled program A lower-priority interrupt The priority o f the interrupts is set as follows: Highest priority: Lowest priority: Interrupt A lnterrupt B lnterrupt C Interrupt D The timed-interrupt level (OB6) and the system error level (OB33, 35, 36) have higher priority and cannot be interrupted. Lower-priority program levels can be interrupted after each operation. Integral function blocks and operating system routines can only be interrupted at predefined locations (cannot be changed!). If you have not programmed an interrupt OB, the interrupted program will be continued immediately a t t h e point of interruption. If a second interrupt request (edge) occurs during processing of the same interrupt OB, the request can be stored. One request can be stored for every interrupt line. CPU 945 Manual Example: Technical Description An interrupt B and, shortly afterwards, an interrupt A occur while the CPU is processing OB2. After the CPU has processed OB2, it re-invokes OB2 (with interrupt A), and only then does it invoke OB3. If another interrupt A (OB2) occurs during processing of OB3, OB3 is immediately interrupted in order t o process OB2. Processing of OB3 is continued after OB2 has been processed. If any section o f your cyclic or time-controlled program is not t o be interrupted, you must protect this section from interruption using the "IA" (disable interrupt) operation. A t the end of the "protected" section, interrupts must be enabled again using the "RA" operation. During interrupt disable, one interrupt per interrupt line can be stored! You can also disable each interrupt level individually using the "SIM" operation if the interrupts are not disabled by the " IA" operation (see Section 8.2.8). Disabling interrupts is necessary in the following cases: If you are using integral data handling blocks both in the cyclicltime-controlled program and in the interrupt program If the data handling blocks access the same page number. You must disable the interrupts before every integral data handling block call in the cyclic porogram, time-controlled program and in a lower-priority program! A CAUTION Many standard function blocks for IPs cancel the interrupt disable because they operate with the IAand RA operations! If you use these standard function blocks during restart or in an "interrupt-protected" program section, the relevant interrupt OBs may be invoked inadvertantly! Enabling interrupts in the restart program (OB21.OB22) If you want interrupt responses already at restart, you must enable the interrupts at the beginning of the restart OB w i t h the "RA" operation (not possible with the 434-7 digital input module and the 485-7 digital inputloutput module). Otherwise, the interrupts will only come into effect after the restart OB has been processed. Notes on avoiding programming errors Note that the block nesting depth of 32 levels must not be exceeded even when calling interrupt OBs! If you use the same flags in the interrupt service routine as in the cyclic program, you must save the contents o f these flags at the beginning of the interrupt service routine (e.g. in a data block); at the end o f an interrupt service routine, transfer the saved contents of the flags back t o the relevant flag bytes (words). EWA 4NEB 81 1 61 50-02d CPU 945 Manual Technical Description Example of interrupt OB (OB2,OB3,OB4,OB5) Save flag contents Identify interrupt-initiating module or interrupt initiating channel, acknowledge interrupt lnterrupt response J. l Transfer saved flag contents back Figure 2-12 Program for interrupt OB (Principle) Calculating interrupt response times The total response time is the sum of the following: Signal delay o f the interrupt-initiating module (=time from interrupt-initiating input signal change until activation of the interrupt line) lnterrupt response time o f the CPU Execution time of the interrupt program (=sum o f all STEP 5 operations in the interruptevaluating program). Calculate the interrupt response time o f the CPU as follows: lnterrupt response time of the CPU = basic response time processing time o f a higher-priority program execution level + additional response times The basic response time is 23 t o 85 p s . Additional response times result from: Integral FBs The parameterized clock ProgrammerIOP functions Activated computer interface (3964(R) procedure) or activated ASCII driver SINEC L1 S5 bus accesses (worst case ready delays see Table 2-10 ) Direct S5 bus access by IP 252 See Table 2-6 for the additional response times which can vary. + CPU 945 Manual Technical Description Table 2-6 Additional Response Times Operating system services (OB250) OB250 cannot be interrupted; additional response time corresponds t o execution time o f OB250, see Pocket Guide Direct S5 bus access via IP 252 0.32 ms OP functions 1 0 . 1 ms Programmer functions a t one interface FORCE VARISTATUS VAR Status BlockITransfer Block Display address Compress block w i t h programmer or FB COMPR - i f no blocks are being shifted - if blocks are being shifted * ** 10.2 ms 1 0 . 2 ms 5 0 . 2 ms 1 3 . 3 ms ms 2 ms per 1K statement o f t h e block t o b e shifted 1 3.3 + Cf. "Programmer functions, compress block" for F8238 (COMPR) Are primarily relevant if TNBITNWare used to access the I10 area (see the Pocket Guide for the execution times of TNBITNW). These operations cannot be interrupted. Technical Description 2.8.5 CPU 945 Manual Timed-Interrupt-Driven Program Processing OB6 is called by the operating system when the time started by operating system service no. 1 (see Section 2.10) has run (provided interrupts are not disabled bythe "IA" or "SIM" operations). In OB6, you program the response after the set time has run (timed interrupt). 7 Note A running clock prompt can be "restarted" by invoking operating system service no. 1 "Activation o f OB6" again. The operating system then restarts the clock prompt specified by operating system service no. 1. A running clock prompt can be stopped by transferring the value " 0 " t o the operating system service (prevents invocation of OB6!). After the clock prompt has been started, system data word 101 (E 10CAH) contains the selected time. When the programmed time has run, the operating system enters the value "0" in system data word 101 and calls OB6. The following applies for OB6: To start the clock prompt, you must activate operating system service no. 1 "Activation of OB6". The set time is flagged in system data word 101 (E IOCAH) while the time is running. You can set the clock prompt in steps of 1 ms. The programmable clock prompt is therefore in the range 1 t o 65535 ms (possible deviation: -1 ms). OB6 can be interrupted by system error OBs 26,33,35. OB6 can interrupt the cyclic and time-controlled program and can also interrupt a running interrupt program (OB 2 t o 5) (save scratchflags, i f necessary)! Invocation o f OB6 can be delayed if Integral blocks are in use The clock has been parameterized ProgrammerIOP functions are active SINEC L1 is connected Computer interface or ASCll driver are active The IP 252 accesses the S5 bus direct The system error level is active or interrupts have been disabled. See Table 2-6 for the time by which invocation of OB6 is delayed. You can disable processing of OB6 selectively with the "SIM" operation or generally with the " IA" operation. OB6 requests received while interrupts are disabled, or while OB6 is running, are stored. If a further OB6 request occurs, the CPU signals "collision of t w o timed interrupts". Example: Starting the clock prompt :L KB 1 L o a d f u n c t i o n n u m b e r of the o p e r a t i n g s y s t e m CPU 945 Manual 2.8.6 Technical Description System Error Level . The CPU 945 allows you t o respond t o system errors w i t h OBs 26, and 35. System errors are errors which can occur a t any t i m e i n t h e control program and are n o t tied t o any one program execution level (see Section 2.8.1). The error OBs 26, 33 and 35 have t h e highest priority. These OBs can only be selectively disabled w i t h t h e SIM operation. They cannot be disabled w i t h IA. If several system errors occur, t h e CPU 945 stores t h e m and processes t h e m consecutively. OB26 Response t o t i m e o u t If t h e scan t i m e is exceeded, t h e scan t i m e can b e restarted over OB26. The f o l l o w i n g sequence takes place after t h e "ZYK" signal: 1 Timeout 1 ti as "ZYK" o c c u h red already and n o t been acknowledqed? I Restart scan t i m e I Invoke OB26 (STOP) If t h e error is n o t acknowledged by restarting t h e scan t i m e w i t h OB31 (e.g. i n OB26) and t h e scan t i m e runs o u t again, t h e CPU goes t o STOP w i t h ZYK. If there is n o OB26, t h e CPU goes t o STOP w i t h ZYK. Technical Description 0633 CPU 945 Manual Response t o collision of t w o timed interrupts If any of the timed interrupt collisions listed in Table 2-7 occur, the operating system interrupts program processing and branches t o OB33. An error code has been assigned t o each of the collision events. This error code is in ACCU 1 when entering OB33 and can be evaluated. If you have not programmed an OB33, no response is made t o the collision. Until a collision event with a specific error code has been processed no further collision event w i t h the same error code will be stored. Table 2-7 Errors Handled in OB33 Interrupt is disabled and a second request arrives OB35 Response t o I10 errors If one o f the I10 error events listed in Table 2-8 occurs, the operating system interrupts program processing and branches t o OB35. An error code has been assigned t o each o f the I10 error events. This error code is in ACCU 1 when entering OB35 and can be evaluated. If you have not programmed an OB35, the CPU goes t o STOP when these errors occur. If one of the I10 errors is detected during restart, the CPU will not start, even with a programmed OB35. Until an I10 error event with a specific error code has been processed, no further I10 error event with the same error code will be stored. Table 2-8 Errors Handled in 0835 If PEU occurs during transfer of a process I10 image, both PEU and QVZ will be detected and stored at process I10 image transfer. This QVZ is responded t o when no more OB35 requests are pending, i.e. you may have t o program an OB24. CPU 945 Manual Technical Description If one of these I10 errors persists, OB35 is called again every time it is processed. This makes any other program processing impossible. However, scan time monitoring continues although it may have t o be restarted. Example In a system with an expansion unit connected in distributed configuration, the PLC is t o restart after POWER UP if the POWER OFF for the expansion unit was up t o 2 s before the POWER OFF of the central controller. : J U FB 3 5 I n v o c a t i o n o f FB35 NAME : WAIT :A F 0.0 :AN MFO. 0 F o r c e RLO = 0 :L KT 2 0 0 . 0 Load t i m e v a l u e 2 :SE TO S t a r t t i m e r a n d r u n w i t h RLO :O F 0.0 :ON F 0.0 :SE TO F o r c e RLO = S = 0 1 S t a r t t i m e w i t h RLO = 1 W A I T : J U OB 3 1 :A TO : J C = WAIT 2.8.7 :STS S T O P i f n o POWER O F F i n c e n t r a l c o n t r o l l e r : BE 2 S a f t e r d e t e c t i o n o f PEU Handling Programming Errors and PLC Malfunctions It is possible t o determine the response of the CPU t o programming errors and PLC malfunctions using error response OBs. The operation which triggers the timeout, substitution or transfer errors can be replaced by calling the relevant error response OB. Appropriate responses t o errors can be programmed in these OBs. If only "BE" is programmed there, no response follows, i.e. the PLC does not go t o STOP. If no relevant OB exists, the CPU jumps t o the STOP mode. Technical Description OB19 CPU 945 Manual Response when an unloaded block is called In OB19, you can program the response o f the CPU when an unloaded block is called. In the event of a fault, RS 102 (E 10CCH)contains the machine code o f the last block call. Only the second word of the machine code is stored in the case of DOU FX and DOC FX. Example: The CPU is t o go t o STOP when an unloaded block is called :JU FB 1 9 NAME :S T S S e t CPU t o STOP :BE :L RS 1 0 2 E v a l u a t e e r r o r code :T F W O Store i n FW Stop statement If OB19 has not been programmed, the control program continues execution (no response) immediately after the jump statement (the destination of the jump does not exist!) OB23 Response t o timeout in the case of direct I10 access The following operations can result in a timeout: L PY; L PW; T PY; T PW; L OY; LOW; T OY; T O W and accesses via indirect addressing LIR, TIR, TNB, TNW, TRW, TRD, TRW, LRD, ... The timeout (QVZ) error occurs if a module fails t o acknowledge within 160 p s of being accessed. The cause may be a program error, a defect in the module or the removal of the module during the RUN mode. The operating system stores the absolute module address at which the QVZ occurred in system data word 103 and 104 (E 10CEHt o E 10D1H) and calls OB23. If OB23 does not exist, the CPU goes t o STOP with QVZ (ISTACK error code: "QVZ"). OB24 Response t o timeout when updating the process I10 image or the interprocessor communication flags If a timeout occurs when updating the process I10 image and the interprocessor communication flags, the absolute address at which the timeout occurred is stored in system data words 103 and 104 (E 10CEH t o I 10D1H) and OB24 is called. If OB24 does not exist, the CPU goes t o STOP with "QVZ" (ISTACK error code: "QVZ"). CPU 945 Manual Technical Description OB27 Response t o substitution error Asubstitution error (SUF) can occur in the following cases - If the formal parameters o f a function block are changed after the block is called ("HU FBx", "JC FBx", DOU FXa", "DOC FXa"). - If the parameter is greater than the current DB length in the case o f the DO DW operation. The operating system interrupts the control grogram when a substitution error has been detected and then executes OB27 instead of the substitution operation. If OB27 does not exist, the CPU goes t o STOP with the ISTACK error code "SUF". OB32 Response t o transfer errors A transfer error (TRAF) occurs under the following circumstances: - When data words are accessed without previously calling a data block (C DB, CX DX). - If the parameter is longer than the data block opened in the case of the operations L DW; T DW; TB D; TBN D; SU D; RU D; etc. - If there is not sufficient program memory available t o generate the specified data block or a length parameter greater than FFF9, in the case of the G DB or GX DX (Generate Data Block). Response t o transfer error: The operating system interrupts processing of the operation where the transfer error occurred and processes OB32 instead. If OB32 does not exist, the CPU goes t o STOP with the ISTACK error code "TRAF". OB34 Response t o the BAU (battery failure) signal The PLC continuously checks the status of the battery in the power supply. If battery failure (BAU) occurs, OB34 is processed before each cycle until the battery has been replaced and the battery failure indicator on the power supply has been acknowledged (RESET key). You program the repsonse t o battery failure in OB34. If OB34 has not been programmed, no response results. 2.9 Scan times of the CPU 945 This chapter shows you how t o estimate and measure the execution time and scan time of a program. The scan time is the sum o f the run times of all operations executed by the CPU or the PLC. For example, Execution of a control program I10 accesses, e.g. process I10 image and interprocessor communication flags Operating system operations, e.g. updating the clock "Interventions in a normal program scan", e.g. bythe programmer/OPfunctions You can influenc the scan time by manipulation of the process I10 image transfer. This process I f 0 image transfer, newly organized compared t o the CPU 941 t o 944, is described in Section 2.8.2. Section 2.9.3 contains an overview o f the times relevant for estimating the scan time. In the case o f purely cyclic execution w i t h interrupt processing and without direct I10 access, the scan time constitutes the main proportion of the response time. EWA 4NEB 81 1 61 50-02d Technical Description 2.9.1 CPU 945 Manual Response Time in the Case of Exclusively Cyclic Program Execution The response time is the time between change o f the input signal and change of the output signal. The response time depends on the delay of the input module and the scan time. The delay of the output modules can be ignored. The response time in the case o f exclusively cyclic program execution is being considered here, i.e. without interrupt processing or direct I10 accesses. The next t w o figures are intended t o illustrate how the response time differs between Sequential process 110 image transfer (see Figure 2-1 3) and Parallel process I10 image transfer (see Figure 2-14). The following figure shows an example of the reponse time in the case of sequential process I10 image transfer. As well as the response time tR, the figure also shows the worst case tRmax. Delay of the input modules \! I* I Response time t, 8::::' .... ....<1 .... ..... .... J I I I I Process signal Signal in PIQ Q 1.0 Process signal I I I I I I I I I I l I I I I I I l L I I I I I I I I I I l I l I I I I I Time I I '~rnax (without delay of the input module) ) )I Legend: I ... Reading the digital input modules into the PI1 o f the bus controller I' ... Transferring the PI1from the bus controller into the PI1o f the control processor B ... Control program Q' ... Transferring the PIQ from the control processor intothePIQofthe buscontroller Q ... Output of the PIQ from the bus controller t o the digital output modules SCP ... Scan control point tR... Response time Figure 2-13 Response Time in the Case of Sequential Process I/O Image Transfer CPU 945 Manual Technical Description The following figure shows an example of the reponse time in the case of parallel process l/0 image transfer. As well as the response time ,R, the figure also shows the worst case tRmax. Delay o f the input modules Response time t, Ir 4 l I I I Process signal Signal in PIQ Q ( I SCP I I I l l I I I I I I I I I Process signal I I l', ;- - -I I I I I I l l I I * Time ---m - --02 SCP l'3 --- Q', SCP l", -- I t~max (withoutdelayof the input module) m )I Reading the digital input modules into the PI1 of the bus controller Legend: I ... I' ... Transferring the PI1from the bus controller into the PI1 of the control processor B ... Control program Q' ... Transferring the PIQ from the control processor into the PIQ of the bus controller Q ... Output of the PIQ from the bus controller t o the digital output modules SCP ... Scan control point tR... Response time Figure 2-14 Response Time in the Case of Parallel Process I/O Image Transfer Technical Description 2.9.2 CPU 945 Manual Estimating the Scan Time The scan time has been divided into various units below t o help you estimate the program runtime and thus the amount o f time needed t o scan the program. The scan time is determined by The control program and m All operating system operations required for executing the control program. The scan time increases if system processing times are additionally necessary. System processing times result from ProgrammerIOP operations or Demands arising from SINEC L1, ASCII driver or computer interface. System processing times can vary are depend on the operations executed. System processing times can almost be ignored in the case of the CPU 945 since the actual communication functions (programmer1OP functions, etc.) are handled by the microcontroller. P SCP I lPCl Scan time without system processing time Control side -----------Communication side Scan time with system processing time SCP ... Scan control point I ... Process input image lPCl ... Reading in the input interprocessor communication flags Q ... Outputting the process output image IPCQ ... Outputting the output interprocessor communication flags PG ... ProgrammerIOP operations SINEC ... SINEC L1 demands Figure 2-15 Breakdown of the Scan Time Technical Description CPU 945 Manual 2.9.3 Basis for Calculating the Scan Time The following table contains the basis for calculating the individual times of a cycle. Table 2-9 Breakdown of the Scan Times < 50 Basic scan time (scan time control point) I Reading in the process input image I' transfer l transfer I I I tl. < 25 tl = 54 +n + I (1.5 ready delay of the module) Sum of the runtimes of all processed STEP 5 statements Control program (incl. runtime of higher-priority levels, e.g. OB2) Outputting the process output image A' transfer tA=54+ m (1.5 A transfer (reduced) + ready delay of the module) A transfer I tA=54 +p ( l -5+ready delay of the module) Basic runtime (interprocessor communication 50ps f)lag (IPC) list valid, no entry: Additional runtime per IPC flag list word 35ps with at least one entry: 1Ops Additional runtime per entry: Ready delay of the module Runtime in the case of invalid 5~s IPC flag list: Reading in and outputting the interprocessor communication flags + I ProgrammerIOPoperations l Dependent on the functions t o be executed I'... Transfer of the Pil from the PI1 of the bus controller into the PI1of the control processor I ... Reading the digital input modules into the PI1 of the bus controller Q' ... Transfer of thePlQ of the control processor to the PIQ of the bus controller Q ... Output of the PIQ of the bus controller t o the digital output modules n ... Number of connected input bytes m ... Number of connected output byte p ... Number of changed output bytes EWA 4NEB 811 6150-02e I Technical Description CPU 945 Manual The Ready delay time is the time that elapses between the arrival of the Request signal in the module and the module's Ready signal. The delay time depends on The Ready delay time of the module itself The interface module used and The length o f the cable In a distributed configuration, the communications link delay must also be taken into account. If the CPU does not receive the Ready signal within 160 psec., it stops and outputs the "QVZ" (time-out) error message if OB2310B24 has not been programmed (see Section 2.8.7). Table 2-1 0 Ready Delays of the Different I10 Modules Digital modules 2 Analog modules 16 313 watchdog modules 1 IP 240 1 IP 241 I 2 4 1 USW 1 IP 242 B 50 IP 243 (Analog module) 35 IP 244 150 IP 246 1.5 IP 247 1.5 IP 252 10 IP 281 0.5 IP 288 1.5 CP 516 1 CP 523 3 ... 100 CP 5241544 1 CP 525 3 CP 526 3 CP 5271528 3 CP 530 3 ... 130 CP 535 3 CP 551 3 CP 552 3 CP 543015431 1 CP 143 3 W F 705/706/7071721 1723 2 CPU 945 Manual Technical Description Different response times in the case of sequential and parallel process I/O image transfer The following figure shows a comparison o f the response times in the case of sequential and parallel process I10 image transfer depending on the control program processing time. tR... Response time tB... Control program processing time tE+tA ... Process I/O image transfer Figure 2- 16 Response Times in Case of Sequentialand Parallel Process I/O Image Transfer Example: The process 110 image transfer requires 500 ps for reading in the process 110 image and 300 p s for outputting the process I/O image t o the I10 modules. These transfer times result in the following control program processing times: A t p o i n t O: Atpoint O: tB= 360 p tB= 1480 p s If the control program processing time tBlies within the interval 360 p < tB < 1480 p,the response time in the case of parallel process 110 image transfer is less than that of sequential process I10 image transfer. However, if tBlies outside this interval, the response time in the case of parallel process I10 image transfer is greater than that of sequential process 110 image transfer. EWA 4NEB 81 1 61 50-O2d CPU 945 Manual Technical Description Measuring the Scan Time 2.9.4 The scan time i s measured by the CPU and stored in the system data area. You can access the current, the minimum and the maximum scan time in the control program at any time. The resolution o f the scan time is one millisecond, and the range of scan time values extends from 0 t o 32,767 (=7FFFH) milliseconds. At the end o f a scan cycle, after it has updated the process output image (PIQ) and the interprocessor communication flags, the operating system stores the scan time, i.e.: Current scan time in SD 121 Maximum scan time in SD 122 Minimum scan time in SD 123 If the scan time exceeds 32,767 milliseconds, bit 15 (which is the overflow bit) o f the current scan time is set and entered in system data word SD 123 (maximum scan time). Scan time measurement begins anew in the next scan cycle. Note The contents of the watchdog timer are also entered in system data words 121 t o 123 when the PLC stops and outputs the "ZYK" (scan time exceeded) message. Example: Function block for measuring the scan time NAME DECL DECL DECL DECL :ZYKLUS-Z :MINI : AKTU I/Q/D/B/T/C: :MAXI I/Q/D/B/T/C: :L O E S I/Q/D/B/T/C: : L : T A A E BI/BY/W/D: BI/BY/W/D: BI/BY/W/D: W W B1 RS 121 =AKTU RS 122 =MAXI : L RS 123 : T =MINI : AN = L O E S : L : T : T KF +O RS 121 RS 122 : T RS 123 : L : T The L O E S o p e r a n d i s u s e d t o r e s e t s y s t e m d a t a words 1 2 1 , 1 2 2 and 1 2 3 ( i f LOES = 1 ) . EWA 4NEB 81 l 61 50-02d CPU 945 Manual Technical Description 2.9.5 Setting the Scan Monitoring Time The scan time comprises the duration of the cyclic program. A t the beginning of each program scan, the processor starts a monitoring time (cycle trigger). This monitoring time is preset t o approximately 500 ms. If the scan trigger is not initiated again within this time - f o r example, as a result of programming an endless loop in the control program or as a result o f a fault in the CPU the PLC goes t o STOP and disables all output modules. If the control program is very complex, and the monitoring time can be exceeded, you should change the monitoring time in the control program. There are t w o possible methods for changing the default scan monitoring time: Initialization in DBI (see Chapter 11) or STEP 5 operations. You can set the scan monitoring time up t o 2.55 s (KF= +255) without having t o restart the monitoring time. If you want t o change the default scan monitoring time (approximately 500 msec.) via STEP 5 operations, you must transfer a factor for this purpose t o system data word 96. The CPU operating system interprets this factor as a multiple of 10 msec. OB31 scan time triggering A scan time monitor monitors the program scan time. If program execution takes longer than the specified scan monitoring time (e.g., 500 msec.), the CPU enters the STOP mode CPU goes t o STOP with "ZYK" or CPU calls the "Error OB"26 (scan time exceeded) if you have programmed an OB26. Calling OB26 restarts the scan time once. However, the timeout must be acknowledged with an OB31 call otherwise the CPU will go t o STOP with ZYK in the event o f a repeated timeout even if OB26 is programmed (see Section 2.8.6). This situation can occur, for instance, when The control program is too long The program enters a continuous loop. Technical Description CPU 945 Manual You can restart the scan watchdog at any time by calling OB31 at any point in the control program (JU OB31). Thescan monitoring time is restarted by calling OB31. The scan monitoring time can be set in the following ways: in system data word 96 (E 1OC4) or In DBI with the WD parameter Please note that the ACCUs and the BR register are changed by OB31! /1\ important Do not call OB31 in an endless loop since important operating system functions are processed at the scan control point. EWA 4NEB 81 1 61 50-02d CPU 945 Manual 2.10 Technical Description Operating System Services in OB250 The operating system services allow you t o : Activate different operating system functions or Change specific parameters during cyclic operation. These functions are: Invocation o f OB6 (collision o f t w o timed interrupts) Setting o f t h e OB10 t o 13 intervals (time-controlled program execution) Manipulation o f t h e process I10 image transfer Regeneration o f t h e block address Iist Generating a data block (DBIDX) without TRAF I10 accesses and page accesses without QVZ Disabling and enabling t h e output modules (setting and resetting BASP) Access t o DBS and DBL registers Indexed access t o DX IndexedaccesstoFX Cancelling a block in t h e block address Iist Changing t h e block identifier The system data can be overwritten direct i n the case o f t h e CPUs 941 t o 944. In the case o f t h e CPU 945, direct overwriting o f the system data has no effect o n the above-listed functions. For this reason, you must call these operating system services over the integral OB250. A function number has been assigned t o the operating system services. You must load this function number into ACCU l-L. You must load service-specific parameters into ACCU 2 or ACCU l-H. The operating system transfers error flags t o ACCU l-L. The following are global error flags: 0-no error 1-invalid function number 2 t o 4-reserved Service specific error flags: 5 t o FFFF, Please note t h a t t h e ACCUs and t h e BR register are changed by OB250! ACCU l - H and ACCU 2 contain output data o f the operating system service. Input o f t h e function numbers and t h e service-specific parameters: 1 ACCU 2-H I ACCU 2-L I ACCU l - H Service-specific parameter ACCU l - L Function number Output o f error flags and service-specific output data: ACCU 2-H ACCU 2-L ACCU l - H Service-specific output data Figure 2- 17 ACCU l - L Error flags Assignment of the ACCUs when Inputting and Outputting Operating System Service Parameters Technical Description CPU 945 Manual Operating system services Interrupt response after t i m e o u t The f o l l o w i n g happens w h e n y o u call operating system service 1 : The clock p r o m p t transferred t o ACCU 2-L is started or Astarted clock p r o m p t is aborted. You program t h e response o f t h e program after a preset t i m e ( " t i m e d interrupt") i n OB6 (see Section 2.8.5). Table 2-11 Operating System Service f o r Activating 0 6 6 t o 65535: Time i n ms Time-controlled program processing OBs 10 t o 13 are available f o r time-controlled program execution (see Section 2.8.3). The t i m e OBs are called b y t h e operating system a t fixed intervals. You can assign n e w intervals t o these t i m e OBs over operating system services 2 t o 5. Table 2-12 Operatinq System Services f o r Time-Controlled Program Execution N e w interval f o r OB10 N e w interval for OBII 3 N e w interval f o r OB12 4 N e w interval f o r OB13 5 ACCU 2-L: 0: 1 t o 65535: No OB10 call lnterval i n ms ACCU 2-L: 0: 1 t o 65535: No OB11 call lnterval i n ms ACCU 2-L: 0: 1 t o 65535: No OB12 call lnterval i n ms ACCU 2-L: 0: 1 t o 65535: N o OB13 call lnterval i n ms ACCU l - L 0: No error ACCU l - L 0: No error ACCU l - L 0: No error ACCU l - L 0: No error CPU 945 Manual Technical Description Changing the process I10 image transfer During the cold restart routine, the CPU determines the I10 module complement (see Section 2.6.1) and writes this into system data words 128 t o 159. You can selectively change the entries for the module complement o f the digital I10 modules (RS 128 t o 143) using operating system service 6. When transferring the process image of the digital outputs, the CPU has the option of outputting t o the modules only those PIQ bytes in which the PIQ has changed (see Section 2.8.2). You can set this "reduction o f PIQ transfer" in the control program with operating system service 7 "Reduction of PIQ transfer" or with the DBI parameter RPlC (see Chapter 11). Table 2-13 Or: :rating System Services for Changing the Process I10 Image Transfer Changing the entries in RS 128 t o 143 (digital 110) ACCU 2: Bits 0 ... 6: Number of the I10 byte (0 t o 127) Bit 7: 0: Input module 1: Output module B i t 8: 0: Delete entry 1: Insert entry Bit 9 ... 31: Not evaluated ACCU l - L 0: No error 5: Function not currently possible (parallel PI transfer active) Reduction of PIQ transfer ACCU 2-LL: 0: "Mechanism" inactive 1 ... 255: Number of program scans with reduced PIQ transfer after one complete PIQ transfer ACCU l - L 0: No error Generation of the list o f all addressable I10 bytes (entries in RS 128 t o 143 and RS 144to 159) None ACCU l - L 0: No error 5: Function not currently possible (parallel PI transfer active) Please note the following when using operating system service no. 8: e The outputs are reset when operating system service no. 8 is called. Operating system service no. 8 must not be used when you are using the 434-7 digital input module and the 485-7 digital inputloutput module. Technical Description CPU 945 Manual Generating a data block (DBIDX) w i t h o u t TRAF Generating data blocks (DBIDX) over operating system services 10 and 11 offers t h e following advantages: If a DBIDX cannot be generated, t h e CPU 945 does n o t g o t o STOP w i t h TRAF Error evaluation is possible immediately over t h e error flag i n ACCU ?-L It is n o t necessary t o program the error-response OB32 (response t o TRAF) Table 2-14 Overatina Svstem Services f o r Generating a DBIDX Without TRAF ACCU 2-LL: 0 t o 255: DB number Generating a DB without TRAF ACCU 2-H: ACCU l - L 0: No error 5: TRAF (as in G DB) 0 : Delete DB 1 t o FFF9,: Generating a DX without TRAF DB length up t o and including DW ACCU 2-LL: 0 t o 255: DX number ACCU 2-H: 1 t o FFF9,: ACCU l - L 0: No error 5: TRAF (as in GX DX) 0: Delete DX DX length up t o and including DW Regenerating the block address l i s t The block address l i s t is regenerated after calling operating system service 12. I Note Use o f operating system service 12 leads t o an increase i n t h e scan time o f up t o several 100 ms (see Pocket Guide). If necessary, t h e scan time must be restarted w i t h OB31. If an error is detected during generation o f t h e address list, t h e CPU goes t o STOP w i t h an Overall Reset request. Regenerating t h e block address l i s t 12 None ACCU l - L 0 : No error EWA 4NEB 81 1 61 50-O2d CPU 945 Manual Technical Description I10 accesses and page accesses w i t h o u t QVZ I10 accesses and page accesses over operating system services 13 t o 18 offer t h e following advantages: If a timeout (QVZ) occurs, the CPU 945 does n o t g o t o STOP Error evaluation is possible immediately overthe error flag i n ACCU l - L It is n o t necessary t o program the error-response OB23 (response t o QVZ) In t h e event o f a QVZ, operating system services 13 t o 98 enter t h e QVZ addresses in system data words RS 103 and 104. Table 2-16 Operating System Services f o r 110 Accesses and Page Accesses Without QVZ (byte) f r o m S5 bus Read address (word) f r o m S5 bus 15 Write address (word) t o S5 bus 16 0 t o FFFFH: Address ACCU 2-HL: 0 t o FF,: Byte t o be written ACCU 2-L: 0 t o FFFE,: Address ACCU 2-L: 0 t o FFFE,: Address ACCU 2-H: 0 t o FFFFH: Word t o b e written 0: ACCU l-L: 0: No error 5: QVZ 7: Invalid address ACCU 2-L: Word read ACCU l-L: 0: No error 5: QVZ 7: Invalid address ~p EWA 4NEB 81 1 61 50-02d No error CPU 945 Manual Technical Description Table 2-16 Operating System Services for 110 Accesses and Page Accesses Without QV2 Read byte from page Byte t o be written 17 18 ACCU 2-L: 0 t o 07FF,: Offset within the page ACCU 2-HL: 0 t o FF,: Page number ACCU 2-L: 0 t o 07FF,: Offset within the page ACCU 2-HL: 0 t o FFH. Page number ACCU 2-HH: 0 t o FFH: Byte t o be written ACCU l-L: 0: No error 5: QVZwhen selecting the page 7: QVZwhen accessing the page 9: Invalid offset in the page ACCU 2-LL: Byte read ACCU l-L: 0: No error 5: QVZwhen selecting the page 7: QVZwhen accessing the page 9: Invalid offset in the page Disabling and enabling digital outputs Table 2-17 Operating System Service for Disabling Digital Outputs Disabling and enabling digital outputs (setting and resetting BASP) /I\ 19 ACCU 2-L: Bit 0: 0: Reset BASP 1: Set BASP important Service no. 19 must not be used if the 434-7 digital input module and the 485-7 digital inputloutput module are being used. CPU 945 Manual Technical Description Access t o DBS and DBL Registers Operating system services 20 t o 23 can be used t o readlwrite in the DBS and DBL registers. Note the following, however: Basically, the DBS register contains only even addresses. The DBS register has a width of 24 bits. When reading the DBS register, the register contents are stored in bits 0 t o 23 of ACCU 2; bits 24 t o 31 have the value zero. For writing, only bits 0 t o 23 of ACCU 2 are relevant. If the DBS register is set t o addresses outside the range of the user RAM, subsequent access operations via the DBS register (TDW, LDW, ...) might result in errors such as QV2 or FAD. No plausibility check is carried out for the address by the operating system service. Table 2-18 Operating System Services for Access t o DBS and DBL Registers * Read DBS register Exec. time: 25 us 20 None ACCU l-L 0: Noerror ACCU 2 Contents of DBS reg. Write DBS register* Exec. time: 26 ps 21 ACCU 2: 0 ... FFFFFEH: address ACCU l - L 0: Noerror 5: Invalid address (Bit 0 7t 0) Read DBL register Exec. time: 25 p s 22 None ACCU l - L 0: Noerror ACCU 2-L Contents of DBL reg. Write DBL register Exec. time: 25 p s 23 ACCU 2-L: 0 ... FFFFH ACCU l-L 0: Noerror If you set the DBS register to an address between OZOOOO, and 0205FF,, subsequent execution of an "MBA" command may result in data falsification in this range. In order to avoid this effect, use the command sequence "ABR+O, MBA" instead of the "MBA" command. EWA 4NEB 81 1 6150-02e CPU 945 Manual Technical Description lndexed Access t o DX Operating system service 24 can be used f o r indexed access when opening a DX block (replacement for DO DWIDO FW, CX DX). Note t h e following, however: If t h e DX t o be opened does n o t exist a t all, t h e DBIDX opened before is closed (DBS and DBL registers are initialized w i t h 0). Table 2-19 O ~ e r a t i n q Svstem Utilities f o r lndexed Access t o DX Indexed access t o DX Exec. time: 29 p s 24 ACCU 2-LL: 0 t o 255: DX number ACCU l - L 0: No error 5: DX n o t available lndexed Access t o FX Operating system service 25 can be used f o r indexed access when opening an FX block (replacement f o r DO DWIDO FW, DOU DX). Note t h e following, however: If t h e FX t o be called does n o t exist a t all, t h e FX call is suppressed. The FX block is n o t accessed until 0 8 250 is completed. The ACCUs, t h e STATUS register and t h e BR register have been modified. When t h e FX is called, however, the same DBIDX as i n the block calling t h e operating system service is opened. Evaluation o f t h e feedback from t h e operating system service is possible only w i t h certain restrictions as t h e FX called might have modified t h e ACCU contents. Table 2-20 O ~ e r a t i n a Svstem Utilities f o r lndexed Access t o FX Indexed access t o FX Exec. time: 30 p s 25 ACCU 2-LL: 0 t o 255: FX number ACCU l - L 0: No error 5: FX n o t available CPU 945 Manual Technical Description Cancelling a Block in the Block Address List Operating system service 26 can be used t o cancel a block in the block address list. Note the following, however: A user block is retained as valid block in the RAM, i.e. it is re-entered in the address l i s t the next time the block address l i s t is regenerated, and for compressing (only when the cancelled block is shifted in the memory). The operating system service can also be used for cancelling integrated blocks in the block address list. Integrated blocks are only re-entered in the address list when regenerating the block address list but not when compressing. The operating system considers a block as being non-existent while i t is cancelled in the block address list. Table 2-21 O ~ e r a t i n aSvstem Services for Cancellina a Block in the Block Address List Cancel block in the block address l i s t Exec. time: 28 p s ACCU 2-LL: 0 t o 255: Block number ACCU 2-LH Block type: 1: PB 2: SB 3: FB 4: FX 5 : DB 6: DX 7: OB EWA 4NEB 81 1 61 50-02d ACCU l - L 0: No error 5: Invalid block type 7: Block does not exist Technical Description CPU 945 Manual Changing the Block Identifier Operating system services 27 and 28 can be used t o change the block identifiers in the RAM t o "valid in EPROM" or "valid in RAM". Note the following, however: The block identifier is changed only in blocks entered in the block address list. When changing the identifier t o "valid in EPROM", the identifiers of DBs and DXs are not changed. Changing of the identifier t o "valid in RAM" changes the identifiers of all user blocks. The identifiers of integrated blocks are not changed. Table 2-22 Operating System Services for Changing Block Identifiers Execution time: 4.8ms n-19ps n = Number o f blocks t o be modified + Change block identifier t o "valid in RAM" Execution time: 6ms n-19ps n = Number o f blocks t o be modified 28 None ACCU 1-L 0 : Noerror + Please refer t o Section 4.3.2 in the manual for further information on transferring the user program t o the CPU. CPU 945 Manual Technical Description Operating system service call example The following example shows the principle of operation with OB250. A reduced PIQ transfer is t o be executed. The PIQ is only t o be output every fifth program scan. For the four program scans between, only the output bytes which have changed will be updated. L KB4 4 program s c a n s w i t h r e d u c e d PIQ t r a n s f e r :L KB7 L o a d the f u n c t i o n number o f the o p e r a t i - n g s y s t e m : J U OB 2 5 0 :L ACCU1: 0000 0007H ACCU2: 0000 0004H C a l l o p e r a t i n g s y s t e m service KBO L o a d code f o r " N o e r r o r " Checkback s i g n a l YES: NO: l EWA 4NEB 81 1 61 50-02d I "No e r r o r " ? Program end Error evaluation (e.g. CPU t o S T O P ) 1 Technical Description 2.1 1 CPU 945 Manual Further CPU 945 Functions in Integral Blocks This chapter is concerned with integral blocks that you call in the control program for special functions. These functions are: a Compressing the program memory (FB238 "COMPR") a Deleting a block (FB239 "DELETE") a Generate a block (OB125) a Variable time loop (OB160) a Copying data areas (OB 182) a Duplicate DX or DB blocks (OB183 and OB184) a Transferring flags t o a data block (OB190 and OB192) a Transferring data blocks t o flag areas (OB191 and OB193) Extension for sign (OB220) a Reading the digital inputs into the PI1 (0B254) a Outputting the PIQ t o the digital outputs (0B255) a PID Control Algorithm. (OB251) More integrated CPU 945 blocks can be found in: Setting the Scan Monitoring Time (OB31), see Chapter 2.9.5 a Operating System Services (0B259), see Chapter 2.10 a Analog Value Matching Blocks(FB241, FB242, FB243, FB250), see Chapter 10.10 a Outputting an Analog Value (FB251), see Chapter 10.10.5 a Data Interchange over Data Handling Blocks FB244 t o FB249), see Chapter 12.2.3 a Note The integral modules change the ACCUs in the BR register. CPU 945 Manual Technical Description 2.1 1.l Compressing the Program Memory with FB238 "COMPR" The integral "COMPR" block (no. 238) compresses the internal program memory. Calling the function block Calling FB238 in the control program has the effect of executing the "Compress PLC" function. This function block signals back with the "AKT" bit whether this function is s t i l l active. When compressing is finished, the "AKT" bit signals back independently of FB238. This signal takes place in the "AKT" bit o f the first F6238 call. The "ERR" bit signals that the "Compress PLC" function cannot be executed. Compressing is restarted at every FB238 call whenever compressing is not activated. Compressing is terminated If there are no further blocks t o be shifted or If an invalid block synchronization pattern is detected. In the case o f an invalid block synchronization pattern, the CPU goes t o STOP with an "Overall reset request". :A I 0.0 :AN F 0.0 :A I 0.0 :A F :JC FB 2 3 8 FB 2 3 8 0.1 NAME :COMPR AKT :F 1.0 ERR :F 1.1 Table 2-23 FB238 Flaas d rit I AKT ERR Meaning ( "Compress PLC' function is active "Compress PLC" function cannot be executed Note The FB COMPR has the same effect as the programmer "Compress" function, i.e. i f FB COMPR is active, other programmer1OP functions will be rejected, e.g. STATUS or block inputloutput. I Technical Description CPU 945 Manual 2.11.2 Deleting a Block with FB239 "DELETE" The integral F5 "DELETE" (No. 239) deletes blocks. Parameterizing the Integral FB DELETE Parameterize the integral FB239 as follows: Store the type of the block t o be deleted in an input word, flag word or data word as an ASCll character (KS). The characters OB. PB, FB, SB and DB are permissible as block identifiers. Store the block number in an input byte or a flag byte. You must also specify a flag byte or an output byte which the operating system can use t o flag errors (see Table 2-24). Calling the Function Block (Example) : JU FB 2 3 9 FB 239 NAME :DELETE TYPE :FW 5 NUM :FY 7 ERR :FY 8 Contents o f FW 5: Block type in ASCII code (e.g. PB for program block) Contents o f FY 7: Block number (e.g. KF+7) Contents o f FY 8: No entry is made in FY 8 until the function block has been invoked (see Table 11-18) Table 2-24 Error Bits Set bv FB239 (ERR Parameter) I 00 I No error F0 I No such block F1 1 Invalid block type specified in the TYPE parameter F2 ( Block exists, b u t has an EPROM identifier I I F4 I DELETE function cannot execute because another function is in progress (e.g. a programmer function) I CPU 945 Manual Technical Description 2.1 1.3 Generating STEP 5 Blocks: OB 125 Function The OB 125 can be used t o generate any STEP 5 blocks (code and data blocks) in the user memory. The generation o f code blocks, however, should be left t o specialists. The specified block is generated in the internal RAM with block header and block body and then entered in the block list. The block body contains the BEU statement in the first word and the BE statement in the last word. In between the t w o words, any data can be stored. For this reason, data must first be written in a newly generated block before it can be employed for processing any useful statements. Execution time: 41 p s Parameters Type of the block t o be generated Number of the block t o be generated Permissible types and numbers of blocks Table 2-25 Permissible Types and Numbers of Blocks Number of words (desired block length without block header). Block lengths o f 1 t o 65530 (1 t o FFFA") words can be parameterized. Result: If a block has been processed correctly and without any errors, the system program sets the RLO t o "0" and deletes condition codes CC 1 and CC 0. Note During generation o f a block, the user interrupts are blocked. Neither timed interrupts nor process interrupts are registered. EWA 4NEB 81 1 61 50-O2d Technical Description CPU 945 Manual Errors and Warnings In t h e case o f an error, the system program aborts processing o f OB 125 and continues program execution a t t h e next STEP 5 operation. It also sets the RLO t o "1" and enters an identifier in ACCU 1-LL (see Table 2-26). When a function is aborted w i t h a warning, a repeated call o f t h e special function (if necessary, several times) may possibly achieve a correct execution o f OB 125. Condition Codes After calling OB 125, you can read t h e result o f t h e logic operation and condition codes CC 1 and CC 0 t o check whether the special function has been processed properly or aborted w i t h an "error" or "warning". The result can be evaluated by means o f a conditional jump. Evaluation o f Condition Codes Table 2-26 Condition Codes o f OB 125 :..,.,.,.,....... .:C.:.:.:.:.:.:.:.: .:.:..;::.:.....:.,:........................ .............:..-:..:., ..............................:I:;:>> .................................... ....;..~.:::::.:.>:::I(,...,.:.:.: ::. :i::::::::~~:~;;:.:.:.:::.;:::i~s;:;:~..i: ::::: ; . ; j >,. :::: ..~..:............................................:.:.:...:.:...:. .'..'.'......,.,.>:.:..:.:. ............................................................................................ ..'.,............................................................................... E:.:::jjjj:.:: : :::.: .,:...'"".'.'. ::::::::g::.:;:=::: .....,.......,. ........... ., ......... ..,.,.,.......,,, ........ :::::::::&$"j ...,......., ~~jj~j~~iIiIijIi;~I~;~$3~~~i~&D@$~.tjX@~BEI& :;:;:;:;:;:;:;:;:;:S>;:;:;:;:;: :;:;:;:;:;:~><~<:;:;:;:;:;:;:;:~:;:;:;:;:$::::;:;<$s.:::::~~.>z<z<~::.::::::::::::: s#,w,:*,z;:;:;:;:;:;:$z: ::::::<*,:mj::::::::: :::::;m:::$::::;:;:;:;= :m @$:e:g Eggs:& mzmiMz;$z;;;$:cfii#g&z 0 0 0 Special function has been processed correctly JB JZ 1 1 0 Special function has been aborted w i t h a "warning" JB JP JN 1 0 1 Special function has been aborted w i t h an "error" JB JM JN Identifiers i n ACCU 1-LL The system program uses ACCU 1-LL for storing descriptions o f t h e causes o f a warning or error in identifiers f o r t h e result o f t h e logic operation. CPU 945 Manual Technical Description Table 2-27 Condition Codes of the 0 6 125 in ACCU 1-LL Example: :L KF + 2 0 0 0 T H I S SEQUENCE O F O P E K A T l O N S :L KY 5 , 2 4 GENERATES :JU OB 1 2 5 A LENGTH O F 2 0 0 0 DATA WORDS THE DB 2 4 W I T H ( T O T A L LENGTH I N C L U D I N G HEADER: 2.1 1.4 Variable Time Loop with OB160 OB160 simulates operation runtimes. You can use this t o program waiting times of up t o 65.5 ms. Proceed as follows: The waiting time must be loaded into the ACCU in psec. (range: 3 t o 65535 or 3,to FFFF,). Example: A waiting time of one millisecond is t o be programmed. Please note the following when programming OB160: A process interrupt (OB2 t o OB5) and the timed interrupt (OB6) can interrupt the waiting time (provided no interrupt disable (IA) has been programmed). The waiting time stops during the interrupt! Similarly, the waiting time is increased by running PGIOP operations. The times set are therefore minimum times! EWA 4NEB 81 1 61 50-02d Technical Description CPU 945 Manual 2.1 1.5 Copying Data Area: OB 182 OB 182 copies a data frame o f variable length from one data block t o another. Both DB and DX blocks can be used as source and destination blocks. The beginnning o f t h e frame can be programmed i n t h e source and destination blocks. OB 182 may be up t o 65530 (FFFA") data words long. Note The source and destination blocks can be identical and t h e data frames o f source and destination may overlap. The original data o f the source area are copied t o t h e destination area in their original form even if t h e areas overlap. After the copy function, t h e area o f the source t h a t overlaps w i t h the destination area is overwritten. You may use this feature for shifting a data area w i t h i n a block. Before calling OB 182, you have t o assign t h e parameters necessary f o r t h e copy function t o a data field. The data field can be created in t h e F or S flag area o f either a DB or DX block. However, you s t i l l have t o specifythe location o f t h e data field in ACCU l - L and ACCU 2-L before calling OB 182. Data Field w i t h Copy Parameters The data field designates the source and destination blocks, t h e start address o f t h e frames in both blocks and t h e number o f data words t o be transferred. It consists o f five words. Bit No. 8 15 7 0 -. Source DB type Is t word No. o f 1st source DB w o r d t o be transferred 2 nd w o r d Destination DB No. Destination DB type 3 rd WO rd 4thword Source DB No. I No. o f 1st w o r d t o be written i n destination DB I Number o f data words 5t h WO rd The parameters have t h e following meanings and permissible value ranges: Data block type (source and destination) 1 = DB 2 = DX Data block number (source and destination) 0 t o 255 No. o f 1st data w o r d (source and destination) 0 t o 65529 (0 ... FFFgH) Number o f data words: 1 t o 65530 (1 ... FFFAH) If you create t h e data field in t h e flag area, enter t h e number o f t h e first flag word i n ACCU l - L when calling OB 182. Execution time: 35 p s + n . 2.65 p (n: number o f data words t o be transferred) CPU 945 Manual Technical Description Defining the Location o f the Data Field and Calling OB 182 Parameters: Before calling OB 182, you have t o enter t h e relevant copy parameters i n the data field as described above. B i t No. 15 - p I 1 8 - 7 1 I - 1 0 Data block No. Address area type Address area type, permissible values: 1 = DB block 2 = DX block 3 = F flag area 4 = S flag area Data block No., permissible values: DB: 0 t o 255; DX: 0 t o 255 irrelevant for F and S flags Number o f first data field word; permissible values (depending on t h e type o f address range): DB, DX: 0 t o 65525 F flag: 0 t o 246 (= No. o f flag word) S flag: 0 t o 4086 ( = No. o f flag word) Possible Reactions i n the Case o f Errors In b o t h cases, error identifiers are entered i n ACCU l - L and ACCU 2-L (see Table 2-28). Table 2-28 Error Identifiers Data block n o t loaded (source or destination n o t existing) 1A06~ 1A 3 4 ~ 0001 H OIOOH 010zH 020OH 0203H 021OH 021 3H 022OH 0221 H 022ZH Description o f data field invalid Illegal address area type "Number o f first word i n data field" illegal Illegal "source data block type" Length o f source data block in block header < 5 words Illegal "destination data block type" Length o f destination data block i n block header < 5 words Illegal "number o f data words t o be transferred" (=0 or >65530) Source data block t o o short Destination data block t o o short If t h e block is processed correctly, ACCU 1 has t h e value 0. EWA 4NEB 81 1 61 50-02d Technical Description CPU 945 Manual 2.1 1.6 Duplicating DX or DB Blocks: OB 183 and OB 184 The OB 183 and OB 184 organization blocks for special functions are used for duplicating a data block in the memory of the CPU. OB 183 handles DX blocks whereas OB 184 is used t o copy DB blocks. The source DB is not manipulated by the copy function and remains valid. n - 2.35 p (n: number of data words in DBIDX). Execution time: 52 p s + Parameters: Number of source block; permissible range: 0 t o 255 Number of destination block; permissible range: 0 t o 255 If the block is processed correctly, the RLO register is set t o 0 and ACCU 1 has the value 0. In the case of an error, however, the RLO = 1 and an error code is entered in ACCU 1. Possible Errors: Table 2-29 Possible Errors EWA 4NEB 81 1 61 50-O2d CPU 945 Manual Technical Description 2.1 1.7 Transferring Flags to Data Blocks: OB 190 and OB 192 The OB 190 and OB 192 organization blocks can be used for transferring a certain number o f flag bytes specified by t h e user t o a particular data block. This can be useful prior t o a block call, in error organization blocks or when cyclic program execution is interrupted by time or interrupt-controlled program execution. The OB 191 and OB 193 organization blocks can be used t o transfer the flag bytes back t o the data block. Note Use OB 192 and OB 193 for saving and reloading flag bytes t o achieve considerably shorter execution times. Prior t o calling OB1901192, the respective data block (DBIDX) must be opened! OBs 1901192 can be used for transfer t o a data block from the F flag area only b u t n o t from the S flag area. - After calling OBsl901192, the flag bytes are entered starting from the data word address specified for t h e data block opened. OBs 1901192 read t h e flag area t o be saved i n ACCU 2. OB 190 and OB 192 are identical apart from t h e manner in which t h e flag bytes are transferred: OB 190 transfers flags byte by byte. OB 192 transfers flags w o r d by word. This is relevant f o r cases i n which data transferred t o a data block is t o be processed subsequently and t h e data block is n o t merely used for intermediate storage. CPU 945 Manual Technical Description The diagram below illustrates the difference: Copy flags using Flag - OB 190: OB 192: Data block Data block FYO 0 DWO FY1 1 DW1 FY2 2 DW2 FY3 3 DW3 4 Figure 2-18 Byte-By-Byte (OB 190) and Word-By-Word (OB 192) Transfer Note If an odd number o f flag bytes is transferred, only one half of the last data word accessed in the data block is used. In the case of OB 190, the left data byte remains unchanged in the destination DB, whereas, in the case of OB 192, the right data byte remains unchanged. Execution times: OB 190: 13ps n.1.85~ OB 192: 12ps n-1.3ps + + (n: number o f bytes) (n: number o f bytes) CPU 945 Manual Technical Description Parameters: Source specifications: First flag byte t o be transferred; permissible range: 0 t o 255 Last flag byte t o be transferred; permissible range: 0 t o 255 (Last flag byte 2 First flag byte) Destination specifications: Number o f the first data word t o be written in the open data block. The permissible values depend on t h e length o f the data block i n t h e memory.The values may thus also be > 255 0 t o 65529 (0 t o FFFgH) If t h e special function OBs 1901192 are processed correctly, t h e RLO is deleted (RLO = 0). The RLO is set (RLO = 1) i n t h e case o f an error. Possible Errors: No DB or DX block open Wrong flag area (last flag byte < first flag byte) No data w o r d number available Length o f DB o r DX block insufficient 2.1 1.8 Transferring Data Blocks to Flag Area: OB 191 and OB 193 Organization blocks OB 191 and OB 193 can b e used t o transfer data from a data block t o a flag area. In this way, f o r instance, flag bytes previously "saved" into a data block can be written back into t h e flag area. OBs 1911193 differ from OBs 1901192 i n as far as source and destination are exchanged: Flags OB 1901192: Flag area OB 1911193: Flag area ) Data block Data 4 Data block Technical Description CPU 945 Manual Note A sufficiently long data block (DBJDX) must b e opened before calling OB 191/193! OBs 191J193 transfer flags f r o m t h e data block o n l y i n t o the F flag area b u t n o t i n t o t h e S f l a g area. OB 191 and OB 193 are identical apart f r o m t h e manner i n which t h e data is transferred: OB 191 transfers data words byte by byte. OB 193 transfers data words w o r d by word. The diagram b e l o w illustrates t h e difference. Data block OB 191 W Flag FYO DWO Data block OB 193 * Flag DWO FYO DW1 FY 1 DW2 FY2 DW3 FY3 Figure 2-19 Byte-By-Byte (OB 191) and Word-By-Word (OB 193) Transfer CPU 945 Manual Technical Description Parameters: Source specifications: Number o f the first data word t o be transferred i n the open data block: 0 t o 65529 (0 t o FFF9") Destination specifications: First flag byte t o be written, permissible range: 0 t o 255 Last flag byte t o be written; permissible range: 0 t o 255 (Last flag byte 2 First flag byte) If t h e special function OBs 1911193 are processed correctly, the RLO is deleted (RLO = 0 ) . The RLO (RLO = 1) is set i n t h e case o f an error. Possible Errors: No DB or DX block open Wrong flag area (last flag byte < first flag byte) No data w o r d number available Length o f DB or DX block insufficient Example 1 : Prior t o calling program block PB 12, all flags (FY 0 t o FY 255) are t o be saved into data block DX 37 from address 100 onwards and then written back t o t h e flag area. :CX I)X 3 7 :I, KY 0 , 2 5 5 l~L,A<:Al<EA FROM FY 0 CO FY 2 5 5 .I, K13 1 0 0 NUMI3RII 01' F 1 l7S'I' DATA WORII l N I I E S T I N A T J O N :JU OR 1 9 0 W R I T E UACK T O O R I G I N : ( IIATA R LOCK A I ,RI<ADY CALLED :L Kn :I, KY 0 , 2 5 5 100 Execution times: OB191: 1 3 p + n.1.85ps O B 1 9 3 : 1 2 p s + n.1.3ps NIJMBRK 01" I<lR:;T UP) IIA'L'A WORD I N SOTJRCE FT,AG AREA FROM b'Y 0 TO 17Y 2 5 5 (n: number o f bytes) (n: number o f bytes) Technical Description CPU 945 Manual Example 2 for OB 190/0B191: Flags used for cyclic execution o f t h e user program cannot be used by a time or interruptcontrolled user program at t h e same time. To each program execution level, a certain section o f the flag area must be assigned. Example: Cyclic user program: Time-controlled user program: Interrupt-controlled user program: FY 0 FYIOO FY 200 ... . ... ....... ... . ... FY 99 FY199 FY 255 If, however, t h e cyclically processed user program uses all o f the 256 flag bytes and, f o r instance, the time-controlled user program also requires all o f the 256 flag bytes assigned t o it, all flags must be changed and buffered when changing t o t h e next execution level. The fastest way o f saving and loading flags is by means o f the special functions provided by OB 192 and OB 193. Figure 2-20 shows h o w t h e flag area FY X t o FY y, which is commonly used by OB 1 and OB 13 (100 mstimed interrupt), is buffered i n a data block DB z. OB 13 DB z OB 190 FYxFYY I I - OB 191 Save DW a-b W t h e FYs DB z D W a-b Write FYs back t o flag area - * ~y _ FYY Figure 2-20 Saving Flag Areas when Changing the Program Execution Level /1\ Caution Coordination bytes CBSICBR (flag bytes or DL) defined f o r SlNEC L1, ASCll driver or computer link may n o t be saved or reloaded since CBSICBR are controlled by t h e operating system independent o f t h e user program cycle. EWA 4NEB 81 1 61 50-02d CPU 945 Manual Technical Description STEP 5 Program in OB 13 :L KY 0 , 2 5 5 :I, KB 0 D E F I N E FLAG AREA FROM 0 TO 2 5 5 FLAG BYTES ARE STORED I N DB FROM DW 0 ONWARDS :JU OB 1 9 0 TRANSFER FLAGS BYTE BY HYTE TO DB :L KB 1 2 8 LOAD NEW DATA FROM DB FROM DW 1 2 8 ONWARDS :L KY 0 , 2 5 5 FLAG AREA FROM 0 TO 2 5 5 :JU OB 1 9 1 TRANSFER DATA BYTE BY BYTE TO FLAG AREA :C DI3 1 0 0 OPEN DATA SAVE DB :L KY 0 , 2 5 5 SAVE FLAG BYTES FROM 0 TO 2 5 5 BYTE BY BYTE I N DB FROM DW 1 2 8 ONWARDS :L KB 1 2 8 :JU OB 1 9 0 :I, KB 0 RELOAD DATA BYTE BY BYTE FROM DW 0 O F DB :L KY 0 , 2 5 5 I N T O FLAG AREA FROM 0 TO 2 5 5 :JU OB 1 9 1 BLOCK END : BE Other Applications of OBs 190 t o 193 High-order byte and low-order byte can be exchanged in the data block without great effort by transferring data words t o the flag area and reloading them in the DB, as shown in Figure 2-21. Data frames can be "shifted" within a data block if you specify the same DB No. but a different data word when reloading the data from the flag area. Data block Flag Data block ~IOB193.~~~y DWx +l FYy+I O B 1 9 0 r ~ ~ w DWx+I Figure 2-21 Exchanging High-Order Byte and Low-Order Byte in a D6 Using OB 193/0B190 x Technical Description CPU 945 Manual 2.1 1.9 Extension for Sign: OB 220 This special function extends the sign o f a 16-bit fixed-point number in ACCU I - L t o the higherorder word (ACCU l-H): If bit 215 = 0 (positive number), KH 0000 is ioaded in the higher-order word. If bit 215 = 1 (negative number), KH FFFF is loaded in the higher-order word. This extension is necessary for converting a negative 16-bit fixed-point number into a 32-bit fixedpoint number prior t o a fixed-pointlfloating-point conversion (32-bit, FDG statement). Parameter: 16-bit fixed-point number Possible Errors: None Execution time: 3 p s Reading the Digital Inputs Into the Process Image of the Inputs with 0B254 Calling OB254 (JU OB254 or JC OB254) causes the digital inputs t o be written new into the process image of the inputs (PII). When 0B254 is called, the digital inputs are read in new at the call point. This takes place regardless o f whether bits 1 t o 7 in system data word 120 are set. These bits are responsible for enabling cyclic reading in or parallel process I10 image transfer (see Section 2.8.2,6.3.1,6.3.2). Please note the increase in the runtime o f OB254 when parallel process I10 image transfer is set. If 0B254 is called while a parallel PI1 transfer is running, the system waits until this is terminated and the result of the PI1transfer has been entered in the PII. while a parallel PIQ transfer is running, the system waits until this is terminated and until the PI1transfer has subsequently been executed. EWA 4NEB 81 1 61 50-O2d CPU 945 Manual Technical Description 2.11.11 Sending the Process Image of t h e Outputs to the Digital Outputs w i t h 0B255 Calling OB255 causes t h e process image o f the outputs (PIQ) t o be sent t o t h e digital outputs. In 0B255, the PIQ is alwys sent t o t h e 110s a t t h e call point. This takes place regardless o f whether bits 2 t o 7 in system data word 120 are set. These bits are responsible for enabling cyclic output o f the process image o f t h e outputs (see Section 2.8.2,6.3.1,6.3.2). Please note the increase in t h e runtime o f 0B255 when parallel process l10 image transfer is set. If 0B255 is called while a parallel PIQ transfer is running, t h e system waits until this is terminated and until t h e PIQ has been output again while a parallel PI1 transfer is running, t h e system waits until this is terminated and until the PIQ transfer has subsequently been executed. EWA 4NEB 811 61 50-02d Technical Description CPU 945 Manual 2.1 1.l2 PID Control Algorithm: OB 251 The operating systems o f t h e central processing units have an integral PID control algorithm which you can use f o r your o w n purposes w i t h t h e help o f organization block OB251. Before calling OB251, a data block (PID controller DB) containing t h e controller parameters and other controller-specific data must be opened. The PID control algorithm is called periodically (sampling interval) and generates the manipulated variable. The more closely the sampling interval is observed, t h e more accurately can t h e controller fulfil1 i t s appointed task. The control parameters specified in t h e controller DB must be matched t o the sampling interval. Typically, timed interrupts are serviced by a timed interrupt OB (OBIO t o OB13). Timed interrupt OBs can be called a t intervals between 1 ms and 1 min. The maximum execution time o f t h e PID control algorithm is 110 ps. YH (STEU BIT 3 a t 0) dYH (STEU BIT 3 a t 1) Z W 1 I X l I 1 0 % ---------- 1 I I I I I I * > - X PI D algorithm (STE U a t 1) (STE U a t 0) F I I I I STEU BIT 3 I 4 A I I L-----I------c-------I--J K R TI TD A STEU BGOG BGUG Figure 2-22 Block Diagram of the PID Controller Legend : K = Proportional coefficient R K>O positivecontrol direction K<O negative control direction = R parameter (usually 1000) TA = Sampling interval TN = = = = TV Integral-action time Derivative-action time TAITN Y dY YH = Manipulated variable = Correcting increment = Value f o r manual input dYH = Correcting increment for manual input BGOG = Upper limiting value BGUG = Lower limiting value = Actual value X Z = Disturbance variable TD TVITA STEU = Control w o r d XZ YA = Substitutevariable f o r system deviation = Controller output: manipulated variable W = Setpoint dYA = Controller output: correcting increment XW = System deviation TI limited limited CPU 945 Manual Technical Description The continuous action controller is designed f o r controlled systems such as those used i n pressure, temperature, or f l o w rate control. The "R" parameter sets t h e proportional component o f the PID controller. If proportional action is required, most controller designs use t h e value R = 1. The individual proportional-action, integral-action, and derivative-action components can be deactivated via their parameters (R, TI, and TD) by presetting the pertinent data words w i t h zero. This enables you t o implement all required controller structures without difficulty, e.g., PI, PD, or PID controllers. You can forward the system deviation XW or, using t h e XZ input, any disturbance variable or the inverted actual value X t o t h e differentiator. Specify a negative K value f o r an inverted control direction. When t h e correction information (dY or Y) is a t a limit, t h e integral-action component is automatically deactivated i n order n o t t o impair t h e dynamic response o f t h e controller. The switch settings i n t h e block diagram are implemented by setting t h e associated bits i n control word STEU when the D controller is initialized. Technical Description CPU 945 Manual Table 2-30 Descri~ti0r-iof the Control Bits in Control Word STEU AUTO Manual mode The following variables are updated i n Manual mode: 1) X, XWK-, and PWK.~ 2) XZK, XZK., and PZK-l, when STEU bit 1= 1 3) ZK and ZK.,, whenSTEU b i t 5 = 0 Variable dDK-, i s set t o 0. The algorithm is n o t computed. ~ 1 I XZ EIN l Automatic mode XWk is forwarded t o the differentiator. The XZ input is ignored. Avariable otherthan XWk is forwarded t o the differentiator. I 2 REG AUS Normal controller processing When the controller is invoked (0B251), all variables (DW 1 8 t o DW 48) w i t h the exception of K, R, TI,TD, BGOG, BGUG, YHkand Wk are reset i n the controller DB. The controller is deactivated. 3 GESCHW Correction algorithm Velocity algorithm HANDART 5 NO Z When GESCHW=O: Following t h e transfer t o Manual mode, t h e specified manipulated variable value YA is adjusted exponentially t o the manual value i n four sampling steps. Additional manual values are then forwarded immediately t o the controller output. When GESCHW= 1: The manual values are forwarded immediatley t o the controller output. The limiting values are i n force i n Manual mode. 1 When GESCHW=O: The manipulated variable last output is retained. When GESCHW= I: Correction increment dYK is setto zero. 0 With feedforward control No feedforward control 1 6t015 The PID algorithm uses these bits as auxiliary flags. The control program can be supplied with fixed values or parameters. Parameters are input via the assigned data words. The controller is based on a PID algorithm. Its output signal can be either a manipulated variable (correction algorithm) or a manipulated variable modification (correction rate algorithm). EWA 4NEB 81 1 61 50-O2d CPU 945 Manual Technical Description Correction Rate Algorithm The relevant correction increment dYk is computed a t instant t = k *TA according t o t h e following formula: Without feedforward control (D1 1.5= 1); XW is forwarded t o the differentiator (D1 1.1 =0) dYk = K[(XWk- XWtl) R+TI *XWk++(TD (XWk- 2XWk.l f XWk.,) = K(dPWk dlk dDk) + + + dDk.,)l W i t h feedforward control (D11.5=0); XW is forwarded t o t h e differentiator (D1 1.1 =0) dYk = K[(XWk- XWk-,) R+TI XWk++ (TD (XWk- 2XWtl = K (dPWk dlk dDk)+dZk + + XWk.2) + dDk.i)I +(Zk-Zk-i) Without feedforward control (D1 1.5= 1); XZ is forwarded t o the differentiator (D1 1.l = 1) dYk = K[(XWk- XWk.,) R+TI XWk+t(TD (X&- 2XZk.l = K (dPWk dlk + dDk) * , + XZk.2) + dDk.l)I W i t h feedforward control (D1 1.5=0); XZ is forwarded t o the differentiator (D1 1.l = 1) dYk = K[(XWk- XWkq) R+TI * X W k + t (TD (XZk- ZXZk-r P component 1 XZk.2) f dDk.,)I +(Zk-Zk.l) \ L l component D component Z component k: kth sample When XW, is applied When XZ is applied: The result is: dPWk dik dDk dZk - TI *XWk - +(TD*QW,+dD,,) - +(TD*QZk+dDk.,) when XZ is applied Zk- Zk-l - (XWk- XWk-1)R when XW is applied Correction Algorithm The formula used t o compute t h e correction rate algorithm is also used t o compute t h e correction algorithm. In contrast t o t h e correction rate algorithm, however, t h e sum o f all correction increments computed (in DW48), rather than t h e correction increment dYkis output a t sampling instantt,. A t instant t,, manipulated variable Yk is computed as follows: EWA 4NEB 81 1 61 50-02d Technical Description CPU 945 Manual Initializing the PID Algorithm OB251's interface t o i t s environment is the controller DB. All data needed t o compute the next manipulated variable value is stored in this DB. Each controller must have its own controller data block. The controller-specific data are initialized in a data block that must comprise at least 49 data words. An error code is entered in ACCU 1 and the CPU goes t o STOP with a transfer error (TRAF) i f no DB has been opened or if the DB is too short. Possible Errors: Table 2-31 Possible Errors /1\ Caution Make sure that the right controller DB has been invoked before calling control algorithm OB251. Proportional coefficient (- 1500t o + 1500) for controllers with D component* trol direction is negative; the specified value is multiplied with the Normally 1 for controllers with P component: the specified value is multiplied with the factor 0.001**. Integral-action time TN The specified value is multiplied with a factor of 0.001**. 7 TD Constant TD 10 t o 9991 Derivative-action timeTV TD= Sampling interval TA A * " Larger gains are possible if abrupt changes t o the system deviation are sufficiently small. Large changes of the system deviation should therefore be divided up into small changes; e.g. by feeding the setpoint via a ramp function. The factor 0.001 is an approximate value. The precise value forthe factor is 111024 or 0.000976. CPU 945 Manual Technical Description Table 2-32 Format of the Controller DB (Continued) 24 z Disturbance value (- 2047 t o +2047) 29 xz Derivative time (- 2047 t o 48 YA Output variable (- 2047 t o t 2047) + 2047) All parameters (with the exception of the control word STEU) must be specified as 16-bit fixed point numbers. Note The PID algorithm uses the data words that are not listed in the table as auxiliary flags. Initializing and Invoking the PID Controller in the STEP 5 Program A number o f different PID controllers can be implemented by calling OB251 repeatedly, so make sure that the relevant controller DB has been invoked before calling OB251. Note Important controller data are stored in the high-order byte o f control word DW 11 (DL 11). Make sure that only write access via T DR 11/SU D 11.0 t o D 11.7 or RU D 11.0 t o D 11.7 operations i s used t o modify user-specific bits in the control word. CPU 945 Manual Technical Description Selecting the Sampling Interval The value selected as sampling interval must not be excessiveley high in order t o be able t o use the well-known analog method in the case of digital control loops. Experience has shown that a sampling interval o f approximately 1/10 o f the counter constant T,,' produces a control result comparable t o the equivalent analog result. Dominant system time ~onstantT,~,,, determines the step response o f the closed control loop. In order t o ensure constant sampling intervals, OB 251 must always be called up in the timed interrupt OB (OB 10 t o OB 13). X t TA = Controlled variable = Time = Sampling time TRKdom= Dominant system time constant W = Reference xd = System error variable/setpoint Figure 2-23 Estimating the Dominant System Time Constant (TRKdom) Example for the Use of the PID Control Algorithm Using a PID controller t o keep an annealing furnace at a constant temperature. The temperature setpoint is entered via a potentiometer. The setpoints and actual values are acquired using an analog input module and forwarded t o the controller. The computed manipulated variable is then output via an analog output module. The controller mode is set in input byte 0 (see control word DW 11 in the controller DB). You must use the well-known controller design procedure t o determine how t o tune the controller for each controlled system. * TRKdom= Dominant system time constant 2-84 CPU 945 Manual Technical Descrip #ion 180 + Control byte (DRI 1) ---) -) Channel 0 W, PID control algorithm X Channel l --+D Manipulated variable Channel 0 L 08251 with controller DB (call in OB13) Setpoint adjuster I S5-115U PLC Analog input module (e.g. 6ES5 460) Analog output module (e.g. 6ES5 470) Controlled system Actual value l/> Temperature sensor Annealing furnace Final control Transducer I Fuel gas f l o w Figure 2-24 Process Schematic The analog signals of the setpoint and actual values are converted into corresponding digital values at each sampling instant. OB251 uses these values t o compute the new digital manipulated variable, from which, in turn, the analog output module generates a corresponding analog signal. This signal is then forwarded t o the controlled system. Technical Description CPU 945 Manual Invoking the controller in the program: :JU FB 10 PROCESS CONTROLLER NAME :REGLER 1 THE CONTROLLER'S SAMPLING INTERVAL DEPENDS ON THE TIME BASE USED TO CALL OB 13 (SET IN S D 9 7 ) . THE DECODTNG TIME OF T H E ANALOG INPTJT MODULES MUST BE TAKEN JNTO ACCOUNT WHEN SELECTING THE SAMPLING INTERVAL. CPU 945 Manual Technical Description NAME : REGJ,EI? 1 :C DB 30 OPEN CONTROLLER DB ................................ READ CONTROLLER'S CONTROL B I T S *R****************************** :L PY 0 :T FY 10 :T DR 11 READ CONTROLTIER'S CONTROL AND STORE I N D R 1 1 CAUTION: D L l l CONTAINS IMPORTANT CONTROL DATA FOR O R 2 5 1 THE CONTROL B I T MIJST THEREFORE BE TRANSFERRED WITH T D R l l TO PREVENT CORRUPTING OF D L l l *******R************************ READ ACTUAL VALUE AND S E T P O I N T ***************R**************** :A F 12.0 FLAG 0 :R F 12.0 FE3 2 5 0 ) FLAG 1 :AN F 12.1 :S F 12.1 :JU FB 2 5 0 ( F O R UNUSED FUNCTIONS I N READ ACTUAL VALUE NAME : R L G : A E MODULE ADDRESS I N P AREA BG : KY0,128 KNKD : KY 0 , G CHANNEL NUMBER 0 , OGR : KD + 2 0 4 7 + 0 4 UPPER L I M I T FOR ACTUAL VALUE LOWER L I M I T FOR ACTUAL VALUE F I X E D - P O I N T BIPOLAR UGR : KD - 2 0 4 7 + 0 4 EINZ : F 12.0 NO S E L E C T I V E SAMPLING XA : FD 22 BUFFER SCALED ACTUAL VALUE FB : F 12.2 ERROR B I T BU : F 1.2.3 RANGE V I O L A T I O N TBIT : F 12.4 ACTIVITY B I T ................................ ADAPT ACTUAL VALUE TO KF FORMAT *****************R************** :L FD 22 :GFD :T LOAD ACTUAL VALUE I N ACCU 1 CONVERT I N T O F I X E D - P O I N T VALUE DW EWA 4NEB 81 1 61 50-02d 22 TRANSFER VALUE TO CONTROLLER DB Technical Description CPU 945 Manual ..................... ....... ................................................ ........................ ............................................................. ................................................................................................................................ ..... .... ,. :.:.:.::.:+:::: ...v. :.:.:.:.:.:.:.:j::~::~:~iIi~<<::~~~..Z:::.:.:...:~:.:"..:~.~:::::::::::::::::::::::~: >:,:,:,:,:,:,:::::*:::::<:.:.:.::: ;$; ..... .... .............................................................................................. g g ~"""".'.'."" @ ~ !.............................................. ; .&:.:..::.:,:,>:.:.:,:,:,:,:,:,:,:,:,:,: ~ $ ~ ) i.............................. f i $ ~ ~...:::$:::;::;$;: $ ~ ~ i $ $ $ $ $ ; ~ ~ ~ ~ ..... : ....... ............................................... ................................................ ............................. ....................... ..................... ...................................... ......................................................................... ::.:.:.:.:.~:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:,:.:.:.:.:.:,~:.:.:.:.:.:,:,:,:,:.>:.:.:.:.:.:.:< ........................................ .............................. ................................................................................................................................................................. ...................................................... . .................................................................................................... ....................................................................... " :::::::::fi:&$g+g~'@$~@~@&Bgn. mmm@$iiij ~~~j~&g&jjISiEsg&f ; """""" : J U FB 2 5 0 READ S E T P O T N T NAME : IILG :AE BG : KF 0 , 1 2 8 MODULE ADDRESS KNKD : KY 1 , 6 CHANNEL N O . OGR : KD + 2 0 4 7 + 0 4 UPPER L I M I T FOR S E T P O I N T UGR : KD - 2 0 4 7 + 0 4 LOWKR L I M I T FOTi S E T P O I N T ETNZ : F XA : FD 12.0 6 I , FIXED-POINT BlPOLAK NO S E 1 ) E C T I V E S A M P L I N G B U F F E R SCALED S E T P O J N T FB : F 13.1 ERROR B I T BU : F 13.2 RANGE V I O L A T I O N TBIT : F 13.3 ACTIVITY B I T ................................ ADAPT S E T P O I N T TO K F FORMAT **R***************************** :L L,OAD S E T P O I N T I N ACCU 1 F D 6 :GFD CONVERT TO F I X E D - P O I N T VALUE DW 9 T R A N S F E R VALUE TO CONTROLLER DB :A F 10.0 I N MANUAL MODE, :J C =WEIT TO FORCE THE CONTROLLER :T THE S E T P O I N T J S S E T TO THE ACTUAL VALUE :L DW 22 :T DW 9 TO REACT TO A S Y S T E M D E V I A T I O N , I F ANY, WIT11 A P S T E P ON T R A N S F E R TO AUTOMATIC MODE WEIT : ............................ : J U OB 2 5 1 INVOKE CONTROLLER ................................ ****************R*************** OUTPUT MANIPULATED V A R I A B L E Y ................................ :L DW 48 : S P A OB 2 2 0 LOAD MRN. VAR. Y FROM CONTROLLER DB I N T O E X T E N S I O N FOR S I G N ACCU 1, CONVERT TO F I X E D - P O I N T FORMAT : FDG :T FD 48 :JU FB 2 5 1 BUFFER I N FD 4 8 NAME :RLG:AA XE : FD BG : KY0,176 KNKD : KY 0,l CHANNEL 0 , OGR : KD + 2 0 4 7 + 0 4 U P P E R L I M I T FOR ACTUATING S I G N A L UGR : KD - 2 0 4 7 + 0 4 LOWER L I M I T FOR ACTUATING S I G N A L FB : F 13.5 ERROR B I T WHEN L I M I T I N G VALUES D E F I N E D BU : F 13.6 RANGE V I O L A T I O N :BE 48 FORWARD MAN. VAR. Y T O ANALOG OUTPUT MOD. MODULE ADDRESS FIXED-POINT BIPOLAR CPU 945 Manual Technical Description K PARAMETER(HERE=l),FACTOR 0 . 0 0 1 (VALUE RANGE: KF = +01000; - 3 2 7 6 8 TO 1 2 7 6 7 ) 11 PARAMETER(IIEKE=l) !FACTOR 0 . 0 0 1 KH = 0000; (VALUE RANGE: KF = +00010; TT=TA/TN(EIEIiE=0.0l),FACTOR 0 . 0 0 1 - 3 2 7 6 0 TO 3 2 7 6 7 ) KH - 0000; (VALUE RANGE: 0 TO 9 9 9 9 ) KF = +00010; TD=TV/TA KH = 0000; (VALUE RANGE: 0 TO 9 9 9 ) KF = +00000; SETPOINT W, KH = 0000; (VALUE RANGE: KM = 00000000 00100000; CONTROL, WORD KF = +00500; MANUAL VATjUE Y H , KH = 0000; (VALUIC RANG):: KF = t02000; UPPER CONT. LIMIT BGOG, KH = 0000; (VALIJE RANGE: (IIERE-10) , FACTOR 1 FACTOR 1 - 2 0 4 7 TO 2 0 4 7 ) FACTOR 1 - 2 0 4 7 TO 2 0 4 7 ) 16 : KF = -02000; LOWER CONT. LIMIT BGUG, 17: KH = 0000; (VALUE RANGE: 18: KH = 0000; 19: KH =- 0000; 20: KH = 0000; 21: KH = 0000; 22 : KF = +00000; ACTUAL VALUE X , 23 : KH = 0000; (VALUE RANGE: 24 : KI: = +00000; DISTURBANCE VALUE Z , 25 : K11 = 0000; (VALUE RANGE: 26 : KM = 0000; 27 : K11 = 0000; 28 : KH = 0000; FACTOR 1 - 2 0 4 7 TO 2 0 4 7 ) KF = t00000; FORWARD X Z FOR D I F F . , KH = 0000; FACTOR 1 , 31: KH = 0000; 0000; KH = KB = 0000; 34 : KH = 0000; ( - 2 0 4 7 7'0 2 0 4 7 ) 35 : KH = 0000; 36 : KH = 0000; 37: KH = 0000; 38 : KH = 0000; 39 : KH = 0000; 40: KH = 0000; 41 : KH = 0000; 42: KH = 0000; 43: KH = 0000; 44 : KH = 0000; 45: KH = 0000; 46 : KH = 0000; 47: KH = 0000; 48: K!? = +00000; CONTROLLER OUTPUT Y , 49 : KH = 0000; (VALUE RANGE: 50 : EWA 4NEB 81 1 61 50-02d FACTOR 1 - 2 0 4 7 TO 2 0 4 7 ) 29 : 32 : FACTOR I - 2 0 4 7 TO 2 0 4 7 ) 30 : 33 : FACTOR 1 - 2 0 4 7 TO 2 0 4 7 ) FACTOR 1 - 2 0 4 7 TO 2 0 4 7 ) 3.1 3.1.1 3.1.2 Mounting Racks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Central Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Expansion Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . 1 3 . 2 3 . 4 3.2 3.2.1 3.2.2 Mechanical Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Installing the Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Installing Fans . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . 7 3 . 7 3 .10 3.3 3.3.1 3.3.2 3.3.3 .. . . . . . . . . . . . . . Configurations .............................. . Centralized Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Distributed Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . Connection Possibilities with Other SIMATIC S5 Systems . . . . . . . . . 3 .11 3 .12 3 .14 3 .20 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 Wiring the Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connecting the PS 951 Power Supply Module . . . . . . . . . . . . . . . . . . . Connecting Digital Modules . . . . . . m , . . . . . . . . . . . . . . . . . . . . . . . . - . Connecting Analog Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Front Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simulator . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . 3 3 3 3 3 3 .22 .23 -24 3.5 3.5.1 3.5.2 3.5.3 3.5.4 3.5.5 3.5.6 3.5.7 3.5.8 3.5.9 Guidelines for Interference-Free Design o f the PLC . . . . . . . . . . . . . . Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Installation with Field Devices . . . . . . . . . . . . . . . . . . . . . . . . Connecting Nonfloating and Floating Modules . . . . . . . . . . . . . . . . . Running Cables Inside a Cabinet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Running Lines Outside Buildings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Taking Measures Against Interference Voltage . . . . . . . . . . . . . . . . . Shielding Devices and Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Equipotential Bonding in the Case o f Distributed Configurations . Special Measures for Interference-Free Operation . . . . . . . . . . . . . . . 3 3 3 3 3 3 3 3 3 3 .25 .25 .27 .32 .34 .35 .35 .36 .38 .38 3.6 Safety Measures and Monitoring Facilities ...................... .21 .21 .22 3 .40 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.1 0 3.1 1 3.1 2 3.1 3 3.14 3.1 5 3.1 6 3.1 7 3.18 3.19 3.20 3.21 3.22 3.23 3.24 3.25 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 Expansion Unit 1 (Example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Installingthe Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slot Coding Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . Installation of a Printed Circuit Board into an Adapter Casing (6ES5491-OLBll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Installing the Fan Subassembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Subassembly Terminal Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Centralized Configuration with the IM 305 and IM 306 lnterface Modules Switch and Jumper Settings on the IM 304.3UBl . for Distributed Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Jumper Settings on the IM 314 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switch Position on the IM 314 for Addressing in the 0 Peripheral Area . . . Distributed Configuration with IM 304lIM 314 . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Module PS 951 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connection t o Floating and Nonfloating Modules . . . . . . . . . . . . . . . . . . . . . . Front Connectors .Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Installing the Front Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating a Programmable Controller with Field Devices on Grounded Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating a Programmable Controller with Field Devices on Centrally Grounded Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating a Programmable Controller with Field Devices on Nongrounded Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simplified Representation o f an lnstallation with Nonfloating Modules . . Simplified Representation for Installation with Floating Modules . . . . . . . . WiringCoils . . . . . . . . . . . . . . . . . . . . . . ............................. Measures for Suppressing Interference from Fluorescent Lamps inthecabinet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Possible Configurations on the CR 700-... Mounting Rack ............... Possible Configurations on the ER 700-... Mounting Rack . . . . . . . . . . . . . . . . Comparison of the IM 305 and IM 306 Interface Modules . . . . . . . . . . . . . . . . Technical Specifications of the lnterface Modules for Distributed Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connection o f the 55-115U System t o other SlMATlC S5 Systems . . . . . . . . . Front Connector Overview ........................................... Overview of the Power Supply Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rules for Common Running of Lines .................................. 3 . 4 3 . 7 3 . 8 3 . 9 3 . 10 3 . 11 3 . 13 3 3 3 3 3 3 3 3 3 .16 . 18 .18 .19 .21 .22 .23 .24 .24 3 .29 3 .30 3 .31 3 .32 3 .33 3 -38 3 .39 3 . 3 3 . 6 3 .12 3 .15 3 .20 3 .23 3 .24 3 .34 CPU 945 Manual 3 lnstalla tion Guidelines Installation Guidelines Programmable controllers o f the 55-115U system consist of a central controller t o which you can connect several expansion units if required. This chapter tells you which different mounting racks are available for the different central controllers and expansion units how the modules are mounted on the mounting racks how you can implement the connection between a central controller and one or more expansion units with the IM30411M314 interface module how you must wire your programmable controller In addition, this chapter contains all the important rules for the noise-immune configuration of your programmable controller. 3.1 Mounting Racks Various mounting racks are available t o suit the performance or the degree of expansion the control system is t o have. Each mounting rack consists of an aluminum mounting rail for fastening all modules mechanically and one or t w o backplanes for connecting the modules t o each other electrically. The module locations (slots) are numbered in ascending order from left t o right (see Figure 3-1). Figure 3.1 Typical Mounting Rack (CR 700- 1) EWA 4NEB 81 1 61 50-02d installation Guidelines CPU 945 Manual 3.1 .l Central Controllers A central controller has a power supply module (PS), a central processing unit (CPU), and various inputloutput modules (110s). Depending on requirements, digital or analog modules, communications processors (CPs), or intelligent inputloutput modules can be used. Figure 3-1 shows a basic CC configuration. Figure 3-2 Typical Central Controller We offer you five different mounting racks for mounting your central controller: CR 700-OLAI 2 and CR 700-OLBI 1 CR700-1 CR 700-2 CR700-3 The first t w o slots o f all mounting racks contain a power supply module (PS) and a central processing unit (CPU). The mounting racks differ in the number of slots (4 or 7 110 modules) and configuration possibilities. EWA 4NEB 81 1 61 50-02d CPU 945 Manual Installation Guidelines The following table gives you an overview o f the configuration possibilities the various mounting racks of a central controller. Table 3-1 Possible Configurations on the CR 700- ... Mounting Rack Power supply PS PS3 PS3 PS3 PS3 CPU CPU CPU CPU CPU Digital modules (block type) Oto3 1,2 0 to 6 0 to6 3to 5 Digital modules (PCBsl 0 0to 2 0 0to5 0to5 Analog modules (block type) 0to3 1,2 Oto6 Oto6 3to 5 Analog modules (PCBS') 0 0to 2 0 0to5 0to 5 IM 305/3062 IM IM IM IM IM 3 6 6 0 t o 3' Oto 6' 0 to 6 3 6 6 CPU IM 3041308' IM 307 AS 3011302' CP 530-7 0 1,2 0 0to 5 3t05 CP 523' 0 Oto2 0 0t o 5 0to 5 CP 516'1524'1 52511528'/530-311 544' Oto2 0to5 0 to 5 CP 5261527 basic board1/528 Oto2 0to 5 0to 5 CP 5261527 expansion board' CP 5430'15431" CP 552-2' CP 535-3MA12'1 CP 143-OAB01' CP 5801581' - 0 04, '1 Oto2 0to5 0 t o 2' OS OS, 1,2 Ot02~,3to5 0to5 O6 Ot02~,3to5 0 t o 26 In adapter casing If neither the IM 305 nor the IM 306 interface module is plugged in, the termination connector must not be removed Use of the IP 2461247 and the CP 51315241525152615271535/580/581/143 and WF 705/706170717211723 is not permissible with a 3 A power supply module. Order No. 6ES5 951-7LB1417NBI3, (the DSI signal i s not generated by the 3 A power supply). CPs 5241525 must not be used with 3 A power supplies because their power consumption is too high Can only be used in the lefthand slot when operated without fan Righthand slot cannot be used because of double-width module Righthand slot cannot be used because of quadruple-width module lnterrupt processing not possible in slot 3 lnterrupt processing not possible in slot 6 Not in operating mode with interrupt processing, except for digital input module 432-4UA11 EWA 4NEB 81 1 6150-02d Installation Guidelines CPU 945 Manual Table 3-1 Possible Confiaurations on the CR 700- ... Mountina Rack (Continued) M~dtlle 8capied Slots an the Mountin-gR& CR3#0-3 i 1 In adapter casing Righthand slot cannot be used because of double-width module Direct I10 access of IP 252 only in slots 0, 1.2; if 3 A power supply is used, direct I10 access is generally not possible (HOLD and HOLDA signals are not provided) 3.1.2 Expansion Units If the central controller does not have sufficient slots for the whole PLC, it is possible t o include one or more expansion units. Depending on the type of connection, there are four subracks available for expansion units: ER701-0 ER 701-1 ER701-2 ER 701-3 Figure 3-3 Expansion Unit 1 (Example) EWA 4NEB 81 1 61 50-O2d CPU 945 Manual lnstallation Guidelines The following expansion unit interface modules connect EU 1 expansion units t o a central controller in centralized configurations (see Section 3.3.1): IM 305 IM 306 The following interface modules connect expansion units t o a central controller in distributed configuration (see Section 3.3.2): AS 3011310 8 AS 3021311 IM 3041314 IM 3071317 IM3081318 Areas of application of the ER 701-... mounting rack ER 701-01-1 mounting rack The ER 701-01-1 mounting rack is suitable for connecting a central controller locally (centralized connection). Interrupt-initiating modules cannot be used. The expansion unit is supplied over the interface module. Up t o three expansion units can be connected t o one central controller or t o one ER 701-2/ER 701-3. ER 701-2 mounting rack The ER 701-2 mounting rack is suitable for connecting a CR 700-21CR 700-3 locally and remote. Up t o three ER 701-1s can be connected t o one ER 701-2 over an IM 306. Interrupt-initiating modules cannot be used. The ER 701-2 can also be connected t o the 55-135U and 55-155U programmable controllers over the AS 310, AS 31 1, l M 314, IM 317 and IM 318 interface modules. ER 701-3 mounting rack Interrupt-initiating modules can only be used over the IM 3071317. Up t o three ER 701-1s can be connected t o one ER 701-3 over an l M 306. The ER 701-3 can also be connected t o the 55-135U, 55-150U and 55-155U programmable controllers over the AS 310, AS 31 1, IM 314, IM 317 and IM 318 central controller interface modules. lnstalla tion Guidelines CPU 945 Manual The following table gives you an overview o f the configuration possibilities of the various mounting racks of an expansion unit. Table 3-2 Possible Configurations on the ER 700-... Mounting Rack In adapter casing Only when using IM 306 Only when using IM 306; not permissible with connections using AS 3021311 Not permissible with connections using AS 302131 1 Use of the IP 2461247 and the CP 5131524/525/526/5271535/5801581/143 and WF 705/706170717211723 is not permissible with a 3 Apower supply module. Order No. 6ES5 951-7LB1417NB13, (the DSI signal is not generated by the 3 A power supply). CPs 5241525 must not be used with 3 A power supplies because their power consumption is too high Except 434-7 input module; 485-7 inputloutput module not in mode with interrupt processing Not permissible with connections using AS 3021311 Only with connections using I M 3041314and 3071317 Not in operating mode with interrupt processing, except for digital input module 432-4UA11 EWA 4NEB 81 1 6150-02d CPU 945 Manual 3.2 Installation Guidelines Mechanical Installation Fasten all modules on the appropriate mounting racks. The mounting racks must be enclosed in grounded metallic housings (e. g. switchgear cabinets). Figure 3.4 shows the prescribed method for mounting. You can also fasten the racks t o surfaces that are at an angle o f up t o 15" from a vertical surface. Block-type modules are mounted directly on the rack. Place printed circuit boards in double-height Eurocard format in adapter casings (see Figure 3.6). 3.2.1 Installing the Modules Any person opening the switchgear cabinet or switchbox should first provide for sufficient discharge of the body in order t o protect the modules against electrostatic discharge. Install block-type modules according t o the following procedure: m Remove the protective caps from the socket connectors on the backplane. m Hook the t o p o f the module into place between the t w o guides on the top of the mounting rack@. m Swing the module back until i t engages with the socket connectors on the backplanea. m Fasten the screws at the top and bottom of the module. Figure 3-4 Installing the Modules If the modules are subjected t o mechanical vibration, they should be installed as close together as possible. EWA 4NEB 81 1 61 50-02d Installation Guidelines /1\ CPU 945 Manual Warning Plug in or remove modules only when the power supply has been turned off. Mechanical slot coding On the back o f each module, with the exception of the power supply and central processing unit, is a slot coding element in the form of a two-part plastic cube. This coding element ensures that when one module is replaced, only another module of the same type will be plugged in in i t s place. The coding element consists o f t w o parts, one like a lock and one like a key. The t w o parts fit together in a defined position. This position is specific t o each type of module. When you install the module, the back o f the coding element is inserted into the mounting rack. When you swing the module out, the key-shaped part of the element stays in the mounting rack and the lockshaped part stays on the module. Now you can install only this particular module or an identical one in this slot. If you want t o install a different module, you have t o remove the coding element from the mounting rack. You can also work without slot coding. To do this, you must pull the coding element off the module before you swing the module into place for the first time. Figure 3-5 Slot Coding Element CPU 945 Manual lnstalla tion Guidelines Adapter casing Use an adapter casing (6ES5 491-OLB12, 6ES5 491-OLC11 oder 6ES5 491-OLD11) t o fasten printed circuit boards in double-height Eurocard format t o a mounting rack as you would fasten block type modules. Figure 3-6 installation of a Printed Circuit Board into an Adapter Casing (6ES5 497-OLBI I ) Installing an adapter casing ) ) ) Swing the adpater casing onto the mounting rack and screw it. Push the printed circuit board into the casing along the guide tracks. Lock the module into place with the eccentric locking collar at the top of the casing. If an opening remains on the front after the module has been inserted, cover i t with a blanking plate. Note A f a n is required for adapter casings with t w o printed circuit boards. EWA 4NEB 81 1 61 50-02d Installation Guidelines 3.2.2 CPU 945 Manual Installing Fans Installing fans Install a fan subassembly under the following conditions: If the power supply modules carry a load o f more than 7 A If the controller uses modules with a high power consumption, e.g., certain communications processors and intelligent inputloutput modules (see Chapter 1 5 "Technical Specifications"). The fan subassembly has t w o fans, a dust filter, and fan monitors with floating changeover contact. You need a set o f installation parts t o mount the fan subassemby. The set consists o f t w o installation brackets and a cable duct. The brackets support the fan subassembly and the cable duct. The cable duct enables you t o run the field cables o f f neatlyto the side. Install the fan subassembly as follows: O Use screws t o fasten the installation brackets onto the uprights o f the cabinet or on the mounting surface under the mounting rack. O The guide tracks on the brackets should be at the bottom. Hook the fan subassembly onto the guide tracks of the installation brackets and O Push it back. C9 Push the fan subassembly up and O Latch it into place with the t w o slides at the top of the installation brackets. O If the machine is subject t o vibration, secure the fan subassembly t o the installation brackets with screws (M 4 x 20 screws with washers). C 3 Hook the cable d u d into the installation brackets. Special features o f the fan subassmbly and installation parts enable you t o do the following: Use the cable d u d without the fan subassembly Install or remove the fan subassembly even when the cable duct is hooked on Screwthe fan subassembly t o the installation brackets through the cable duct Replace the filters while the unit is in operation (see Appendix B). Figure 3-7 Installing the Fan Subassembly CPU 945 Manual lnstalla tion Guidelines Connecting the fan subassembly Figure 3.8 shows the wiring necessaryto operate a fan subassembly. 1201230VAC N Mains selector switch - 4 -- 24VDC M & [I 1AT []600m~~ 6ES5 981OHA11 6- 8 - 115V 220V 6ES5981OHA2l 24 V DC M L+ 4 3 @ @ @ Figure 3-8 Fan Subassembly Terminal Assignment Afloating changeover contact gives a fault signal via terminals 1,2 and 3 if the fan fails. The diagram in Figure 3.8 shows the switch positions in the case of a fault! Under normal operating conditions, the contacts 1 - 2 are closed and the contacts 1 - 3 open. 3.3 Configurations The links between a central controller and expansion units are referred t o as configurations. We distinguish between t w o types of configuration: Centralized configuration Distributed configuration Centralized configuration Centralized configurations are connections between a central controller and up t o three expansion units over a distance o f up t o 2.5 m. The expansion units are supplied and connected t o the S 5 bus over interface modules. The possible distance and the number of expansion units are dictated by the type o f interface module in each case. Distributed configuration Distributed configurations are connections between one central controller and expansion units over a distance o f up t o 23.8 km. The possible distance and the number o f expansion units are dictated by the type of interface module in each case. EWA 4NEB 81 1 61 50-O2d CPU 945 Manual lnsta lla tion Guidelines 3.3.1 Centralized Configurations A CR 700-0/1/2 central controller connected via short connecting cables t o as many as three expansion units o f t h e type ER 701-1 makes u p a centralized configuration. Use only the I M 305 or IM 306 interface modules t o connect an ER 701-1 mounting rack. For centralized configuration w i t h t h e I M 305, please note the following points: You can use fixed slot addressing only (see Chapter 6). Addressing o n slot 0 o f t h e expansion unit always starts a t 28.0 regardless o f h o w many slots are available o n t h e central controller. The 0.5 m (1.6 ft.) connecting cable i s n o t long enough t o connect t h e EU under t h e CC. Use an IM 306 interface module or the I M 305 version w i t h a longer cable f o r such an arrangement. Table 3-3 Comparison o f the I M 305 and I M 306 Interface Modules Number o f expansion units (maximum) Total cable length a 3 0.5 m or 1.5 m maximum 2.5 m variable fixed Slot addressing I I Current supplied t o expansion units (maximum) * The expansion unit with the most current supplied should be as close to the central controller as possible. EWA 4NEB 81 1 61 50-O2d CPU 945 Manual Installation Guidelines Power Supply Module ** Central Processing Unit I M 306 lnterface Module I M 305 Interface Module 705 Connecting cable ** You can also order a 1.25 m (4.1 ft.) 705 connecting cable (Order No. 6ES5 705-08820) or a 2.5 m (6.7 ft.) 705 connecting cable (Order No. 6SE5 705-OBCSO), and use them t o mount two EUs nextto each other. Figure 3-9 Centralized Configuration with the I M 305and I M 306 lnterface Modules EWA 4NEB 81 1 61 50-O2d Installation Guidelines 3.3.2 CPU 945 Manual Distributed Configurations This chapter describes distributed configurations with the IM 3041314 interface modules. Distributed configurations using the following are not described here: AS301lAS310 AS 3021AS 31 1 IM 307lIM 317 IM 308 -3UA.. /IM 318-3UA.. (55-115U 110) or IM 318-8MA.. (ET 100U) IM 308-3UB.. IIM 318-8MB.. (ET 200U) or lM 418-8MB.. (ET 2OOK) You can order these interface modules with a separate description. Please note the following points concerning distributed configuration versions: Each ER 701-2 or ER701-3 expansion rack requires a PS951 power supply module and an IM 306 interface module for addressing inputloutput modules (Exception: ET 1001ET200). If the expansion units have their own power supply, please note the following: - When switching on: Switch on the power supplies o f the expansion units first and only then the power supply o f the central controller. - If you switch on the power supplies o f the central controllers and the expansion units at the same time, you must program a restart delay. See Section 3.5.7 (Shielding)! If you use digital input modules on the ER 701-2 or ER 701-3, it is recommended that you use modules with revision level "2" (or higher). EWA 4NEB 81 1 61 50-02d CPU 945 Manual Installation Guidelines Table 3-4 Technical Specifications of the interface Modules for Distributed Configurations * Number of EUs depends on the length of the fiber optic cable used and the ready delay time of the individual modules Distributed configurations w i t h the I M 304lIM 314 interface modules Using these interface modules, you can conned up t o 4 distributed expansion units per interface t o one central controller. Prerequisites are One IM 304 interface module must be installed on a CR 700-21-3-OLB mounting rack One lM 314 interface module must be installed on each ER 701-21-3 mounting rack The interface modules are linked via a connecting cable. The following sections show the different switch and jumper settings for The l M 304-3UB1. and TheIM314. EWA 4NEB 81 1 61 50-02d CPU 945 Manual Installation Guidelines Switch and jumper settings on the IM 304-3UBl. for distributed connection Figure 3-21 shows the positions of the switches and jumpers on the IM 304-3UB1. module. All switches on switch block S3 must be in the ON position. Figure 3- 10 Switch and Jumper Settings on the IM 304-3UBl. for Distributed Connection In Figure 3-21, the l M 304 has been set for distributed connection. Permissible cable length up t o 100 m (330 ft.) (X11) PEU signal (110s not ready) is located at Pin b18 o f the X2 base connector, (setting at X1 5) The PEU signal is generated by the IM 304 if atleast one interface reports "Not ready" (X14) An EU is connected t o both interfaces (X21 and X22). You can change the setting at jumpers X21, X22 as well as at X1 1, X14 and X1 5. You can switch the interfaces on or o f f with jumpers X21 and X22. ON lnterface is switched on OFF ON lnterface is switched o f f (no EU connected) OFF EWA 4NEB 81 1 61 50-02d CPU 945 Manual Installation Guidelines Use jumper X1 1 t o set t h e t o t a l length o f t h e 721 connecting cables o f one interface u p t o t h e last EU. The decisive factor f o r setting jumper X1 1 is t h e interface w i t h t h e longest connection line. I f you use IPs and CPs o n t h e EU, you must set t h e longest cable length! Jumpers X14 a n d X1 5 can b e set as follows f o r t h e IM 3041314 distributed connection: 1 PEU signal is generated if a t least one interface reports "Not ready". 2 3 3 2 1 PEU signal is generated only if both interfaces report 2 "Not ready". 1 (0001 3 I 2 1 PEU signal is not evaluated. PEU signal is evaluated. Note: When power is t u r n e d o n i n t h e EU o r i n t h e CC, manual cold restart (RN-ST-RN) is also necessary. Note I f t h e PEU signal is n o t evaluated, t h e f o l l o w i n g must b e ensured a t restart: The expansion u n i t is ready f o r operation before t h e central controller or A relevant w a i t i n g t i m e must b e programmed. I Installation Guidelines CPU 945 Manual I_ Switch and jumper settings on the IM 314 interface module for distributed connection Jumpers BR1 t o BR3 must be set as follows depending on the EU used: Using the lM 314 in the ER 701-2. ER 701-3 (55-1 15U) b BR1 Using the IM 314 in the EU 185U and EU ; : "1 3 BR3 2 1 m I I I Using the IM 314 in the EU Figure 3-1 1 Jumper Settings on the /M 314 If you use the 313 watchdog module in the EU, you must switch o f f the PESP (memory I10 select) monitoring facility on the watchdog module. The switch positions at S1 are preset on the IM 314 for the P area o f module addresses. Figure 3-1 2 shows the switch position o f S1 if you want t o address the I10 modules in the 0 peripheral area on the ER or in the EU. Figure 3- 12 Switch Position on the /M 314 for Addressing in the 0 Peripheral Area EWA 4NEB 81 1 61 50-02d CPU 945 Manual Installation Guidelines Distributed configuration w i t h I M 3041IM 314 interface modules After setting all the necessary switches and jumpers on the IM 4041IM 314 interface modules, you can set up the configuration in the PLC. ) ) ) b Install the IM 304 on a CR 700-21-31-OLB mounting rack Install the IM 314 on an ER 701-21-3 or EU 18311851186 mounting rack Link the modules with the 6ES5 721-... connecting cable Plug a 6ES5-760-1AA11termination connector into the lower front socket (X4) in the last IM 314 in each case. Figure 3-1 3 shows a connection example. 721 Connecting cable 721 Connecting cable 721 Connecting cable 721 Connecting cable IM 314 * lnterface Module c,:.:.:.:.:< .,.,.,.,.,.,.. .....,.,.,.,.. .....,.,...... IM 306 Interface Module Termination connector 6ES5 760-1AA You can conned up t o three ER 701-1 expansion racks here. * In adapter casing Figure 3- 13 Distributed Configuration with /M 304/IM 314 Connections with the IM 3041IM 314 interface modules have the following special features: Using the IM 3041IM 314 symmetrical interface modules, you can connect EUs on ER 701-2 or ER 701-3 expansion racks with full address bus t o CCs o f the 55-115U, 55-135U, 55-150U, and 55-1505 and 55-155U systems. Connection t o EU 183, EU 185 and EU 186 is possible. The potential difference between CC and EU must not exceed 7 V. An equipotential bonding conductor should therefore be provided (see Section 3.5.8)! lnstallation Guidelines 3.3.3 CPU 945 Manual Connection Possibilities with Other SIMATIC S5 Systems Central controllers and expansion units o f the 55-1 15U system can also be connected t o CCs and EUs o f other SIMATIC S5 systems. Table 3-5 shows the possible configurations. Table 3-5 Connection of the 55-1 15U Svstem to other SIMATIC S5 Svstems Centralized up t o 2.5 m (8 ft.) EG1 (ER 701-1) or 6ES5 306-7LA11 EG2 (ER 701-2 without PS) l Distributed up t o 200 m (650 ft.) EG2 (ER 701-2) 1 EG3 (ER 701-3) 6ES5 310-3AB11 1 Distributed up t o 600 m (2000 ft.) serial Distributed up t o 1000 m (3800 ft.) serial * ** No word-orientated 110 access (L PW; T PW) possible This connection is possible only i f a cold restart is prevented by t h e "STP" statement i n 0 0 2 2 Installa tr'on Guidelines CPU 945 Manual Wiring the Modules 3.4 The backplane on the mounting rack establishes the electrical connection between all modules. Make the following additional wiring connections: The PS 951 power supply module t o the power line The sensors and actuators t o the digital or analog modules. Connect the sensors and actuators t o a front connector that plugs into the contact pins on the front of each module. You can connect the signal lines t o the front connector before or after you plug it into the module. The connection diagram of each module is on the inside of the front door. Perforated label strips are included with each input and output module. Use these strips t o note the addresses o f the individual channels on the module. Slip the strips along with their protective transparent covers into the guides on the front door. Chapter 10 "Analog Value Processing" describes how transducers are connected up t o analog input modules and the feedback modules of the analog output modules. The following sections explain how t o connect individual modules. Please consult the appropriate operator's guide or manual for information on wiring the intelligent inputloutput modules and communications processors. 3.4.1 Connecting the PS 951 Power Supply Module Connect the PS 951 power supply module as follows: O Set the voltage selector switch O t o the appropriate voltage (only in the case o f AC modules). O Connect the power cable t o terminals L1, N and 0. -L VOLTAGE SELECTOR Figure 3- 14 POwer Supply Module PS 951 CPU 945 Manual Installation Guidelines 3.4.2 Connecting Digital Modules Digital modules are available in nonfloating and floating versions. For the nonfloating modules, the reference voltage of the external process signals (Mea) has t o be connected t o the internal reference voltage (Mint, i.e., PE) (see Figure 3.1 5). For floating modules, an optocoupler separates the external voltages from the internal ones. Floating Nonfloating - Reference bus (Mint) Figure 3-15 Connection to Floating and Nonfloating Modules Note See Chapter 6 "AddressingIAddress Assignment" for information on address assignment in the case of digital modules. 3.4.3 Connecting Analog Modules The connection of analog modules in described in Chapter 10 "Analog Value Processing". lnstalla tion Guidelines CPU 945 Manual 3.4.4 Front Connectors Various front connectors are available for wiring: Table 3-6 Front Connector Overview 6ES5 490-7LB11 Screw connection 6ES5 490-7LB21 46 Screw connection*** (box terminal) 46 Crimp snap-in (mini-spring contact) 1 X (1.0 or max. 1.5 mm2 in the case of combinations of conductors in one end sleeve 6ES5 490-7LA11 (with crimp snap-in contacts) 6ES5 490-7LA12 (without crimp snap-in contacts)z 1 2 * ** *** ... 2.5) mm2 1 X (0.5 ... 2.5) mm2 2 X (0.5 ... 0.75) mm2 or When plug-in jumpers are used, the conductor cross sectionsare reduced. Use crimp snap-in contacts with the order no. 6XX5 070 (Qty: 250) Flexible cable with end sleeves: 0.75 t o 1.5 mm2 With end sleeves: 0.5 t o 1.5 mm2 1.5 mm2with jumer comb In general, w e recommend use of end sleeves, especially where corrosion is t o be expected. Screw-type connections Crimp snap-in connections Spring-loaded connection - Figure 3- 16 Front Connectors Front View The connectors have openings at the bottom for standard strain-relief clamps. installation Guidelines CPU 945 Manual Installing the front connector Install the front connector as follows: 1. Open the front door of the module. 2. Hook the front connector in the pivot at the bottom of the module. 3. Swing the front connector up and in until it engages with the module. 4. Tighten the screw at the top of the front connector t o secure it. O Module O Front door is open O Frontconnectorin pushed back O Fastening screw O Pivot Figure 3-1 7 Installing the Front Connector 3.4.5 Simulator You can use an appropriate simulator instead of a front connector. Use the toggle switches on the front of this device t o simulate input signals (see Figure 3.18). Asimulator needs an external power supply. The simulators cannot be used in the case of mixed digital inputloutput modules or in the case of output modules. O Fastening screw O Screw-type terminals for supply voltage Figure 3- 18 Simulators CPU 945 Manual Installation Guidelines Guidelines for Interference-Free Design of the PLC 3.5 This chapter describes The circuits controller you must distinguish and the requirements made of the power supply mod U le 0 Connection and grounding concepts in the case o f higher-level supply from grounded, centrally grounded and nongrounded mains Connection o f power supply modules t o nonfloating and floating modules Routing cables t o ensure electromagnetic compatibility (EMC) and measures against interference voltage 3.5.1 Power Supply You require the following for a completely configured SlMATlC S5 controller Power supply with internal PLC circuits (control power supply module) and Load power supply modules for the input and output circuits (load power supply module). PS 951 control power supply module The control power supply module supplies the following CPU Programmer interface Control circuits o f the 110 modules. The following table gives you an overview of the power supply modules for an 55-115U. Table 3-7 Overview of the Power Supply Modules I201230 VAC 3A Yes 6ES5 951-7LB21 1201230 VAC 7A (1 5 A with fan) Yes 6ES5 951-7LD21 24 V DC 3A NO 6ES5 951-7NB21 5.2 V DC 24 V DC 7A (1 5 A with fan) No 6ES5 951-7ND51 24 V DC 24V DC 7A (15 A with fan) Yes 6ES5 951-7ND41 5VDC Note Please ensure that the control power supply module is not overloaded. Estimate the power consumption o f all modules. EWA 4NEB 81 1 61 50-02d Installation Guidelines CPU 945 Manual When using t h e different PS 951 power supply modules, you must note the following: a For t h e 6ES5 951-7ND41 floating module, the input voltage must be a functional extra-low voltage in accordance w i t h VDE 010015.73 5 8c or a comparable standard. Otherwise, t h e PE terminal must be conncted t o t h e protective ground wire. a For the 6ES5 951 7NB21/7ND41/7ND51 power supply modules, there is no galvanic isolation between t h e 24 V side and t h e 5 V side, whose reference potential is permanently connected t o t h e mounting rack. a The use o f t h e following modules is not permissible due t o t h e missing DSI signal i n the case o f t h e 3 A power supplies w i t h t h e order numbers 6ES5 951-7LB1417NB13: - IP 2461247 - CP 5131526/5271535/5801581/143. a The CP 5241524 must n o t be used w i t h 3 A power supply modules since their power consumption is t o o high. a Magnetic voltage stabilizers must not be connected direct on the input side o f power supply modules! If you use magnetic voltage stabilizers in parallel network branches, you must expect overvoltages t o occur as a result o f mutual interference. These voltage peaks can destroy the power supply module! If such a case arises, please consult t h e department responsible. a The power supply modules 6ES5 951-7LD2117ND4117ND51 have 2 backup batteries. If one o f t h e batteries is discharged, the corresponding singal lamp lights up and t h e 2nd battery automatically takes over t h e backup function. a You must observe the following for external backup in t h e case o f t h e power supply modules w i t h 2 batteries: - If you c o n n e d an external backup battery w i t h o u t inserting a new battery in the power supply module, t h e "BATT LOW" LEDs continue t o flash. - Execute a RESET o n t h e power supply module after connection o f t h e external backup battery. You thus reset t h e battery l o w signal. The "BATT LOW" LEDs, however, continue t o flash after t h e reset. a You must observe the following f o r external backup i n t h e case o f t h e power supply modules w i t h 1 battery: - Execute a RESET o n t h e power supply module after connection o f t h e external backup battery. You thus reset t h e battery l o w signal. The load power supply The load power supply supplies t h e following: a Inputloutput circuits (load circuits) and a Sensors and actuators. /1\ Warning For SIMATIC modules supplied w i t h functional extra-low voltages (V 5 120 V DC, V 5 50 V AC), you require load power supply units w i t h safe (electrical) isolation t o DIN VDE 0106, Part 101. All Siemens power supply units o f t h e 6EV1 range meet this requirement. EWA 4NEB 81 1 61 50-02d CPU 945 Manual Installation Guidelines Dimensioning the load power supplies The electronic short-circuit protection of DQ modules activates only when the triple nominal current has been exceeded. For this reason, dimension the load power supply units in such a way that the power supply can deliver the current required for switching off in the case of a shortcircuit at an output. If the load power supply unit has not been sufficiently dimensioned, this can result in a current higher than the nominal current flowing for an extended period in the case o f a short-circuit at digital outputs, without the short-circuit protection of the DQ module activating. Load power supply for nonfloating modules If you use nonfloating modules, you must create a common reference potential for the internal control circuits o f the PLC and for the load circuits. For this reason, connect the reference potential of the load power supply unit with the ground connection of the PLC (PE terminal or@ ). The ground connection is permanently connected t o the internal reference potential o f the controller. Load power supply for floating modules Note If you use switched-mode power supply units t o supply floating analog modules and BEROs, you must first run this supply over a mains filter. 3.5.2 Electrical Installation with Field Devices The following figures each show an example circuit for connecting control power supply and load power supply. They also show the grounding concept for operation from the following: Grounded supplies Centrally grounded supplies Nongrounded supplies. Please note the following when installing your controller. The text contains reference numbers which you can find in Figures 3.19t o 3.21. Master switch and short-circuit protection You must provide a master switch O t o DIN VDE 01 13,Part l, or a disonnecting device t o DIN VDE 0100,Part 460,for the programmable controller, sensors and actuators. These devices are not required in the case o f subsystems where the relevant device has been provided at a higher level. You can provide the circuits for sensors and actuators with short-circuit protection andlor overload protection O in groups. According t o DIN VDE 0100, Part 725, single-pole shortcircuit protection is required in the case of grounded secondary side and all-pole protection is required in all other cases. For nonfloating input and output modules, connect terminal M o f the load power supply unit with the PE ground conductor o f the control circuit's PS 951 power supply module. Installation Guidelines CPU 945 Manual Load power supply For 24 V DC load circuits, you require a load power supply unit O with safe electrical isolation. You require a back-up capacitor O (rating: 2OOpF per 1 A load current) for nonstabilized load power supply units. For controllers with more than five electromagnetic operating coils, galvanic isolation by a transformer is required by DIN VDE 01 13,Part 1; it is recommended by DIN VDE 0100,Part 725 0. For nonfloating input and output modules, connect terminal M of the load power supply unit with the PE ground conductor o f the control circuit's PS 951 power supply module. Grounding You should ground load circuits where possible O . Provide a removable connection t o the protective conductor on the load power supply unit (terminal L- or M) or at the isolating transformer in secondary circuit. To protect against stray noise, use copper conductors of at least 10 mm2 cross section t o ground the mounting racks by the shortest possible route. /1\ Warning You must provide insulation monitoring devices for nongrounded power supply modules If hazardous plant conditions could arise from double-line-to-ground faults or double fault t o frame faults If no safe (electrical) isolation is provided If circuits are operated with voltages > 120 V DC If circuits are operated with voltages > 50 VAC. The mounting racks of the 55-115U must be connected t o the protective conductor. This grounds the reference potential o f the controller. Nongrounded operation o f S5-115U controllers is only permissible i f all the circuits are operated with functional extra-low voltage. In this case, connect the mounting rack or DIN rail over an RC network with the protective conductor. lnstalla tion Guidelines CPU 945 Manual Operating a programmable controller with field devices on grounded supply Operation from grounded power supplies offers the best protection against interference. Low voltage distribution e.g. TN-S system L1 L2 L3 N PE bar in cabinet I I Field devices Figure 3-19 Operating a Programmable Controller with Field Devices on Grounded Supply EWA 4NEB 81 1 61 50-02d Installation Guidelines CPU 945 Manual Operating a programmable controller with field devices on a centrally grounded supply In plants with their own transformers or generators, the PLC is connected t o the central grounding point. A removable connection must be provided for measuring ground faults. Installation o f the PLC must be such that there is insulation between the cabinet potential and the protective conductor potential. In order t o maintain the insulation, all connected devices must be grounded capacitively or they must be nongrounded. For this reason, programmers must be supplied only over an isolating transformer. Low voltage distribution L1 L2 L3 - T - I , I , I I I 1 . I . I 0 . 1 , I , I I I Field devices Figure 3-20 Operating a Programmable Controller with Field Devices on Centrally Grounded Supply installation Guidelines CPU 945 Manual Operating a Programmable Controller with Field Devices on Ungrounded Supply Neither the outer conductor nor the neutral are connected t o the protective conductor in the case of nongrounded supplies. Operation of the PLC with nonfloating power supply modules is not permissible. Please note the following when connecting power suppfy modules: In networks with 3 X 230 V, you can connect the power supply module direct to t w o outer conductors (see Figure 3.21). In networks with 3 X 400 V, connection between the outer conductor and the neutral conductor is not permissible (unacceptably high voltage in the case of ground fault). Use intermediate transformers in these networks. Low voltage distribution e.g. IT system L1 L2 L3 PE- Protective conductor bar I , I , 1 . . I I I I I I m m Field devices ---nonfloating DC modules I I 5 t o 60 V A C load power supply unit for floating DC modules Figure 3-21 Operating a Programmable Controller with Field Devices on Nongrounded Supply CPU 945 Manual Installation Guidelines 3.5.3 Connecting Nonfloating and Floating Modules The following sections show the special features involved in installations with nonfloating and floating modules. Installation w i t h nonfloating modules In installations with nonfloating modules, the reference potential o f the control circuit (Minternal) and the load circuits (Meaernal) are not galvan icaliy isolated. The reference potential o f the control circuit (Minterna,) is at the PE terminal or @ and must be connected t o the reference potential of the load circuit via a line t o be run externally. Figure 3.22 shows a simplified representation o f an installation with nonfloating modules. The installation is independent o f the grounding concept. The connections for the grounding measures are therefore not shown: Uint D a a t Mint ernal connection for form reference potential 24 V DC load power supply Figure 3-22 Simplified Representation of an Installation with Nonfloating Modules Voltage drop on line O must not exceed 1 V, otherwise the reference potentials will shift and result in failures o f the module. installation Guidelines CPU 945 Manual Note It is imperative t h a t you connect the reference potential o f the load power supply unit w i t h the L- terminal o f the module in the case o f 24 V DC DQ modules. If this connection is missing (e.g. wirebreak), a current o f typically 1 5 m14 can f l o w a t the outputs. This output current can be sufficient t o ensure t h a t Energized contactors d o not drop out and e Hig h-resistance loads (e.g. miniature relays) can be driven.. lnstallation w i t h floating modules Control circuit and load circuit are galvanically isolated in the case o f floating modules. Installation with floating modules is necessary In the following cases: e A11 AC load circuits and Non-connectable DC load circuits. The reasons for this are, e.g. different reference potentials o f the sensors or t h e grounding o f t h e plus poles o f a battery, ... Figure 3-23 shows the simplified representation o f an installation w i t h floating modules. The installation is independent o f t h e grounding concept. The connections f o r grounding measures are therefore notshown. U,nt Data M,"t 2 4 V DC control power SUPP~X 2L- 0 24 V DC load power supply I N 230 V A C load power supply Figure 3-23 Simplified Representation f o r lnstallation with Floating Modules EWA 4NEB 81 1 61 50-02d Installation Guidelines CPU 945 N%nual 3.5.4 Running Cables Inside a Cabinet Dividing the lines into the following groups and running the groups separately will help you t o achieve electromagnetic compatibility QEMC). Group A: Shielded bus and data lines (for programmer, OP, SINEC L1, SINEC L2, printer, etc.) Shielded analog lines Unshielded lines for DC voltage 5 60 V Unshielded lines for AC voltage I 25 V Coaxial lines for monitors Group B: Unshielded lines for DC voltage Unshielded lines for AC voltage Group C: > 60 V and 5 400 V > 25 V and 5 400 V Unshielded lines for AC voltage > 400 V Group D: Lines for SINEC H1 You can use the following table t o see the conditions which apply t o the running of the various combinations o f line groups. Table 3-8 Rules for Common Runnina of Lines Group A '3 0 O 0 Group B 0 '3 O 0 Group C O O '3 O Group D O O O '3 Legend for table: O Lines can be run in common bundles or cable ducts 0 Lines must be run in separate bundles or cable ducts (without minimum distance) O Inside cabinets, lines must be run in separate bundles or cable ducts and outside cabinets but inside buildings, lines must be run on separate cable trays with a gap of a least o f 10 cm between lines. O Lines must be run in separate bundles or cable ducts with at least 50 cm between lines. CPU 945 Manual 3.5.5 installation Guidelines Running Lines Outside Buildings Run lines outside buildings where possible in metal cable supports. Connect the abutting surfaces of the cable supports galvanically with each other and ground the cable supports. When you run cables outdoors, you must observe the regulations governing lightning protection and grounding. Lightning protection If cables and lines for SIMATIC S5 devices are t o be run outside buildings, you must take measures t o ensure internal and external lightning protection. Outside buildings run your cables either e In metal conduit grounded at both ends or In steel-reinforced concrete cable channels Protect signal lines from overvoltage by using: Varistors or Lightning arresters filled with inert gas Install these protective elements at the point where the cable enters the building. Note Lightning protection measures always require an individual assessment of the entire system. If you have any questions, please consult your local Siemens branch office or any company specializing in lightning protection. 3.5.6 Taking Measures Against Interference Voltage Frequently, measures t o suppress interference voltage are taken only after the control system is in operation and problems develop with the reception of an information signal. You can reduce the effort involved in such measures (e.g. using special contactors) significantly if you note the following points when you are configuring your control system: e Arrange devices and wiring spaciously Ground all inactive metal parts t o chassis Filter power lines and signal lines Shield devices and wiring Take special measures t o suppress interference installation Guidelines CPU 945 Manual Arranging devices and wiring spaciously Sufficiently attenuating direct-current or alternating magnetic fields of low frequency (e.g. 50 Hz) is expensive. You can often solve this problem by maintaining the largest possible clearance between the source o f the interference and any potentially susceptible device. Chassis grounding all inactive metal parts Proper chassis grounding is an important factor in ensuring that your installation is immune t o interference. Chassis grounding refers t o the conductive connection of all inactive metal parts (VD0160). Always use surface-contact grounding. Ground all conductive inactive metal parts t o chassis. When chassis grounding, please note the following: Connect inactive metal parts with as much care as active parts Ensure low-resistance metal t o metal connections, e.g. large-surface, good-conductive contacts If painted or anodized metal parts are involved in grounding, these protective insulating layers must be penetrated. Use special contact washers for this purpose or remove the insulating layers. Protect the connected surfaces from corrosion, e.g. by using grease Movable grounded parts (e.g. cabinet doors) are t o be connected over flexible grounding strips. The grounding strips should be short and they should have a large surface area since the surface area is a decisive factor in discharging high-frequency interference. 3.5.7 Shielding Devices and Cables Shielding is a measure t o weaken (attenuate) magnetic, electric or electromagnetic interference fields. Shielding can be divided into the following t w o categories: Device shielding Line shielding Shielding devices 0 You must connect inactive metal parts (e.g. cabinet doors and supporting plates) with grounding strips. The grounding strips should be short and they should have a large surface area. There must be a large surface metal t o metal connection between the supporting bar (of the cabinet) and the fixing bracket of the mounting rack. In the case o f shielded signal lines, the shield must be secured with cable clamps t o the protective conductor bar or an additionally secured shield bar. Cable clamps must grip and connect w i t h the shield braiding over a large surface area The line t o the protective conductor system (ground point) must have a large area of contact w i t h the protective conductor system. CPU 945 Manual Installation Guidelines Shielding cables Shielding is a measure t o weaken (attenuate) magnetic, electric or electromagnetic interference fields. Interference currents on cable shields are discharged t o ground over the shield bar which has a conductive connection t o the housing. So that these interference currents do not become a source of noise in themselves, a low-resistance connection t o the protective conductor is of special importance. Use only cables w i t h shield braiding if possible. The effectiveness of the shield should be more than 8 0 % . Avoid cables with foil shielding since the foil can easily be damaged by tension and pressure; this leads t o a reduction in the shielding effect. As a rule, you should always shield cables at both ends. Only shielding at both ends provides good suppression in the high frequency range. As an exception only, you can connect the shielding at one end. However, this attenuates only the lower frequencies. Shielding at one end can be o f advantage in the following cases: If you cannot run an equipotential bonding conductor If you are transmitting analog signals (e.g. a few microvolts or microamps) If you are using foil shields (staticshields). Always use metallic or metalized connectors for data lines for serial connections. Secure the shield of the data line at the connector housing. Do not connect the shield t o the PIN1 of the connector strip! In the case of stationary operation, you are recommended t o insulate the shielded cable without interrupt and t o connect it t o the shieldlprotective ground bar. Note If there are fluctuations in potential t o ground, a compensating current can flow over the shielding that is connected at both ends. For this reason, connect an additional equipotential bonding conductor. EWA 4 N E B 81 1 61 50-02d CPU 945 Manual Installation Guidelines 3.5.8 Equipotential Bonding in the Case of Distributed Configurations For distributed configurations, differentiate between the following cases: Separate arrangement of central controllers and expansion units when connected by the 3011310 interface modules (up t o 200 m1656.2 ft) or the 3041314 interface modules (600 m11986 ft) The 3011310 and 3041314 interface modules are not floating. If the potential difference between the devices can be more than 7 V, you must provide an equipotential bonding line. Use the following dimensions for the cross-section o f the equipotential bonding line: - 16 mm2 copper wire for equipotential bonding line up t o 200 m1656.2 ft - 25 mm2 copper wire for equipotential bonding line over 200 m1656.2 ft The equipotential bonding line should be run in such a way as t o achieve the smallest possible surfaces between equipotential bonding line and signal lines Separate arrangement o f central controllers and expansion units when connected serially by the 3021311, IM 3081318 interface modules or IM 3071317 fiber optic link. These interface modules are floating. In this case, equipotential bonding line are not required. Signal transfer between separate systems via input and output modules. Floating input and output modules must be used for signal transfer. Equipotential bonding lines are not required here either. 3.5.9 Special Measures for Interference-Free Operation Arc suppression elements for inductive circuits Normally, inductive circuits (e.g. contactor or relay coils) energized by SIMATIC S5 d o not require t o be provided with external arc suppressing elements since the necessary suppressing elements are already integrated on the modules. It only becomes necessary t o provide supressing elements for inductive circuits in the following cases : If SIMATIC S5 output circuits can be switched o f f by additionaly inserted contactors (e.g. relay contactors). In such a case, the integral suppressing elements on the modules become ineffective. a If the inductive circuits are not energized by SIMATIC 55. You can use free-wheeling diodes, varistors or RC elements for wiring inductive circuits. Wiring coils activated by alternating current Wiring coils activated by direct current w i t h diode w i t h Zener diode with varistor Figure 3-24 Wiring Coils with RC element CPU 945 Manual Installation Guidelines Mains connection for programmers Provide a power connection for a programmer in each cabinet. The plug must be supplied from the distribution line t o which the protective ground for the cabinet is connected. Cabinet lighting Use, for example, LINESTRAmlamps for cabinet lighting. Avoid the use of fluorescent lamps since these generate interference fields. If you cannot do without fluorescent lamps, you must take the measures shown in Figure 3.25. Shielding grid over lamp Shielded cable Metal-encased switch Mains filter or shielded mains cable Figure 3-25 Measures for Suppressing Interference from Fluorescent Lamps in the Cabinet EWA 4NEB 81 1 61 50-02d Installation Guidelines 3.6 CPU 945 Manual Safety Measures and Monitoring Facilities When configuring programmable controllers - and also contactor controllers - follow the relevant VDE regulations (e.g. DIN VDE 0100, DIN VDE 0113 Part 1 (corresponds t o IEC 204-1)). Pay special attention t o the following measures for avoiding dangers: Prevent conditions that can endanger people or property. When power is restored after a power failure or after EMERGENCY OFF devices are released, machines must not be able t o restart automatically. When a PLC malfunctions, commands for EMERGENCY OFF devices and safety limit switches must remain effective under all circumstances. These safety measures must affect the actuators in the power circuit directly. When EMERGENCY OFF devices are activated, safety must be guaranteed for personnel and the controlled system as follows: - Actuators and drives that could cause dangerous situations (e.g. main spindle drives for machine tools) must be shut off. - On the other hand, actuators and drives that could endanger persons or the controlled system by being shut o f f (e.g. clamping devices) must not be shut o f f by EMERGENCY OFF devices. The programmable controller must be able t o record the activation of EMERGENCY OFF equipment and the user program must be able t o evaluate it. Protection in case o f indirect contact Accessible parts must not be dangerous t o touch even in the event of a fault. Such parts must be included in measures for protection against electrical shock. This requirement is met if all accessible metal parts, such as standard sectional rail, supporting bar and the cabinet itself, which could all be dangerous t o touch in the event of a fault, are made electrically safe and connected t o protective ground (PE). Maximum permissible resistance between the protective conductor connection and the accessible part t o be protected is 0.5 ohms. EWA 4NEB 81 l 61 50-02d 4 'Festsdtrg and Loadingthe Corrarof Wogmm and Starting Up a System ........................... 4 . 1 Testing the Control Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Testing the Control Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "Program Test" Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STATUSISTATUS VAR Test Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . FORCE Outputs and Variables . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . Points t o Note When Using the 2nd Interface as a Programmer Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 . 1 4 . 1 4 . 2 4 . 3 4 . 4 Loading the Control Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overall Reset ............................................... Transferring the Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Activating Software Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Determining the Retentive Feature of Timers, Counters. Flags and S Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 4 4 System Configuration and Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Notes on Configuring and Installing a System ................... Notes on the Use of Input/Output Modules . . . . . . . . . . . . . . . . . . . . . System Startup Procedure .................................... Active and Passive Faults in Automation Equipment . . . . . . . . . . . . . 4 4 4 4 4 Prerequisites for Starting Up the PLC 4 . 5 . . . . 5 5 7 9 4 .10 . 12 . 12 . 13 .I 4 . 16 CPU 945 Manual Testing and Loading the Control Program and Starting Up a System Testing and Loading the Control Program and Starting Up a System 4 This chapter contains notes on starting up an 55-115U with the CPU 945. It describes how t o Test your STEP 5 control program Load it into the PLC Start it. Knowledge o f the principle o f operation of the PLC is a prerequisite (see Chapter 2). There are notes on configuring and starting up a system at the end of the chapter. There is also a short description o f active and passive faults of a programmable control system. 4.1 Prerequisites for Starting Up the PLC Check the following before starting t o test and load your control program: All required I10 modules must be plugged into suitable slots (see Chapter 3) The address assignment of the inputs and outputs must be in order (see Chapter 6) Your system must have interference-free wiring (see Chapter 3) The control program t o be tested must be available on the programmer. 4.2 Testing the Control Program Before loading your control program into the PLC, you must test it. In this Chapter, we will show you the procedure for testing the control program. This is followed by a description o f the test functions for finding logical errors in program execution. 4.2.1 Testing the Control Program Note Always test your control program with the load circuits switched off. You can check the function o f the outputs by the LEDs on the output modules. ) ) ) ) ) Overall reset o f the PLC before transferring the control program (see Section 4.3.1) Transfer o f the control program without the OBs (see Section 4.3.2) Transfer o f OB21 and OB22 and testing of the restart characteristics of the PLC at cold restart If you have programmed the function blocks yourself, you should call them up individually in OBI, parameterize them and test them. Finally, call each block from the control program individually in OB1 and test it. Always start with the last block o f a block chain. Please note that the relevant DBs will also be called. Testing and Loading the Control Program and Starting Up a System CPU 945 Manual Figure 4.1 Typical Program Structure You can proceed as follows with the program structure represented in Figure 4.1 b b b b Call and test FB2Ol in OB1 CallPB2inOBlandtest CallPB3inOBlandtest If PB2 and PB3 are free o f errors, call PBI in OB1 and test it. This means that all blocks o f the PBI, PB2 and PB3 chain have been tested. You can test the entire control program using this procedure. 4.2.2 "Program Test" Function This programmer function causes the CPU t o process a control program step by step. You can set a breakpoint in the control program. This breakpoint is a statement in the program which you specify with the cursor. The control program will then be processed up t o this breakpoint by the CPU. The CPU scans the program up t o the selected statement. The current signal states and the RLO are displayed up t o the selected statement. You can scan the program in sections by shifting the breakpoint as you require. Program scanning takes place as follows: All jumps in the block called are traced. Blocks called are executed without delay. Program scanning is terminated automatically when block end (BE) is reached. The following applies during Program Test: Both operating mode LEDs are o f f All outputs are switched off. The "BASP" LED lights up. Inputs and outputs are not scanned. The program writes t o the PIQ and reads the PII. Testing and Loading the Control Program and Starting Up a System CPU 945 Manual Corrections are n o t possible during Program Test. However, the following test and PLC functions can be executed: Input and output (program modifications are possible) Direct signal status display (STATUS VAR) Forcing outputs and variables (FORCE, FORCE VAR) Information functions (ISTACK, BSTACK) If t h e Program Test function is interrupted by PLC or program errors, t h e PLC goes into the STOP mode and t h e corresponding LED lights up o n the CPU control panel. Consult t h e relevant manual f o r information on calling the Program Test function o n a programmer. 4.2.3 STATUSISTATUS VAR Test Function The STATUS and STATUS VAR test functions indicate signal states o f operands and the RLO. Depending o n when t h e signal states are observed, a distinction is made between programdependent signal status display (STATUS) and direct signal status display (STATUS VAR). PII + Scan trigger STEP 5 PIQ Figure 4.2 Comparison of the "STATUS" and "STATUS VAR" Test Functions EWA 4NEB 81 1 61 50-02d Testing and Loading the Control Program and Starting Up a System CPU 945 Manual Program-dependent signal status display "STATUS" This test function shows the current signal states and the RLO of the individual operands during program execution. When FBs are called, the values of the actual operands are shown. In addition, program corrections can be made. Direct signal status display "STATUS VAR" This test function gives the status o f any operand (inputs, outputs, flags, S flags, data word, counters or timers) at the end of a program scan, i.e. at the cycle control point. This information is taken from the relevant data area of the operands involved. During "Program Test" or in the STOP mode, the inputs are read direct. In other cases, only the process I/O image of the called operands is shown. 4.2.4 FORCE Outputs and Variables "FORCE" outputs All outputs are set t o "0" at the start and the end o f the FORCE function. You can set outputs t o a specific signal state directly without using the control program. Use this direct method t o check the wiring and functioning o f output modules. This procedure does not change the process image but it does cancel the output disable state. Note For the "FORCE" test function, the PLC must be either set t o the Program Test function or in the STOP mode. The function must only be executed without the load voltage. "FORCE" variables With the "FORCE VAR" test function, the process image o f binary and digital operands is modified regardless o f the PLC mode. The following variables can be modified: I, Q, F, S, T, C, and D. Program scanning w i t h the modified process variables is executed in the RUN mode. However, the variables can be modified again in the remaining program run, without a checkback signal. Process variables are forced asynchronouslyto the program run. CPU 945 Manual 4.2.5 Testing and Loading the Control Program and Starting Up a System Points to Note When Using the 2nd lnterface as a Programmer lnterface If you use an interface module at the second interface, you connect programmers and operator panels t o S1 1 and SI 2. Connecting a programmer, OP or SINEC L1 t o SI 1 or SI 2 has a negligible effect on the grogram scan time (see Section 2.9.3). There are restrictions on the simultaneous use of interfaces SI 1 and S1 2 as programmer interfaces. Depending on the status (activity) of an interface, certain requests from the programmer/OP t o the other interface are at times not possible. If this fault occurs, the function o f the relevant interface will be aborted by the CPU. The "Interface function disabled: current function" error message appears. This message draws your attention t o the fact that a function is running on the interface and blocking the requested function. Example: If "STATUS BLOCK" is running on S1 1, "INPUT BLOCK" cannot be performed on the same block on S1 2. 4.3 Loading the Control Program The following sections describe: Overall reset o f the PLC The t w o methods of transferring the control program t o the PLC The retentive characteristics of the timers, counters and flags Activation o f software protection Start o f the program. 4.3.1 Overall Reset You are recommended t o perform the Overall Reset function before entering a new program. Overall Reset deletes the following: PLC program memory All data (flags, S flags, timers and counters) All error IDs. In addition, all system data is automatically assigned default values after Overall Reset so that the system data area assumes a defined "basic status". The extended system data area (RT) is not deleted. There are t w o ways o f deleting the internal program memory: Offline via the switch for "DefauIt/OveraII Reset" Online w i t h the "Delete" programmer function. EWA 4NEB 81 1 61 50-02d Testing and Loading the Control Program and Starting Up a System CPU 945 Manual Overall Reset via the switch for "Default/Overall Reset" on the control panel of the CPU ) ) ) Switch on the power supply module Set the CPU mode selector t o STOP (ST) Set the switch for "Default/Overall Reset" t o the "OR" position and hold it in this position (if the switch is not held in position it will automatically spring back t o the "RE" position). While you hold down the switch for "Default/OveraII Reset" in the "OR" position: ) Switch the CPU mode selector twice from "ST" t o "RN". The STOP LED will momentarily go off. ) Release the switch for "Default/Overall Reset". The switch automatically springs back 'to the '"RE" position. Overall reset has now been performed on the internal program memory. Overall Reset w i t h the "Delete" programmer function ) ) ) ) Link the programmer and the CPU over a suitable connection cable Switch on the PLC power supply module Set the CPU mode selector t o "ST" or set the CPU t o the STOPstate using the STOP programmer function. Call the "Delete" auxiliaryfunction on the programmer and select "Delete all blocks" Overall reset has now been performed on the internal program memory. EWA 4NEB 81 1 61 50-02d CPU 945 Manual 4.3.2 Testing and Loading the Control Program and Starting Up a System Transferring the Program There are t w o ways of transferring the control program t o the CPU: Transfer the control program t o the memory submodule and then insert the memory submodule in the receptacle on the CPU. The CPU copies the contents of the memory submodule into internal program memory after POWER UP or Overall Reset so that they can be processed at very high speed. This method allows you t o start up a PLC or a system without using a programmer. Note: The memory submodule may be plugged in and removed in the POWER OFF state only! Transfer the control program into the internal program memory of the CPU using a programmer. Transferring the program to a memory submodule You require the following t o program a memory submodule A programmer with the S5-DOS "EPROMIEEPROM" PACKAGE An adapter (6ES5 985-2MC11) which is plugged into the submodule receptacle of the programmer, if the programmer has no receptacle for S5 memory cards. Transferring your STEP 5 control program t o a memorysubmodule: ) b b b Plug the adapter for the memory submodule into the submodule receptacle o f the programmer (if required). Plug the memory submodule into the programmer or the adapter and program it with the S5-DOS "EPROMIEEPROM" PACKAGE. This package is explained in detail in the programmer manuals. After programming the memory submodule, plug it into the submodule receptacle of the CPU when the PLC is switched off. Switch on the power supply o f the PLC. If there are s t i l l valid blocks in internal program memory after POWER UP, the following happens: Blocks loaded from flash EPROM have the ID "Block in EPROM" in internal program memory. These blocks are deleted after POWER UP and then loaded again from the flash EPROM. Blocks with the ID "Block valid in RAM" are retained in internal program memory after POWER UP. Before the blocks are loaded into internal program memory from the memory submodule, the CPU compresses the internal program memory (Compress function)! ) Overall reset Point t o note after Overall Reset: After Overall Reset, the STEP 5 control program is loaded automatically from the memory submodule into the internal program memory of the CPU. Testing and Loading the Control Program and Starting Up a System CPU 945 Manual Transferring the program into the internal program memory of the CPU using the programmer If you transfer the control program into the internal program memory of the CPU using the programmer, you must do the following: ) ) Connect the programmer t o the CPU with a suitable connecting cable. Connection is possible over interface l or m overthe programmer interface module of S1 2 Prerequisite for programmer connection t o the interface module s that none of the following functions is active: - ASCll driver - Point-to-point master function - Computer interface Switch on the power supply o f the PLC Check that the backup battery has been inserted and is functional Note It is possible for an internal passivation coating t o develop in new lithium batteries or in lithium batteries left unused for long periods. This coating has the effect o f substantially increasing the internal resistance. Remedy: Depassivatethe battery by loading it for approx. 2 hours w i t h 100 ohms. ) ) Select operating mode "Online" in the Presets (Defaults) screen form Transferthe program from the programmerto the CPU with the "Transfer" function Note Transfer takes place in the RUN or STOP state of the CPU. If you transfer blocks in the RUN state, you should: transfer tested blocks only transfer blocks in the correct order so that the CPU does not enter the STOP state (e.g. first the data blocks, then function blocks and lastly blocks which use these data and function blocks). If blocks o f the same name are already in the internal program memory of the CPU, the following message appears in the message line "... already in the PLC, overwrite?" By pressing the transfer key again, a new block is transferred t o the program memory of the CPU and the old block declared invalid. invalid blocks continue t o take up memory space and can only be deleted using "Overall reset" or "Compress" (see Chapter 2). EWA 4NEB 81 1 61 50-02d CPU 945 Manual Testing and Loading the Control Program and Starting Up a System Points t o note when setting up data blocks Data blocks generated in the control program with the "G DB" or "GX DX" operation are automatically dumped by the operating system direct in internal program memory. The contents of the data blocks can be changed using STEP 5 operations. 0 The contents of the memory submodule are copied into the internal program memory after POWER UP and after Overall Reset; this means that the contents of the data blocks can also be changed. However, after POWER UP (and after Overall Reset), the "old" data blcoks are copied from the memory submodule into the internal program memory; the "current" contents are lost. 4.3.3 Activating Software Protection Activate software protection by setting bit 0 in system data word 120 (E 10FOH). You can use the software protection facility in RAM operation, i.e. when the control grogram is not stored on the memorysubmodule (flash EPROM). Bit 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0: Software protection not active 1 : Software protection active X 0 1 = Bits which determine system characteristics (must not be changed when software protection is active!) Figure 4.3 Activating Software Protection by Setting Bit 0 in System Data Word 120 Software protection prevents the following: Input and output o f blocks by the programmer and Deletion o f blocks by the programmer. Software protection can be activated in the following ways: In DBI via the "PROT" parameter (see Chapter 11) In the control program (e.g. with the SU RT operation) or with the programmer function "Display memory contents". Bit 0 in system data word 120 can be reset only in the following cases: In the control program (e.g. with the RU RS operation) or By Overall Reset. Testing and Loading the Control Program and Starting Up a System 4.3.4 CPU 945 Manual Determining the Retentive Feature of Timers, Counters, Flags and S Flags Use the "Presetting the retentive feature1Overall Reset" switch on the operator panel of the CPU t o determine the behaviour o f timers, counters, flags and 5 flags at cold restart (both manually and automatically after power restore). Timers, counters, flags and S flags are "retentive" if they do not lose their contents at coId restart. Those timers, counters, flags and S flags which are reset at cold restart are "nonretentive". The following retentive feature is set as default after Overall Reset: All timers, counters, flags and S flags are nonretentive in the NR switch position. In the RE switch position, half of all timers, counters, flags and S flags are retentive: Table 4.1 Preset Retentive Feature of the CPU after Overall Reset ....... ,.......,......................................................................... ... "fi::::::x::::::;, ........................ ..C................. ':.:' ...... . ...... ' ....... ......' ....... . ...... ' .................. . . .....'. :'..."''. :::::::c. #&i;i:i ~ j j ~ i ; : ~ : ~ j ; ; : E $-g@@Q:-&$~ m $ & ; i:;" .,.i...,; ....,....; .....;.,,,B ,, .".. ..' ... ..' ... .." ..' ... .: ..$ ... ..: ..y ... .:p .. ... .. ....:.:*".'.'.'.'.:.:* ......................................... ...............:....:...:............ .................................................................. ................................................................................... .; ............. ";-.:,:,:, ...... . .... .... .... .... .... .... .... ...... .......... .. '.'.'.'.'...'.......:.:.:.:.~.:,s .. ;:;: ma&g&m{@; $$$$#@gkf S::::::.,.,.,. :.:.: ............................................. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ::::::<::::~:~:::<<::::::::<::::~~:::<:.,,:,:,>:,:,>>:.:,:,>>:,:,>:.:.:, :.:.,:.:.>:.:.:.>:.:.:.:,>:.:.:.>>:.:,>>>:,:,:,>:,:,:,:,>:,:,:.~.:.:, :::::::fi::e::::fi::::::::::::;:<::::::::c:::, RE (retentive) F 0.0 t o 127.7 retentive SY 0.0 t o 2047.7 F128.0 t o 255.7 nonretentive SY 2048.0 t o retentive 4096.7 nonretentive No retentive S flags No retentive flags NR (non retentive) TO t o T63 retentive CO t o C63 retentive T64 t o T255 nonretentive C64 t o C255 nonretentive No retentive timers No retentive counters Note If the battery fails on a cold restart after POWER UP and the switch is in the RE (retentive) position, the programmable controller goes t o STOP with BAU (Overall Reset request). The retentive feature in the RE switch position is determined by an entry in system data word 120 (EAFO,) : Bit 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 X X X X X X X X X X 5 I 4 3 I 2 1 0 I L 0: FYOtoFY127and SY 0 t o 2047 retentive and FY 128 t o FY 255 and SY 2048 t o 4095 nonretentive 1: All flags and S flags retentive X = bits that determine system characteristics (must not be changed when setting the retentive feature!) I 0: T 0 to T 63 retentive and T 64 t o T 255 nonretentive 1 : All times retentive 0: C 0 t o C 63 retentive and C 64 t o C 255 nonretentive 1 : All counters retentive Figure 4.4 Relevant Bits for Setting the Retentive Feature in System Data Word 120 CPU 945 Manual Testing and Loading the Control Program and Starting Up a System Bits 3,4 and 5 of system data word 120 are set t o "0" after Overall Reset of the CPU. You can influence the retentive feature separately for flags, timers and counters by setting these bits 0 in the restart program (OB20, OB21) or using the "Display memory contents" programmer function (only permissible when the PLC is in the STOP state!). You can also determine the retentive feature by setting parameters in DBI (see Chapter 11). In the case of Overall Reset, all timers, counters, flags and S flags are reset regardless of the switch position or the contents of system data word 120. 4.4 Starting the Control Program Starting point: PS 951 power supply module is switched o f f The CPU mode selector is at STOP The control program is stored on the E(E)PROM submodule ) Insert the memorysubmodule in the receptacle of the CPU ) Switch on the power supply module The green LEDs o f the PS 951 light up (otherwise: power supply module (PS 951) defective) ) (if desired:) Overall Reset of CPU After switching on the power supply module or after Overall Reset (mode selector at STOP), the STOP LED and the BASP LED light up. If the STOP LED flickers, the CPU is defective; flashes, there is a fault in the memorysubmodule (see Chapter 5.1). Online functions with the programmer over the serial interface are possible when the CPU is in the STOP state. Set the mode selector from STOP t o RUN Both operating mode LEDs light up during the entire restart. After the restart OB has been processed, the RUN LED lights up (cyclic program execution). In the event o f a fault, the CPU remains in the STOP state, i.e. the STOP LED lights up. Analysis o f the cause o f the interrupt is described in Chapter 5. If the control program does not work properly, you can debug the program w i t h the "BLOCK STATUS", "STATUS VAR" and "FORCE VAR" test functions. EWA 4NEB 81 1 61 50-O2d Testing and Loading the Control Program and Starting Up a System CPU 945 Manual System Configuration and Startup 4.5 The following section contains: 0 Notes on configuring a system with important regulations which must be observed in order t o avoid hazardous situations. Notes on the use of input and output modules The description of the system startup procedure. Notes on active and passive faults in automation equipment 4.5.1 Notes on Configuring and installing a System Since the product is usually used as a constituent part of a larger sytem or plant, these notes are designed as guidelines f o r t h e hazard-free integration of the product into i t s larger environment. When configuring programmable controller systems, you must also take into account the appropriate VDE regulations (e.g. VDE 0100 or VDE 0160). The safety regulations and accident avoidance regulations in individual applications must be observed. Situations posing a hazard t o personnel or material must be prevented. In the case o f equipment with fixed connections (fixed devices, systems) without all-pole mains disconnector and/or fuses, a mains disconnector or fuse must be installed in the building; the equipment must be connected t o a protective conductor. In the case o f devices operated on mains voltage, check before startup that the rated voltage range set agrees with the local mains voltage. In the case o f 24 V supply, safe electric isolation of the low voltage must be ensured. Use only power supplies which conform t o IEC 364-4-41 or HD 384-04-41 (VDE 0100 Part410). Fluctuations in and deviations from the rated value in the supply voltage must not exceed the tolerance limits specified in the technical specifications, otherwise malfunctions and hazardous states at the electrical modules/equipment cannot be excluded. Precautions must be taken t o ensure that an interrupted program can be resumed properly after voltage dips and power failures. In doing so, hazardous operating states, even o f short duration, must be avoided. If necessary, "emergencystop" must be programmed. Emergency stop facilities according t o EN 60204lIEC 204 (VDE 01 13) must remain effective in all operating modes o f the automation system. Deactivation of the emergency off facility must not result in any uncontrolled or undefined warm restart. In the event of faults in the PLC, commands from EMERGENCY OFF facilities and from safety limit switches must remain in effect under all circumstances. These protective measures must take effect direct at the actuators in the power section. CPU 945 Manual Testing and Loading the Control Program and Starting Up a System Activation o f the EMERGENCY STOP facility must create a hazard-free state for personnel and plant: - Actuators and drives which could cause hazardous states (e.g. main spindle drives for machine tools) must be switched off. - On the other hand, actuators and drives which could constitute a hazard t o personnel or plant when switched off (e.g. clamping devices) must not be switched o f f by the EMERGENCY STOP facility. Activation of the EMERGENCY STOP facility must be detected by the programmable controller and evaluated in the control program. Connecting cables and signal cables must be installed in such a way that inductive and capacitive interference does not adversely affect the automation functions. Automation equipment and the operator controls for the equipment must be adequately protected against unintentional operation. In order that wirebreaks on the signal side cannot lead t o undefined states in the automation equipment, relevant hardware and software precautions must be taken when connecting inputs and outputs. 4.5.2 Notes on the Use of InputIOutput Modules Digital InputIOutput Modules We offer floating or nonfloating modules t o suit the different signal levels. The wiring of the power supply, signal sensors and actuators is printed on the front flaps of the modules. LEDs on the front side display the signal statuses o f the inputs and outputs. The LEDs are assigned t o the terminals of the front connector (see also Chapter 15, "Technical Specifications"). Analog InputIOutput Modules See Chapter 10 ("Analog Value Processing") for information on the use of analog modules. Note ~ n p u t l o u t p umodules t can only be inserted or removed when the power supply for the central controller and the signal sensors is switched off. EWA 4NEB 81 1 61 50-02d Testing and Loading the Control Program and Starting Up a System CPU 945 Manual 4.5.3 System Startup Procedure The following is a prerequisite for starting up a system: The system and the 55-115U must not be live, i.e. the main switch must be off. b Step 1: Visual check of the installation; t o VDE 0100 and 0113. - - b Check mains voltage. Protective g round conductor must be connected. Make sure that all plugged-in modules are screwed tight t o the subrack. Compare I10 modules plugged in with the assignment plan (note fixed or variable slot addressing). In the case o f I10 modules, make sure that high-voltage lines (e.g. 220 V AC) do not terminate at low-voltage connectors (e.g. 24 V DC). When using nonfloating I10 modules, make sure that the M (OV reference) potential o f the supply voltages for sensors and actuators is connected t o the grounding terminal of the mounting rack (M,-M,, connection). Step 2: Starting up the PLC - Disconnect fuses for sensors and actuators. Switch o f f the power circuits t o the actuators. Turn on the main switch. Turn on the power supply. Switch the PLC without memorysubmodule t o STOP. Connect the programmer t o the CPU. After the power switch is turned on, the green LEDs light up on the power supply and the red STOP LED lights up on the CPU. - OVERALL RESET of the PLC. - Transfer the program in the case o f RAM operation. - Switch the PLC t o RUN. The red STOP LED goes out and the green RUN LED lights up. b Step 3: Testing the signal inputs (peripheral) - Insert the fuse for the signal sensors. Leave the fuses for the actuators and the power circuits disconnected. Activate all sensors in sequence. - You can scan all inputs using the "STATUS VAR" programmer function. - If the sensors function properly and their signals are received, the appropriate LEDs must light up on the I10 module. CPU 945 Manual b Testing and Loading the Control Program and Starting Up a System Step 4: Testing the signal outputs (peripheral) - Insert t h e fuse f o r the actuators. Leave the power circuits o f the actuators disconnected You can force each output using the "FORCE VAR" programmer function. The LEDs o f t h e forced outputs must light up and the circuit states o f the corresponding actuators must change. b Step 5: Entering, testing and starting the program Leave t h e power circuits for the actuators disconnected. - Enter t h e program using the "INPUT" programmer function. You can enter the program in t h e STOP or RUN mode. The red STOP LED or the green RUN LED Bights up. A battery must be ~nstalledif a RAM submoduie is used. - Test the program block by block and make any necessary corrections. Dump the program in a memorysubmc~dule Qiddesired). Switch t h e PLC t o STOP Switch o n t h e power circuits for t h e actuators. Switch t h e PLC t o RUN. The green RUN LED lights up and t h e PLC scans the program. Testing and Loading the Control Program and Starting Up a System 4.5.4 CPU 945 Manual Active and Passive Faults in Automation Equipment Depending on the particular task for which the electronic automation equipment is used, both active as well as passive faults can result in a dangerous situation. For example, in drive control, an active fault is generally dangerous because it can result in an unauthorized startup of the drive. On the other hand, a passive fault in a signalling function can result in a dangerous operating state not being reported t o the operator. The differentiation of the possible faults and their classification into dangerous and nondangerous faults, depending on the particular task, is important for all safety considerations in respect t o the product supplied. Warning In all cases where a fault in automation equipment can result in severe personal injury or substantial property damage, i.e., where a dangerous fault can occur, additional external measures must be taken or equipment provided t o ensure or force safety operating conditions even in the event o f a fault (e.g., by means of independent limit monitors, mechanical interlocks, etc.). Procedures for maintenance and repair If you are carrying out measurement or testing work on an active unit, you must adhere t o the rules and regulations contained in the "VBG 4.0 Acccident Prevention Regulations" of the German employers liability assurance association ("Berufsgenossenschaften"). Pay particular attention t o paragraph 8, "Permissible exceptions when working on live parts." Do not attempt t o repair an item o f automation equipment. Such repairs may only be carried out by Siemens service personnel or repair shops Siemens has authorized t o carry out such repairs. 5.2 5.2.1 5.2.2 Interrupt Analysis with the Programmer . . . . . . . . . . . . . . . . . . . . . . . "ISTACK" Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Meaning of the ISTACK Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Error Messages When Using Memory Submodules .............. 5 . 9 5.4 5.4.1 5.4.2 Program Errors . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . Determining the Error Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Trace with the Bsock Stack ("BSTACK") Function . . . . . . . . 5 . 9 5 .10 5 .ll 5.5 Other Causes of Malfunction 5.6 System Parameters .................................. ........................................... 5 . 3 5 . 3 5 . 6 5 .12 5 .12 .................... 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.1 0 General Error Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .. . . . . . . . . . Meaning of the Error LEDs on the CPUs ................................. DisplayoftheControl Bits ........................................... Display of the Interrupt Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISTACK Entries in System Data Words 203 to 229 . . . . . . . . . . . . . . . . . . . . . . . Meaning of the ISTACK Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mnemonics for Control Bits and Cause of Error . . . . . . . . . . . . . . . . . . . . . . . . . Errors when Using Memory Submodules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Other Causes of Malfunction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 . 1 5 . 2 5 . 3 5 . 4 5 . 4 5 . 6 5 . 8 5 . 9 5 . 9 5 .12 CPU 945 Manual 5 Error Diagnostics Error Diagnostics Malfunctions in the 55-115U can have various causes. If the PLC malfunctions, first determine whether the problem is in the CPU 945, the program, o r t h e I10 modules (see Table 5-1). Table 5.1 General Error Analvsis The CPU is in the STOP mode. The red LED is lit up. The problem is in the CPU. Perform an interrupt analysis with the programmer (see Section 5.2). The CPU is in the RUN mode. The green LED is lit up. Operation is faulty. There is a programerror. Determinetheerror address (see Section 5.4). There is an I10 problem. Perform a malfunction analysis (see Section 5.5). Note To make a general distinction between PLC and program errors, program OB1 with "BE" as the first statement. A properly functioning PLC enters the RUN mode on a Cold Restart. Caution There are risks involved in changing the internal program memory direct with the "Display memory contents" programmer function. For example, if the CPU is in RUN mode, memory areas (e.g. BSTACK) may be overwritten causing the CPU t o "crash". Take the following measures t o avoid such risks: Change only the system data area documented in this manual Use only the control program t o change the system data area! EWA 4NEB 81 1 61 50-02d Error Diagnostics 5.1 CPU 945 Manual LED Error Signalling Certain errors are indicated by LEDs on the CPU depending on i t s design. Table 5.2 explains these error signals. Table 5.2 Meaning o f the Error LEDs on the CPUs I I lights u p lights ZYKu p I I Timeout (CPU went into STOP mode) Scan time exceeded (CPU went into STOP mode) Digital outputs aredisabled (CPU is in RESTARTor STOP mode) BASP lights u p Memory error (block structure damaged) Red STOP LED is flashing After CPU COLD RESTART and after POWER UP, a memory error message may result i f t h e user program contains t h e TNB, TNW, TRW, TRD, TIR or TDI operations. It is possible t o inadvertently overwrite the following w i t h these operations: Block headers Memory areas designated as "free" by t h e operating system. The operating system writes t h e erroneous address found when generating t h e address l i s t into system data w o r d 103 and 104 (E l0CE t o E IODI). You can display t h e contents o f t h e system data locations using t h e "Display memory contents" programmer function. I Red STOP LED is flickering I Error i n t h e CPU self-test routine Remedy: Exchange CPU EWA 4NEB 81 1 61 50-02d CPU 945 Manual 5.2 Error Diagnostics interrupt Analysis with the Programmer When malfunctions occur, the operating system sets various "analysis bits" that can be scanned with the programmer using the "ISTACK" function. LEDs on the CPU also report some malfunctions. 5.2.1 "ISTACK" Analysis The interrupt stack (ISTACK) is an internal memory o f the CPU where malfunction reports are stored. When a malfunction occurs, the appropriate bit is set. Use a programmer t o read this memory byte by byte. Note You can read only part o f the ISTACK when the PLC is in the RUN mode. The following tables show which control bits and which malfunction causes are reported in the ISTACK. The system data words containing the ISTACK bits are also specified. See the subsequent tables for an explanation of the abbreviations or error codes used here. ISTACK display in the PG 710/730/750 and 770 The following tables show ISTACK as displayed on programmers. The bits relevant for the CPU 945 are in bold type. Table 5.3 Display of the Control Bits Absolute Address Control Bits NB PBSSCH BSTSCH SCHTAE ADRBAU SPABBR NAUAS QUIT E lOOA KM-AUS KM-EIN NB REMAN X NB NB NB NB ElOOB STOZUS NEUSTA NB BARB BARBEND E lOOC MAFEHL EOVH BATPUF X NB NB NB STOANZ X UAFEHL AF X NB NB EIOOD ASPNEP ASPNRA KOPFNI PROEND ASPNEEP PADRFE ASPLUE RAMADFE EIOOE KEINAS SYNFEH NlNEU NB NB NB SUMF URLAD E100F EWA 4NEB 81 1 61 50-02d System Data Word Error Diagnostics CPU 945 Manual Table 5.4 Display of the Interrupt Stack Interrupt Stack BLOCK: 01 SAC(new): ELK-STP: E2820 PAGE ACCU 1: 91 FE-NO.: REL-SAC: NUMBER: 80FBO 00066 DB-ADD: 83EAO DB-No.: DEL-REG: 81 0064 RS-REG: E26DE 0000 0000 7C09 CONDITION CODE: AKKU2: CC 1 0000 7C08 CC0 OVFL OVFLS ODER ERAB X STATUS CAUSE OF INTERR.: RLO X X KOLlF SYSFE TRAF SUF STUEB BAU NAU Qw NNN ASPFA ZY K STOP STS FAD PEU HALT The ISTACK is located in system data words RS 203 to 228. Table 5-5 shows the assignment of ISTACK entries to system data words. Table 5.5 ISTACK Entries in System Data Words 203 to 229 SD 209 DBA register H E llA2 SD 210 DBA register L E llA4 SD 21 1 BR register H (RS-REG) E llA6 SD212 BR register L (RS-REG) E llA8 SD 21 3 DBL register E IlAA SD 214 STATUS register (CONDITION CODE) E llAC EWA 4NEB 81 1 6150-02d CPU 945 Manual Error Diagnostics ISTACK Entries i n Svstem Data Words 203 t o 229 (Continued) Table 5.5 I I I I SD215 SD216 SD 217 I I I Nesting level 0 Nesting level 1 E llAE E llBO Nesting level 2 E llB2 SD218 Nesting level 3 E llB4 SD 219 Nesting level 4 E llB6 SD 220 Nesting level 5 E llB8 SD221 Nesting level 6 E IIBA SD 222 Nesting level 7 E llBC SD 223 Nesting level pointer E IlBE SD 224 reserved E llCO I SD 225 SD 226 - - I BSTACK pointer H BSTACK pointer L E llC2 E llC4 SD 227 User interrupt mask E llC6 SD 228 Interrupt condition code w o r d E llC8 SD229 Last set page number E llCA Figure 5.1shows t h e assignments i n t h e interrupt condition code w o r d Bit 15 n.a. 14 13 12 11 10 9 8 7 n.a. n.a. 6 5 QVZ KOLl 2 1 ZYK SYSFE PEU BAU 4 3 ... n o t assigned Figure 5.1 Assingments in the Interrupt Condition Code Word EWA 4NEB 81 1 61 50-02d 0 I I I Error Diagnostics 5.2.2 CPU 945 Manual Meaning of the ISTACK Displays Use Table 5-5 t o determine the cause o f a fault or an error when program execution is interrupted. In each case, the CPU goes into the STOP mode. Table 5.6 Meaning of the ISTACK Displays interrupted by a power failure Block transfer between programmer and PLC was interrupted by a power failure Program error (TIR, TNB, TNW, TRW, TRD, TDI) KOLlF lnterprocessor communication flags in DBI programmed incorrectly. Checkthe following: ID for interprocessor communication flag definitions ("MASK01 "); (see Section 12.2.1) the end IDs in each case for interprocessor communication flag definitions SYSFE Error in interpreting DBI See Chapter 11.5 Faulty submodule ASPFA The submodule ID is illegal Plug in the correct submodule Battery failure BAU There is no battery or the battery is low and the retentive feature is required. Replace the battery. Perform an Overall Reset. Reload the program. 110s not ready PEU The 110s are not ready: There has been a power failure in the expansion unit. The connection t o the expansion unit has been interrupted. There is no terminator in the central controller. a Check the power supply in the expansion unit. Check the connection. Install a terminator in the central controller. Program scanning interrupted STOP The mode selector is on STOP. Put the mode selector on RUN. EWA 4NEB 81 1 61 50-O2d CPU 945 Manual Error Diagnostics Table 5.6 Meaning of the ISTACK Displays (Continued) programmed with data word number greater than the data block length - Adata block statement has been programmed without opening a DBIDX first - The DBIDX t o be generated is too long for the program memory (G DBICX DX operation) STS - Software stop by statement (STP, STS) - STOP request from programmer - STOP request from SINEC L1 master NNN STUEB - Astatement cannot be decoded - A parameter has been exceeded Correct the program error BLock stack overflow Correct the program error - The maximum block call nesting depth ( 5 0 ) has been exceeded QVZ Timeout from 110s: Correct program eror or - A I10 byte that was not replace the 110 module addressed has been referenced in the program or an I10 module does not acknowledge ZYK Scan time exceeded: The program execution time is greater than the set monitoring time Check the program for continuous loops. If necessary, restart the scan time with OB31 or change the monitoring time Incorrect addressing Correct program error FAD - Write-protected areas accessed - Memory gaps accessed - Timerslcounters accessed with TN B - Odd addresses accessed with TNW EWA 4NEB 81 1 61 50-02d Error Diagnostics CPU 945 Manual Table 5.7 Mnemonics for Control Bits and Cause of Error Block shift active (function: Construction of address lists Compress operation aborted lnterprocessor communication flag output address l i s t available lnterprocessor communication flag input address list available 0: all timers, counters, and flags are reset on Cold Restart 1 : the second half of timers, counters, and flags are reset on Cold Restart STOP state (external request for example via the programmer) NEUSTA BATPUF BARB BARBEND PC in Cold Restart Battery backup okay Program check BARBEND Request for end STOP state after program check (cold restart required) AF Interrupt enable ASPNEP Memory submodule i s an EPROM Block header cannot be interpreted Memory submodule is an EEPROM KOPFNI ASPNEEP KEINAS SYNFEH NlNEU URLAD No memory submodule Synchronization error (blocks are incorrect) Cold Restart not possible Bootstrapping required Other mnemonics: RS System data (from address E1OOH) EAU ASPFA FA^ Substitution error Transfer error for data block statements: data word number >data block length. Statement cannot be interpreted in the 55-115U Operation interrupted by a programmer STOP request or programmed STOP statements. Block stack overflow: The maximum block call nesting depth of 50 has been exceeded. Time-out from 110s: A nonexistent module has been referenced. lnterprocessor communication flag transfer list is incorrect. Scan time exceeded: Theset maximum permissible program scan time has been exceeded . Error in DB1 110s not ready: power failure in the I10 expansion unit; connection to the 110 expansion unit interrupted No terminator in the central controller Battery failure Illegal memorysubmodule Incorrect addressing Other mnemonics: UAW Interrupt display word AN21 IANZO See Section 8.4Condition Code Generation OVFL Arithmetic overflow (+or -) OVFLS Latching arithmetic overflow ODER (OR) OR memory (set by "0" operation) STATUS STATUS of the operand of the last binary statement executed RLO Result of logic operation ERAB First scan SAC Step address counter DB-ADD Data block address ELK-STP Block stack pointer NO Block number (00, PE, FB, FX, SE, DB, DX) REL-SAC Relative step address counter BS-REG Basic address register (see Section 7.1) CPU 945 Manual 5.3 Error Diagnostics Error Messages When Using Memory Submodules A flashing red LED (STOP LED) indicates errors when memory submodule blocks are loaded into the internal RAM. The cause of error is stored in system data word 102. Table 5.8 Errors when Usina Memorv Submodules URLAD ASPFA Use the appropriate submodule. Faulty contents of memory submodule. URLAD Delete and reprogram the submodule. All blocks cannot be copied. URLAD The internal memory already contains blocks. Check t o see if these blocks are needed. Delete the blocks or optimize the program. User program operations TNB, TNW, TIR, TRD, TRW or TDI have overwritten block headers or free memory space. NlNEW Invalid memory submodule. - 5.4 Overall Reset; reload program SYNFEW Program Errors Table 5-9 lists malfunctions caused by program errors. Table 5-9 ProaramErrors 1 All inputs are zero I Check the program All outputs are not set One input is zero. One output is not set I - Check program assignments (double assignment, edge formation) Timer or counter is not running or is incorrect Cold Restart is faulty radic malfunctions occur Check Cold Restart blocks OB21lOB22 or insert them Check the program with STATUS Error Diagnostics 5.4.1 CPU 945 Manual Determining the Error Address The STEP address counter (SAC) i n the ISTACK (bytes 25 t o 26) indicates t h e absolute memory address o f t h e STEP 5 statement i n the PLC before which t h e CPU went into t h e "STOP" mode. The relative STEP address counter (REL SAC) indicates the relative address o f t h e STEP 5 statement within the block before which the CPU went i n t o the "STOP" mode. Example: You have entered a control program consisting o f OBI, PBO and PB7. L DW 10 has been programmed in PB7 without previously opening a DB. RE L-SAC OOOA OOOC OOOE Figure 5.2 Structured Program with Incorrect Programming The CPU interrupts program execution a t t h e illegal statement and goes t o STOP w i t h t h e TRAF error message. The STEP address counter is a t t h e absolute address o f t h e next unexecuted statement i n program memory. The REL SAC is a t t h e relative address o f t h e next unexecuted statement w i t h i n PB7 (000E). CPU 945 Manual 5.4.2 Error Diagnostics Program Trace with the Block Stack ("BSTACK") Function During program execution, jump operations enter the following information in the block stack: the data block that was valid before program execution exited a block; the relative return address. This address indicates the location at which program execution continues after it returns from the block that was called. the absolute return address. This address indicates the location in the program memory at which program execution continues after it returns from the block that was called. You can call the information listed above using the "BSTACK" programmer function in the STOP mode i f the CPU has entered this mode as the result of a malfunction. The "BSTACK" reports the status of the block stack at the time the interruption occurred. Example: Program scanning was interrupted at function block FB2. The CPU went into the STOP mode with the error message "TRAF" (because of incorrect access. DB5 is t w o words long. DB3 is ten words long). You can use the "BSTACK" function t o determine the path used t o reach FBZ and t o determine which block has passed the wrong parameter. The "BSTACK" contains the three return addresses (as marked in Figure 5-6). Interruption with the "TRAF" error message Figure 5.3 Program Trace with the "BSTACK" Function The display in Figure 5-7 indicates that DB5 was accessed incorrectly on the path OB1 +PB 2+PB4. Error Diagnostics CPU 945 Manual 5.5 Other Causes of Malfunction Hardware components or improper installation can also cause malfunctions. Table 5-10 summarizes such malfunctions. Table 5-10. Other Causes of Malfunction One input is zero. One output is not set. Note If the PLC still does not operate properly after you have taken the appropriate action recommended in Table 5-1 0, try t o determine the faulty component by replacement. 5.6 System Parameters Use the "SYSPAR" programmer function t o read the system parameters (e.g. software release) out of the CPU. EWA 4NEB 81 1 61 50-02d 6.1 6.1.1 6.1.2 Address Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Module Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Module Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 6 - 1 - 1 - 1 6.2 6.2.1 6.2.2 6.2.3 Slot Address Assignments ..................................... Fixed Slot Address Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Variable Slot Address Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Addressing in the 0 Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 6 6 - 6.3 6.3.1 6.3.2 6.3.3 Handling the Process Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AccessingthePII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accessing the PIQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . DirectAccess . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . 6 - 7 6 - 8 6 - 9 6 -90 6.4 Address Allocation on the CPU ................... . . . . . . ... . . . 6 1 2 3 6 - 11 6.3 6.4 6.5 6.6 6.7 6.8 6.9 Fixed Slot Addressing in the Expansion Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting Addresses on the Addressing Panel o f the IM 306 Interface Module Setting a DIPSwitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accessing thePII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accessing the PIQ ..................................................... Loading InputIOutput Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Allocation in the CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 6 6 6 6 6 . 3 . 4 . 6 . 8 . 9 .10 .11 6.1 6.2 6.3 6.4 6.5 Addresses of the Input and Output Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . Addresses of the Process I10 Images . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Allocation in the System Data Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Allocation in the Flag, Timer and Counter Areas . . . . . . . . . . . . . . . . Block Address List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 6 6 6 . 7 . 7 . 13 . 15 .16 EWA 4NEB 81 1 61 50-02d Addressing/Address Assignments CPU 945 Manual AddressingIAddress Assignments In orderto be able t o access inputloutput modules, these modules must be assigned addresses. With the CPU 945, you can address the 0 extended peripheral area in addition t o the address areas for digital and analog modules. 6.1 Address Structure Digital modules are usually addressed by bit over the process I10 image but also by byte, by word and by doubleword. Analog modules are addressed either by byte or by word. Consequently, the addresses have different structures. 6.1. l Digital Module Addresses One bit represents a channel on a digital module. You must therefore assign a number t o each bit. When numbering, note the following: The CPU program memory is divided into different address areas (see Section 6.3). Number individual bytes consecutively in relation t o the start address o f the relevant address area. Number the eight bits of each byte consecutively (0 t o 7). Figure 6-1 shows the format o f a digital address: 0 . 5 I Bit No. (channel number) I Figure 6-1. Format of a Digital Address 6.1.2 Analog Module Addresses Each channel o f an analog module is represented b y t w o bytes (=one word). An analog channel address is thus represented by the number o f the low address (high-order byte). 6.2 Slot Address Assignments You can establish addresses for 55-115U modules in the following t w o ways: Fixed Slot Addressing Each slot has a fixed address under which you can reference the module plugged into that slot. Variable Slot Addressing The user can specify an address for each slot. Fixed slot and variable slot addresses are relevant only for modules of block design. The addresses of intelligent I10 modules and modules o f ES 902 design (55-135Ul155U) are set on the modules themselves. In this case, the address need not be set on the IM 306. EWA 4NEB 81 1 61 50-02d Addressing/Address Assignments 6.2.1 CPU 945 Manual Fixed Slot Address Assignments Fixed slot addressing is only possible in the case o f block-type digital and analog modules. Inputloutput modules are referenced under permanently assigned slot addresses when the following conditions exist for the 55-115U: The PLC is operated without an expansion unit interface module and a terminating resistor is used. The PLC is operated with the IM 305 interface module (centralized configuration, see Section 3.3.1 The number of address bytes available for digital and analog modules varies. Digital modules Each slot has four bytes, so that 32 binary inputs or outputs can be addressed. If you plug in digital modules with 8 or 16 channels, use the low-order byte numbers for addressing. In this case, the high-order byte numbers are irrelevant. Analog modules For fixed slot addressing, analog modules can be plugged into slots 0 t o 3 of a central controller only. Each slot has 32 bytes. You can thus address '16 analog channels. If you plug in 8-channel modules, use the 16 low-order byte numbers for addressing. In this case, the 16 high-order byte numbers are irrelevant. Note the following: Input and output modules cannot have the same address. If an analog module has been assigned an address for a particular slot, this address cannot be used for digital modules and vice versa. In slot 0 of the expansion unit, addressing always begins with address 28.0, regardless of the number o f slots of the central controller. Figures 6-2 and 6-3 show the exact assignment of fixed addresses (please observe the "Installation Guidelines" in Sections 3.1 .l and 3.1.2). Slot numbers in Digital modules Analog modules 12.0 16.0 20.0 24.0 0.0 4.0 8.0 3.7 7.7 11.7 15.7 19.7 23.7 27.7 128 160 192 159 191 223 224 Analog modules . cannot be plug. ged into these slots 255 Figure 6-2. Fixed Slot Addressing in the Central Controllers CPU 945 Manual Addressing/Address Assignments Slot numbers in Digital . 305 modules 31.7 35.7 39.7 43.7 47.7 Analog modules IM 51.7 55.7 59.7 63.7 Analog modules cannot be plugged in here. Figure 6-3 Fixed Slot Addressing in the Expansion Unit 6.2.2 Variable Slot Address Assignments The 55-1 15U offers you the possibility of assigning an address t o each slot. You can do this if an IM 306 interface module is plugged into the central controller and each expansion unit. For addressing purposes, it does not matter whether the module in question is plugged into a central controller or an expansion unit. Under a hinged cover on the right side of the interface module is an addressing panel. I t has a DIP switch for each slot. Use the DIP switch t o set the least significant byte number for a particular slot. Addressing is independent o f a whether the module is plugged into a central controller or an expansion unit whether you want t o address the I10 in an expansion in the 0 peripheral area. Note Input and output modules in different slots can have the same address. The slot addressing only applies t o block-type digital and analog modules. Note Addresses for compact modules are set on the module! Addressing/Address Assignments ! STPL I ADDRESS BIT CPU 945 Manual ! lF Addresses for digital 1 l l Address switches (ON = 1, OFF=O) 7 6 5 4 3 2 1 2 1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 Addresses for analog I modules Address switches 7 6 5 4 @ : Slot number @ : Address switches @ : Switch for setting the number of inputs or outputs per slot @ : DIPswitch 3 Figure 6-4 Setting Addresses on the Addressing Panel of the /M 306 Interface Module EWA 4NEB 81 1 6150-02d CPU 945 Manual A ddressing/Address Assignments Setting addresses Use the left-hand switch (O in Figure 6-4) on the addressing panel o f the IM 306 t o indicate what type of module you have plugged into the slot. Proceed as follows: Set the switch t o OFF: for a 32-channel digital module or a 16-channel analog module. Set the switch t o ON: for a 16-channel digital module or an &channel analog module. The following modules must also beset as 16-channel digital modules: 482-7 digital inputloutput module 434-7 digital input module with process interrupt. Use the seven address switches (O in Figure 6-4) on the addressing panel o f the IM 306 t o indicate the least significant address (the address for channel "0") for the module in question. This setting establishes the addresses of the other channels in ascending order. When setting start addresses, note the following: 32-channel digital modules can only have start addresses whose byte numbers are divisible by 4(e.g.,0,4, 8...). 16-channel digital modules can only have start addresses whose byte numbers are divisible by 2 (e.g., 0, 2,4 ...). 16-channel analog modules can only have the start addresses 128,160,192 and 224. 8-channel analog modules can only have the start addresses 128, 144, 160 t o 240. Addressing/Address Assignments CPU 945 Manual A 16-channel digital input module is plugged into slot 2. Assign it start address 46.0 by performing the following steps: Example: Check t o see if the byte number of the start address can be divided by 2 since you are dealing with a 16-channel digital module. 46 : 2=23 Remainder 0 Set the number of input channels (set switch t o ON). Set the address switches on the DIPswitch for slot number 2 as shown in Figure 6-5. Binary Weight o f the Address Bits I I 12864 ! 32 16 8 4 2 i The address is equal t o the sum of the by the individual coding 32 2+4+8+32=46 I Figure 6-5. Setting a DIP Switch The module is then addressed as follows: Channel No. 0 1 Address 46.0 46.1 6.2.3 2... 7 8 9 46.7 47.0 47.1 10 . . . 15 47.7 Addressing in the 0 Area Modules can be addressed in the 0 area (see Section 6.3) only via a distributed link. You can address the 0 area on an expansion unit via the interface module of a distributed link (see Section 3.3.2). For block-type modules, the addresses of the 0 area are set on the IM 306 interface module in exactlythe same way as the addresses of the P area (see Section 6.2.2). If you want t o operate CPs and IPs in the 0 area, you must additionally set them t o the 0 area on the module itself. Modules cannot be addressed in the 0 area on the module. CPU 945 Manual 6.3 Addressing/Address Assignments Handling the Process Signals With the CPU 945, you can additionally use the 0 area for addressing input and output modules. This area i s not available on the CPUs 941 t o 944. The signal states o f the input and output modules can be written t o or read under the following addresses. Table 6-1 Addresses of the l n ~ uand t Output Modules Digital modules Analog modules 0 peripherals - 128 OOFO80, 255 OOFOFF, 0 O O F I 00, I 255 I O O F I FFH I 0 I OOFDOOH IM3 area IM4 area Digital module signal states are also stored in a special memory area called the process image. The process image has t w o sections, namelythe process input image (PII) and the process output image (PIQ). Table 6-2 shows where the process images are located in the program memory. Table 6-2 Addresses o f the Process I10 Images Process image o f the inputs (PI11 Process image o f the outputs (PIQ) Process signals can be read or output either via the process image or directly. Addressing/Address Assignments 6.3.1 CPU 945 Manual Accessing the PI1 At the beginning of program execution, the input module signal states are written t o the PII. The statements in the control program use a particular address t o indicate what information is currently needed. The control logic then reads the data that was current at the beginning of program execution and works with it. PII Bit No. Reading bit by bit in binary operations: A 1 2.2 - 4 Reading byte b y byte when loading into ACCU 1: L IB 12 Byte 2 31 16 Byte l 2 15 0 ACCU1 H ig h-order Low-order byte byte High-order word Reading word by word when loading into ACCU 1: High-order Low-order byte byte Low-order word L lw 40 Byte 40 Byte 41 Hig h-order Low-order byte byte High-order word Reading a doubleword when loading into ACCU 1: High-order Low-order byte byte Low-o rde r WO rd LID 58 Byte 58 Byte 5 9 Byte 60 Byte 61 byte byte byte High-order word - V byte Low-order word Value00, Figure 6-6. Accessing the PI1 Reading o f the PI1 can be inhibited. To do so, it is necessary t o act upon bit 1 of system data word 120 (E 10FOH) using system operations (Load and Transfer). Reading of inputs is inhibited. Bit 1 ="l": Bit 1 ="on: Reading of inputs is enabled. The default setting is bit 1 = "0" (read enabled). CPU 945 Manual Addressing/Address Assignments 6.3.2 Accessing the PIQ New signal states are entered in the PIQ during program execution. This information is transferred t o the output modules at the end o f each program scan. B i t No. Writing bit by bit in binary operations: Byte 4 - Writing byte by byte t o transfer from ACCU 1: 31 ACCU 1 Byte 36 16 15 tzzzmEm Hig h-order Low-order byte byte High-order word Hig h-order byte Low-order word Writing word b y word t o transfer from ACCU 1: 31 ACClJ1 Byte 52 Byte 53 16 15 --flmhTm&l Hig h-order Low-order byte byte High-order word High-order byte Low-order WO rd Transferring a doubleword from ACCU 1: 31 Byte 60 Byte 6 l Byte 62 Byte 63 16 15 I ACCU 1 I Figure 6-7. Accessing the PIQ Output of the PIQ t o the output modules can be inhibited by setting b i t 2 in system data word 120 (E 10FO"). .. ~ ;2="1": t B i t 2="0": Output o f the PIQ is inhibited. Output o f the PIQ is enabled. The default setting is bit 2= "0" (output o f the PIQ enabled). EWA 4NEB 81 1 61 50-02d Addressing/Address Assignments 6.3.3 CPU 945 Manual Direct Access Analog module signal states are not written t o the process image. They are read in or transferred t o an output moduledirectlywiththe "L PY X, L PW X, T PY X or T PW X I L OY , L OW X, T OY X or TOW X" statements. You can also exchange information with digital modules directly. This is necessary when signal states have t o be processed immediately in the control program. Figure 6-8 shows differences during the loading of signal states. j LPWx LOY X LOWx Control Program I I I Plid-dre~~s~ ofthe Ou+pv% M Q ~ U ~ S Figure 6-8 Loading Input/Output Modules Note If you use direct access t o call an address whose slot is unoccupied, the CPU enters the STOP mode with error code "QVZ" (timeout) or the error DB is activated. CPU 945 Manual Addressing/Address Assignments Note The digital inputs can be read w i t h 0B254 and t h e PIQ o u t p u t t o t h e o u t p u t modules w i t h 0B255, irrespective o f t h e contents o f system data w o r d 120 (see Section 2.1 1.4 a n d 2.1 1.5). 6.4 Address Allocation on the CPU You can see f r o m Figure 6-9 h o w t h e CPU address space is allocated. CPU address space Operating system 02 0600, 02 0500, Process image Figure 6-9 MemoryAllocation in the CPU Addressing/Address Assignments Adress CPU 945 Manual Bytes A CPU address area S5 bus address area 00 0 0 0 0 ~ absolute addresses v Figure 6-9 Memory Allocation in the CPU (Continued) EWA 4NEB 81 1 61 50-02d CPU 945 Manual Addressing/Address Assignments The following table lists t h e system data o f relevance t o t h e user and indicates the sections which provide more detailed information. Integrated hardware clock; clock data area, status word, error codes, correction value Start add ress o f internal RAM End address o f internal RAM Address level indicator f o r internal RAM CPU ID and firmware status in ASCll code Driver number and error message (e.g. in t h e case o f ASCll driver) Driver parameter block (e.g. for ASCII driver) 1 57-63 I E1072 I SINEC LT parameter field Address list f o r IPC output flags 8 0 - 95 E lOAO Address list f o r IPC input flags E IOBF 96 E lOCO E lOCl Scan monitoring time (multiple o f 10 ms) 97 E 10C2 E 10C3 Interval timer f o r OB 13 (in ms) 98 E 10C4 E 10C5 Interval timer f o r OB 12 (in ms) Addressing/Address Assignments CPU 945 Manual Table 6-3 Address Allocation in the System Data Area (Continued) Interval timer for OB 11 (in ms) Interval timer for OB 10 (in ms) Time (in ms) t o calling OB6 I 102 I E IOCC EIOCD - I E lOCE Error when copying the memory submodule Address of the faulty module in the case of QVZ or error address in the case of address list generation E 1OD1 System characteristics: software protection disable reading in of PI1 disable output of PIQ retentive feature o f flags, counters and timers parallel transfer of process image Current scan time E 10F4 E 10F5 E 10F6 E 10F7 E lOFC E IOFD Maximum scan time ( Startup delay in ms List of all addressable I10words Error buffer for system error handling E 1196 Interrupt stack E llCB From RS 240 onward, the system data words are reserved for standard FBs. The unnamed system data words between RS 0 and RS 239 are either used by the operating system of the CPU or they are reserved. CPU 945 Manual Addressing/Address Assignments Table 6.4 Address Allocation in the Flag, Timer and Counter Areas Flags (F) Flags (S) (extended) FYO FY 1 SY 0 SY 1 SY 4095 Counters (C) CO C1 C 255 RS 0 System data RS area RS 255 RT 0 System data RT area RT 255 EWA 4NEB 81 1 61 50-02d E OFFF Addressing/AddressAssignments CPU 945 Manual Table 6-5 Block Address List E 39FE,E 39FF E 3A02,E 3A03 blocks (extended) DX1 E 3C02,E 3C03 DX255 E 3DFE,E 3DFF Note In the CPU 945, blocks are stored in program memory in such a way that the 4 least significant bits (bits 0 t o 3) of the block start address (1st operation in block or 1st data word) are always zero. These 4 bits are not stored in the block address list and instead only the significant part of the address is stored. Example: Start address o f FBI is address OA0040, in the program memory. The value A004, is stored at address E3202, and E3203, in the block address list. . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . . 7 . 7.1 The Registers of the CPU 945 7.2 7.2.1 7.2.2 Generating a Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 . 5 Methods of Representation ................................... 7 . 6 Operands and Blocks ......................................... 7 . 7 7.3 7.3.1 7.3.2 Program Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Linear Programming . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . 7 Structured Programming ..................................... 7 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 BlockTypes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 .10 Organization Blocks (OBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 . 11 Program Blocks (PB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 . 13 Sequence Blocks (SBs) ........................................ 7 .13 Function Blocks (FBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 .13 Data Blocks (DBsIDXs) . . . . . . . . . . . . . . . . . . .. .. . . . . . . .. .. . . . . . . 7 .18 7.5 7.5.1 7.5.2 7.5.3 Processing Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modifying the Program .......................... .. . . . . . . . . . . Modifying Blocks . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . Compressing the Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6 Number Representation EWA 4NEB 81 1 61 50-O2d ...................................... 2 . 8 . 8 .8 7 .19 7 .20 7 .20 7 .20 7 .21 ............................................. 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.1 0 Structure o f a Block Header ............................ . ... . . . . . . . . . . Assigning Function Block Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example o f t h e Contents o f a Data Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Validity Areas o f Data Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Compression Process ....................... .. . . . . . . . . . . . . . . . . . . . . . . . &Bit Number Representation . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . 16-Bit Number Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-Bit Number Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 7.3 7.4 7.5 7.6 eglster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comparison o f Operation Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comparison o f Block Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview o f t h e Organization Blocks ................................. Block Parameter Types and Data Types w i t h Permissible Actual Operands Number Representations i n t h e CPU 945 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 7 7 7 7 7 7 7 7 7 7 - 11 - 17 - - 18 19 20 21 22 - 6 - 10 - 12 - 15 - 21 CPU 945 Manual Introduction t o STEP 5 lntroduction to STEP 5 This chapter describes the registers of the CPU 945 and deals with programming of automation tasks with the CPU 945 o f the S5-115U PLC. It explains how t o generate programs and which blocks can be used t o structure a program. In addition, you will find an overview o f the different types of number representation available in the STEP 5 programming language. The CPU 945 offers a STEP 5 which has been expanded compared t o the CPUs 941 t o 944. The following are new additions in the CPU 945: New operations - Floating-point operations - Doubleword operations - Fixed-point multiplication and division Expanded register set 32-bit ACCUs BR register - New operand areas - S flags - 0 peripherals (see Chap. 6) - Expanded system data New blocks - FX blocks - DX blocks A new integral organization block - OB250 for calling and parameterizing operating system services (see Section 2-10) New organization blocks for error handling - OB26,OB33,OB35 Additional number representation methods - Processing o f 32-bit fixed-point binary numbers (see Section 7-6) - Processing o f 32-bit floating-point numbers (see Section 7-6) EWA 4NEB 81 1 61 50-02d CPU 945 Manual Introduction t o STEP 5 7.1 The Registers of the CPU 945 The register set of the CPU 945 exists for every program execution level. ACCU 1 ACCU - (Accumulator) BR SAC DBS (Base address register) (STEP address counter) (Data block start address register) DBL (Data block length register) 0 15 1 m m 2 STATUS (STATUS register) KST (Nesting stack) KSTP (Nesting stack pointer) 0 Figure 7-1 Registers of the CPU 945 EWA 4 N E B 81 1 61 50-02d Introduction t o STEP 5 CPU 945 Manual ACCU 1 ACCU 1 is 32 bits wide. ACCU 1 is t h e main accumulator o f t h e CPU 945 and is used as a working register f o r t h e operands. The operands can be processed i n byte format, word format or doubleword format. The load and transfer operations always refer t o this ACCU. ACCU 1 contains t h e destination address f o r t h e TNW and TNB operations. ACCU 1 contains t h e operand address f o r the LLIR, TIR, LDI and TDI operations. Descriptors: 31 24 23 8 7 16 15 0 Bits ACCU l ACCU 1-HH ACCU 1-HL ACCU 1-LH ACCU l - H ACCU 1-LL ACCU l-L ACCU 2 ACCU 2 is also 32 bits wide. ACCU 2 contains t h e second operand f o r logic and arithmetic operations. The operands can be processed i n byte format, word format or doubleword format. ACCU 2 usually takes over t h e contents o f ACCU 1 i n the case o f load and transfer operations. ACCU 2 contains t h e source address for t h e TNW and TNB operations. Descriptors: 31 24 23 ACCU 2-H H ACCU 2-HL ACCU 2-H EWA 4NEB 81 1 61 50-02d 8 7 16 15 ACCU 2-LH 0 ACCU 2-LL ACCU 2-L Bits Introduction t o STEP 5 CPU 945 Manual Base address register (BR) The base address register (BR) is 24 bits wide. This register i s available f o r f o r address calculations in t h e case o f absolute addressing. The contents o f the base address register is used as a byte address. Descriptors: 23 16 15 8 7 0 Bits BR BR-H BR-L STEP address counter (SAC) The STEP address counter (SAC) is 24 bits wide. The SAC is responsible for addressing t h e operation store and always points t o t h e address o f t h e next operation t o be executed. The SAC contains even addresses since t h e STEP 5 operations are stored exclusively a t even addresses and are always an even number o f bytes long. Bit 0 o f t h e SAC is fixed a t logic "0". Descriptors: 23 16 15 SAC- H 8 7 o Bits SAC-L Data block start address register (DBS) The data block start address register (DBS) is 24 bits wide. THE DBS contains t h e start address o f the data o f t h e last opened data block. The DBS contains even addresses. Bit 0 o f t h e DBS is fixed a t logic "0". Descriptors: 23 16 15 8 7 11111111111111111111111 O Bits DBS V DBS-H DBS-L EWA 4NEB 81 1 61 50-02d Introduction to STEP 5 CPU 945 Manual Data block length register (DBL) The data block length register (DBL) is 16 bits wide. THE DBL contains the data length of the last opened data block. The data length is given in words. The data length is the value taken over from the data block after the length of the data block header has been subtracted. STATUS register (STATUS) The status register is 8 bits wide. Table 7-1 Bit Assignments in the STATUS Register Result o f logic operation Latching overflow Overflow Condition code bit 0 Bits 0 t o 7 are defined by the result of a logic or arithmetic operation. Nesting stack (NST) The nesting stack supports execution of nested operations. The intermediate results of logic operations are stored in the nesting stack in order t o ensure the preset order o f execution of the logic operations. The nesting stack contains up t o 8 entries. Block calls d o not affect the nesting stack. Nesting stack pointer (NSTP) The nesting stack pointer (NSTP) points t o the current level of the nesting stack in each case. The NSTP is incremented by an "Open bracket" operation and decremented by a "Close bracket" operation. Block calls do not affect the nesting stack pointer. 7.2 Generating a Program In programmable controllers (PLCs), automation tasks are formulated as control programs. In the control program, the user draws up a series of statements which defines how the PLC is t o perform i t s control task. So that the programmable controller (PLC) can "understand" the program, it must be written according t o fixed rules in a specific language, the programming language. The STEP 5 programming language has been developed for the SIMATIC S5 family. EWA 4NEB 81 1 61 50-02d CPU 945 Manual Introduction t o STEP 5 7.2.1 Methods of Representation The following methods o f representation are possible with the STEP 5 programming language: Statement List (STL) STL represents the program as a sequence of operation mnemonics. A statement has the following format: I I Operation 7 Operand 002: A 1 0.1 I Parameter Operand ID Relative address of the statement in a particular block The operation instructs the PLC what t o do with the operand. The parameter indicates the operand address. Control System Flowchart (CSF) CSF represents logic operations with symbols. Ladder Diagram (LAD) LAD represents control functions with circuit diagram symbols. GRAPH 5 GRAPH 5 is a graphic representation of the structure of sequence controls. Types of operation The STEP 5 programming language has the following t w o operation types: basic supplementary Table 7-2 provides further information on these operations. Table 7-2 Comparison o f Operation Types Application Methods of Representation Basic Operations Supplementary Operations in all blocks only in function blocks STL, CSF, LAD STL Refer t o Chapter 8 for a description o f all operations and programming examples. EWA 4NEB 81 1 61 50-02d CPU 945 Manual 7.2.2 Introduction to STEP 5 Operands and Blocks The CPU 945 has the following new operands and blocks compared t o the CPUs 941 t o 944: Sflags 0 peripherals FX blocks DX blocks You can use the following operands in the CPU 945 I (inputs) interfaces from the process t o the PLC Q (outputs) interfaces from the PLC t o the process F (flags) memory for intermediate results of binary operations (S flags) additional memory for intermediate results of binary operations D (data) memory for intermediate results of digital operations T (timers) memory for implementing timers C (counters) memory for implementing counters (peripherals) interface between process and programmable controller K (constants) defined numeric values RS, RT (system data) interface between operating system and control program You can use the following blocks in the CPU 945: OB, PB, SB, FB, FX (code blocks) aids for structuring the program DB, D X (data blocks) blocks for storing and structuring data You will find a complete list o f operations, operands and the blocks already integrated on the CPU 945 in the enclosed Pocket Guide for the CPU 945. EWA 4NEB 8 1 1 6 150-O2d Introduction t o STEP 5 7.3 CPU 945 Manual Program Structure An S5-115U program can be one o f the t w o following types: linear structured Sections 7.3.1 and 7.3.2 describe these program types. 7.3.1 Linear Programming When processing simple automation tasks, it is enough t o program the individual operations in one block. In the case o f the 55-115U, this is organization block 1 (OBI) (see Section 7.4.1). This block is scanned cyclically, i.e. after processing the last statement, the processor returns t o the first statement. Please note the following: Five words are assigned t o the block header (see Section 7.4). Normally, a statement takes up one word in the program memory. Two word and three word statements also exist (e.g., with the operation "Load a constant"). Count these statements twice or three times when calculating the program length. Like all blocks, OB1 must be terminated by a Block End statement (BE). 7.3.2 Structured Programming To solve complex tasks, it is advisable t o divide an entire program into individual, self-contained program parts (blocks). This procedure has the following advantages: This procedure has the following advantages: simple and clear programming, even for large programs capability t o standardize program parts easy alteration simple program test simple startup subroutine techniques (block call from different locations) The STEP 5 programming language has the following five blocktypes: Organization Block (OB) Organization blocks manage the control program. Program Block (PB) Program blocks arrange the control program according t o functional or technical aspects. Sequence Block (SB) Sequence blocks are special blocks that program sequence controls. They are handled like program blocks. EWA 4NEB 81 1 61 50-O2d introduction to STEP 5 CPU 945 Manual Function Block (FBIFX) Function blocks are special blocks for programming frequently recurring or especially complex program parts (e.g., reporting and arithmetic functions). You can assign parameters t o them. They have an extended set of operations (e.g., jump operations within a block). Data Block (DBIDX) Data blocks store data needed t o process a control program. Actual values, limiting values, and texts are examples of data. The program uses block calls t o exit one block and jump t o another. You can therefore nest program, function, and sequence blocks randomly in up t o 50 levels (see Section 7.4). Note When calculating the nesting depth, you must take into account that in the event o f specific events occurring, the system program can call an organization block (e.g. OB32) autonomously or it can interrupt the different execution levels (e.g. cyclic, timecontrolled and interrupt-driven program execution) according t o their priority. The total nesting depth is the sum of the nesting depths o f all programmed organization blocks. If nesting goes beyond 50 levels, the PLC goes into the STOP mode with the error message "STUEB" (block stack overflow) (see Section 5.2). Figure 7-2 illustrates the nesting principle. Operating system Level l Level 2 Level 3 Figure 7-2 Nesting Depth EWA 4NEB 81 1 61 50-O2d Level 4 Level 50 CPU 945 Manual Introduction t o STEP 5 7.4 Block Types You w i l l f i n d t h e most important characteristics o f t h e individual block types i n Table 7-3: Table 7-3 Comparison of Block Types FBO t o FB255 FXO t o FX255 DX 256 DXO t o DX255 64K words4 Bit pattern 5 WO rds Numbers Texts 1 Organization blocks have already been integrated into the operating system (see Chap. 2). A few OBs are called autonomously by the operating system (see Section 7.4.1) 2 Function blocks have already been integrated into the operating system (see Section 2.1 1 and Chap. 12) 3 Data block DBI is reserved for parameterization of the CPU 4 Can be accessed with "L DW", "T DW" up t o DW 255 Only 2042 DWs can be entered with the programmer. CPU 945 Manual Introduction t o STEP 5 Block structure Each block consists o f the following: Block header specifying the block type, number, and length. The programmer generates the block header when it transforms the block. Block body with the STEP 5 program or data. Synchronization pattern Absolute byte adresses (in ascending order) Block type Block number Programmer ID Library - number - Block length - \ Figure 7-3 Structure of a Block Header Programming Blocks are programmed with the "LAD, CSF, STL" software package. See your programmer manual for details o f programming individual blocks. 7.4.1 Organization Blocks (06s) Organization blocks are the interface between the operating system and the control program; they can be divided into three groups: An organization block is called cyclically by the operating system (OBI) Some organization blocks are event-driven or time-controlled; i.e. they are called by - STOP+RUN or POWER OFF-+POWER ON transitions (OB21,OB22) - Interrupts (OB2 t o OB6) - Programming errors or PLC faults (OB19,OB23,OB24,OB27,OB32,OB34) - Expiry of an interval (Of310 t o OB13) Other organization blocks represent operating functions (similar t o integral function blocks), which can be called from the control program (see Chapter 2). Program execution by OBs takes place on different levels. The OBs have different interrupt characteristics depending on the execution levels. You will find a detailed explanation o f the program execution levels in Section 2.8. Handling o f programming errors and PLC faults via OBs is explained in Section 2.8.7. Handling o f system errors via OBs is explained in Section 2.8.6. CPU 945 Manual Introduction t o STEP 5 Table 7-4 Overview of the Oraanization Blocks OB called cyclically by the operating system OB 1 1 Cyclic prosram execution 1 2.8.2 OBs for interrupt-driven and time-controlled program execution OB2 Interrupt A: OB3 Interrupt B: Interrupt generated by the 434-7 and 487-7 modules and by IP Interrupt generated by IP OB4 Interrupt C: Interrupt generated by IP OB 5 Interrupt D: Interrupt generated by IP 2.8.4 OBlO Time-controlled program execution (variable in each case: 1 rns t o 65535 ms) OBl l OB12 OB13 OBs for timed-interrupt-driven program execution OB6 I Interrupt triggered by internal timer 2.8.5 OBs for controlling restart characteristics OB21 Cold restart after STOP-RUN transition OB22 Cold restart after POWER ON 2.6.2 OBs for handling programming errors and PLC faults OB 19 I When a block is called which has not been loaded I ~ OB23 Timeout during direct 110 access OB 24 Timeout during update of the process image and the interprocessor communication flags OB32 1substitution error 1 Transfer error 0834 I Batter" failure 2.8.7 I I OBs for handling system errors OB26 I Scan time exceeded OB33 Collision o f t w o timed interrupts OB35 I10 error I 2.8.6 OBs which offer operating functions I OB31 Scan time triggering 3B 160 Programmable time loop 2.1 1.3 3B250 Operating system services 2.10 3B254 I Read in process I10 imaqe 3B255 I Output process 110 image 1 2.9.5 2.11.4 2.1 1.5 EWA 4NEB 81 1 61 50-02d CPU 945 Manual 7.4.2 lntroduction to STEP 5 Program Blocks (PB) Self-contained program parts are usually programmed in blocks. Special feature: Control functions can be represented graphically in program blocks. Call Block calls JU and JC activate program blocks. You can program these operations in all block types except data blocks. Block call and block end cause the RLO t o be reloaded. However, the RLO can be included in the "new" block and be evaluated there. 7.4.3 Sequence Blocks (SBs) Sequence blocks are special program blocks that process sequence controls. They are treated and used like program blocks. 7.4.4 Function Blocks (FBs) Frequently recurring or complex control functions are programmed in function blocks. Function blocks have the following special features: You can also use FX blocks in the CPU 945. You can program and process FX blocks in the same way as FBs. Function blocks have the following special features: FBs can be assigned parameters. Actual parameters can be assigned when the block is called. FBs have a supplementaryset o f operations not available t o other blocks. The FB program can be written and documented in STL only. The 55-115U has the following types of function blocks: FBs that you can program FBs that are integrated in the operating system (see Chapter 2 and Chapter 12) FBs that are available as software packages (Standard Function Blocks, see Catalog ST 57). EWA 4NEB 81 1 61 50-O2d Introduction t o STEP 5 CPU 945 Manual Block header In contrast t o other types o f blocks, function blocks have other organization information in addition t o the block header. Its memory requirements consist of the following: block description as for other blocks (five words) block name (five words) block parameter for parameter assignment (three words per parameter). Creating a function block In contrast t o other blocks, parameters can be assigned t o FBs. To assign parameters, you must program the following block parameter information: Name of the block parameter (formal operands) Each formal operand receives a name (declaration "DECL"). The name can contain up t o four characters and must begin with an alpha character. You can program up t o 40 block parameters per function block. Block parameter type You can enter the following parameter types: -I input parameters -Q output parameters -D data -B blocks -T timers -C counters Output parameters are represented t o the right of the function symbol in graphics representation (CSF). The other parameters are t o the left. Blockdatatype You can specify the following data types: - BI for operands with bit address - BY for operands with byte address -W for operands with word address -D for operands w i t h doubleword address -K for constants You can specify the following types for parameter D for a bit pattern for t w o numbers expressed in byte format for a hexadecimal number - KC for t w o alphanumeric characters - KF for a fixed-point number - KT for a timer - KZ for a counter - KG for a floating-point number - KM - KY - KH Data type specification is not permissible with the B, T, Cparameters. EWA 4NEB 81 1 61 50-02d CPU 945 Manual fntroduction t o STEP 5 Table 7-5 Block Parameter Types and Data Types with Permissible Actual Operands BY M D D KM KY KH KS KT KC KF KG B * for an operand with byte address for an operand with word address for an operand with doubleword address for a binary pattern (16 digits) for two absolute numbers, one byte each, each in the range from 0 to 255 for a hexadecimal pattern (maximum 4 digits) for a character (maximum 2 alphanumeric characters) for a time (BCD-coded time) with time base 0.0 t o 999.3 for a count (BCD-coded) 0 t o 999 for a fixed-point number in the range from - 32768 t o 32767 for a floating-point number IB QB FB DL DR P0 X IW QW FW DW PW X ID QD FD DD X X X X X X X X X X X X X input bytes output bytes flag bytes data bytes left data bytes right peripheral bytes inputwords output words flag words data words peripheral words Input doubleword Output doubleword Flag doubleword Data doubleword Constants + Type designation not permitted DB X FB X PB X SB X OB X Data blocks. The C DBx operation is executed. Function blocks (permissible without parameters only) are called unconditionally (JU..x). Program blocks are called unconditionally (JU..x). Sequence blocks are called unconditionally (JU..x). Organization blocks are called unconditionally (SPA..x). T Type designation not permitted T Timer. The time should be assigned parameters as data or be programmed as a constant in the function block. C Type designation not permitted C Counter. The count should be assigned parameters as data or be programmed as a constant in the function block. Note: S flags are not permissible as actual operands EWA 4NEB 81 1 6150-02d Introduction t o STEP 5 CPU 945 Manual Calling a function block Function blocks are stored like other blocks under a specific number (e.g. FB47) in internal program memory. Numbers 238 t o 251 are reserved for integral FBs and can therefore not be used for user-written FBs! FB calls can be programmed in all blocks except data blocks. A function block call consists of: Call statement JU FBx Unconditional call o f the FB X (Jump Unconditional...) DOU FXa Unconditional call o f the FXa JC FBx Call if RLO= 1 (Jump Conditional ...) DOC FXa Call if RLO = 1 Parameter l i s t (only necessary if block parameters have been defined in the FB) - Function blocks can only be called if they have already been programmed. When a function block call is being programmed, the programmer automatically requests the parameter l i s t for the FB, provided block parameters have been defined in the FB. Assigning function block parameters The program in the function block specifies how the formal operands (the parameters defined as "DECL") are t o be processed. As soon as you program a call statement (e.g. JU FBZ), the programmer displays the parameter list. The parameter l i s t consists o f the names o f the parameters each followed by a colon (:). Actual operands must now be assigned t o the parameters. When the FB is called, the actual operands replace the formal operands defined in the FB so that the FB "actually" works with actual operands. The parameter l i s t may contain up t o 40 parameters. Example: The name (DECL) o f a parameter is IN 1, the parameter type is I (input) and the data type is BI (bit). The formal operand o f the FB then has the form DECL: IN1 I BI. The parameter list in the calling block specifies which (actual) operand is t o replace the formal operand in the event o f the FB being called; in the example this is the operand "1 1.0". The parameter l i s t must therefore contain the entry INI: 11.0. When the FB is called, it replaces the formal operand "EINI" with the actual operand "1 1.O". Figure 7-4 contains a detailed example o f the parameter assignment of a function block. EWA 4NEB 81 1 61 50-02d Introduction to STEP 5 CPU 945 Manual The function block call occupies three words in the internal program memory and each parameter a further memory word. The required memory length of the standard function blocks as well as the execution time are specified in Catalog ST 57. The identifiers for the inputs and outputs o f the function block appearing on the programmer during programming are deposited, together with the name, in the function block itself. It is therefore necessary t o transfer all required function blocks t o the program diskette (in the case of off-line programming) or enter them directly into the program memory of the PLC before programming begins on the programming unit. Executed program ... l l NAME: EXAMPLE DECL: X11 BI DECL: X21 BI DECL: X3Q BI at first call Parameter l i s t for first call 4 Formal operands - Actual operands ; ;1 ; 14.5 15.3 I at second call l} Parameter l i s t for second call Formal operands Figure 7-4 Assigning Function Block Parameters EWA 4NEB 81 1 61 50-02d Introduction to STEP 5 7.4.5 CPU 945 Manual Data Blocks (DBsIDXs) The data which is t o be processed in the program is stored in data blocks. You can also use DX blocks in the CPU 945. You can program and use DX blocks in the same way as DBs. For indexed calling of a DX block, you must use the operating system service No. 24 (OB 250) (see Section 2.10). The following data types are permissible: bit pattern (representation of controlled system states) hexadecimal, binary or decimal numbers (times, results of arithmetic operations) alphanumeric characters (message texts) Programming data blocks Begin data block programming by specifying a block number between 2 and 255. DBI is reserved for parameterizing internal functions (see Chapter 11) for defining interprocessor communication flags (see Chapter 12.2.1) The data is deposited in this block in words. If the information is less than 16 bits in volume, the higher-order bits are filled with zeros. Entry of the data begins at data word zero and is continued in ascending order. The data block can accommodate up t o 65530 data words. Only 2042 o f these 65530 data words can be entered with the programmer. Accessing is possible up t o DW 255 using the "L DW" and "T DW" operations. Data words 256 t o 65529 can only be accessed using the "LRW", "LRD", "TRW", "TRD", LIR", "TIR" und "TNB" operations. Input 0000 : 0001 : 0003 : Values stored KH = A13C KT = 100.2 KF = +21874 DWO DW1 DW2 A1 3C 2100 5572 Figure 7-5 Example of the Contents of a Data Block Data blocks can also be generated or deleted in the control program (see Section 8.1.8). EWA 4 N E B S1 1 61 50-02d Introduction to STEP 5 CPU 945 Manual Program processing w i t h data blocks: A data block must be called i n the program w i t h the C DB X (x=O t o 255) or QX DXa (a=O t o 255) operation. Within a block, a data block remains valid until another data block is called. When the program jumps back into the higher-level block, t h e data block t h a t was valid before t h e block call is again valid. In all organization blocks (OBs), t h e data blocks used by the user program must be opened w i t h t h e relevant C DBxx operation. When PB20 is called, the valid data area is entered into a memory. When t h e program jumps back, this area is reopened. Figure 7-6 Validity Areas of Data Blocks 7.5 Processing Blocks The preceding sections have already described h o w t o use blocks. In addition, Chapter 8 describes all operations necessaryto work w i t h blocks. Of course, blocks t h a t have already been programmed can be changed. Possibilities for changing blocks are described here only briefly. The operating instructions f o r t h e particular programmer used explain t h e necessary steps in detail. EWA 4 N E B 81 1 61 50-02d Introduction to STEP 5 7.5.1 CPU 945 Manual Modifying the Program You can modify the program, regardless of block type, with the following programmer functions: INPUT a OUTPUT a STATUS (see Chapter 4.2.3) a With the above functions, you can make the following changes: a insert, delete, or overwrite statements m insert or delete segments. 7.5.2 Modifying Blocks Program modifications relate t o the contents of a block. You can also delete or overwrite entire blocks. However, this does not delete the blocks in the program memory. Instead, i t simply invalidates the blocks. The memory locations of these blocks cannot be written t o again. As a result, new blocks might not be accepted. The programmer reports the error message "No memory space". Eliminate this by compressing the PLC memory. 7.5.3 Compressing the Program Memory Figure 7-7 explains compressing. Internally one block is shifted per cycle. Program memory RAM Program memory RAM = Compression Available memory locations Lowest add ress Input possible Highest address Figure 7-7 Compression Process You can compress the internal program memory in the following ways: With the COMPRESS programmer function or a With the integral FB238 (COMPR, see Chapter 2.11.1). Shifting o f blocks cannot be interrupted. a EWA 4NEB 81 1 61 50-02d introduction to STEP 5 CPU 945 Manual 7.6 Number Representation STEP 5 allows you t o work w i t h numbers in different representations: Constant bytes (KB, KY) Fixed-point numbers (KF) Hexadecimal numbers (KH, DH) Floating-point numbers (KG) BCD-coded numbers Bit patterns (KM) Table 7-6 gives you an overview o f the different number representations. Table 7-6 Number Representations i n the CPU 945 number 0000 t o FFFF Hexadecimal number 0000 0000 t o FFFF FFFF number Floating-point number + + 16 (4 Tetrads) - 999 t o 999 (KH: F999 t o 0999) (8 Tetrads) - 999 9999 t o 999 9999 (DH: F999 9999 t o 0999 9999) + k 0.1469368 X 10-38... und 0.0 X 100 f 0.1701412 X 1039 The following figures show you t h e representation inside t h e CPU f o r 8-bit numbers 16-bit numbers 32-bit numbers 8-bit numbers Byte No. Bit No. KB format .+interpreted as number Figure 7-8 8-Bit Number Representation EWA 4NEB 81 1 61 50-02d Introduction t o STEP 5 CPU 945 Manual 16-bit numbers Word No. Byte No. Bit No. Fixed-point number (KF) + interpreted as twoascomplement KH format -+ represented as hexadecimal number KX x,y format -+ represented as 2-byte number Sign BCD number S=0000, for positive number S= 1111, for negative number Figure 7-9 16-Bit Number Representation 32-bit numbers ----.word No. Byte No. Bit No. Fixed-point number -+ interpreted as two's complement DH format -+ represented as hexadecimal number W2 I Io6 I 105 I BCD number 1 Exponentexp 24 23 Io4 I Sign 1o3 I 102 I 10' I I loo s=00002 for positive number S= ll11, for negative number Mantissa m Floating-point doubleword Figure 7- 10 32-Bit Number Representation 0 CPU 945 Manual lntroduction to STEP 5 Floating-point numbers A floating-point number consists of the mantissa m (24 bits) and the exponent exp (8 bits) (see Figure 7-11) The value of the floating-point number is derived from: G = m X 2exp. The exponent is a whole binary number in two's complement representation. Value range: 128 5 127 The mantissa is a scaled broken binary number in two's complement representation (see Figure 711). Value range: m=O +0.55m<+l -1 <m<-0.5 Mantissa m Mantissa m I Sign I Sign Figure 7- 1 1 Floating-Point Numbers - Values of the Bits Floating-point numbers can be represented in the following value range EWA 4NEB 81 1 61 50-02d 101 1 0 I Introduction t o STEP 5 CPU 945 Manual Entering floating-point numbers Z with the programmer Mantissa 1) Exponent (base 10) with sign Z= + 0.1 234567 X 10+2= 12.34567 Mantissa 1) Exponent (base 10) with sign Z=-0.5X 10-2=-0.005 Use floating-point numbers for large calculations, especially Multiplication and division and if you are working with very large or very small numbers. l) The entry is interpreted as a value after the decimal point (+0.1234567 or -0,.000 000) EWA 4NEB 81 1 61 50-02d 8.1 8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.1.6 8.1.7 8.1.8 8.1.9 Basic Operations ................... . . ....................... 8 Boolean Logic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SetIReset Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Load and Transfer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Timer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............ 8 Counter Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Comparison Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block Call Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Other Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 . 1 . 2 . 3 . 4 . 8 . 14 . 18 .20 .22 .28 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.2.7 8.2.8 8.2.9 8.2.10 8.2.1 1 Supplementary Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Load Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enable Operation . . . . . . . . . . . . . . . . . . . . . . ... . .. . . ... . . . . . . . . Bit Test Operations and Bit Setting Operations . . . . . . . . . . . . . . . . . . Digital Logic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shift Operations and Rotate Operations . . . . . . . . . . . . . . . . . . . . . . . Conversion Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrementllncrement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DisableIEnablelnterrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Processingoperation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sump Operations ............................................. Substitution Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 8 8 8 8 8 8 8 8 8 8 .29 .29 .30 .31 .33 .36 .41 .45 -46 -48 .51 .54 8.3 8.3.1 8.3.2 8.3.3 System Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Load and Transfer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Other Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 .61 8 .61 8 .67 8 .68 8.4 Condition Code Generation EWA 4NEB 81 1 61 50-02d ................................... 8 .69 ............................................... ............................. . . . . . . . . Transferring a Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output o f t h e Current Time (Example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Outputting t h e Current Counter Status (example) . . . . . . . . . . . . . . . . . . . . . . Conversion Characteristics o f GFD Conversion ........................... Structure o f t h e Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Effect o f t h e Processing Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . peration 8.3 8.4 8.5 8.6 8.7 8.8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.1 0 8.1 1 8.1 2 8.1 3 8.14 8.1 5 8.1 6 8.17 8.1 8 8.1 9 8.20 8.21 8.22 8.23 8.24 8.25 8.26 8.27 8.28 8.29 8.30 8.31 8.32 8.33 8.34 8.35 Overview o f operation types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview o f Boolean Logic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview o f t h e SetIReset Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview o f Load and Transfer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview o f Timer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview o f Counter Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview o f Fixed-Point Comparison Operations (16-Bit Operations) . . . . . Overview o f Fixed-Point Double-Word Comparison Operations (32-Bit Operations) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview o f Floating-Point Comparison Operations (32-Bit Operations) . . Overview o f Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview o f Code Block Call Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview o f Data Block Call Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview o f Other Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Load Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enable Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview o f Bit Operations .......................................... Effectof"TB"and"TBN"ontheRL0 ................................. Overview o f Digital Logic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview o f Shift Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview o f Conversion Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Decrement/lncrement Operations .................................... Disable/Enable Interrupt Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Selective DisablingIEnabling o f Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Processing Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview o f Jump Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview o f Binary Logic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview o f SetIReset Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview o f Load and Transfer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview o f Timer and Counter Operations ........................... ProcessingOperation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview o f Load and Transfer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Condition Code Settings f o r Comparison Operations ................... Condition Code Settings f o r " +Fv/"-F" Operations ..................... 8 8 8 8 8 8 - 6 -10 -16 -44 -47 -49 8 8 8 8 8 8 8 - 1 - 2 - 3 - 5 - 8 -44 -18 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 -19 - 19 -20 -22 -23 -28 -29 -30 -31 -31 -33 -36 -41 -45 -46 -47 -48 -51 -54 -55 -56 -58 -60 -62 -67 -68 -69 -70 EWA 4NEB 81 1 61 50-02d ........................... 8.38 8.39 8.40 8.41 8.42 8.43 + Condition Code Settings for " D"/"-D" Operation . . . . . . . . . . . . . . . . . . . . Condition Code Settings for floating-point arithmetics . . . . . . . . . . . . . . . . . Condition Code Settings for Digital Logic Operations . . . . . . . . . . . . . . . . . . Condition Code Setting for Shift Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . Condition Code Settingsfor Digital LogicOperations (16-bit arithmetics) . Condition Code Settings for Digital Logic Operations (32-bit arithmetics) . 8 - 71 8 - 72 8 - 72 8 - 73 8 - 73 8 - 74 STEP 5 Operations CPU 945 Manual 8 STEP 5 Operations This chapter describes the operations of the STEP 5 programming language. Compared with CPUs 941 t o 944,the operation set of CPU 945 has been considerably extended. The following operations, for example, are new in the CPU 945: Floating-point arithmetics Conversion operations Fixed-point multiplication and division Bit operations with data blocks S flag operations and Additional system operations For an overview o f the operations which can be used in the CPU 945 also refer t o the CPU 945 Pocket Guide. The STEP 5 programming language has the following three operation types Basic Operations include functions that can be executed in organization, program, sequence, and function blocks. Except for the addition (+F), subtraction (-F), and organizational operations, the basic operations can be input and output in the statement l i s t (STL), control system flowchart (CSF), or ladder diagram (LAD) methods of representation. Supplementary Operations include complex functions such as substitution statements, test functions, and shift and conversion operations. They can be input and output in STLform only. System operations usually involve absolute addressing and therefore require exact knowledge of the hardware, address space, etc. Only an experienced programmer should use them. System operations can be input and output in STL form only. Table 8.1 Overview of operation types Basic operations X X Supplementary operations X System operations X 8.1 Basic Operations Sections 8.1 .lthrough 8.1.9describe the basic operations. EWA 4NEB 81 1 61 50-02d X X STEP 5 Operations CPU 945 Manual 8.1.l Boolean Logic Operations Table 8.2 provides an overview o f Boolean logic operations. Combine AND operations through logic OR. Combine the result of the next AND logic operation (RLO) w i t h the previous RLO through logic OR. Combine expression enclosed in parentheses through logic AND. Combine the RLO o f the expression enclosed in parentheses with the previous RLO through logic AND. 1 Combine expression enclosed in parentheses through logic OR. Combine the RLO o f the expression enclosed in parentheses with the previous RLO through logicOR. 1 Close parenthesis. Conclude the expression enclosed in parentheses. Scan operand for "1" and combine w i t h RLO through logic AND. The result is "1" when the operand in question carriessignal state "1 ". Otherwise the scan results in "0". Combine this result with the RLO in the processor through IogicAND. 1 Scan operand for "1" and combine w i t h RLO through logic OR. The result is "1" when the operand in question has signal state "1 ". Otherwise the scan results in "0". Combine this result with the RLO in the processorthrough logic OR. 1 Scan operand for "0" and combine with RLO through logic AND. The result is "1" when the operand in question has signal state "0". Otherwise the scan results in "0". Combine this result with the RLO in the processorthrough logic AND. 1 - ON A ID I Q F S D T C A Scan operand for "0" and combine w i t h RLO through logic OR. The result is "1" when the operand in question has signal state "0" Otherwise the scan results in "0". Combine this result with the RLO in the processor through logic OR. 1 Parameter 0.0 t o 127.7 0.0 t o 127.7 0.0 t o 255.7 0.0 t o 4095.7 0.0 t o 255.15 0 t o 255 0 t o 255 If the scan follows an RLO limiting operation directly (first scan), the scan result is reloaded as a new RLO. STEP 5 Operations CPU 945 Manual 8.1.2 SetIReset Operations Setlreset operations store the result o f logic operation (RLO) formed i n the processor. The stored RLO represents the signal state o f t h e addressed operand. Storage can be dynamic (assignment) or static (set and reset). Table 8.3 provides an overview of the setlreset operations. Examples follow the table. Table 8.3 Overview of the SetIReset Operations Set The first time t h e program is scanned w i t h RLO= "1 ",signal state "1" is assigned t o the addressed operand. An RLO change does n o t affect this status. U t Reset The first time t h e program is scanned w i t h RLO= "1 ",signal state "0" is assigned t o the addressed operand. A n RLO change does n o t affect this status. Assign Every time the program is scanned, the current RLO is assigned t o t h e addressed operand. I Parameter 0.0 t o 127.7 0.0 t o 127.7 0.0 t o 255.7 0.0 t o 4095.7 0.0 t o 255.1 5 EWA 4NEB 81 1 61 50-O2d CPU 945 Manual STEP 5 Operations 8.1 -3 Load and Transfer Operations Use load and transfer operations t o do the following: exchange information between various operand areas prepare times and counts for further processing load constants for program processing. Information flows indirectly via accumulators (ACCU 1 and ACCU 2). The accumulators are special registers in the CPU for temporary storage. In the CPU 945 they are each 32 bits long. The accumulators are structured as shown in Figure 8.1. 24 23 31 16 1 5 8 7 0 llllll111lllll111ll1111111111111 High-Byte Hig h-Byte ACCU I - H H - ACCU 1 ACCU 1-LL High-Word ACCU l-H Low-Word ACCU l - L Figure 8.1 Accumulator Structure When processing 16-bit commands, the CPU 945 is fully compatible with CPUs 941 t o 944. You can load and transfer permissible operands in bytes or words. For exchange in bytes, information is stored right-justified, i.e., in ACCU-LL. The remaining bits are set t o zero. For exchange in words, information is stored right-justified, i. e. in ACCU l-L. The remaining bits are set t o zero (not for LIR command). You can process the information in the t w o accumulators using various operations. You can program load and transfer operations graphically only in combination with timer or counter operations; otherwise you can represent them only in STLform. The various operations are listed in the following table. STEP 5 Operations CPU 945 Manual Load ACCU 1 is loaded into ACCU 2. The operand contents are copied into ACCU 1 regardless o f the RLO. The RLO is n o t affected. Transfer The contents o f ACCU 1 are assigned t o an operand regardless o f t h e RLO. The RLO is n o t affected. Parameter 0 t o 127 0 t o 126 0 t o 124 0 t o 127 0 t o 126 0 t o 124 0 t o 127 128 t o 255 0 t o 126 128 t o 254 0 t o 255 0 t o 254 0 t o 255 0 t o 254 0 t o 252 0 to4095 0 to4094 0 to4092 0 t o 255 0 t o 255 0 t o 255 0 t o 254 0 t o 255 0 t o 255 random b i t pattern (16 bits) 0 t o FFFF - 32768 t o + 32767 0 t o 255 per byte (2 bytes) 0 t o 255 any 2 alphanumeric characters 0.0 t o 999.3 0 t o 999 0 t o FFFF FFFF k0.1469368X 10-38t o ~ 0 . 1 7 0 1 4 1 2 X1039; 0.0X 100 4 1 1 2 Load i n BCD Binary times and counts are loaded i n t o ACCU 1 in BCD code regardless o f t h e RLO. Parameter 0 t o 255 These operands cannot be used for transfer For "transfer" the process image is updated EWA 4NEB 81 1 61 50-02d CPU 945 Manual STEP 5 Operations Load Operation: During loading, information is copied from a memory area, e.g., from the PII, into ACCU 1. The previous contents of ACCU 1 are shifted t o ACCU 2. The original contents of ACCU 2 are lost. Example: An input byte, an input word and an input double word are loaded consecutively from the PI1 into the accumulator. Loading does not change the PI1 (see Figure 8.2). ACCU 2 Lost information Information from the PI! ACCU 1 Figure 8.2 Execution of the Load Operation Transfer Operation: During transfer, information from ACCU 1 is copied into the addressed memory area, e.g., into the PIQ. This transfer does not affect the contents of ACCU 1. When transfer t o the digital output area (T PY 0 t o 127, T PW 0 t o 126) occurs, the byte or word in question in the PIQ is automatically updated. Example: Figure 8.3 shows how byte a, the low byte o f the low word in ACCU 1, is transferred t o QB 5. ACCU 2 mI 31 23 15 Information in the PIQ ACCU 1 7 0 31 23 15 7 0 TAB 5 4 ~ ~ I C ~ I ! ~ a Lost information Previous value o f QB 5 Figure 8.3 Transferringa Byte EWA 4NEB 81 1 61 50-02d CPU 945 Manual STEP 5 Operations Loading and Transferring a Time (See also Timer and Counter Operations) During graphic input, QW 62 is assigned t o output BI o f a timer. The programmer automatically stores the corresponding load and transfer operation in the control program. Thus the contents of the memory location addressed with T 10 are loaded into ACCU 1. Afterwards, the contents o f the accumulator are transferred t o the process image addressed with QW 62. In this example, you can see timer T 10 at QW 62 in binary code. Outputs BI and DE are digital outputs. The time at output BI is in binary code. The time at output DE is in BCD code with time base. A I L W I 22 SP T 10 L T 10 T QW 62 A I L IW 22 SP T 10 LC T 10 T QW 50 5.0 Loading and Transferring a Time (Coded) transfer operation transfers the accumulator contents t o the process image memory location addressed by QW 50. A coding operation is possible only indirectly for the graphic representation forms LAD and CSF by assigning an address t o output DE of a timer or counter location. However, with STL, this operation can be entered with a separate statement. EWA 4NEB 81 1 61 50-02d 5.0 STEP 5 Operations CPU 945 Manual 8.1.4 Timer Operations The program uses timer operations t o implement and monitor chronological sequences. The following table provides an overview of timer operations. Examples follow the table. Table 8.5 Overview of Timer Operations Pulse Timer The timer is started on the leading edge of the RLO. When the RLO is "O", the timer is set to "0". Scans result in signal state "1" as long as the timer is running. U Extended Pulse Timer The timer is started on the leading edge of the RLO. When the RLO is "O", the timer is not affected. Scans result in signal state "1" as long as the timer is running. U On-Delay Timer The timer is started on the leading edge of the RLO. When the RLO is "O", the timer is set to "0". Scans result in signal state "1" when the timer has run out and the RLO is still pending at the input. Stored On-Delay Timer The timer is started on the leading edge of the RLO. When the RLO is "O", the timer is not affected. Scans result in signal state "1" when the timer has run out. The signal state becomes "0"when the timer is reset with the "R" operation. Off-Delay Timer The timer is started on the trailing edge of the RLO. When the RLO is "l",the timer is set to its initial value. Scans result in signal state "1" as long as the RLO at the input is "1" or the timer is still running. P - - - P P P P P P Reset Timer The timer is reset t o its initial value as long as the RLO is "1 ". When the RLO is "O", the timer is not affected. Scans result in signal state "0"as long as the timer is reset or has not been started yet. I Parameter ID T 0 to 255 * The corresponding graphical PG symbol is indicated below the operations. EWA 4NEB 811 6150-02e CPU 945 Manual STEP 5 Operations Loading a Time Timer operations call internal timers. When a timer operation is started, the word in ACCU l - L is used as a time value. You must therefore first specify time values i n the accumulator. You can load a constant time value w i t h L KT constant time value or any other load command These data types must be i n BCD code w i t h t h e corresponding time base. A timer can also be loaded w i t h random ACCU contents. However, t h e correct format o f t h e time value must be observed. Loading a Constant Time Value: The following example shows h o w you can load a time value o f 40 sec. 0 Operation Operand I KT L 40.2 I Coded time base (0 t o 3) L Time(Oto999) Key f o r Time Base: Base 0 Factor 0.01 S 1 0.1 3 2 S 10s IS Example: KT 40.2 corresponds t o 40 X 1 sec. Tolerance: The time tolerance is equivalent t o t h e time base. Therefore, always use the smallest time base possible. Possible settings f o r the time 40 sec. KT 400.1 400 X 0.1 sec. - KT 40.2 40 X lsec. - Isec. 39 sec. t o 40 sec. KT 4.3 4 - 30 sec. t o 40 sec. X 10 sec. 0.1 sec. 10 sec. 39.9 sec. t o 40 sec. CPU 945 Manual STEP 5 Operations Loading a Time as Input, Output, Flag, or Data Word Load Statement: L DW 2 The time 638 sec. is stored in data word DW 2 in BCD code. Bits 14 and 15 are insignificant for the time value. 15 0 11 y Three-digit time value (in BCD code) Bit 2 Time base Key for Time Base: Base 00 01 Factor 0.01 S 0.1 S 10 19 IS 10s You can also use the control program t o write t o data word DW 2. Example: Store the value 270 X 100 msec. in data word DW 2 of data block DB3. Output of the Current Time 1 You can use a load operation t o put the current time into ACCU 1 and process i t further from there (see Figure 8.4). Use the "Load in BCD" operation for digital display output. ' 1 Current time in T1 LCTI L T1 ACCU 1 I I I Binary time value Time base Three-digit time value in BCD code ..-...,.... ;; : :: :: * : , :: :S . . . . . . . . . . .L, indicates bit positions occupied by "0" ..........L ., Figure 8.4 Output of the Current Time (Example) 1 The current time is t h e time value in the addressed timer STEP 5 Operations CPU 945 Manual Starting a Timer In the PLC, timers run asynchronously t o program execution. The time that has been set can run out during a program execution cycle. I t is evaluated by the next time scan. In the worst case, an entire program execution cycle can go by before this evaluation. Consequently, timers should not activate themselves. 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Program + Signal from timer 17 0 The schematic shows the "nth 1" processing cycle since timer T 17 *was started. Although the timer ran out shortly after the statement " = Q 8.4", output Q 8.4 remains set. The change is not considered until the next program execution cycle. 1 I I L KT 100.0 SP T A I I I T 17 17 - - - --- -- - f 1sec. - n . t p = Q 8.4 L ------ --- n: number o f program execution cycles tp: program scan time * KT 100.0 is equal t o 1 sec. Except for "Reset timer," all timer operations are started only on an edge o f the RLO. (The RLO alternates between "0" and "1 ".) After being started, the loaded time is decremented in units corresponding t o the time base until it reaches zero. If there is an edge change while the timer is running, the timer is reset t o its initial value and restarted. The signal state of a timer can be interrogated with Boolean logic operations. CPU 945 Manual STEP 5 Operations Pulse Example: Output Q 4.0 is set when the signal state at input 1 3.0 changes from "0" t o "1 ". However, the output should not remain set longer than 5 sec. A 1 3.0 L KT 50.1 SP T 1 A T 1 = Q 4.0 . . . ... ... . I .. . .. ~ ~ m * .~ Time in sec. Extended pulse Example: Output Q 4.1 is set for a specific time when the signal at input 13.1 changes t o "1 ". The time is indicated in IW 15. .... .... t ... ... ..... . A I L IW 3.1 15 SE T 2 A T 2 = Q 4.1 Time t Note The time tolerance is equivalent t o the time base. EWA 4NEB 81 1 61 50-O2d STEP 5 Operations CPU 945 Manual Example: Output Q 4.2 is set 9 sec. after input 1 3.5. It remains set as long as t h e input is " I " A I 3.5 L KT 9.2 SD T 3 A T 3 = Q 4.2 * Time in sec. Note The time value "9 sec." will have a sharper tolerance if you load t h e timer w i t h t h e statement "L KT900.0". Stored On-Delay and Reset Example: Output Q 4.3 is set 5 sec. after 1 3.3. Further changes i n t h e signal state a t input 1 3.3 d o n o t affect t h e output. Input 1 3.2 resets timer T 4 t o its initial value and sets output Q 4.3 t o zero. EWA 4NEB 81 1 61 50-O2d STEP 5 Operations CPU 945 Manual Off-Delay Example: When i n p u t 1 3.4 is reset, o u t p u t Q 4.4 is set t o zero after a certain delay (t). The value i n FW 13 specifies t h e delay time. A I L FW 1.4 13 5 SF T A T 5 Q 4.4 = Time i n sec. 8.1.5 Counter Operations The CPU uses counter operations t o handle counting jobs directly. Counters can count u p and down. The counting range is f r o m 0 t o 999 (three decades). The f o l l o w i n g table provides an overview o f t h e counter operations. Examples f o l l o w t h e table. Table 8.6 Overview o f Counter Operations I Operation Opiand Mearting Set Counter The counter is set o n t h e leading edge o f t h e RLO. l - Reset Counter The counter is set t o zero as long as t h e RLO is "1 " countup The count is incremented by 1 o n t h e leading edge o f t h e RLO. W h e n t h e RLO is "Q", t h e count is n o t affected. CountDown The count is decremented b y 1 o n t h e leading edge o f t h e RLO. W h e n t h e RLO is "O", t h e count is n o t affected. Parameter Q t o 255 EWA 4NEB 81 1 61 50-02d STEP 5 Operations CPU 945 Manual Loading a Count Counter operations call internal counters. When a counter is set, the word in ACCU 1 is used as a count. You must therefore first store counts in the accumulator. A constant count is loaded with: L KC constant count 0r The data for these words must b e in BC0 code. any other load command A count can also be loaded with random ACCU contents. However, the correct format o f the count must be observed. Loading a Constant Count: The following example shows howthe count 37 is loaded. - Operation Operand L KC 37 Count (0 t o 999) Loading a Count as Input, Output, Flag, or Data Word Load statement: L DW 3 The count 410 is stored in data word DW 3 in BCD code. Bits 12 t o 1 5 are insignificant for the count. 15 I Bit 0 11 Three-digit count (in BCD code) I Scanning the Counter Use Boolean logic operations t o scan the counter status (e.g., A Cx). As long as the count is not zero, the scan result is signal state "1 ". EWA 4NEB 8 1 1 61 50-02d CPU 945 Manual STEP 5 Operations Outputting the Current Counter Status You can use a load operation t o put the current counter status into ACCU 1 and process it further from there. The "Load in BCD" operation outputs a digital display (see Figure 8.5). The "Load in BCD" operation is suitable for output via a numeric display. Current Counter Status in C2 L C2 ACCU 1 I Binary count I Three-digit count in BCD code indicates bit positions occupied by "0". Figure 8.5 Outputting the Current Counter Status (exampie) Setting a Counter "S" and Counting Down "CD" Example: When input 14.1 is switched on (set), counter 1 is set t o the count 7. Output Q 2.5 is now "1 ". Every time input 14.0 is switched on (count down), the count is decremented by 1. The output is set t o "0"when the count i s "0". EWA 4NEB 81 1 61 50-02d CPU 945 Manual STEP 5 Operations Resetting a Counter "R" and Counting Up "CU" Example: When input 14.0 is switched on, the count in counter 1 is incremented by 1. As long as a second input (1 4.2) is "1 ",the count is reset to "0". The A C1 operation results in signal state "1" at output Q 2.4 as long as the count is not "0". CPU 945 Manual STEP 5 Operations 8.1.6 Comparison Operations Processing a Comparison Operation When using comparison operations, make sure that the operands have the same number format. Execution of the operations is independent of the RLO. The result is binary and is available as RLO for further program execution. If the comparison is satisfied, the RLO is "1 ",otherwise it is ' ' 0 " ~ Executing the comparison operations sets the condition codes (see Section 8.4). Example: The values o f the input words 18 and 20 are compared. If they are equal, output Q3.0 is set. Comparison Operations Fixed-point comparison operations compare the contents of ACCU 2-L and ACCU l-L. The contents of the accumulators are interpreted as two's complement and remain unchanged. The comparison takes into account the number notation o f the operands, i.e. the contents of ACCU l - L and ACCU 2-L are interpreted as fixed-point numbers. Table 8.7 Overview of Fixed-Point Comparison Operations-61( Mearting Comparison for equal t o Compare t w o fixed-point numbers for equal to: if ACCU 2-L = ACCU l-L, the RLO is "1 ". - Comparison for not equal t o Compare t w o fixed-point numbers for not equal to: if ACCU 2-Ls ACCU 1-L, the RLO is "1 ". Comparison for greater than Compare t w o fixed-point numbers for greater than: if ACCU 2-L > ACCU l-L, the RLO is "1 ". Comparison for greater than or equal t o Compare t w o fixed-point numbers for greater than: if ACCU 2-L2ACCU l-L, the RLO is "1 ". Comparison for less than compare t w o fixed-point numbers for less than: if ACCU 2-L < ACCU l-L, the RLO is "1 ". Comparison for less than or equal t o compare t w o fixed-point numbers for less than or equal to: if ACCU 2-LIACCU l-L, the RLO is "1 ". STEP 5 Operations CPU 945 Manual The comparison operations are also possible as 32-bit operations. 32-bit operations compare the whole acccumulator contents. The fixed-point double word comparison operations interpret the contents o f the accumulators as two's complement. The floating-point comparison operations interpret the contents o f the accumulators as floating-point numbers. I I Comparison for equal t o Compare t w o fixed-point double words for equal to: if ACCU 2=ACCU l , the RLO is "1". I Comparison for not equal t o Compare t w o fixed-point double words for not equal to: if ACCU 2;tACCU l , the RLO is "1 ". I Comparison for greater than Compare t w o fixed-point double words for greater than: if ACCU 2 > ACCU l , the RLO is "1 ". Comparison for greater than or equal t o Comparetwofixed-pointdoublewordsforgreaterthan or equal to: if ACCU 2lACCU l.the RLO is "1 ". I Comparison for less than compare t w o fixed-point double words for less than: if ACCU 2 < ACCU l.the RLO is "1 ". Comparison for less than or equal t o Compare t w o fixed-point double words for less than or equal to: if ACCU 2 SACCU l, the RLO i s "1 ". Table 8.9 Overview of Floating-Point Comparison Operations (32-Bit Operations) Meaning Comparison for equal t o Compare t w o floating-point numbers for equal to: if ACCU 2=ACCU 1,the RLO is "1". Comparison for not equal t o Compare t w o floating-point numbers for not equal to: if ACCU 2sACCU l , the RLO is "1". Comparison for greater than Compare t w o floating-point numbers for greater than: if ACCU 2 > ACCU l,the RLO is "1 ". Comparison for greater than or equal t o Comparetwofloating-point numbers forgreaterthan or equal to: if ACCU 2lACCU l, the RLO is "1 ". Comparison for less than Compare t w o floating-point numbers for less than: if ACCU 2 < ACCU l , the RLO is "1 ". Comparison for less than or equal t o Compare t w o floating-point numbers for less than or equal to: if ACCU 2sACCU l,the RLO is "1 ". EWA 4NEB 81 1 61 50-O2d I STEP 5 Operations 8.1.7 CPU 945 Manual Arithmetic Operations Arithmetic operations interpret the contents of the accumulators as fixed-point numbers ( l 6 bits) fixed-point numbers (32 bits) or as floating-point numbers (32 bits) and manipulate them. The result is stored in ACCU 1. The operations are listed in the following table and explained in an example following the table. For condition code generation and overflow and underflow behaviour refer t o Section 8.4. "F" and "D" operations expect fixed-point numbers in two's complement notation in ACCU l - L or ACCU 2-L and ACCU 1 or ACCU 2. After the operation, the sign of "+F" operations and "-F" operations is also in ACCU l - H : - : FFFFH : O0OOH "G" operations expect normalized floating-point notations in ACCU I or ACCU 2 (for SlMATlC floating-point format refer t o Section 7.6). + Table 8.10 Overview of Arithmetic O~erations I Addition Add t w o fixed-point numbers ACCU 1-L=(ACCU 2-L)+(ACCU l - L ) ACCU l=ACCU 2 +ACCU 1 Add t w o floating-point numbers ACCU 1=ACCU 2 +ACCU 1 Subtraction Subtract t w o fixed-point numbers ACCU 1-L=(ACCU 2-L) - (ACCU l-L) ACCU 1= ACCU 2 - ACCU 1 Subtract t w o floating-point numbers ACCU 1=ACCU 2 - ACCU 1 Multiplication Multiply t w o fixed-point numbers ACCU 1=(ACCU 2-L) X (ACCU l-L) Multiply t w o floating-point numbers ACCU 1=ACCU 2 X ACCU 1 Division Divide t w o fixed-point numbers ACCU 1= (ACCU 2-L) : (ACCU l-L) In ACCU l-L: result; in ACCU l-H: remainder Divide t w o floating-point numbers ACCU 1 =ACCU 2 : ACCU 1 EWA 4NEB 81 1 61 50-02d STEP 5 Operations CPU 945 Manual Processing an Arithmetic Operation Before an arithmetic operation is executed, both operands must be loaded into the accumulators. Note When using arithmetic operations, make sure the operands have the same number format. Arithmetic operations are executed independently o f the RLO. The result is available in ACCU 1 for further processing. The contents of ACCU 2 are not changed. These operations do not affect the RLO. The condition codes are set according t o the results. L C 3 L C l The v a l u e o f c o u n t e r 3 i s l o a d e d i n t o ACCU l . The v a l u e o f c o u n t e r 1 i s l o a d e d i n t o ACCU 1 . The p r e v i o u s c o n t e n t s o f ACCU 1 a r e s h i f t e d t o ACCU 2. The c o n t e n t s o f t h e two a c c u m u l a t o r s a r e i n t e r p r e t e d a s 1 6 - b i t f i x e d p o i n t numbers a n d a d d e d . T QW The r e s u l t , 12 c o n t e n t s o f ACCU 1, i s t r a n s f e r r e d t o o u t p u t word QW 1 2 . 0 ACCU2 876 +F + 668 m Accul - 1 544 EWA 4NEB 81 1 61 50-02d mwfl ACCU1 CPU 945 Manual STEP 5 Operations 8.1.8 Block Call Operations Block call operations specify the sequence of a structured program. Tables 8.1 1 and 8.1 2 provide an overview of the block call operations. Examples follow the table. Table 8.1 1 Overview of Code Block Call Operations Jump unconditionally Program scanning continues in a different block regardless of the RLO. The RLO is not affected. Jump conditionally Program scanning jumps t o a different block when the RLO is "1 ". Otherwise program execution continues in the previous block. The RLO is set t o "1 ". Q A Parameter 0 t o 255 * 0 t o 255 0 t o 255 * 0 t o 255 DOU * DOC 1 Jump unconditionally Afunction block (extension) is called regardless of the RLO. Jump conditionally Afunction block (extension) is called conditionally when the RLO is "l". Otherwise, program execution continues in the previous block. The RLO is set t o " 1". I Parameter 0 t o 255 * Please notethat certain OBsIFBs are reserved by the operating system. CPU 945 Manual STEP 5 Operations Table 8.11 Overview of Block Call Operations (continued) Block end The current block is terminated regardless of the RLO. Program scanning continues in the block in which the call originated. The RLO is "carried along" but not affected. - BEU Block end, unconditional The current block is terminated regardless of the RLO. Program scanning continues in the block in which the call originated. The RLO is "carried along" but not affected. BEC Block end, conditional When the RLO is "l ",the current block is terminated. Program scanning continues in the block in which the call originated. During the block change, the RLO remains "1 ". If the RLO is "O", the operation is not executed. The RLO is set t o "1" and linear program execution continues. Program scanning is not interrupted. The RLO is not affected. A data block (DX) is called regardless of the RLO. G DB U Generate and delete a data block * Adata block t o store data is set up regardless o f the RLO. GX DX U Generate and delete a data block * A data block (extension) is generated regardless o f the RLO. A Parameter 0 t o 255 ** * ** The length o f the DBlDX must be deposited in ACCU 1 prior t o execution of the operation. In the case of length 0, the DB is deleted. Data block DBl is reserved. CPU 945 Manual STEP 5 Operations Call a Data Block "C DB" Data blocks are always called unconditionally. All data processed following the call refers t o the data block that has been called. This operation cannot generate new data blocks. Blocks that are called must be loaded or generated prior t o program execution. Example: Program block PB3 needs information that has been programmed as data word DW 1 in data block DB10. Other data, e.g., the result o f an arithmetic operation, is stored as data word DW 3 in data block DB20. C DB 10 T h e i n f o r m a t i o n from d a t a word DW I i n d a t a block DB 1 0 i s loaded into L DW l t h e a c c u m u l a t o r . The c o n t e n t s of ACCU 1 a r e s t o r e d i n d a t a word DW 3 of d a t a block D B 2 0 . C DB 20 T DW 3 The "CX DX" operation calls a Dx data block and operates like the "C DB" operation. Generating and Deleting a Data Block The "G DB X" statement does not call a data block. Instead, it generates a new block. If you want t o use the data in this data block, call it with the "C DB" statement. Before the "G DB" statement, indicate in ACCU l - L the number of data words the block is t o have (see the example below). A data block generated w i t h the "G DB" statement can have 2 t o 65530 data words. If you wish t o generate a DB with n data words, you must load n - l into ACCU l-L. If you specify zero as the data block length, the data block in question is deleted, i.e., it is removed from the address list. I t is considered nonexistent (see sections 2.1 1.1 and 2.1 1.2). EWA 4NEB 81 1 6150-02d CPU 945 Manual STEP 5 Operations The length o f t h e data block set u p is optional. It can be set up i n the CPU 945 w i t h a maximum length o f 64k words. However, please note t h a t programmers can process blocks o f limited length only. The following overview shows the response o f t h e CPU t o various events during t h e generation o f a new DB. r ..,., j;:::::::;222;jj j j2~~i;;;jj22222jj~2jj2~;2; zi.::::;2222j <<<. :.:<.: .:::::::::::: i.... :;:;:;~;:;:;<:;:;::::;222$$$$$$$$$$$$$$$$$$$:;::::::;:;22222~$jj:;:;:$~~;~:;:;:;$@ ovBfNgKGn;;~;~2;;;;;; $;;;;g$$;;;;:${;;;;;$;;;;;;;;;;;;;;;;;;;;;;;;<;;;;;;;;;;;;@g#~#$&$;~@::; ;j: jj2#;Z:E:;::::::::.: :.:.m::A::::::::::::::::-::::::-:m::-::z::::::::::ms G DB - DB is t o be deleted DB is deleted - DB is t o be deleted, b u t is n o t None existing - DB is t o be deleted, b u t cannot be None deleted as it is stored in the EPROM - DB is t o be regenerated DB is generated. - DB is t o be regenerated, b u t DB is None already existing - Memory space is not sufficient - Length in ACCU I - L > FFFgH The CPU goes into STOP w i t h "TRAF" or jumps t o t h e relevant error response OB and does n o t generate a DB. The CPU goes into STOP w i t h "TRAF" or jumps t o t h e relevant error response OB and does n o t generate a DB. The "GX DX" operation generates a DX data block and operates like "G DB". Note The block is retained as a "dead" block until t h e PLC memory is compressed (see Section 7.5.3). CPU 945 Manual STEP 5 Operations Generating a Data Block t h e same t i m e , t h e o l d c o n t e n t - s of ACCU 1 a r e s h i f t e d t o ACCU 2 Data block 5 i s g e n e r a t e d w i t h a l e n g t h of 1 2 8 d a t a words ( 0 0 0 0 ) i n t h e RAM o f t h e PC and e n t e r e d i n t h e block address l i s t . The n e x t t i m e t h e "G DB5" operation is processed. it h a s n o e f f e c t i f t h e c o n t ~ e n t sof ACCU l a r e n o t 0 . Deleting a Data Block G DB 5 +O i s l o a d e d i n t o ACCU l . A t t h e same t i m e , t h e o l d c o n t e n t s of ACCU 1 a r e s h i f t e d t o ACCU 2 Data b l o c k 5 , which i s i n t h e RAM o f t h e P C , is declared i n v a l i d and removed from t h e block address l i s t . CPU 945 Manual STEP 5 Operations Block End "BE" The "BE" operation terminates a block. Data blocks do not need t o be terminated. "BE" is always the last statement in a block. In structured programming, program execution jumps back t o the block where the call for the current block was made. Binary logic operations cannot be continued in a higher-order block. Example: Program block PB3 is terminated by the "BE" statement. The "RE" s t a t e m e n t t e r m i n a t e s p r o g r a m b l o c k PB 3 a n d causes program e x e c u t i o n t o r e t u r n t o o r g a n i z a t i o n b l o c k OB1. Unconditional Block End "BEU" The "BEU" operation causes a return within a block. However, jump operations can by-pass the "BEU" operation in function blocks (see Sections 8.2.1 0 and 8.3.4). Binary logic operations cannot be continued in a higher-order block. Example: Scanning of function block FB21 is terminated regardless o f the RLO. PB8 FB21 The "BEU" s t a t e m e n t c a u s e s p r o g r a m 1 JC= JU F 6 2 1 execution t o leave function block FB21 and r e t u r n t o program b l o c k .:=: --: BEU i ... \ . BE \ BE E W A 4 N E B 8 1 1 6 1 50-02d BEU PB8. CPU 945 Manual STEP 5 Operations Conditional Block End "BEC" The "BEC" operation causes a return within a block if the previous condition has been satisfied (RLO = 1). Otherwise, linear program execution is continued with RLO "1 ". Example: Scanning o f program block FB 20 is terminated if the RLO= "1 ". ....................... P07 F0 20 T h e "BEC" 1 s t a t e m e n t c a u s e s program e x e c u t i o n t o r e t u r n t o program block P R 7 f r o m f u n c t i o n b l o c k FB20 i f A 1 20.0 S Q 1.0 A I 20.0 in- p u t I 2 0 . 0 is " I . " BEC JU F020 8.1.9 EEC Other Operations These operations can be programmed in STL form only. Table 8.1 3 Overview of Other Operations "No" Operation "No" Operation U Display Generation Commands for the Programmer 4 1 Parameter 0 t o 255 130 131 132 133 255 Is treated by the CPU like a no-operation Generate space line by carriage return Switch over t o statement l i s t (STL) Switch over t o control system flowchart (CSF) Switch over t o ladder diagram (L4D) Terminate segment Display generation operations Within a block, program parts are subdivided by "BLD" display generation operations into segments. The no-operations and display generation operations are only relevant for the programmer when representing the STEP 5 program. During the execution of these statements, the CPU executes no operation. CPU 945 Manual 8.2 STEP 5 Operations Supplementary Operations Supplementary operations extend the operations set. However, compared t o basic operations, which can be programmed in all blocks, supplementary operations have the following limitations: They can be programmed in function blocks only. They can be represented in STL form only. Sections 8.2.1 through 8.2.1 1 describe the supplementary operations. 8.2.1 Load Operation As with the basic load operations, the supplementary load operation copies information into the accumulator. Table 8.1 4 explains the load operation. Table 8.14 Load Operation L Q 4 ID 4 Load A word from the system data is loaded into ACCU 1 regardless o f the RLO. I parameter :L and SD 104. An important output module is plugged in atstart address 4.If the time-out is triggered by this address, the CPU is t o g0 into the STOP mode. Otherwise a signal is t o be given and program execution is t o continue. YOUcan program this example in OB24. KH 0 0 0 0 high word of the address of the important module are loaded into the accumulators. ~f the two values are not equal, output Q 1 2 . 0 is set. :L RS 1 0 4 The contents of SD 104 and the :L KH F004 low word of the address of the important module are loaded into the accumulators. If the two values are not :><F L1 := Q 12.0 equal, output Q 1 2 . 0 is set again. :EEC Program scanning continues in the block where the call originated. :STP If the two values are equal, the CPU goes into the STOP mode. STEP 5 Operations 8.2.2 CPU 945 Manual Enable Operation Use t h e enable operation (FR) t o execute t h e f o l l o w i n g operation even w i t h o u t edge change: starta t i m e r set a counter count up a n d down. Table 8.1 5 presents t h e enable operation. A n example follows t h e table. Table 8.1 5 Enable Operation Enable a TimerICounter Timers and counters are enabled o n t h e leading edge o f t h e RLO. This operation restarts a timer, sets a counter, o r causes a counter t o count u p o r d o w n w h e n t h e RLO "1" is pending a t t h e "Start" operation. A Parameter 0 t o 255 0 t o 255 Input 1 2.5 starts a timer T 2 as A I 2.5 SE T 2 duration o f t h e pulse. A T 2 = Q 4.2 If o u t p u t Q 3.4 i s reset repeatedly, t h e t i m e r should also b e restarted repeatedly. S t a r t a timer T 2 a s extended O u t p u t Q 4 . 2 i s set f o r 50 s e c . A Q 3.4 ~f o u t p u t Q 3 . 4 is set ( p o s i t i v e FR T 2 e d g e c h a n g e o f t h e RLO) d u r i n g t h e t i m e i n w h i c h i n p u t I 2 . 5 is BE s e t , t h e timer T 2 is r e s t a r t e d . Output Q 4.2 t h e r e f o r e remains s e t a t t h e r e s t a r t e d t i m e o r is reset. I f i n p u t I 2 . 5 is n o t set d u r i n q t h e edqe change of o u t p u t Q 3 . 4 , t h e t i m e r is n o t r e s t a r t e d . * This time value has a tolerance o f + 10 sec. Use a smaller time base if necessary. STEP 5 Operations CPU 945 Manual Bit Test Operations and Bit Setting Operations 8.2.3 Bit test a n d b i t setting operations scan digital operands b i t by b i t and affect them. Bit test operations must always be a t t h e beginning o f a logic operation. Table 8-12 provides an overview o f these operations. Table 8.16 Overview o f Bit Operations TB Test a b i t f o r signal state "1" A single b i t is scanned regardless o f t h e RLO. The RLO is affected according t o t h e bit's signal state (see Table 8.13). U Test a bit f o r signal state "0" Asingle b i t is scanned regardless o f t h e RLO. The RLO is affected according t o t h e bit's signal state (see Table 8.13). TBN SU Set a bit unconditionally The addressed b i t is set t o "1" regardless o f t h e RLO. The RLO is n o t affected. I U A Reset a bit unconditionally The addressed b i t is set t o "0" regardless o f t h e RLO. The RLO is n o t affected. Parameter 0.0 t o 127.7 0.0 t o 127.7 0.0 t o 255.7 0.0 t o 255.1 5 0.0 t o 255.1 5 0.0 t o 255.1 5 0.0 t o 255.1 5 0.0 t o 255.1 5 Table 8.17 shows h o w t h e RLO is f o r m e d during t h e b i t test operations "TB" a n d "TBN". A n example f o r applying t h e b i t operations follows t h e table. Table 8.17 Effect o f "TB" a n d "TBN" o n t h e RLO Result o f logic operation CPU 945 Manual STEP 5 Operations A photoelectric barrier that C DB 10 CU C 10 C a l l d a t a b l o c k 10. I n p u t I 3.0 l o a d s t h e c o u n t o f c o u n t e r 10 w i t h t-he c o n s t a n t 0. With e a c h p o s i t i v e edge change a t I 2.0, t h e c o u n t e r i s i n c r e m e n t e d tically and start counting again. o 0 I F R LC C C T DW TBND 4.0 5.2 10 10 12 b y 1. The c o u n t e r i s r e s e t b y 12.8 A s l o n g a s b i t 8 o f d a t a word e i t h e r i n p u t 1 4.0 o r f l a g F 5.2. The c u r r e n t c o u n t o f t h e c o u n t e r i s s t o r e d i n d a t a word D W 12 i n BCD c o d e . D W 12 i s z e r o , p r o g r a m p r o c e s s i n g JC FB TB D jumps t o f u n c t i o n b l o c k FB5. T h i s 5 is t h e c a s e f o r t h e f i r s t , t h i r d , f i f t h e t c . b a t c h o f 100 p i e c e s . 12.8 A s l o n g a s b i t 8 o f d a t a word JC FB TB D 6 D W 12 i s "l", p r o g r a m e x e c u t i o n jumps t o f u n c t i o n b l o c k FB6. T h i s 12.11 is t h e c a s e f o r t h e s e c o n d , fourth, = F 5.2 s i x t h e t c . b a t c h o f 100 pieces. When d a t a b i t 11 o f d a t a word DW 12 becomes "1" ( t h e c o u n t i s t h e n 800), f l a q F 5 . 2 i s s e t conditionally. A photoelectric barrier that counts piece goods is installed at input 1 10.0. After every 256 pieces, the counter is supposed to be reset and start counting again. I :cu C :A I :L K C :A :S C 10.0 20 11.0 0 20 I n p u t I 11.0 l o a d s t h e c o u n t o f c o u n t e r 20 w i t h t h e c o n s t a n t O . The c o u n t i s i n c r e m e n t e d b y 1 w i t h each p o s i t i v e edge change a t i n p u t I 10.0. ~f t h e c o u n t h a s r e a c h e d 256-1008 ( b i t 8 i s "ln), p r o g r a m :TB C 20.8 : J C =FULL e x e c u t i o n jumps t o t h e l a b e l "FULL". O t h e r w i s e t h e b l o c k i s terminated. :BEU FULL :RU :BE C 20.8 B i t 8 o f c o u n t e r C 20 i s s e t t o ,,(J rr u n c o n d i t i o n a l l y . Then t h e c o u n t i s a g a i n 0008. NOTE Times and counts are stored in the timerlcounter word in hexadecimal notation in the 10 least significant bits (bits 0 to 9). The time base is stored in bits 12 and 13 of the timer word. STEP 5 Operations CPU 945 Manual Digital Logic Operations 8.2.4 Digital logic operations combine the contents of ACCU l - L and ACCU 2-L logically bit by bit. The result isdeposited in ACCU l-L; the contents o f ACCU l - H and ACCU 2 are retained. Table 8.18 provides an overview of these digital logic operations. Examples follow the table. Table 8.1 8 Overview of Diqital Loqic Operations I I I l , w I Combine bit by bit through logic AND Combine bit by bit through logic OR Combine bit by bit through EXCLUSIVE OR Processing a Digital Logic Operation A digital logic operation i s executed regardless of the RLO. It also does not affect the RLO. However, it sets condition codes according t o the result o f the arithmetic operation (see Section 8.4). The result o f the arithmetic operation is available in ACCU 1 for further processing. The contents o f ACCU 2 are not affected. L K H OOFF Load a c o n s t a n t i n t o ACCU 1. The p r e v i o u s c o n t e n t s o f ACCU 1 a r e s h i f t e d t o ACCU 2 . Combine t h e c o n t e n t s o f b o t h a c c u m u l a t o r s b i t b y b i t t h r o u g h l o g i c AND. T QW 82 T r a n s f e r t h e r e s u l t i n g c o n t e n t s f r o m ACCU 1 t o o u t p u t word QW 8 2 . Set the 8 high-order bits in input word IW 92 t o "0". Compare both words bit by bit. If corresponding bits are both "1 ",the result bit is set t o "1 ". 16 15 IW 92 ACCU 2 31 16 31 16 KH OOFF AND ACCU l ACCU l 1- ~o~o~o~o~o~o~o~o~ Result mM f l I QW82 EWA 4NEB 8 1 1 61 50-O2d CPU 945 Manual STEP 5 Operations L IW 71 Load input word IW 71 into ACCU 1. L IW 5 Load input word IW 5 into ACCU 1. The previous contents of ACCU 1 are shifted to ACCU 2 . Combine the contents of both accumulators bit by bit through EXCLUSIVE OR. T QW 86 Transfer the result (contents of ACCU 1) to output word QW 8 6 . The result bit is set t o "1" only if corresponding bits in ACCU 1 and ACCU 2 are unequal. 16 EWA 4NEB 81 1 61 50-02d 15 CPU 945 Manual STEP 5 Operations 8.2.5 Shift Operations and Rotate Operations These operations shift a bit pattern in ACCU 1. The contents of ACCU 2 are not affected. Table 8.1 9 provides an overview of these operations. Examples follow the table. Table 8.19 Overview of Shift Operations SLW Shift t o the left The bit pattern (16 bits) in ACCU l - L is shifted t o the left. Positions becoming vacant are padded with zeros. The result is stored in ACCU l-L. The contents o f ACCU l - H and ACCU 2 are not affected. SRW Shift t o the right The bit pattern (16 bits) in ACCU l - L is shifted t o the right. Positions becoming vacant are padded with zeros. The result is stored in ACCU l-L. The contents o f ACCU l - H and ACCU 2 are not affected. SSW Shift t o the right (with sign) The bit pattern (16 bits) with sign in ACCU l - L is shifted t o the right. Positions becoming vacant are padded with the sign (bit 15). The result is stored in ACCU l-L. The contents o f ACCU l - H and ACCU 2 are not affected. 1 4 I I parameter 0 t o 15 SLD Shift t o the left The bit pattern (32 bits) in ACCU 1 is shifted t o the left. Positions becoming vacant are padded with zeros. The result is stored in ACCU 1. ACCU 2 is not affected. SS D Shift t o the right (with sign) The bit pattern (32 bits) with sign in ACCU 1 is shifted t o the right. Positions becoming vacant are padded with the sign (bit 31). The result is stored in ACCU 1. ACCU 2 is not affected. RLD Rotate t o the left (32 bits) The bit pattern in ACCU 1 is rotated t o the left. Positions becoming vacant are padded with the bits shifted. The result is stored in ACCU 1. ACCU 2 is not affected. RRD Rotate t o the right (32 bits) The bit pattern in ACCU 1 is rotated t o the right. Positions becoming vacant are padded with the bits shifted. The result is stored in ACCU 1. ACCU 2 is not affected. 4 I parameter 0 t o 32 STEP 5 Operations CPU 945 Manual Processing a Shift Operation Execution o f shift operations is unconditional. The RLO is not affected. However, shift operations set condition codes. CC 1 indicates the status o f the last bit shifted out of the accumulator, CC 0 = "0".The condition codes can be scanned with jump functions. The shift statement parameter indicates the number o f bit positions by which the contents of ACCU 1 are t o be shifted t o the left (SLW) or t o the right (SRW). Bit positions vacated during shifting are assigned zeroslsign. The contents of the bits that are shifted are lost. Following execution of the operation, the status of the last bit shifted out o f the accumulator is indicated in the CC 1 bit. This bit can be evaluated. A shift operation with parameter "0" is handled like a "NOP" operation. The central processor processesthe next STEP 5 statement with no further reaction. Before executing a shift operation, load the operand t o be processed into ACCU 1. The altered operand is available there for further processing. L DW 2 Load t h e c o n t e n t s of d a t a word DW 2 i n t o ACCIJ 1. S h i f t t h e b i t p a t t e r n i n ACCU 1 t h r e e p o s i t i o n s t o t h e l e f t . T DW 3 T r a n s f e r t h e r e s u l t ( c o n t e n t s o f ACCU 1 ) t o d a t a word DW 3 . positions t o the left. 16 EWA 4NEB 81 1 61 50-O2d 15 464,, (DW 2) CPU 945 Manual STEP 5 Operations L IW128 Load t h e v a l u e o f i n p u t word I W 1 2 8 i n t o ACCU 1. S h i f t t h e b i t p a t t e r n i n ACCU l - L f o u r p o s i t i o n s t o t h e r i g h t . T QW 160 T r a n s f e r t h e r e s u l t ( c o n t e n t s of ACCU P T , ) t.o o u t p u t word QW 1 6 0 . The value 35Zl0 is stored in IW 128. Shift the corresponding bit pattern in ACCU 1 four positions t o the right t o divide the value 35210by 24 = 16 (without remainder). 16 15 3521, (IW 128) ;*,m1\ --I SRW4 L KF-64 Load t h e f i x e d - p o i n t number - 6 4 i n t o ACCU 1. S h i f t t h e b i t p a t t e r n i n ACCU l - L f o u r p o s i t i o n s t o t h e r i g h t . Transfer t h e r e s u l t ( c o n t e n t s of ACCU l - L ) t o o u t p u t word QW 1 0 . Therefore, the bit pattern is shifted four positions t o the right (SSW 4). ssw4 16 15 16 15 + mmmmTi&j CPU 945 Manual STEP 5 Operations S h i f t t h e b i t p a t t e r n i n ACCU 1 t h r e e p o s i t i o n s t o t h e r i g h t . T QD20 T r a n s f e r t h e r e s u l t ( c o n t e n t s o f ACCU I.) t o t h e o u t p u t d o u b l e word Therefore, the bit pattern is shifted 3 positions t o the right (SSD 3). 16 15 16 15 mm SSD3 11111111111111111-1 rnlllllllllllololol CPU 945 Manual STEP 5 Operations Processing a Rotate Operation Execution of rotate operations is unconditional. The RLO is not affected. However, rotate operations set condition codes. CC1 indicates the status o f the last bit shifted out o f the accumulator, CC0 = " 0 " .The condition codes can bescanned with jump functions. The rotate statement parameter indicates the number of bit positions by which the contents of ACCU 1 are t o be rotated t o the left or right. Bit positions vacated during rotating are padded with the bits shifted. Following execution of the operation, the status of the last bit shifted out o f the accumulator is indicated in the CC1 bit. This bit can be evaluated. Before executing a rotate operation, load the operand t o be processed into ACCU l . The altered operand is available there for further processing. L I D 12 Rotate the bit pattern in ACCU 1 five positions to the left. Transfer the result (contents of ACCU 1) t o the output double word 16. mmM 17 ~ l ~ o ~ l ~ l ~ o ~ l ~ l l l ~ RLD 5 ACCU l EWA 4NEB 81 1 61 50-02d CPU 945 Manual 8.2.6 STEP 5 Operations Conversion Operations Conversion operations convert the values in ACCU 1. ACCU 2 is unaffected. The individual operations are listed in Table 8.20 and explained in examples following the table. Execution o f these operations does not depend on the RLO. The effects on the condition codes and the behaviour in the case o f non-convertibility are explained in Section 8.4. Table 8.20 Overview of Conversion Operations CSW Two's complement (32 bits) The contents o f ACCU 1 are inverted bit by bit. Afterwards the double word 0000 0001, is added. Result in ACCU 1. DEF Fixed-point conversion (16 bits) BCD += binary The contents o f ACCU l - L are interpreted as a three-digit BCD number with sign (see Section 7.6) and converted into a 16-bit fixed-point number. Result in ACCU l-L, ACCU l - H is unaffected. DUF Fixed-point conversion (16 bits) binary 4 BCD The contents o f ACCU l - L are interpreted as a 16-bit fixed-point number and converted into a three-digit BCD number with sign. Result in ACCU 1-L, ACCU l - H is unaffected. DED Double word conversion (32 bits) BCD 4 binary The contents o f ACCU 1 are interpreted as a seven-digit BCD number and converted into a 32-bit fixed-point number. Result in ACCU 1. DUD Double word conversion (32 bits) binary += BCD The contents o f ACCU 1 are interpreted as a 32-bit fixed-point number and converted into a BCD number. Result in ACCU 1. FDG Conversion of fixed-point number into floating-point number The contents o f ACCU 1 are interpreted as a 32-bit fixed-point number and converted into a floating-point number. Result in ACCU 9 . GFD Conversion of floating-point number into fixed-point number The contents o f ACCU 1 are interpreted as a floating-point number and converted into a 32-bit fixed-point number. Result in ACCU 1. EWA 4NEB 81 1 61 50-02d 8-41 STEP 5 Operations CPU 945 Manual Example L DW 12 Load the contents of data word DW 12 into ACCU 1 . Invert all bits in ACCU 1. T QW 20 15 L IW 12 15 Load the contents of input word IW 12 into ACCU 1. Invert all bits. Add a "1" at the least significant position. T DW100 Transfer the altered word to data word DW 100. Form the negative value of the value in input word I W 12. 15 10(0101010(010101-1 15 I m m l CPU 945 Manual STEP 5 Operations Conversion of accumulator cont-ents; BINARY SPS=FEHL T DD100 + BCD (BCD -+ BINARY) Evaluation of the latching overflow bit in case of non-convertibility Transfer the altered word to DD 1 0 . Error evaluation 32-bit fixed-point number 231. L ID 12 . . . . . . . . . . . . . . 0 20 Load the contents of ID 1 2 into ACCU 1 . Conversion of accumulator contents; fixed-point number + floatingpoint number (floating-point number + fixed-point number) SPS=FEHL Evaluation of the latching overflow bit in case of non-convertibility T Transfer the altered accumulator contents to DD 1 0 0 . DD 1 0 0 Error evaluation . . o 32-bit floating-point number CPU 945 Manual STEP 5 Operations Accuracy of GFD Conversion Exact conversion is possible with integer floating-point numbers only. Floating-point numbers with fractions of 1 are converted t o the next-smaller integer value. An exception are the floating-point numbers in the range o f (-1 < G < 0 ) . The floating-point numbers o f this range are converted t o a fixed-point zero. The floating-point number -1 is converted t o the fixed-point number -1. The absolute conversion error is < 1 (see Fig. 8.6). Fixed-point value ideal conversion line .Floating-point value Figure 8.6 Conversion Characteristicsof GFD Conversion EWA 4NEB 81 1 61 50-02d STEP 5 Operations CPU 945 Manual 8.2.7 Decrernentllncrement The decrementlincrement operations change the data loaded into ACCU 1-LL. Table 8.21 provides an overview of the decrementlincrement operations. An example follows the table. Table 8.21 Decrementllncrement O~erations The contents of ACCU 1-LL are either decremented or incremented by the number indicated in the parameter (without carry). Execution of the operation is unconditional. ACCU l - H , ACCU 1-LH and ACCU 2 are unaffected. Decrement Decrement ACCU 1-LL 17 Increment lncrement ACCU 1-LL t I Parameter 0 t o 255 Processing Execution o f the decrement and increment operations is independent o f the RLO and does not affect the RLO or the condition codes. The parameter indicates the value by which the contents o f ACCU 1 are t o be changed. The operations refer t o decimal values; however, the result is stored in ACCU 1 in binary form. Changes relate only t o ACCU 1-LL. Call data block DB6. 1010, by 16 and storethe result in data word D W 8. L KH 1010 Load hexadecimal constant 10IOH into ACCU ].-L. Increment the low byte of ACCU l by 16. The result, 1 0 2 0 ~ ,is located in ACCU l. In addition, decrement the incrementation result by 33 and store the new result in data word T DW D Transfer the contents of ACCU 1 (1020H) to data word DW 8 . Since the incrementation result is still in ACCU 1, you can decrement by 33 directly. D The result would be F F F H . However, since the high byte of 33 ACCU l-L is not decremented along with the low byte, the result in ACCU 1 is 10FFH. T EWA 4NEB S1 1 61 50-O2d DW 9 The contents of ACCU l-L are transferred to DW 9 (lOFFH). STEP 5 Operations 8.2.8 CPU 945 Manual DisableIEnable lnterrupt Global disablinglenabling of interrupts The disablelenable interrupt operations affect interrupt and time-controlled program execution. They prevent process or time interrupts from interfering with the processing o f a sequence o f statements or blocks. Table 8.22 lists the disablelenable interrupt operations. An example follows the table. Operation I Table 8.22 DisableIEnable Interrupt . Operations . Operand I I 1 Meaning IA Disable interrupt RA Enable interrupt IAIRA applies for OBs 2,3,4, 5,6,10,11,12,13. IAIRA does not apply for OBs 26,33,35. (System error level) Processing Execution o f the disablelenable interrupt operations does not depend on the RLO. These operations do not affect the RLO or the condition codes. After the "IA" statement is processed, no more interrupts are executed. The "RA" statement cancels the effect o f "IA". Disable interrupt processing in a specific program section and then = Q 7.5 A I 2.3 JU FB 3 Disable interrupt. If an interrupt occurs, the program section between the operations IA and RA is scanned without interruption (unless "RA" has been programmed in FB3 ) . RA Enable interrupt. Interrupts that occurred in the meantime are processed after the "RA" operation.1 L 1 Only one interrupt can be stored for each interrupt line. 8-46 EWA 4NEB 81 1 61 50-02d STEP 5 Operations CPU 945 Manual Selective disablinglenabling of interrupts The SIM operation sets the interrupt mask. With this interrupt mask, each interrupt can be disabledienabled individually. The LIM operation is used t o read the current interrupt mask. Execution o f these operations does not depend on the RLO. These operations do not affect the RLO and the condition codes. Table 8.23 Selective DisablingIEnabling of Interrupts Meaning SIM Set interrupt mask (32 bits) The system error level and the time and process interrupt OBs are selectively disabledienabled. Time and process interrupts (OBs 2 t o 6, 10 t o 13) enabled in the interrupt mask are not processed, if the interrupts have been disabled by the IA operation. After interrupt enabling with RA, the time and process interrupts enabled in the interrupt mask are processed. IAIRA does not affect processing of the system error OBs (OBs 26, 33, 35). OBs 26, 33, 35 can be enabled1 disabled only bysettingiresetting of bit 0 in the interrupt mask. LIM Read interrupt mask (32 bits) The current interrupt mask can be read in ACCU 1. Structure of the interrupt mask In the interrupt mask, each time and process interrupt OB and each system error OB is assgined one bit (see Fig. 8.7). If a b i t is set, the corresponding OB is enabled. If a b i t is not set, the OB is disabled. Bits 0 t o 9 are defaulted with " 1",i.e. the interrupts are enabled. . . . I I l I reserved I OBII OBlO Figure 8.7 Structure of the Interrupt Mask STEP 5 Operations CPU 945 Manual B i t p a t t e r n w i t h m a r k i n g of OB4 a n d O B 1 3 b i t s Set i n t e r r u p t m a s k . L o a d b i t p a t t e r n w i t h b i t s set Otherwise, the interrupt mask should remain unaffected. f o r s y s t e m e r r o r OBS, O B ~a n d Set i n t e r r u p t m a s k . 8.2.9 Processing Operation The processing operation (DO) can handle STEP 5 statements in "indexed" form. Use it t o change the parameter o f an operand while the control program is being scanned. Table 8.24 and the example that follows explain the processing operation. Table 8.24 Processina Ooerations Process a flag or data word. DO A ID T FW DW A parameter 0 t o 254 0 t o 255 Processing The statement "Process flag or data word pendently o f the RLO. X" is a two-word statement that is executed inde- I t consists o f the following t w o related statements: The first statement contains the processing operation and specifies a flag or data word. The second statement specifies the operation and the operand ID that the control program is t o process. Enter 0 or 0.0 here as parameter. CPU 945 Manual STEP 5 Operations Note If a value other than 0 o r 0.0 is specified in the CPU 944, this value is replaced by 0 or 0.0. The control program works w i t h t h e parameterthat is stored in the flag or data word called by t h e first statement. I f you are indexing binary operations, inputs, outputs, or flags, indicate the b i t address i n t h e high byte o f this w o r d and t h e byte address in the l o w byte. In all other cases, the high byte must be "0". The following operations can be combined w i t h t h e processing statement: A, AN, 0, ON' (with operands I, Q, T, C, F) (with operands I, Q, F) FR T, RT, SF T, SD T, S1 T, SS T, SE T FR C, RC, SC, CD C, CU C Binary logic operations Setlreset operations Timer operations Counter operations DL, DR, DW, DD, T, C, RS, RT Load operations i n BCD code DL, DR, DW, DD, RS, RT JU=, JC=, JZ=, JN=, JP=, JM=, JO= SLW, SRW, SLD, RLD, SSD, RRD * Jump operations Shift operations Decrement and increment The A I, AN I, 0 I, ON I operations become t h e A Q, AN Q, 0 Q, ON Q operations in combination with DO FW or DO DW if the byte address in the data or flag word is greater than 127. Figure 8.8 shows h o w data w o r d contents specify t h e parameter o f the next statement. FB X DB6 DW12 DW13 KH=0108 KH=OOOl Executed program :C DB 6 :DO DW 12 :A I :DO DW : F R T 0.0 DB 6 :A I 8.1 :FR T 1 13 0 Figure 8.8 Effect of the Processing Operation EWA 4NEB 81 1 61 50-02d :C STEP 5 Operations CPU 945 Manual The following example shows how new parameters are generated each time the program is scanned. :L KB 20 Load constant 20 into ACCU l. :L KH 0 Load hexadecimal constant 0 into state "0". The "index register" for the parameter of the data words is DW 1. L1 to the data word whose address is stored i n data word DW 1 . :L DW :L KB1 1 Load data word DW 1 into ACCU 1. Load constant 1 into ACCU 1. Data word DW 1 is shifted to ACCU 2. ACCU 2 and ACCU I are added and the result is stored i n ACCU 1 : +F (incrementing the data word address). DW :T 1 Transfer the contents of ACCU 1 to data word DW 1 (new data word address) . KB 100 :L The constant 100 i s loaded into ACCU 1 and the new data word address is shifted to ACCU 2. :<=F The accumulators are compared to see if ACCU 2-L :J C =L1 ACCU l-L. Jump conditionally to label L 1 if ACCU 2 - L ACCU l-L. STEP 5 Operations CPU 945 Manual 8.2.1 0 Jump Operations Table 8.25 provides an overview of the jump operations. An example follows the table. Table 8.25 Overview of Jump Operations Jump unconditionally The unconditional jump is executed independently o f conditions. Jump conditionally The conditional jump is executed if the RLO is "1 ". If the RLO is "On, the statement is not executed and the RLO is set t o "1 ". JZ = Sump if the result is "zero" The jump is executed only if CC 1 =O and CCO=O The RLO is not changed. JN = Jump if the result is "not zero" The jump is executed only if CC 1 #CC 0 The RLO i s not changed. JP = U JM = JO Jump if the result is positive The jump is executed only if CC 1 = 1 and CC 0 = 0 The RLO is not changed. Jump if the result is negative The jump is executed only if CC 1 =O and CC O= 1 The RLO is not changed = Jump on overflow (OV= 1) The jump is executed i f an overflow occurs and the OV bit is set t o 1. Otherwise the jump is not executed. The RLO is not changed. JOS = A Jump on overflow/latching (OS= 1) The jump is executed if an overflow occurs and the OS bit is set t o 1. The RLO i s t not changed. ID Jump label (up t o 4 characters) JUR & Jump relative Linear program processing is interrupted and continued at the position which has been determined by the jump displacement. Jump displacement in words: - 32768 t o + 32767 STEP 5 Operations CPU 945 Manual Processing the Jump Operations A symbolic jump destination (jump label) must always be entered next t o a jump operation. This jump label can have up t o four characters, the first of which must be a letter of the alphabet. When programming, please be aware o f the following: The absolute jump displacement cannot exceed+ 127 or - 128 words in the program memory. Some statements take up t w o words (e.g., "Load a constant"). For long jumps, insert an intermediate destination. Jumps can be executed only within a block. Jumping over segment boundaries ("BLD 255") is not permitted. Load i n p u t word IW I i n t o set, program execution jumps t o the label "AN 1". If input word IW 1 and output word QW 3 do not agree, program processing jumps back t o the label "AN 0 " . Otherwise input word IW 1 and data word DW 12 are compared. If input word IW 1 is greater than or less than data word DW 12, program execution jumps t o the "Destination" label. :L KH 0 0 0 0 ACCU 1. ~f the c o n t e n t s o f ACCU 1 e q u a l z e r o 1, j u m p t o t h e l a b e l " A N 1". O t h e r w i s e :JZ A N = I :A I 1.0 process t h e n e x t s t a t e m e n t (A I 1 . 0 ) . AN^ :L IW 1 C o m p a r e i n p u t w o r d IW :L QW 3 o u t p u t w o r d QW 3 . ~f t h e y a r e : XOW not equal, 1 and set i n d i v i d u a l b i t s i n ACCU 1 . I f t h e c o n t e n t s o f ACCU 1 a r e :JN =AN0 :L :L IW DW 1 12 not zero, "AN 0 " . j u m p t o the label O t h e r w i s e process t h e next statements. :><F Compare i n p u t word I W 1 a n d d a t a w o r d DW 1 2 . I f t h e y a r e not equal, :JB = s e t RLO t o " 1 " . Desti- If t h e R L O = " l " , nation "Destination" j u m p t o the label. I f t h e RLO="On, next D e s t . :A 1 I process the statement. 12.2 The "L ..." statement does not affect the condition codes. An addition (+F) is executed with the constant OOOOH so that the "JZ" operation can evaluate the contents of the accumulator. CPU 945 Manual STEP 5 Operations Processing the "JUR" Operation Execution o f the "JUR" operation is independent o f the RLO. The parameter specifies the jump displacement directly. For example, parameter " 1 " means that processing will continue with the next one-word statement. Parameter " 2" means processing will continue with the one-word statement directly after the next one-word statement. Such labeling includes the following special features: The jump displacement is not corrected automatically. If changes are made in the Section of the program that is jumped over, the jump destination can be displaced. Caution Avoid jumps over block boundaries since you have no control over the absolute location of blocks in the internal user memory. EWA 4NEB 81 1 61 50-02d STEP 5 Operations CPU 945 Manual 8.2.1 1 Substitution Operations If you plan t o process a program with various operands, i. e. independent of the current operand, it is advisable t o assign parameters t o individual operands (see Section 7.4.4). Substitution operations are possible in function blocks only. If you have t o change the operands, you only need t o reassign the parameters in the function block call. These parameters are processed in the program as "formal operands". Special operations are necessary for this processing. However, these special operations are no different in their effect than operations without substitution. A brief description o f these operations and examples follow. Binary Logic Operations Table 8.26 provides an overview of binary logic operations. Table 8.26 Overview of Binarv Loaic O~erations AND operation, scan for signal status "1 " The scan result is "1 ",if the corresponding actual operand is in signal status " 1 ". Otherwise, the scan result is "0".This result is combined with the RLO in the processor through logic AND. 1 OR operation, scan for signal status "1" The scan result is "1 ",if the corresponding actual operand is in signal status " 1 ". Otherwise,the scan result is "0".This result is combined with the RLO in the processor through logic OR. 1 AN = ON = AND operation, scan for signal status "0" The scan result is "1 ",if the corresponding actual operand is in signal status "0".Otherwise, the scan result is "0".This result is combined with the RLO in the processor through logic AND. 1 U OR operation, scan for signal status "0" The scan result is " 1 ",if the corresponding actual operand is in signal status "0".Otherwise, the scan result is "0".This result is combined with the RLO in the processor through logic OR. 1 Inputs, outputs, and flags addressed in binary form Timers and counters I,Q BI T, C 1 If t h e scan follows immediately after an operation which reloads the RLO (first input bit scan), the scan result is taken t o form the new RLO. EWA 4NEB 81 1 61 50-02d CPU 945 Manual STEP 5 Operations SetIReset Operations Table 8.27 provides an overview of the setlreset operations. Table 8.27 Overview of SetIReset Operations A change of the RLO does not affect this status. Example: FB30 is assigned parameters in OBI. :JU FB 3 0 NAME :LOGIC :A =ON1 :A I 2.0 :AN =ON2 :AN I 2.1 : I 2.0 :O =ON3 :O I 2.2 O N 2 I 2.1 :S =MOT5 :S Q 7.3 ON3 I 2.2 := =OFF1 .= Q 7.1 VAL1: I 2.3 :A =VALl :A I 2.3 OFF1: Q 7.1 :A =ON2 :A I 2.1 OFF2 : Q 7.2 :ON =ON3 :ON I 2.2 MOT5 : Q 7.3 :RB =MOT5 :R Q 7.3 := =OFF2 .= Q 7.2 ON1 : : BE :BE :BE STEP 5 Operations CPU 945 Manual Load and Transfer Operations Table 8.28 provides an overview o f t h e load and transfer operations. A n example follows t h e table. Operation I Table 8.28 Overview of Load and Transfer Operations Opennd I I I I L = LC = = T = for L 1 Meatiin~f I Load a formal operand. 0 Load a formal operand in BCD code. I 1 I LW = LD I = 1 I U I I 1 I Load the bit pattern of a formal operand. Load the bit pattern of a forme1 operand. Transfer toaforrnal operand. FY, FW, FD IB, IW, ID, QB, Q w , QD, PY, PW, DL, DR, DW, DD, RS, RT, C, T I,Q BY, W, D T, C for LC = Timers and counters for LW = Bit pattern D KF, KH, KM, KY, KS, KT, KC for LD = Bit pattern (32 bits) D KG 1, Q BY, W, D forT = FD, FY, FW, IB, IW, ID QB, QW, QD, PY, PW, DL, DR, DW, DD, RS, RT T,C STEP 5 Operations CPU 945 Manual Example: FB34 is assigned parameters in PBI. NAME : LOAD/TRAN I0 I1 L1 LW1 LC1 T1 LW2 : : : : :A :L :S 34 :J U FB 1 2.0 1 2.1 FW 1 0 KC 1 4 0 7 : C : QW 4 KC 1 6 0 : : BE EWA 4NEB S1 1 61 50-02d :A :LW :S :A :CU :CU :LC :T :A :R :R :LW :LC -. .I =F :R :BE =I0 =L1 C =I1 =LW1 C 1 C C =LC1 =T1 1 C C 6 7 2.2 6 7 2.7 6 7 =LW2 =LC1 :A :I, :S :A :L :S :A :CU :CU :LC :T :A :R :R :L 1 2.0 FW 1 0 C 6 I 2.1 KC 1 4 0 C 7 1 2.2 6 C C 7 C 7 QW 4 I 2.7 6 C C 7 KC 1 6 0 :LC C 7 C 7 . .U =F C 7 :R :BE STEP 5 Operations CPU 945 Manual Timer and Counter Operations Table 8.29 provides an overview of timer and counter operations. Examples follow the table (also refer t o Sections 8.1.4 and 8.1.5). Table 8.29 Overview of Timer and Counter Operations FR = Enable a formal operand for cold restart. (For a description, see "FT" or "FC", according t o the formal operand). RD = Reset a formal operand (digital). SP = Start a pulse timer specified as a formal operand using the value stored i n the accumulator. SD = Start an on-delay timer specified as a formal operand using the value stored in the accumulator. SEC = Start an extended pulse timer specified as a formal operand using the value stored in the accumulator or set a counter specified as a formal operand using the count specified in the accumulator. SSU = Start a stored on-delay timer specified as a formal operand using the value stored in the accumulator or start the count up of a counter specified as a formal operand. SFD = Start an off-delay timer specified as a formal operand using the value stored in the accumulator or start the count down of a counter specified as a formal operand. 1 Formal operand Timers and counters1 1 "SP" and "SD" do not apply to counters Specifying Times and Counts As with the basic operations, you can specify a time or count as a formal operand. In this case, you must distinguish as follows whether the value is located in an operand word or is specified as a constant. Operand words can be o f parameter type "I" or "Q" and of data type "W". Use the "L=" operation t o load them into the accumulator. Constants can be o f parameter type "D" and o f data type "KT" or "KC". Use "LW=" t o load these formal operands into the accumulator. EWA 4NEB 811 6150-O2e STEP 5 Operations CPU 945 Manual The following examples show how to work with timer and counter operations. Example 1 : ,::=?. .............................. ......................... ......................... ............................................................................ ............ .............................................. ....................... ,:,:,:,:,:,:,:,:,;:;:;:X#$*::::?:::: ................................. .......... .......... .......... ................................ ....................... :.:.:.:............................................................................................ ................................................................................................................................... ................................................................ ........................................................ A a.;;Eg#gw@f@gg# :,:,:.:.:.:.:.:.:.:,~&@&f@~;;g~@~~;;;g#$g;~ :J U F B 3 2 NAME : T I M E I 5 : I 6 : ;$:;:;:;:;:;:;:;z~353~$$$~:;2:;:;:;22222~:;,~;:;:;:;:;3$2~;22; ;;;;gg~~~~&.gg###&*$;;;;;;;;;;;;;;$ A:$::;:;:;::;:~~:;~::;:;:;:;:;:;:;:;::.:.A:::::::?:~.:~~~?:::: :AN =I5 :AN I 2.5 :A =I6 :A I 2.6 :L KT :L KT 5.2 :SF T 5 2.5 5.2 I 2.5 :SFD =TIM5 I 2.6 :A =I5 :A I TIM5 : T 5 :AN =I6 :AN I 2.6 TIM6 :T 6 :L KT :L KT 5.2 OUT6: Q 7 . 6 :SSU =TIM6 :SS T 6 :A =TIM5 :A T 5 :O =TIM6 :O T 6 .= =OUT 6 .= Q 7.6 :A 12.7 :A I 2.7 :RD =TIM5 :R T 5 :RD =TIM6 :R T 6 :BE 5.2 :BE :BE Example 2: ............................................................... ... :::::::::::::::::::::j:.~zz2:;22jjjl~j::j:.~:f:::::::: ............ ~<.~.:~<<<$<<(#<.:.:~.:.:.:.#;;.:.:~.:.:::j#::::::@ ~ & @ ~ @.::.::........................ @ # [ @ :::# @ # ~ ~ ~ $ ~:.,.:.:.:................................... ............ ......... ....... ........... ::::f:::~:::::::::::::::::::::~::::: ;::::::::::::::::::::::::::......................................................... .......................................................................................... .......................................................................... ::::::::*:::i::i.:.' m::.::+:::::z.7 :::::A:%=:;:;:; @sjggem$& K$a@$&m s.g;3BgflD$t~E@]i@Q&&$m ; ; ; ; ; STL :JU FB 3 3 :A =I2 :L KC 17 :A I :L KC 2.2 17 : S E C =COU5 :S C I 2 : I 2.2 :A :A 1 2.3 I 3 : I 2.3 : S S U =COU5 :CU C 5 I 4 : I 2.4 :A :A I 2.4 COU5 : C 5 : S F D =COU5 :CD C 5 OUT3: Q 7.3 :A =COU5 :A C 5 .. - =OUT3 := Q 7.3 :A I :A I 2.7 :RD =COU5 :R C 5 NAME :COUNT :BE - :BE EWA 4NEB 81 1 61 50-02d =I3 =I4 2.7 : BE 5 CPU 945 Manual STEP 5 Operations Processing Operation Table 8.30 and the example that follows explain the processing operation. Table 8.30 Processina Operation DO = t Process formal operand The substituted blocks are called unconditionally. DB, PB, SB, FBI, OB 1 As actual operands,function blocks cannot have block parameters Example: B CPU 945 Manual 8.3 STEP 5 Operations System Operations System operations and supplementary operations have the same limitations. You can program them only as follows: in function blocks in the STL method of representation System operations involve absolute addressing and therefore require exact knowledge o f the hardware of the CPU address space of the system data area, etc. Only experienced programmers should use them. 8.3.1 Load and Transfer Operations Use these load and transfer operations t o address the entire program memory o f the CPU. They are used mainly for data exchange between the accumulator and memory locations that cannot be addressed by operands. Table 8.31 provides an overview o f the load and transfer operations. /I\ Caution The TIR, TDI, TNB, TNW, TRW, TRD operations are memory changing operations with which you can accesss the program memory of the CPU. These accesses are not monitored by the operating system. Improper use o f the operations can lead t o changes in the program and t o a CPU crash or dangerous statuses. STEP 5 Operations CPU 945 Manual Table 8.31 Overview of Load and Transfer Operations lOperation Operand LIR Meart#n# Load the register indirectly Load the contents o f a 16-bit wide memory location (addressed by ACCU 1) into the specified 16-bit register. Transfer the register indireclty Transfer the contents of a 16-bit wide memory location (addressed by ACCU 1) t o the specified 16-bit register. A Parameter (register number) 0 1 P 3 8 ACCU l - L ACCU l - H ACCU 2-L ACCU 2-H DB L LDI Load the register indirectly Load the specified 32-bit register w i t h the contents of a double word, which is addressed by ACCU 1. TDI Transfer the register indirectly Load the contents o f the specified 32-bit register into a double word, which is addressed by ACCU 1. Code (register) AI ACCUI A2 ACCU2 SA* SAC= Step address counter BR Base address register Transfer a data block (word by word) Transfer a memory area block by block into another memory area. End address destination area: ACCU 1 End address source area: ACCU 2 Use even addresses (20 bits wide) only. Afterthe execution o f the operation, the accumulators are decremented by 2 X the number o f words TNW A Parameter (Number o f words t o be transferred) 0 t o 255 * TDI SA: The absolute address o f t h e operation following the TDI operation is transferred t o the double word addressed by ACCU 1. Note Operations LIR 0 t o LIR 3 change only the specified 16 bits of the ACCUs. The othe 16 bits remain unchanged. CPU 945 Manual STEP 5 Operations Table 8.31 Overview of Load and Transfer Operations (continued) End address destination area (20 bits wide): End address source area (20 bits wide): ACCU 1 Load a word from the system data area into ACCU l-L. 0 t o 255 The offset is multiplied by 2 (word offset) and the result added t o the contents of the BR register. t o the contents of the BR register. The word with this address is loaded into ACCU l-L. The BR register is not changed. The original ACCU 1 value is available in ACCU 2. The specified offset is multiplied by 2 (word offset) and the result added t o the contents of the BR register. The double word with this address is loaded into ACCU 1. The BR register is not changed. The original ACCU 1 value is available in ACCU 2. ID Parameter (offset) -32768 t o 32767 EWA 4NEB 81 1 61 50-02d CPU 945 Manual STEP 5 Operations Table 8.31 Overview of Load and Transfer Operations (continued) TRW Transfer ACCU l - L into the word addressed by the BR register offset Multiply the offset specified by 2 and add the result t o the contents of the BR register and transfer the contents of ACCU 1L t o the word with this address. The BR register is unchanged. TRD Transfer ACCU 1into the double word addressed by the BR register offset Mulitply the offset specified by 2 and add the result t o the contents of the BR register and transfer the contents o f ACCU 1 t o the double word with this address. The BR register is unchanged. + + 4 Parameter (offset) - 32768 t o * W + 32767 MAS Transfer the contents of ACCU 1into SAC Transfer the contents of ACCU 1 (bits 31 t o 20 must be zero) into the step address counter (SAC). MAB Transfer the contents of ACCU 1into BR Transfer the contents of ACCU 1 (bits 31 t o 20 must be zero) into the base address counter (SAC). MSA Transfer the contents of SAC into ACCU 1 Transfer the contents of the step address counter into ACCU 1 (bits 31 t o 20 are set t o zero) (address of next command). MSB Transfer the contents of SAC into BR Transfer the contents of the step address counter into the base address register (address of next command). MBA* Transfer the contents of the BR into ACCU 1 Transfer the contents of the base address register into ACCU 1 (bits 31 t o 20 are set t o zero). MBS Transfer the contents of the BR into the SAC Transfer the contents of the base address register into the step address counter. If the DBS register is set to an address between 020000, to 0205FF, and an "MBA" command is executed, data may be falsified in this range. In order to avoid this effect, use the command sequence "ABR+O, MBA" instead of the "MBA" command. /1\ Caution Execution of the MAS, MBS operations is continued with the address stored in the accumulator or in the BR register. 8-64 EWA 4NEB 811 61 50-O2e CPU 945 Manual STEP 5 Operations Loading and Transferring Register Contents L o a d t h e i n f o r m a t i o n f r o m t h e m e m o r y l o c a t i o n w i t h t h e a d d r e s s 8 OOlOH Example: Load the contents o f the double word with the absolute address E 10CEH into ACCU 2. The area E IOCE t o E 10Dl corresponds t o RS 103 and RS 104. Contents o f memory area: 0008 1122 A f t e r this o p e r a t i o n , ACCU 2 c o n t a i n s t h e c o n t e n t s of m e m o r y l o c a t i o n s E ~ O C E Ht o E 1 0 D 1 ~ , i . e . 0 0 0 8 1 1 2 2 ~ . Example: Transferring the values 2 2 4 4 ~and M C D H t o memory locations E 1 0 F 4 ~and E 1 0 F 7 ~ (corresponds to RS 122,123). L DH 2 2 4 4 A A C D L DH 0 0 0 E 1 0 F 4 L o a d t h e c o n s t a n t 2 2 4 4 AACDH i n t o ACCU 1. A f t e r this operation, ACCU 1 c o n t a i n s OOOE 1 0 F 4 a n d ACCU 2 c o n t a i n s 2 2 4 4 AACD. T D I A2 A f t e r the t r a n s f e r o p e r a t i o n , m e m o r y l o c a t i o n s E 1 0 F 4 t o E 1 0 F 7 c o n t a i n t h e v a l u e 2 2 4 4 AACDH. STEP 5 Operations CPU 945 Manual Processing a Field Transfer A field transfer is processed independently o f t h e RLO. The parameter indicates t h e length o f the data field (in bytes) t h a t is t o be transferred. The maximum field length is: For TNB 255 bytes For TNW 255 words. The end address o f the source field is in ACCU 2. The end address o f t h e destination field is in ACCU 1. The highest address o f each field must be specified. The bytes in the destination field are overwritten during t h e transfer. Transfer a 12-byte data field from address 0 F097 t o 0 FOA2 t o address area 2 0485 t o 2 0490. :L DH 0 0 0 0 FOA2 :L DH 0 0 0 2 0 4 9 0 Load the upper address of the source field into ACCU 1 Load the end address of the destination field into ACCU 1. The source address is shifted to ACCU 2 . Transfer the data field to the destination field. Contents of the accumulators after TNB: ACCU 1: 2 0 4 8 4 ACCU 2 : 0 F 0 9 6 EWA 4NEB 81 1 61 50-02d STEP 5 Operations CPU 945 Manual Transferring t o the system data area Example: Set the scan monitoring time t o 1000 msec. after each mode change from STOP t o RUN. Program the time as a multiple o f ten in system data word 96. The following function block can be called from OB21, for example. L KF + l 0 0 T BS L o a d ACCU l w i t h t h e f a c t o r 1 0 0 . T r a n s f e r t h i s v a l u e t o s y s t e m data w o r d 9 6 . 96 Caution The TIR, TDI, TBS und TNB, TNW, TRW, TRD operations are memory changing operations with which you can access the user memory and the system data area. These accesses are not monitored by the operating system. Improper use of the operations can lead t o changes in the program and t o a CPU crash. The MAS, MBS operations continue processing at another point in the program. 8.3.2 Arithmetic Operations These operations add the value specified t o the contents o f ACCU 1. This value is represented by the parameter as a positive or negative decimal number (refer t o Table 8.32). Table 8.32 Arithmetic Operations 4 Add a constant Byte or word constants or double words (as hexadecimal number) can be added. I Parameter -128t0+127 - 32768 t o 32767 0 t o FFFF FFFF + EWA 4NEB 81 1 61 50-02d STEP 5 Operations CPU 945 Manual Processing: The operation is executed independent of the RLO. Neither the RLO nor the condition codes are affected. Subtractions can be executed by entering negative parameters. With ADD BN there is no carry t o ACCU l - H . With ADD KF there is no carry t o ACCU l-H. With ADD DH there is no carry t o ACCU 2. The c o n s t a n t 1 0 2 0 H i s l o a d e d i n t o ACCU 1. T h e c o n s t a n t -3310 i s a d d e d t-o 256 t o the result and store the sum in flag word FW 30. t h e ACCU c o n t e n t s . T FW 28 The n e w ACCU c o n t e n t s a r e 0000 OFFFE. ACCU l-L i s s t o r e d i n f l a g word F W 2 8 . ADD KF + 2 5 6 The c o n s t a n t 2 5 6 1 0 i s a d d e d t o the last result. T FW 30 The new ACCU c o n t e n t s a r e 0000 ~ O F F H AKKU l - L i s s t o r e d i n f l a g w o r d FW 3 0 . 8.3.3 Other Operations Table 8.33 provides an overview of the remaining system operations. Table 8.33 Svstem Operations TAK Swap accumulator contents Swap the contents o f ACCU 1 and ACCU 2. The RLO and the condition codes are not affected. Stop immediately The CPU goes into STOP immediately. STP Stop a t the end o f program execution Current program processing is terminated; the PIQ is output. Then the PLC goes into STOP. CPU 945 Manual STEP 5 Operations Processing of STS operation: When executing the STS operation, the CPU goes into STOP immediately. Program processing is interrupted at this position. The STOP status can be exited only manually (mode selector switch) or with the programmer function "PLC start". Processing of STP operation: The STP operation is used t o bring the PLC into the STOP status at the cycle checkpoint. This may be necessary in the case o f time-critical plant statuses or when a device error occurs. After execution o f the operation, the control program is executed up t o i t s end. Afterwards, the PLC goes into STOP with the "STS" error code. Restart is possible via the mode selector switch (STOP + RUN) or with the programmer. 8.4 Condition Code Generation The processor of the 55-115U programmable controller has the following four condition codes: CC0 CC 1 OS (latching overflow) OV (overflow) The following operations affect the condition codes: comparison operations arithmetic operations shift operations some conversion operations. The OS bit i s reset by transfer operations. The condition codes can be evaluated with conditional jump operations. Condition Code Generation for Comparison Operations Execution of comparison operations sets condition codes CC0 and CC 1 (see Table8.34). The overflow condition code is not affected. However, comparison operations affect the RLO. When a comparison is satisfied, the RLO is 1. Consequently, the conditional jump operation "JC" can also be used after a comparison operation. Table 8.34 Condition Code Settings for Comparison Operations Equal t o 0 0 JZ, JC, JN Less than 0 1 JM, JC, (JN) Greater than 1 0 JP, JC, (JN) STEP 5 Operations CPU 945 Manual Condition Code Generation for Arithmetic Operations Execution of arithmetic operations sets all condition codes according t o the result of the arithmetic operation (see Tables 8.35 t o 8.39). + Table 8.35 Condition Code Settings for " F"/"-F" Operations * This number is the result of the calculation - 32768 - 32768 Table 8.36 Condition Code Settinas for " X F" O~eration x=O 0 0 0 JZ, (JN) - 3 2 7 6 8 5 ~<O 0 1 0 JM, (JN) 327672~ >o I o o JP,(JN) 1073741 8 2 4 2 x > 32767 1 0 1 1 JO, JOS, (JN, JP) -1 0 7 3 7 0 9 0 5 6 5 ~<-32768 0 1 1 1 JO, JOS, (JN, JM) CPU 945 Manual STEP 5 Operations Table 8.37 Condition Code Settinas for ":F" Operation =O' 0 0 0 JZ, (JN) -327685~ <O 0 1 O JM(JN) 32767 > X >O 1 0 0 JP, (JN) 1 0 1 1 1 1 1 1 X X = 32768 Division by 0 * x = O occurs, if the dividend = 0 and the divisor # JO, JOS, (JN) JO, JOS 0 or if the absolute value of the dividend is smaller than the absolute value of the divisor. Table 8.38 Condition Code Settings for " x=O 0 0 0 Jz, (JN) -21 47483648 r x < o o 4 o JM, (JN) 2 1 4 7 4 8 3 6 4 7 2 ~>O 1 0 0 JP, (JN) 0 0 1 1 JO, JOS, (JZ) 4 2 9 4 9 6 7 2 9 4 2 ~> 21 47483647 0 1 1 1 JO, JOS, (JN, JM) -4294967295 <X <-2147483648 1 0 1 1 JO, JOS, (JN, JP) X * + DUI"-D"Operation = -4294967 296* This number is the result of the calculation -2147483648-2147483648 CPU 945 Manual STEP 5 Operations Table 8.39 Condition Code Settinas for floatina-point arithmetics -0,1701412X10~~5~5 -0,1469368X 10-38 0 1 0 JM, (JN) 0,1469368X 10-385x5 0,1701412X10~~ 1 0 0 JP, (JN) O< 1x1<0,1469368X 10-38 0 0 1 1 JO, JOS, (JN, JZ) X<-0,1701412X 1039 0 1 1 1 JO, JOS, (JN, JM) x>0,1701412X10~~ 1 0 1 1 JO, JOS, (JN, JP) Division by 0 1 1 1 1 - JO, JOS Condition Code Generation f o r Digital Logic Operations Digital logic operations set CC 0 and CC 1. They d o n o t affect the overflow condition code (see Table 8.40). The setting depends on t h e contents o f t h e ACCU after t h e operation has been processed. Table 8.40 Condition Code Settings f o r Digital Logic Operations Zero (KH = 0000) 0 0 Jz, (JN) Not zero 1 0 JP, (J N) CPU 945 Manual STEP 5 Operations Condition Code Generation for Shift Operations and Rotate Operations Execution o f the shift and rotate operations affects condition codes CC0 and CC1. The overflow condition code is not affected (see Table 8.41). Setting of CC1 depends on the status of the last bit shifted. Table 8.41 Condition Code Setting for Shift Operations "0" 0 0 Jz, (JN) "1" 1 0 JP, (JN) Condition Code Generation for Conversion Operations The formation of the two's complement (CSW, CSD) sets all condition codes (see Table 8.42). The state of the condition codes is based on the result of the conversion function. The CFW operation does not set any condition codes. Table 8.42 Condition Code Settings for Digital Logic Operations (16-bit arithmetics) U Jump Operaxiens = - 32768* 0 l 1 1 JM, JO, (JN) - 3 2 7 6 7 s ~1-1 O I O O JM, (JN) x=O 0 0 0 0 JZ 1 0 0 0 JP, (JN) X 327672> ~ =1 * This number i s the result o f t h e conversion o f KH = 8000 (KF = -32768) STEP 5 Operations CPU 945 Manual Table 8.43 Condition Code Settinqs for Diqital Loqic Operations (32-bit arithmetics) I x=2147483648 1 -2147483648s x r - I IS x s 2147483647 0 I 1 I 1 I 1 I JO, JM, (JN) 0 1 0 JM, (JN) 1 0 0 JP, (JN) I DEF, DED, DUD, DUF, GFD Conversion Operations Normally, these operations do not affect the condition codes. Only in case of non-convertibility, the condition code OS is set. The accumulators are unaffected. Special case: FDG is always convertible. .............................................9 . 9.1.1 Usable Modules 9.2 9.2.1 9.2.2 9.2.3 9.2.4 9.2.5 Process Interrupt Generation with the 434-7 Digital Input Module Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Startup . . . . . . . . . . . . . . . . . . . . . . . .. . . . ... ................ Initialization in Restart OBs . . . . . . . . . . . . . . . . . . . . .. . . ........ Reading in the Process Sign ........................... Programming Example for EWA 4NEB 81 1 61 50-02d . . 1 9 . 2 9 . 2 9 . 2 9 . 3 9 . 4 CPU 945 Manual lnterrupt Processing Interrupt Processing This chapter describes the following: Which blocks are provided for handling process interrupts in the 55-115U when the CPU 945 is used How t o start up the 434-7 digital input module (with process interrupt) 9.1 Programming lnterrupt Blocks Each o f these interrupts causes the operating system of the CPU t o interrupt the cyclic or timecontrolled program and t o call an interrupt OB: OB2 in the case of interrupt A (interrupt A is triggered by the 434-7 DI module, the 485-7 DIIDQ module, by some CPs or by IPs) OB3 in the case of interrupt B (interrupt B is triggered by some CPs or by IPs) OB4 in the case of interrupt C (interrupt C is triggered by some CPs or by IPs) OB5 in the case of interrupt D (interrupt D is triggered by some CPs or by [PS) Depending on the priorities of the individual alarms, the interrupt OBs have different interrupt behaviour. For a description of the priorities of the interrupts and the interrupt behaviour of the interrupt OBs and notes on the calculation o f interrupt response times see Section 2.8.4 "Interrupt-Driven Program Processing". 9.1 . l Usable Modules You can use interrupt-initiating modules in the S5-115U (e.g. intelligent I10 modules or the 434-7 digital input module or the 485-7 digital inputloutput module). These modules activate the CPU over an interrupt line in the I10 bus (S5 backplane bus). The CPU distinguishes between A, B, C or D interrupts depending on which interrupt line has been activated. Exception: You must not use the digital inlut module 6ES5 432-4UA11 in the 55-1 15U. EWA 4NEB 81 1 61 50-02d Interrupt Processing 9.2 CPU 945 Manual Process lnterrupt Generation with the 434-7 Digital Input Module The 434-7 is a digital input module with programmable interrupt generation. 9.2.1 Function Description The process interrupts are processed in t w o different ways: Interrupt-initiating inputs can be identified by the control program. A yellow LED lights up on the module and a relay contact is closed (the relay contact can be accessed externally via the "MELD" outputs). This signal remains even in the event of power failure and can be reset by applying 2 4 V t o the 24 V RESET input. Although the 434-7 digital input module has only eight inputs, it occupies t w o bytes in the input I10 area and t w o bytes in the output I10 area, i.e. you can access t w o bytes o f inputs and t w o bytes of outputs (input byte and output byte each have the same address). Because the 434-7 digital input module occupies t w o 110 bytes, the IM 306 has t o be set t o 16 channels for this module. The addresses o f the t w o consecutive I10 bytes occupied by the 434-7 are referred t o in the following as "module address" and "module address* 1". Use the t w o bytes o f outputs in the restart OB for parameterizing the module (the "module address" byte indicates which input triggers the interrupt and the "module address* 1" byte determines the type o f the interrupt-initiating edge) You must use the t w o bytes of inputs when - you want t o scan the status of the inputs (scan the "module address" byte) - you want t o indentify inputs which have triggered the interrupt (scan the "module address+ 1" byte; only in interrupt program). The status o f the inputs must be scanned direct (L PY) since it is nottransferred t o the PII. 9.2.2 ) Startup Assign a slot address t o the module; the IM 306 interface module is t o be set t o 16 channels for the 434-7 digital input module! EWA 4NEB 81 1 61 50-02d CPU 945 Manual 9.2.3 Interrupt Processing Initialization in Restart OBs The following must be programmed in the RESTART blocks OB21 and OB22: Which inputs are t o trigger an interrupt Whether the interrupt is t o be triggered by a rising or falling edge. This information is stored in t w o bytes which the program in OB2l or OB22 transfers t o the module. In the "module address" byte, mark which inputs are t o trigger an interrupt, and in the "module address+ 1" byte, mark which edge is t o trigger the interrupt. Programming the RESTART Blocks .............. ::~:::::::::i~$~xs:jljl(jljljlg<$g;;;;@:{:{::j::~jl?jljl~jljljjjjjjjjjljl?jl?jljl???jj?jljljljljljljl;~?jljl ......................... ... ....... ,.................................................. .:,:.: ................................. ................................................................ ................ ..................................................................................... ................................................................................. , ................................................................. .................... ................................................................... .................................................................................................................................... :k............. :::::::::::: ...................................................................................... ....................................................................................... qy&m- ; ; ; ; ; L KM a b Load a two-byte bit pattern into ACCU 1 . (a: Bit pattern of the interrupt enable; b: Bit pattern of the edge initiating the interrupt) T PW Transfer the information from ACCU 1 to the module X (X is the module start address). The bits in the high-order byte (byte a in this example) that was loaded into ACCU 1 with the statement "L K M ab" correspond t o the bit addresses of the eight input channels. If a bit i s set t o "1 ",the interrupt is enabled forthis channel. The bits in the low-order byte indicate whether the interrupt on this channel is triggered on a leading edge ("0") or on a trailing edge ("l "). Example: Triggering inputs 2, 4, and 6 on a leading edge. Triggering inputs 1, 3, and 5 on a trailing edge. Interrupt enable B i t address o f the input 7 Interrupt-generating edge 0 High-order byte t .............. ]= .............. ............. indicates irrelevant bits, since the corresponding bits in the high-order byte are set t o "0" (no interrupt). EWA 4NEB 81 1 6150-02d 7 0 Low-order byte Interrupt Processing 9.2.4 CPU 945 Manual Reading in the Process Signals The module offers a choice o f t w o bytes for reading in the process signals: The "module address" byte reproduces the status of the inputs (regardless o f whether the inputs have been parameterized for interrupt processing). In the "module address+lM byte, the bits assigned t o the interrupt-initiating input are set after an interrupt, regardless of the type of initiating edge! (The module has t o be parameterized at restart). Example: The 434-7 digital input module has starting address 8; it occupies I10 bytes 8 and 9. At startup, only bit 0 has been enabled for interrupt initiation. The interrupt is t o be triggered by a falling edge. In the event o f an interrupt, bytes 8 and 9 have the following values (provided the status of input 8.0 has not changed after edge change): Status of the inputs (8.0 t o 8.7) Bit address of the input 0 7 Module address (byte 8) Interrupt trigger 7 0 Module address+ 1 (byte 9) x=Status o f the inputs (0 or 1) There are t w o ways o f evaluating the input signals with bytes 8 and 9: You can read the status o f the inputs with direct I10 access (L PY 8) at any point in your control program. I t is irrelevant whether the status o f the inputs is read in the cyclic, time-controlled or interrupt-processing program. If you have parameterized inputs at restart as interrupt-triggering inputs, you must program a specific interrupt response in OB2: - Acknowledge interrupt by reading the "module address+ 1" byte (in the example: byte 9; L PY 9) - Transfer the byte read t o the PI1 (in the example: T IB 9) - Evaluate all inputs enabled for interrupt - Trigger interrupt response. After the byte "module address+ 1" (byte 9 in the example) has been loaded into the ACCU, is automatically reset on the module! The module is therefore in a position t o trigger another interrupt and so set another bit in this byte! This means that the "module address+Iv byte can be read out only once after an interrupt in orderto identify the "interrupt trigger". CPU 945 Manual 9.2.5 Interrupt Processing Programming Example for lnterrupt Processing Task Atray is t o be accurately positioned at t w o points: Position 1 is determined by terminating switch 1. When the signal status o f limit switch 1 changes from 0 t o 1 (positive edge), drive 1 is t o be switched off. Position 2 is determined by limit switch 2. When the signal status of limit switch 2 changes from 0 t o 1 (negative edge), drive 2 is t o be switched off. The status of the limit switches is t o be indicated by t w o LEDs: LED 1 for "Signal status o f limit switch 1 " LED 2 for "Signal status o f limit switch 2" Implementation The 434-7module has starting address 8. The IM 306 is set t o 16 channels for the 434-7. Limit switch 1 is assigned t o channel 0 of the module, limit switch 2 is assigned t o channel l o f the module. The OB21 and OB22 restart programs have the task of parameterizing the module: L KM 0000 0011 0000 0010 Initialization of the interrupt inputs: Enable channel 0 : positive edge T PW 8 Enable channel 1 : negative edge BE The interrupts are evaluated in OB2: Drive 1 is switched o f f by resetting output Q 0.0 Drive 2 is switched o f f by resetting output Q 0.1. The status o f the LEDs is updated in the cyclic program section: When output Q 1.0is set, LED 1 lights up When output Q 1.1 is set, LED 2 lights up. EWA 4NEB S1 1 61 50-02d CPU 945 Manual interrupt Processing Evaluating the interrupt request in OB2: zm;&giii5jii~;;;mgg&g#& g&:mgg-&gm .:.:.:.:.:.>:.:.:.:.:.:.:.:.:.:.:~y..:.:.:.:.:.:.:.:. ....................................... :;:;:;:;2ig2i~~j>322;:;:22i:i:i:i:i:i:;:;:;:;:;:;:i:i:i:i:::~;:~:::::::w:%:::::::::::::*~::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::$>>2$>>222jjjj2;: .......... ;.. ;. ..:::::::.:.: ..................................................... ......................... .............................:,:,:, . ........................................................................................................ ...................................................................... ................................................................. ............................................... .:.:.:,:,:,:,:,:,:................................................... ... "" ; L PY 9 Acknowledge i n t e r r u p t b y l o a d i n g t h e "mod. a d d r . + l " T IB 9 byte; Transfer t o PI1 A I 9.0 Scan: D i d l i m i t s w i t c h l t r i g g e r t h e i n t e r r u p t ? R Q 0.0 I f y e s , r e s e t o u t p u t Q 0 . 0 ( s w i t c h o f f d r i v e 1) A I 9.1 Scan: D i d l i m i t s w i t c h 2 t r i g g e r t h e i n t e r r u p t ? R Q 0.1 I f y e s , reset o u t p u t Q 0 . 1 ( s w i t c h o f f d r i v e 2 ) L QB 0 T r a n s f e r u p d a t e d o u t p u t b y t e QB 0 d i r e c t t o t h e o u t - p u t T PY 0 module ( d i r e c t I/O a c c e s s t o m i n i m i z e r e s p o n s e t i m e ! ) BE J Updating the LED statuses in the cyclic program: ... ................................................................... :::::::.................................................................................................. L PY 8 Load t h e s t a t u s o f t h e i n p u t s ( l o w b y t e ) T IB 8 T r a n s f e r low b y t e t o P I 1 A I 8.0 = Q 1.0 A I 8.1 = Q 1.1 ::::, T r a n s f e r t h e s t a t u s o f l i m i t s w i t c h 1 t o t h e LED T r a n s f e r t h e s t a t u s o f l i m i t s w i t c h 2 t o t h e LED BE Estimating the interrupt response time (Prerequisite: no interrupts have been disabled with "IA") The response time (i.e. the time between energizing the limit switch and switching off the drive) can be estimated as follows: + + Signal delay of the 434-7 DI (approx. 1 ms) Response time o f the CPU (see Section 2.8.4) Execution time of OB2 (=sum o f all operation execution times) = Total response time 10.1 Analog Input Modules ...................................... 10- 1 10.2 10.2.1 10.2.2 Analog Input Module 460-7LA12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connecting Transducers t o the 460-7LA12 Analog lnput Module Startup of Analog Module460-7LA12 . . . . . . . . . . . . . . . . . . . . . . .. 10- 3 10- 4 10- 12 10.3 460-7LAl3 Analog Input Module 10.4 10.4.1 10.4.2 Analog Input Module 465-7LA13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connecting Transducers t o the 465-7LA13 Analog lnput Module Startup of the 465-7LA13 Analog Input Module . . . . . . . . . . . . . . . 10- 18 10- 19 10- 23 10.5 10.5.1 10- 26 10.5.2 463-4UA.J-4UB .. Analog Input Module . . . . . . . . . . . . . . . . . . . . . . . Connection of Measuring Transducers t o the 463-4UA.J-4UB .. Analog Input Module . . . . . . . . . . . . . . . . . . . . . . .... . .......... Startup of the463-4UA.J-4UB .. Analog Input Module . . . . . . . . . . 10- 27 10- 29 10.6 10.6.1 10.6.2 466-3LA11 Analog Input Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connecting Transducers t o the466-3LA11 Analog lnput Module Startup of the466-3LA11 Analog Input Module . . . . . . . . . . . . . . . 10- 32 10- 33 10- 37 10.7 10.7.1 Representation of the Digital Input Value . . . . . . . . . . . . . . . . . . . . Types of Representation of the Digital lnput Value for the 460 and 465 Analog Input Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . Types of Representation of the Digital lnput Value for the 463 Analog Input Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Forms of Representation of the Digital Input Values for the 466Analog Input Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10- 45 10.7.2 10.7.3 ............................. ..... 10- 15 10- 46 10- 53 10- 55 10- 58 10.8 Wirebreak Signal and Sampling for Analog Input Modules 10.9 10.9.1 10.9.2 Analog Output Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connecting Loads t o Analog Output Modules . . . . . . . . . . . . . . . . . Digital Representation of an Analog Value . . . . . . . . . . . . . . . . . . . . 10- 61 10- 63 10- 65 10.10 Analog Value Matching Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.10.1 FB25O-Reading and Scaling Analog Values o f the 460 and 465 Analog Input Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.10.2 FB24l-Reading and Scaling Analog Values o f the 463 Analog Input Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.10.3 FB242-Reading and Scaling Analog Values of the 464-8MxxxAnalog Input Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.10.4 FB243-Reading and Scaling Analog Values o f the 466 Analog Input Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.10.5 Outputting an Analog Value -FB251- . . . . . . . . . . . . . . . . . . . . . . . . . 10.10.6 Extended Error Diagnostics with the Analog Value Matching Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10- 67 10.1 1 Example of Analog Value Processing EWA 4NEB 81 1 61 50-02d ......................... 10- 68 10- 70 10- 71 10- 72 10- 73 10- 74 10- 75 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.1 1 10.12 10.13 10.14 10.1 5 10.16 10.17 10.18 10.19 10.20 10.21 10.22 10.23 10.24 10.25 10.26 10.27 10.28 10.29 10.30 10.31 Block Diagram with Signal interchange between the 460 Analog Input Module and the CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignments for the 460 Analog input Module . . . . . . . . . . . . . . . . . . . . . Connecting Transducers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connecting Thermocouples . . . . . . . . . . . . . . . . . . . . . . . . . . ..... ... . . ... . . Connecting a Compensating Box t o the lnput of an Analog Input Module Connecting Resistance Thermometers (PT 100s) t o a 460 Analog Input Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignments for Analog input Moduies . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connecting Transducers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connecting Transducers (Four-Wire Transducer t o a Two-Wire Range Card) Position of the Function Select Switches of the 460-7LA12 Analog Input Module . . . . . . . . . . . . . . . . . . . . .. . . .. . . . . . . . . . . . . . . . . . . . . Wiring of Transducers on the 460-7LA13 Analog input Module . . . . . . . . . . Block Diagram with Signal lnterchange between a 465 Non-Isolated Analog Input Module and the CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignments f o r t h e 465 Analog Input Module . . . . . . . . . . . . . . . . . . . . . . Connecting Resistance Thermometers (PT 100s) t o a 465 Analog Input Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignments for Analog Input Module 465 ......................... Position of the Function Select Switches of the 465-7LA13 Analog Input Module (Rear of the Module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram with Signal Exchange between 463 Analog lnput Module andCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignments of the 463 Analog Input Module . . . . . . . . . . . . . . . . . . . . . . Connection of Measuring Transducers and Setting of Measuring Range on the 463 Analog Input Module ..................................... Position of Switches on the 463Analog Input Module . . . . . . . . . . . . . . . . . . Labelling o f Switch on the Cover of the463 Analog Input Module . . . . . . . Block Diagram o f the 466-3LA11 Analog Input Module . . . . . . . . . . . . . . . . . Pin Assignments of the 466 Analog lnput Module in the Case o f Common-Reference Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connecting Transducers t o the 466 Analog lnput Module (Common-Reference Measurement) .................................. Pin Assignments of the 466Analog lnput Module in the Case of Differential Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connecting Transducers t o the 466 Analog input Module (Differential Measurement) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Locations o f the Mode Selectors on the 466-3LA11 Analog lnput Module . Assignment of Switches S 11s 2 t o Channel Group ...................... Representation of the Digitized Measured Value . . . . . . . . . . . . . . . . . . . . . . . PT 100 on SIMATIC Analog Input Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Representation o f Digitized Measured Values of the 463 Analog Input Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010101010- 3 4 5 7 8 10101010- 9 10 11 12 10- 14 10- 17 10- 18 10- 19 10- 21 10- 22 10- 24 10- 26 10- 27 10- 28 10- 29 10- 30 10- 32 10- 33 10- 34 10- 35 10- 36 10- 37 10- 40 10- 45 10- 51 10- 53 10.32 10.33 10.34 10.35 10.36 10.37 10.38 10.39 10.40 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.1 1 10.12 10.13 10.14 10.1 5 10.16 10.17 10.18 10.18 10.19 10.20 10.21 10.22 10.23 10.24 10.25 10.26 10.27 Block Diagram with Signal Interchange between CPU and a 470 Analog Output Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connecting Loads .......................... . . . .. . . . . . . . . . . . . . . . Connecting Loads t o Current and Voltage Outputs . . . . . . . . . . . . . . . . . . . . . Representation of an Analog Output Signal in Digital Form . . . . . . . . . . . . . Schematic Representation o f Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example o f Analog Value Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function of the 460Analog Input Module . . . . . . . . . . . . . . . . . . . . . . ...... .. . . . . . . . . . . Setting Mode Selectors I and iI . . . . . . . . . . . . . . . . . . . . . . . . . . . Function of the 470 Analog Output Module . . . . . . . . . . . . . . . . . . . . . . . . . . . Rangecards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting Functions on the 6ES5 460-7LA12 Module . . . . . . . . . . . . . . . . . . . . . . Setting Functions on the 6ES5 460-7LA4 3 Module . . . . . . . . . . . . . . . . . . . . . . Rangecards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting Functions on the 6ES5 465-7LA13 Module . . . . . . . . . . . . . . . . . . . . . . Address Setting on the 463 Analog input Module ...................... Setting the Type of Measurement (Common-Reference or Differential) . . Setting CurrentIVoltage Measurement for Channel Group I . . . . . . . . . . . . . Setting CurrentIVoltage Measurement for Channel Group II . . . . . . . . . . . . Setting ............................................................ Setting CurrentIVoltage Measurement for Channel Group II . . . . . . . . . . . . Setting CurrentIVoltage Measurement for Channel Group Ill . . . . . . . . . . . . Setting CurrentIVoltage Measurement for Channel Group IV . . . . . . . . . . . Setting the Measuring Range for One Channel Group (4 Channels per Group) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting the Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting the Connection Type and Address Range . . . . . . . . . . . . . . . . . . . . . . . Setting the Module Starting Addresses (P area) . . . . . . . . . . . . . . . . . . . . . . . . Setting the Module Starting Addresses (Q area) . . . . . . . . . . . . . . . . . . . . . . . . Setting the Module Starting Addresses (Q area) (continued) ............. Meaning o f Bits 0 t o 2 for Analog input Modules . . . . . . . . . . . . . . . . . . . . . . . Representation of Digitized Measured Values of the 460 and 465 AI (Two's Complement; Measuring Rangef 50 mV, f 500 mV, & 1000 mV) ... Representation o f Digitized Measured Values of the AI 460 and 465 (Two's Complement; Measuring Rangef 5 V, k 10 V, & 20 mA) . . . . . . . . . . Representation of Digitized Measured Values of the 460 and 465 A1 (Number and Sign; Mesuring Rangef 50 mV, f 500 mV, f 1000 mV) . . . . . . Representation of Digitized Measured Values of the 460 and 465 AI (Number and Sign; Measuring Rangek 5 V, f 10 V, k 2 0 mA) . . . . . . . . . . . . Representation o f Digitized Measured Values of the 460 and 465 AI (Current Measuring Range 4 t o 20 mA) ................................ Representation of Digitized Measured Values of the 460 and 465 A l for Resistance-Type Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Representation o f Digitized Measured Values for the PT100 Climatic Measuring Range o f the 460-7LA13 AI . . . . . . . . . . . . . . . . . . . . . . . . Representation o f Digitized Measured Values of the 463 AI (Two's Complement; Measuring Range 0 t o 10 V, 0 t o 1 V, 0 t o 20 mA, 4 t o 20 mA) 10- 62 10- 63 10- 64 10- 65 10- 69 10- 75 10- 76 10- 76 10- 77 10101010101010101010101010- 13 14 16 23 25 31 38 38 38 39 39 39 39 10- 40 10- 41 10- 41 10- 42 10- 43 10- 44 10- 45 10- 46 10- 47 10- 48 10- 49 10- 50 10- 51 10- 52 10- 53 10.28 Representation o f Digitized Measured Values o f t h e 466 A I (Measuring Range 0 t o 20 mA; 0 t o 5 V and 0 t o 10 V; unipolar) . . . . . . . . . . 10.29 Representation o f Digitized Measured Values (Two's Complement; Measuring R a n g e f 5 V , f 20 m A and* 10 V; bipolar) 10.30 Representation o f Digitized Measured Values (Number a n d Sign; Measuring Range? 5 V,& 20 m A and+ 40 V; bipolar) . 10.31 Representation o f Digitized Measured Values (Binary; Measuring R a n g e f 5 V , f 2 0 m A a n d f l0 V; bipolar) . . . . . . . . . . . 10.32 Representation o f Digitized Measured Values (Measuring Range 0 t o 1.25 V, and 0 t o 2.5 V; unipolar) . . . . . . . . . . . . . . . . . 10.33 Representation o f Digitized Measured Values (Two's Complement; 10.34 10.35 10.36 10.37 10.38 Measuring Rangek1.25 V , a n d f 2.5V; bipolar) . . . . . . . . . . . . . . . . . . . . . . . . Representation o f Digitized Measured Values (Number a n d Sign; Measuring R a n g e f 1.25V, a n d f 2.5 V; bipolar) . . . . . . Representation o f Digitized Measured Values (Binary; Measuring R a n g e f 1.25 V, a n d f 2 . 5 V; bipolar) . . . . . . . . . . . . . . . . Representation o f Digitized Measured Values (Measuring Range 4 t o 20 m A and 1 t o 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wirebreak Signal i n Conjunction w i t h Resistance Thermometers . . . . . . . . . ScanTimes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................ 10- 55 10- 55 40- 55 10- 56 10- 56 10- 56 10- 57 10- 57 10- 57 10- 59 10- 60 CPU 945 Manual 10 Analog Value Processing Analog Value Processing Analog input modules convert analog process signals t o digital values that the CPU can process. Analog output modules convert the digital values processed by the CPU t o analog process signals. ll Analog lnput Modules The analog measured value is digitized and stored in a data register on the module. I t can then be read and processed further by the CPU. Signal Interchange Between Module and CPU The CPU can read the digitized value from the module's RAM in the following t w o ways: Via an integrated FB Via a load operation (L PW). In the CPU 945, an integrated FB is available for each analog input module for reading o f analog values. 4601465 analog input module: 463 analog input module: 464-8 analog input module (if ET 100IET 200 are used): 466 analog input module: The complete measured value (2 bytes) is stored in the CPU. 460,463,464-8,465 and 466 Analog lnput Modules Five analog input modules with the following characteristics are available: 6ES5 460-7LA12lLA13 - Galvanically isolated - 8channels - Encoding time: max. 60 ms per channel (worst case max. 400 ms with cyclic scanning) - 2 range cards - Max. permissible isolating voltage 60 V ACl75 V DC; between the channels and ground (M) in each case and between the channels themselves 6ES5 463-4UA11l-4UA121-4UB11l-4UB12 - Galvanically isolated - 4channels - Encoding time: max. 20 ms per channel - Max. permissible isolating voltage 25 V ACl60 V DC; between the channels and ground (M) in each case and between the channels themselves Analog Value Processing CPU 945 Manual The 464-8 analog input module can be used in conjunction with ET 100/ET 200 applications. 6ES5 465-7LA13 - Non-isolated - 8116 channels (selectable) - Encoding time: max. 60 ms per channel (worst case max. 960 ms with cycle scanning) - 214 range cards - 1 V max. permissible voltage between a channel and ground as well as between channels 6ES5 466-3LA11 Floating 8116 channels (switchable) Short coding times: 2 ms (8 channels) or 4 ms (16 channels) 12 different measuring ranges can be set using switches on the module Choice between common-reference measurement (16 channels) or differential measurement (8 channels) - All operating modes can be set using switches on the module - Maximum permissible isolation voltage Vlso: 60 V ACl75 V DC; between the channels and ground (M) in each case; however, not between the channels themselves! - The block diagrams (Figures 10.1, 10.12, 10.17 and 10.22) illustrate the method o f operation as well as the signal interchange between the analog input modules and the CPU. In the case of the 460 and 465 modules, a processor (ADCP) controls the multiplexer, analog-digital conversion and the forwarding o f the digitized measured values t o the memory or t o the data bus of the programmable controller. The controller takes account of the module's operating mode, which is set a t the relevant switch. The process signals must be matched t o the input level of the analog digital converter (ADC) t o suit the application. You can match the signals with the 460 and 465 modules by plugging a suitable range card (voltage divider or shunt) into the receptacle on the frontplate o f the analog input module. In the case o f the 463 module the analog input signals are digitized by voltage-frequency converters and written into a counter via rapid optocouplers. Presetting o f the counters, the duration o f the integration time and the transfer of the counting result o f the four input channels into the four measured value memories are coordinated by sequential control. The measuring range of each channel is adjusted via the connection o f sensors and through jumpers in the front connector of the module. In the case o f the 466 module an internal controller handles all required functions. You can adapt the process signals t o the input level o f the analog input modules in the case of the 466 module by specificsettings o f the measuring range switches. EWA 4NEB 81 1 61 50-02d CPU 945 Manual 10.2 Analog Value Processing Analog lnput Module 460-7LA12 S5 bus AID ADUS MUX Analog-digitaIconverter(ADC) ADU processor Multiplexer Figure 10- 1 Block Diagram with Signal Interchange between the 460Analog lnput Module and the CPU EWA 4NEB 81 1 61 50-02d CPU 945 Manual Analog Value Processing 10.2.1 Connecting Transducers to the 460-7LA12 Analog lnput Module Pin assignments of the front connector a b a=Pin No. b=Assignment * Switching off the test current in the case of non-activated wirebreaksignal Figure 10.2 Pin Assignments for the 460Analog lnput Module CPU 945 Manual Analog Value Processing Certain precautionary measures must be taken in order t o make sure that potential difference VCM is not exceeded. Different measures are required for isolated and non-isolated transducers. Isolated Transducers When isolated transducers are used, the measuring circuit can assume a potential t o earth that exceeds the permissible potential difference UCM(refer t o the maximum values for the various modules). To prevent this, the transducer's negative potential must be connected t o the module's reference potential (reference bus). Example: Measuring temperature on a busbar with an isolated thermocouple. In a worst-case situation, the measuring circuit can assume a potential that would destroy the module; this must be prevented through the use o f an equipotential bonding conductor (see Figure 10-3). Possible causes: Static charge Contact resistors through which the measuring circuit assumes the potential of the busbar (e.g. 220 VAC). Non-isolated Transducers When using non-isolated transducers, the permissible potential difference UCM between the inputs and the reference bus must not be exceeded. Example: Measuring the temperature of the busbar o f an electroplating bath with a non-isolated thermocouple. The difference between the potential of the busbar and the reference potential of the module is max. 24 V DC. A 460 analog input module with floating input (permissible UCMis 60 VAC175 V DC) is t o be used. Isolated transducer Module I Non-isolated transducer Module I Equipotential bonding conducto~ L - Reference bus Figure 10.3 Connecting Transducers - I Reference bus Analog Value Processing CPU 945 Manual You must observe various conditions when connecting current or voltage sensors t o analog input modules, depending on what type of sensors are used. Note Detailed information on address assignment for analog modules is presented in Chapter 6 (AddressingIAddress Assignments). Please observe the information regarding the overall structure (see Sections 3.5.2 t o 3.5.4). Note Unused inputs must be terminated with a voltage divider or shunt (see Table 10-1). In the case o f the 498-1AA11 module, the unused inputs must be short-circuited (M+ with M - in each case). Other modules require no additional wiring. The galvanic isolation between the analog inputs and L+or L - is nullified when using the 498-1M A 5 1 module for a 2-wire transducer! EWA 4NEB 81 1 61 50-02d CPU 945 Manual Analog Value Processing Connecting Thermocouples w i t h Compensating Box The influence o f the temperature on the reference junction (in the terminal box, for instance) must be equalized using a compensating box. Please observe the following: The compensating box must have an isolated power supply. The power supply unit must have a grounded shielding winding. Compensate as follows when all thermocouples connected t o the module's inputs have the same reference junction: Provide a separate compensating box for each analog input module Bring the compensating box into thermal contact with the terminals Apply compensating voltage t o pins 23 and 25 (KOMP+and KOMP -) on the analog input module (Figure 10-4) Set Function Select switch I1 on the module for operating a compensating box (see also Table 10-2) Terminal box Analog input module I Thermal contact Compensation unit A resistor on the jumper, which is balanced a t 0 "C, is temperature-dependent, and produces a compensating voltage when the temperature rises or drops - I - Reference bus Power supply unit Figure 10-4 Connecting Thermocouples Detailed information on thermocouples and compensating boxes can be found in Catalog MP 19. Analog Value Processing CPU 945 Manual When several thermocouples are distributed over areas with different temperature ranges, i t is often advantageous t o acquire different reference junction temperatures. In this case, the central compensating input i s no longer used. A separate compensating box is used for each analog input channel t o be compensated. KOMP+and KOMP - remain unconnected. Connect the relevant thermocouple in series with the compensating box. Run the remaining terminal leads from compensating box and thermocouple t o the analog module (terminal M+and M -see Figure 10-5). Set Function Select switch I1 on the module t o "Without reference junction compensation". Compensation, i.e. correction o f the temperature error, subsequently takes place in the compensating box rather than on the module. The corrected value is thus available at terminals M+and M - of the relevant analog input channels, and is then converted into a digital value. Analog input module Figure 10.5 Connectinga Compensating Box to the lnput of an Analog lnput Module EWA 4NEB 81 1 61 50-O2d CPU 945 Manual Analog Value Processing Connecting Resistance Thermometers (e.g. PT 100) w i t h 6ES5 460-7LA12 A constant-current generator supplies the series-connected resistance thermometers (max. 8 PT 100s) with a current of 2.5 mA over pins " S + " and "S -". If you use the 498-1AA11 submodule, you need not terminate the unused input channels with a short-circuiting jumper (see Figure 10-6, range card 2, channel 5 and 6). Range card 1 I I I I Range card 2 (Reference bus - P P P P P - P Figure 10-6 Connecting Resistance Thermometers (PT 100s) t o a 460Analog Input Module If no PT 100 is connected t o input channels 4 t o 7, other voltages and currents can be measured on these channels using range card 498-1AA21, -1AA31, -1AA41, -1AA51, -1AA61 or-1AA71. EWA 4NEB 81 1 6150-02d Analog Value Processing CPU 945 Manual The diagram below shows the pin assignments for resistance thermometers used on analog input module 460. a=Pin No. b=Assignment Required only for disconnecting the test current when the wirebreaksignal is not activated Figure 10.7 Pin Assignments for Analog Input Modules CPU 945 Manual Analog Value Processing Connecting Transducers with Module 468-7LA12 The inherently short-circuit-proof supply voltage is fed t o the two-wire transducer over the range card. Four-wire transducers have a separate power supply. The diagram below shows how t o connect two-wire and four-wire transducers. Module with two-wire transducer Module with four-wire transducer MUX, ADC Observe rnax. perm. I potential difference!; I II L - _ _ _ - _ I - - Reference bus Reference bus ........ .X:..:::::... :::::.:.:.:. ::::::::: :.:.:...: .:..:..:..:.,:,:, .:......,,, ...:...:...:.,.,.,., ::::::::.:.:.:.:.: 6ES5 498-1AA51 range card (with internal circuitry) 6ES5 498-1AA71 range card (with internal circuitry) Galvanic isolation between t h e analog input and L+/L- is removed. Figure 10.8 Connecting Transducers EWA 4NEB 81 1 61 50-02d Analog Value Processing CPU 945 Manual The diagram below shows how t o connect a four-wire transducer t o a two-wire transducer range card (498-1AA51). Analog input module TransMUX. ADC - Reference bus ......,.,.,.,.,.,. ...... .:.:.:...:.:.:.:.: $$jiiji$$ 6ES5 498-1AA51 range card :::::*.A.:.:.: p p (with internal circuitry) p Figure 10.9 Connecting Transducers (Four- Wire Transducer to a Two- Wire Range Card) 10.2.2 Startup of Analog Module 460-7LA12 Voltage dividers or shunt resistors can be plugged into the input modules as cards (see Table 10-1). They match the process signals t o the input level o f the module. These cards make it possible t o set different measuring ranges. Connecting Range Cards Two range cards can be plugged into the 460 analog input module. One card specifies the measuring range of four inputs. We offer voltage dividers, shunts and through-connection cards (see Table 10-1). EWA 4NEB 81 1 61 50-O2d CPU 945 Manual Analog Value Processing Table 10.1 Ranae Cards M+ r-g I I I I I - 1AA11 M- k 500 mV; k 5 0 mV PT l 0 0 I M+ - 1AA21 M- M I I I I + I I I I I I I k l V f l00 m v * f1 o v +l v * - 1AA31 I I M - l - - - - - -- -- !p! - 1AA41 "+ k 2 0 mA I ! ----- :+S r---- L- - + +4 ... 20 mA two-wi re transducer M - L, - 1AA61 f 2 mA* I M- - 1AA51** ! #- M+p-q f 5V M- - 1AA71 M+ M- ! ! 1 6 : l k 500 mV * ! + 4 . . . + 2 0 mA four-wire transducer * Possible measuring range for "50 mV" setting, but with higher incidence of error ** When a -1AA51 range card is used, there is no longer any galvanic isolation between analog inputs and L+ ! Note Jumpers must be set in the front connector in the case o f through-connection card 1AA11. Unused inputs need not be short-circuited in the case o f voltage dividers or shunts. Analog Value Processing CPU 945 Manual You can set various functions on an input module by setting the Function Select switches on the rear of the module accordingly (see Table 10-2). PCB plug connector Switch I Switch I I Figure 10.10 Position of the Function Select Switches of the 460-7LA l 2 Analog Input Module Note Selection of a function entailsthe setting of all switches. Table 10.2 ettina Functions on the 6ES5 46( -7LA12 Module Yes Referencejunction compensation P P Measuring range* (nominal value) Two's complement Analog value Absolute value and sign representation - Cyclic Selective Channel 0 t o 3 Channel 4 t o 7 Channel 0 t o 3 Channel 4 t o 7 Sampling System frequency r Wirebreak signal No wirebreak signal l * Setting for PT 100: Measuring ran< 500 mV EWA 4NEB 81 1 61 50-02d CPU 945 Manual 10.3 Analog Value Processing 460-7LA13 Analog Input Module The 460-7LA13 analog input module has been developed from the 460-7LA12 analog input module. I t offers the following advantages: Lower power consumption and heating Lower weight New PT 100 climatic measurement range (-100 "C t o + 100 "C) with high resolution (1140 "C) All functions of the 460-7LA12 module are also available on the 460-7LA13 module. The following features are identical with the 460-7LA12 module: Transducer cabling Use of the 6ES5 498 range cards Assignment o f the front connector System behaviour Compared t o the 460-7LA12 analog input module, the following features o f the 460-7LA13 analog input module are new or different: New PT100 climatic measuring range (as alternative t o the previous PT100 measuring range) Setting o f the mode selector switches for the PT100 measuring ranges Setting of the mode selector switched for the measuring range 50 mV (e. g. for connection o f thermocouples). New PT100 Climatic Measuring Range The same measuring range as with the 460-7LA12 analog input module exists also on the 460-7LA13 analog input module; i.e. the PT100 temperature range (-200 "C t o +850 "C) is resolved in this measuring range t o approximately 4000 units. This corresponds t o a resolution of approx. 0.25 "C. If the new PT100 climatic measuring range is selected via the mode selector switches, all eight analog inputs can be used in this measuring range only. Do not use other than the 6ES5 498-1AA11 (50 mVlO.5 V) range card. The following must be observed in conjunction with wire break monitoring in the PT 100 climatic measuring range: If a line o f the auxiliary circuit (K+, IC-) is interrupted, the value "negative end value" is encoded for all inputs and the overflow bit is set t o "1 ". In the case of transducer or measuring line break, the error bit for the corresponding channel is additionally set t o " 1 ". For an exact representation o f measured values in the PT100 climatic measuring range refer t o Table 10.26. For setting of the "PT100" mode, the following markings are printed on the cover of the module: Standard range: "resistance thermometer uncompensated full range" Climatic measuring range: "resistance thermometer uncompensated low range" CPU 945 Manual Analog Value Processing Setting o f Mode Selector Switches Iand II The mounting position and t h e setting o f the mode selector switches corresponds t o t h a t o f the 460-7LA12 module. The only difference is the setting o f the PT100 measuring ranges (see Table 10.3). Table 10.3 Setting Functions on the 6ES5 460-7LA13 Module Reference junction Yes compensation Measuring range* resistance (nominal value) 500 mV, V ... mA thermometer System frequency Wirebreak signal No wirebreak signal No CPU 945 Manual Analog Value Processing Transducer Wiring Transducers are wired in t h e same way as w i t h the 460-7LA12 module. Unused inputs must be connected i n parallel w i t h switched inputs. An example is given i n Fig. 10.1 1. Figure 10.11 Wiring of Transducers on the 460-7LA 13 Analog Input Module (for Climatic Measuring Range) Analog Value Processing CPU 945 Manual Analog lnput Module 465-7LA13 10.4 . Control signals S5 bus Address bus . Data bus I J. CPU AID ADCP MUX * Analog-digital converter (ADC) ADC processor Multiplexer Required only when using a -1AA51 module Figure 10-12 Block Diagram with Signal Interchange between a 465 Non-Isolated Analog Input Module and the CPU CPU 945 Manual Analog Value Processing 10.4.1 Connecting Transducers to the 465-7LA13 Analog Input Module Pin assignments of the front connector a 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 b KOMP -** L+ = 24 V** M8 M8M9 M9MlO+ M10M11 M11 - + + + Mext * M12+ M 12 M13+ M13M14+ M14M15+ M15- a=Pin No. b = Assignment * Connection to the central grounding point of the controller ** Connection of the compensating box *** Switching off the test current in the case of non-activated wirebreak Figure 10.13 Pin Assignments for the 465Analog Input Module Analog Value Processing CPU 945 Manual Note Connection of transducers is described in detail in Section 10.2.1. Note Unused inputs must be short-circuited when using the 6ES5 498-1AA11 through-connection card. Note Detailed information on address assignment for analog modules is presented in Chapter 6 (AddressingIAddress Assignments). Please observe the information regarding wiring, electrical structure and conductor arrangement (see Sections 3.5.2 t o 3.5.4). Connecting Thermocouples w i t h Compensation Boxes Connection of thermocouples is the same as for the 460 module (see Section 10.2.1) CPU 945 Manual Analog Value Processing Connecting Resistance Thermometers (PT 100) t o a 465-7LA13 Analog Module A constant-current generator supplies the relevant resistance thermometer w i t h a current o f 2.5 mA over pins "S+" and "S -" via a range card (6ES5 498-1AAll) (see Figure 10-14). The voltage on t h e PT l 0 0 is picked and " M -". o f f over inputs "M Other potential-free voltage sensors (500 mV voltage range) can be connected t o those inputs ( M + / M -) not used f o r resistance thermometers. If no PT l 0 0 is connected over input channels 4 t o 7, other voltages and currents can be measured over these 498-1AA21, channels using a -1AA31, -1AA41, -1AA51, -1AA61 or -1AA71 range card (see Figure 10-14 range card 2). In this case, you must short-circuit t h e current outputs (S+, S-) belonging t o the relevant card w i t h a jumper. Should you fail t o d o so, t h e error b i t would be set for t h e relevant channel and the value "0" decoded (see Figure 10-14 range card 4). If you use a -1AA21, -1AA31 or -1AA61 range card for a channel group, no wirebreak signal may be enabled f o r t h a t channel group. A correction of 100 ohms (100 ohms=OC) must be made via the control program by specifying the appropriate upper and lower limiting values in FB250 (see Section 10.10.1). +" Figure 10-14 Connecting Resistance Thermometers (PT 100s) to a 465Analog Input Module EWA 4NEB 81 1 61 50-02d Analog Value Processing CPU 945 Manual The following figure shows the pin assignments of the 465-7LA13 module for resistance thermometers. a = Pin No. b=Assignment " Connection t o the central grounding point o f the controller Required only for disconnecting the test currentwhen the wirebreak signal is not activated Figure 10.15 Pin Assignments for Analog Input Module 465 Connecting Transducers Transducers are connected as in the case of the 460 module (see Section 10.2.1). CPU 945 Manual Analog Value Processing 10.4.2 Startup of the 465-7LA13 Analog Input Module Voltage dividers and shunts can be plugged in as range cards (see Table 10-4). They match the process signals t o the input level of the module. In this way, various measuring ranges can be set. Table 10.4 Range Cards + +4to 20mA two-wire transducer L - lAA61 M+ M - - 1AA71 M+ M- * ** ----------- d p-7 I I m ! k 500 mV * ! P l f 5V ! + 4 t o + 20 mA four-wire transducer Possible measuring range for "50 mV" setting, butwith higher incidence of error When a -1AA51 range card is used, there is no longer any galvanic isolation between analog inputs and L+/L-! EWA 4NEB 81 1 61 50-02d Analog Value Processing CPU 945 Manual Note In the case o f the 1AA11 through-connection card, unused inputs must be shortcircuited. In the case of a voltage divider or shunt card, unused inuts must not be short-circuited. Function select switches for setting various functions are located on the back of the 465 module. For this purpose, the switches must be set t o the positions shown (see Table 10-5). PC6 plug connector ~ w i t i hI switch 11 Figure 10.16 Position of the Function Select Switches of the 465-7LA13 Analog Input Module (Rear of the Module) Analog Value Processing CPU 945 Manual Table 10.5 Settina Functions on the 6ES5 465-7LA13 Module Yes Reference junction No compensation Measuring range* (nominal value) Measure with resistance therm., 4-wire1 8-channelx* Measure current orvoltage I I I I 8 Channels I Cyclic Selective 8 channels 16 channels Sampling System frequency Channel operation I No wirebreak .! . . -l I Monitor S+lineto the PT 100 resistance therm. for wirebreak I * ** Channel 0 t o 3 (Channel 0 t o 7) I ... mV/... mA I Channel 4 t o 7 (Channel 8 t o 15) PT100 I Setting for PT 100: Measuring Range 500 rnV Additional setting for PT 100: Reference junction compensation: No EWA 4NEB 81 1 61 50-02d I l 6 Channels Analog Value Processing 10.5 CPU 945 Manual 463-4UA.J-4UB.. Analog lnput Module Figure 10.17 shows the block diagram of the 463-4U.. module. F+ F- L+ L- TSo I, R TS, CO R I, C, Bus interface Control signals I I COt o 3 .l t o 3 R SP 11 s5 bus Data bus Data bus II 1 Central processing unit (CPU) Common lnput (reference potential of inputs 0 t o 3) lnput (inputs 0 t o 3) Range (measuring range) RAM I TSo t o 3 Transducer Supply (supply for 2-wire MU of inputs 0 t o 3) VIF Voltage-frequency converter Z Counter Figure 10.17 Block Diagram with Signal Exchange between 463Analog lnput Module and CPU EWA 4NEB 81 1 61 50-O2d Analog Value Processing CPU 945 Manual 10.5.1 Connection of Measuring Transducers to the 463-4UA.J-4UB.. Analog lnput Module 1 F+ 2 F- 3 L+ 4 +(measuring transducer supply) 5 +10v 6 +1V 7 Common 8 Common 9 0-1ov 10 0-20mA 11 4-20mA 12 13 +(measuring transducer supply) 14 +10V 15 +lV 16 Common 17 Common 18 0-10V 19 0-20mA 20 4 - 20 mA 21 L- 22 23 24 25 +(measuring transducer supply) 26 +10V 27 +lV 28 Common 29 Common 30 0 - 10V 31 0-20mA 32 4-20mA 33 34 +(measuring transducer supply) 35 +1ov 36 +lV 37 Common 38 Common 39 0-10v 40 0 - 20 mA 41 4 - 20 mA 42 Figure 10.18 Pin Assignments of the 463 Analog lnput Module Analog Value Processing CPU 945 Manual Pin Assignments of the Front Connector The following figure shows the connection of the measuring transducers t o the front connector the setting o f the measuring range by plugging in jumpers at the front con nector Connection o f t h e process signal leads and setting of range Range Oto10V Range 0 to 1V Range Oto20mA Range Range 4to20mA 4 t o 20 mA 2-wire measuring transducer Front connector Pin 3 L+ 4 +(Meas.transd.supply) 5 +10v 6 +1V 7 Common 8 Common 9 0-10v 10 0-20mA 11 4-20mA 12 L- - L- L- --L -4 L- - 13 +(Meas.transd.supply) 14 +10V 15 +1V 16 Common 17 Common 18 0-1ov 19 0-2OmA 20 4 - 20 mA 21 L- 22 23 24 25 +(Meas.transd.supply) 26 +1OV 27 +lV 28 Common 29 Common 30 0-10V 31 0-20mA 32 4-20mA 33 34 +(Meas.transd.supply) 35 +1ov 36 +lV 37 Common 38 Common 39 0-10v 40 0 - 20 mA 41 4-20mA 42 Figure 10.19 Connection of Measuring Transducers and Setting of Measuring Range on the 463 Analog Input Module Analog Value Processing CPU 945 Manual Connection of Measuring Transducers The measuring transducers are connected t o the analog input module via shielded cables of a maximum length of 200 m. Cable lengths of up t o 500 m are possible, if the cables are not laid together with power cables. Voltage sensors, current sensors, 2-wire and 4-wire measuring transducers can be connected in any configuration. Four short-circuit-proof supply connections are available on the front connector for 2-wire measuring transducers. Note If 2-wire measuring transducers are used, the reference potential (Common Input) of these channels has t o be connected t o L-. There is then no longer a galvanic isolation between the channels and the supply voltage L+/L-. Please note that the module's bus interface is activated with 24 V via the F + and F- enable lines at the front connector. 10.5.2 Startup of the 463-4UA.J-4UB.. Analog lnput Module The individual measuring ranges are set by jumpering the inputs on the front connector (see Figure 10.19). Two switches are provided on the module for setting the data format f o r t h e 4 t o 20 mA range and the module addressing. H' Switch for addressing o f module , , Backplane connector t o the S5 I10 bus Frontpanel -Switch for setting the data format for the 4 t o 20 mA range Figure 10.20 Position of Switches on the 463 Analog lnput Module EWA 4NEB 81 1 61 50-02d Analog Value Processing CPU 945 Manual Note An adapter casing (6ES5 491-OLB12) is required t o use the 463 analog input module in the 55-1 15U programmable controller. A 42-pin front connector is required as accessory; 6ES5 497-4UA22 for crimp connection or 6ES5 497-4UB12 for screw connection Setting the Data Format for the 4 t o 20 mA Range If the 4 t o 20 mA inputs are used, data representation from 0 t o 1032 bits or 256 t o 1279 bits can be selected by pressing the corresponding switch. All four input channels can have different data formats. When the voltage or 0 t o 20 mA inputs are used, the corresponding switches remain in the "OFF" position. "ON" switch position (pressed) 1) Theswitch position selected should be marked in these fields. Figure 10.21 Labelling of Switch on the Cover of the 463 Analog Input Module CPU 945 Manual Analog Value Processing Addressing and Address Setting on the 463 Module The analog input module uses an address space of 8 bytes. The four 16-bit (2-byte) measured value memories can be scanned one afterthe other by the control program through word operations via the S5 bus. (L PW (module address channel add ress X 2)) + Table 10.6 shows the switch positions for the individual addresses selected. Whether address space is used in the 0 peripheral area or in the P area is set on the IM 314 (see section 3.3.2). " means switch position "ON " (pressed). "m CPU 945 Manual Analog Value Processing 10.6 466-3LA11 Analog lnput Module Figure 10-22 shows the block diagram of the 466-3LA11 module. m m 8/16Processsignals I I I 4- 4- Voltagelcurrent selection Voltagelcurrent selection OV - - - - W 5V + 15V -1 5V - -Galvanic - - -isolation ----- - Ser.1par. converter Switched-mode power suppl 2- 4- selector Bus driver I Control signals Address bus S5 bus Data bus Central Processing Unit (CPU) PGA= Programmable amplifier Figure 10-22 Block Diagram of the 466-3LAll Analog lnput Module Note Please note that the 466 module has very fast processing times. Since it is very fast, it is more suitable for closed-loop control tasks than for the connection of thermocouples and resistance thermometers. Analog Value Processing CPU 945 Manual 10.6.1 Connecting Transducers to the 466-3LA11 Analog lnput Module The pin assignments of the 466-3LA11 analog input module depend on the type of measurement (common-reference measurement or differential measurement). Common-reference Measurement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 MO+ MOM8M8+ + M1 M1M9M9+ M2+ M 2M10M10+ M3+ M 3M11M11 + M4+ M4M12M12+ M5+ M 5M13M13+ M6+ M6M14M14+ In the case o f common-reference measurement, all signal lines have a common reference point. The reference point is produced by running all M - inputs t o one point (see Figure 10.24). Since this type of measurement is susceptible t o noise, the signal sources should be located close t o the 466 analog input module. There are 46 channels available; unused channels must be short-circuited (jumper between M and M -). + Labelling and Grouping of Channels The channels are labelled as follows on the module: Channel 0: MO+ MO Channel 1: M1 M1 - + Channel 15: + M15 M15 - The channels are arranged in groups of four, for which separate measuring ranges can be set: Channel group I: Channel 0 t o 3 Channel group II: Channel 4 t o 7 Channel group Ill: Channel 8 t o 11 Channel group IV: Channel l 2 t o l 5 + M7 M7- 43 Figure 10-23 Pin Assignments o f the 466Analog lnput Module in the Case o f Common-Reference Measurement Analog Value Processing CPU 945 Manual Figure 10.24 shows the connection of transducers t o the 466 analog input module. All "M-" connection points are linked t o each other internally on the module (this applies only t o common-reference measurement!). 466 Analog input module --V,,,, V, * Reference bus I : : Input voltage Isolating voltage : Equipotential: this potential is determined by the sensor reference potential (external reference potential) Figure 10.24 Connecting Transducers to the 466Analog Input Module (Common-Reference Measurement) Note See Sections 3.5.2 t o 3.5.4 for further information on wiring, electrical structure and conductor arrangement. CPU 945 Manual Analog Value Processing Differential Measurement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 MO+ M ext M ext MO- + M1 M ext M ext M1M2+ M ext M ext M2- + M3 M ext M ext M3- Differential measurement is a method o f measuring which compensates for noise on t h e line. Each signal line is assigned i t s o w n signal reference line. By measuring the difference between t h e signal line and t h e signal reference line, noise on both lines is compensated for. Unused channels also must be short-circuited when using this method o f measuring (jumper between M +and M -). Differential measurement is required i n the following cases: m m m M4+ M ext M ext M 4M5+ M ext M ext M 5M6+ M ext M ext M6- + M7 M ext M ext M7- When t h e sensors are connected t o different supplies When different signal sources are physical ly separate When signals must b e captured w i t h high accuracy When a high level o f noise is expected. Labelling and Grouping o f Channels The channels are labelled as follows on t h e module: Channel 0: MO+ MOChannel 1: M1 M1- + Channel 7: M7+ M7- The channels are arranged in groups o f four, f o r which separate measuring ranges can be set: Channel group l: Group 0 t o 3 Channel group II: Group 4 t o 7 Figure 10.25 Pin Assignments of the 466Analog Input Module in the Case of Differential Measurement CPU 945 Manual Analog Value Processing Figure 10.26 shows the connection of transducers t o the 466 analog input module. When connecting transducers, you must take account o f the following conditions: (i.e. the sum of the voltage measuring set and the common mode must VI VCM < 12V be less than 12 V; current measuring ranges correspond t o a voltage o f + 2.5 V) 466 Analog input module I,+ - I I,,,, ,,,,,I 1150 6 : : : : Input voltage Common mode Isolating voltage Equipotential: this potential is determined by the sensor reference potential (external reference potential) Figure 10.26 Connecting Transducers to the 466Analog lnput Module (Differential Measurement) Note See Sections 3.5.2 t o 3.5.4 for further information on wiring, electrical structure and conductor arrangement. EWA 4NEB 81 1 61 50-O2d CPU 945 Manual Analog Value Processing 10.6.2 Startup of the 466-3LA11 Analog Input Module The operating mode of the 466 analog input module is set exclusively via switches on the the printed circuit board. Figure 10.27 shows the labelling and locations of the switches on the PCB. Front side Backplane connector t o S5 110 bus Figure 10.27 Locations of the Mode Selectors on the 466-3LA11 Analog Input Module Note An adapter casing (e.g. 6ES5 491-OLB42) is required for using the 466 analog input module in the 55-1 15U. You also require a 43-pin front connector K; 6XX3 068 for crimp connections or 6XX3 081 for screw connections. EWA 4NEB 81 1 61 50-02d Analog Value Processing CPU 945 Manual Setting the Type of Measurement Common-reference MeasurementIDifferential Measurement Set switch S 9 t o t h e type o f measurement (common-reference or differential). The switch positions refer t o the module as represented in Figure 10.27: Table 10.7 Setting the Type o f Measurement (Common-Reference or Differential) 1 9 ON Common-reference measurement OFF 1 9 ON Differential measurement OFF CurrentIVoltage Measurement f o r Individual Channel Groups If you have set differentialmeasurement a t Switch S 9, there are t w o channel groups available t o you, each w i t h four channels. You can configure each channel group separately f o r current or voltage measurement. For this purpose, you must set t h e switches S 5, S 6, S 7 and S 8 (see Table 10.8 and 10.9). Switches S 5 and S 7 permit three settings (Left, Middle, Right); switches S 6 and S 8 permit t w o settings (Left, Right). The switch positions refer t o t h e module as represented in Figure 10.27: Table 10.8 Settinu CurrentIVoltaue Measurement for Channel G r o w I I Current I m I I Voltage I m I Table 10.9 Setting CurrentIVoltage Measurement f o r Channel Group II I I Current Voltage I I I m EWA 4NEB 81 1 61 50-02d I Analog Value Processing CPU 945 Manual If you have set common-reference measurement a t Switch S 9, there are four channel groups available t o you, each w i t h four channels. You can configure each channel group separately f o r current or voltage measurement. For this purpose, you must set the switches S 5, S 6, S 7 and S 8 (see Table 10.10 t o 10.13). Switches S 5 and S 7 permit three settings (Left, Middle, Right); switches S 6 and S 8 permit t w o settings (Left, Right). The switch positions refer t o the module as represented i n Figure 10.27: Table 10.10 Settincl I Current I I Table 10.1 1 Setting CurrentIVoltage Measurement f o r Channel Group II I Current I I Table 10.12 Setting CurrentIVoltage Measurement for Channel Group Ill Current IfEl Voltage m Table 10.13 Setting CurrentIVoltage Measurement f o r Channel Group IV EWA 4NEB 81 1 61 50-02d Current E l Voltage m CPU 945 Manual Analog Value Processing Setting the Measuring Range The 466 analog input module has 12 measuring ranges. One measuring range can be selected for each channel group (i.e. for four inputs each), independently of the other channel groups. Set the measuring ranges with switches S 1 and S 2. See Figure 10.28 for the assignment of switches t o channel group. Channel group l (Channel 0 to 3) Channel group ll (Channel 4 to 7) Channel group Ill (Channel 8 to ll ) Channel group lV (Channel l 2 to 15) Figure 10.28 Assignment of Switches S 1/S 2 to Channel Group The same measuring range coding applies t o all channel groups. For this reason, the following table (see Table 10.14) contains only the measuring range setting for one channel group. The switch positions referto the module as represented in Figure 10.27. Please note that the type o f measurement (current/voltage) must be set additionally with switches 5 5 t o 5 8! Table 10.14 Settina the Measurina Ranae for One Channel Group (4Channels per Group) Analog Value Processing CPU 945 Manual Setting the Data Format The data format must be set with switch S 9: Two's complement - Number with sign - Binary - 12-bit two's complement representation (range: 0 t o 4095 units unipolar, or - 2048 tod-2047 units bipolar) Il - b i t number and l - b i t sign (range: 0 t o 4095 units unipolar, or - 2048 t o 2047 units bipolar) 12-bit binary number (range 0 t o 4095 both for unipolar and bipolar variables) + Table 10.1 5 Settinq - the Data Format #axa Form&% Switch Position S 9 I 1 9 ON Two's complement OFF Number with sign Setting the Connection Type and the Module Starting Address Table 10.16 Setting the Connection Type and Address Range When operating in CC or EU over distributed connections with lM 3041314.307131 7,308131 8-3 1 Address in extended 110 area (Q area)* P - * Possible in expansion unitwith distributed connections only EWA 4NEB 81 1 61 50-02d ON OFF 1 Address in I10 area (P area) 9 9 ON OFF Analog Value Processing CPU 945 Manual Table 10.16 Setting the Connection Type and Address Range (continued) When operating in distributed EU 701-213 with AS 301 1310, only in I10 area (P area) 1 9 ON OFF See Table 10.17 for the precise setting of the module starting addresses. Table 10.17 Setting the Module Starting Addresses (P area) 123456789 ON OFF 123456789 ON OFF 123456789 ON OFF 123456789 ON OFF - - . - - . - - ON OFF 123456789 ON OFF 123456789 ON OFF 123456789 ON OFF * Can only be set in the case of differential measurement Analog Value Processing CPU 945 Manual Table 10.18 Setting the Module Starting Addresses (Q area) * Can only be set in the case of differential measurement Analog Value Processing Table 10.18 CPU 945 Manual Setting the Module Starting Addresses (Q area) (continued) 123456789 ON OFF 123456789 ON OFF L * I Can only be set in the case of differential measurement CPU 945 Manual 10.7 Analog Value Processing Representation of the Digital lnput Value The analog value has t h e same representation i n t h e three analog i n p u t modules. However, t h e r e are differences i n t h e case o f analog value evaluation where t h e individual analog input modules are concerned, especially bits 0 t o 2 (see Figure 10.29). After an analog signal is converted, t h e digital result is stored i n t h e module's RAM. Figure 10.29 explains t h e individual bits o f t h e t w o bytes. Byte Bit U Binary measured value Activity bit; n o t used o n t h e Al466-3LAA Fault bit; is set i n t h e event o f a n internal fault; t h e measured value read i n is t h e n n o t valid I d Overflowbit; is set when t h e measuring range l i m i t is reached Figure 10.29 Representation of the Digitized Measured Value Bits 0 t o 2 are irrelevant f o r t h e measured value. They provide information o n t h e measured value representation. Table 10.19 describes these bits i n detail. Table 10.19 Meaning o f Bits 0 t o 2 f o r Analog l n p u t Modules I * terminated An overflow a t one measuring point has no effect on t h e overflow bits o f the other channels, i.e. t h e values on the other channels are correct and may be evaluated. CPU 945 Manual Analog Value Processing Special Features of the 466 Module m Bit 15 (212) indicates the sign in the case of bipolar measured value representation (two's complement and number with sign). Bit 14 (211) is not used in the case of bipolar measured value representation (no overrange!). The 466 module has no overrange. Selective sampling is not possible on the 466 module (activity bit is not set). 10.7.1 Types of Representation of the Digital lnput Value for the 460 and 465 Analog lnput Modules Theway inwhich the analog value is represented depends on the type o f module (see Tables 10.20 t o 10.25). Table 10.20 Representation of Digitized Measured Values of the 460 and 465 Al (Two's Complement; Measuring Range& 50 mV,? 500 mV, & 1000 mV) 100.000 1000.00 2000.00 4095+0V 0 1 1 1 1 1 1 1 1 1 1 1 10 99.976 999.76 1999.52 4095 0 l 1 1 l 50.024 500.24 1000.48 2049 0 1 0 1 0 1 0 l 0 0 l 0 0 0 1Overflow 1 1 1 1 1 1 1 10 0 0 Overrange 0 0 0 1 l 0 0 OOverrange 0 0 0 l l 0 0 l 0 0 l l 0 0 0 0 l 0 0 0 l 0 0 1 1 0 I 0 I Analog Value Processing CPU 945 Manual Table 10.21 Representation of Digitized Measured Values of the AI 460 and 465 (Two's Complement; Measuring Range& 5 V,& 10 V,? 20 mA) 9.9976 19.9952 39.9902 4095 0 1 1 1 1 1 1 1 1 1 1 1 l 0 0 OOverrange 5.0024 10.0048 20.0098 2049 0 1 0 0 0 -5.0024 -10.0048 -20.0098 -2049 1 0 1 1 1 1 1 1 1 1 1 1 l 0 0 0 Overranqe -9.9976 -19.9952 -39.9902 -4095 1 0 0 -10.0000 -20.0000 -40.0000 -4095+0V 0 1 Overflow 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 l 0 CPU 945 Manual Analog Value Processing Table 10.22 Representation of Digitized Measured Values of the 460 and 465 AI (Number and Sign; Mesuring Range k 50 mV, k 500 mV, k 1000 mV) 100.000 1000.00 2000.00 4095+0V 0 1 1 1 1 1 1 l 1 1 1 1 10 0 1Overflow 99.976 999.76 1999.52 4095 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 OOverrange 50.024 500.24 1000.48 2049 0 1 0 -50.024 -500.24 -1000.48 -2049 1 1 0 -99.976 -999.76 -1999.52 -4095 1 0 0 0 0 0 0 0 0 1 1 1 1 1 l 0 0 0 0 l Note Bit 7 in the high-order byte is the sign (S). If S is 0, the value is positive. If S is l , the value is negative. 1 0 0 0 1 0 0 0 0 0 0 l 0 0 0 Overranqe 1 1 1 1 0 0 0 CPU 945 Manual Analog Value Processing Table 10.23 Representation of Digitized Measured Values of the 460 and 465 AI (Number and Sign; Measurina Range* 5 V,& 1 0 V , k 2 0 mA) 10.0000 20.0000 40.0000 4095+OV 0 l 1 1 1 1 l l l 1 1 1 10 9.9976 19.9952 39.9902 4095 0 l P 1 1 P l l l 5.0024 10.0048 20.0098 2049 0 1 0 0 0 0 0 -5.0024 -10.0048 -20.0098 -2049 1 1 0 -9.9976 -19.9952 -39.9902 -4095 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 0 l Overflow 1 1 1 1 0 0 OOverranqe 0 0 0 0 1 0 0 1 1 0 1 0 0 l 0 0 OOverrange 1 1 0 0 0 CPU 945 Manual Analog Value Processing Set the measuring range of the module t o 500 mV and plug in a 6ES5 498-1AA 71 module. The measuring range 4 t o 20 mA is resolved into 2048 units from 512 t o 2560. For representation in the range 0 t o 2048, 512 units must be subtracted at the software level. Table 10.24 Representation of Digitized Measured Values of the 460 and 465 AI (Current Measurina Ranae 4 t o 20 mA) 32.796 * 1024.00 4096+ 0 1 1 1 1 1 l 1 1 1 1 1 1 0 0 loverflow 31.992 4095 1023.76 0 1 1 1 1 1 1 1 1 1 1 1 10 0 0 Overranqe* 24.000 3072 750.00 0 1 0 0 0 23.992 3071 749.76 0 1 0 1 . 1 1 20.008 2561 625.24 0 1 3.992 511 124.76 0 0 0 3.000 384 93.75 0 0 0 2.992 383 93.50 0 0 0 0.000 0 0.00 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 ORanqe 0 1 1 0 0 0 0 0 0 0 0 Oviolation 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 OOverflow 0 0 0 1 0 1 1 Short-circuit o f the two-wire transducer Note The 31.25 C 2 shunt resistor integrated in the 498-1AA71 suppresses the wire break signal (the F bit is not set). You can thus detect a wire break only by comparing the measured value with a lower limiting value in the user program. A measured value lower than, for example, 1 mA (= 128 units) would then be interpreted as a wire break. CPU 945 Manual Analog Value Processing Table 10.25 Representation o f Digitized Measured Values o f t h e 460 a n d 465 AI for Resistance-Tv~eSensors 400.000 4095 0 1 1 1 1 1 1 1 1 1 1 1 1 0 399.900 4095 0 1 1 1 1 200 098 2049 0 1 0 0 0 1 1 1 1 I 0 0 0 0 0 1 0 1 10 0 1 0 0 loverflow 0 0 Overrange 0 0 The resolution i n t h e case o f t h e PT 100 is approximately 113 "C 10 units correspond t o approximately 1 Q. You can use t h e assignment i n Figure 10.30f o r t h e PT l00 resistance sensor Linearization o f t h e digital i n p u t values is n o t carried o u t via t h e modules. You can linearize t h e i n p u t values only via t h e relevant software solution. -270 "C -220 0 I I t I 0 270 750 10 100 200 approx. 890 ...................I I I 360 ------ 400 ................... " / / I Nonlinear range U =R - I = R . 2.5 mA (constant current) 0 Units 102 1024 2048 3 680 I I I I I I I I Overrange Resolution: l 0 units=1 s2 270C : 1024 units=0.3 OClunit Figure 10.30 PT 100 on SlMATlCAnalog Input Modules EWA 4NEB 81 1 61 50-02d 4096 CPU 945 Manual Analog Value Processing Representation of Measured Value for the New PT100 Climatic Measuring Range of the 4607LA13 AI Table 10.26 Representation of Digitized Measured Values for the PT100 Climatic Measuring Range of the 460-7LA13 AI t4095 140 350 100 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 10verflow k4095 139.99 103.74 349.976 99.976 0 1 1 1 1 1 1 l 1 1 1 1 l 0 0 0 Overrange +2049 120.01 51-61 300.024 50.024 0 1 0 0 0 10 0 0 -2049 79.99 -50.81 199.976 -50.024 1 0 1 1 1 1 1 1 1 l l 1 10 0 0 Overrange -4095 60.01 -100.60 150.024 -99.976 1 0 0 0 0 0 0 0 0 0 0 0 10 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 loverflow <-4095 60 150 -100 0 0 0 0 0 0 0 W i r e break t i 0 10 0 1W i r e b r e a k Ic+/Ic- 0 10 2, 1 1W i r e b r e a k transducer measuring circuit l ) T: Active F: Error bit OV: Overflow X: Any Only with wire break detection activated 1) Error bit = 1 only in case of faulty channel; In case of transducer break overflow bit = 1 for all channels 2) Through the PT100 series connection, this bit combination is set for all channels in the case of a break in the supply circuit. Analog Value Processing CPU 945 Manual 10.7.2 Types of Representation of the Digital lnput Value for the 463 Analog lnput Module With t h e analog input, t h e analog value is represented in the two's complement w i t h t h e following data format. Byte Bit J Binary measured value Overflow bit (is set when t h e measuring range limit is reached) d Figure 10.31 Representation of Digitized Measured Values of the 463Analog Input Module Table 10.27 Representation o f Digitized Measured Values o f the 463 AI (Two's Complement; Measuring Range 0 t o 10 V, 0 t o 1 V, 0 t o 20 mA, 4 t o 20 mA) n. b. Unused Analog Value Processing CPU 945 Manual Table 10.27 Representation of Digitized Measured Values of the 463 AI (Two's Complement; Measuring Range 0 t o 10 V, 0 t o 1 V, 0 t o 20 mA, 4 t o 20 mA) (continued) n.b. Unused * With data format setting 0 t o 1023 (via switch on the module) ** With data format setting 256 t o 1279 (switch on the module) A shunt resistance o f 50 ohms is used for the 0 t o 20 mA measuring range; for the 4 t o 20 mA range, the resistance is 62.5 ohms. The shunt resistors are permanently installed on the 463 analog input module. Wire break detection is in principle not possible; f o r t h e 4 t o 20 mA current measuring range, a wire break can be detected for currents < 3 mA. If 2-wire measuring transducers (4 t o 20 mA) are used and their plus and minus terminals are shortcircuited, the current is limited t o approximately 28 mA. Until activation of the thermal current Iimiter (approx. 3 S),a short-circuit current o f approx. 250 mA flows, which sets the overflow bit on the short-circuited channel during the 3-s period. Analog Value Processing CPU 945 Manual 10.7.3 Forms of Re resentation of the Digital lnput Values for the 466 Analog P lnput Modu e Tables 10.28 t o 10.36 give information on the representation o f t h e digitized measured value depending o n t h e measuring range selected. The 466 analog input module has no overrange. Table 10.28 * Representation o f Digitized Measured Values o f the 466 A I (Measuring Range 0 t o 20 mA; 0 t o 5 V and 0 t o 10 V; unipolar) 4 .g988 9.9976 19.9951 4095 0 l 1 4.9976 9.9951 19.9902 4094 0 1 1 1 . 1 1 1 1 1 1 . 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 0.0012 0.0024 0.00488 0001 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0.0000 0.0000 0.00000 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Same representation as fortwo's complement, number and sign and binary representation Table10.29 Representation o f Digitized Measured Values (Two's Complement; Measuring Range ? 5 V, ?20 m A and k 10 V; bipolar) Table 10.30 Representation o f Digitized Measured Values (Number and Sign; Measuring Range? 5 V,? 20 m A and ? 10 V; bipolar) Analog Value Processing * CPU 945 Manual Table 10.31 Representation of Digitized Measured Values (Bmary; Measuring Range 5 5 V, k 20 mA and k 10 V; bipolar) Table 10.32 Representation of Digitized Measured Values (Measuring Range 0 to 1.25 V, and 0 to 2.5 V; unipolar) Same representation as fortwo's complement data format, number and sign and binary representation Table 10.33 Representation of Digitized Measured Values (Two's Complement; Measuring Range k 1.25 V, and 52.5 V; bipolar) EWA 4NEB 81 1 61 50-02d CPU 945 Manual Analog Value Processing Table 10.34 Representation o f Digitized Measured Values (Number and Sign; Measuring Range ? 1.25 V, and 2 2.5 V; bipolar) Table 10.35 Representation o f Digitized Measured Values (Binary; Measuring Range? 1.25 V, a n d ? 2.5 V; bipolar) Table 10.36 Representation o f Digitized Measured Values (Measuring Range 4 t o 20 m A a n d lt o 5 V) * Same representation as for two's complement data format, number and sign and binary representation The measuring ranges 4 t o 20 m A and 1 t o 5 V (see Table 10-31) are resolved t o 2048 units i n t h e interval 51 2 t o 2560. For representation i n t h e range 0 t o 2048, 51 2 units must b e subtracted per software. A wirebreak signal is n o t provided. You can scan t h e measured value i n t h e user program f o r a lower l i m i t a n d interpret values b e l o w this limit as wirebreak. Analog Value Processing 10.8 CPU 945 Manual Wirebreak Signal and Sampling for Analog Input Modules Wirebreak Signal Wirebreak is signalled only in the case of the 460 and 465 analog input modules. If a 6ES5 498-1AA11 range card (through-connection card) is used, you can select the "Wirebreak signal" function t o monitor the sensors connected t o the inputs (see Tables 10.1 t o 10.5). You can select wirebreak detection for 8 or 16 inputs for 16-channel operation or for 418 inputs for 8-channel operation. The wirebreak signal is issued under the following conditions: Before each input value i s decoded, a constant current is applied briefly (1.6 ms) t o the input terminals and the resulting voltage compared with a limiting value. If the sensor circuit or supply lead is interrupted, the voltage exceeds the limiting value and a wirebreak signal is generated (bit 1 is set in data byte 1; refer t o Section 10.5.1). The ADCdecodes the value "0". When the signal at the input is measured with a digital voltmeter, the constant-current pulses may cause apparent fluctuations in the signal. When the input circuit that supplies the analog value has capacitive characteristics, the constant current falsifies the measured value. Should these apparent fluctuations in the signal prove annoying, e.g. on startup, the test current can be deactivated on the 460-7LA12 and 465-7LA12 analog input modules by applying 24 V t o pin 26 in the front connector and 0 V t o pin 47 (L-) of the 460-7LA12 module or t o pin 37 (Mefi) of the 465-7LA13 module. In addition, mode selector I must be set t o "No wirebreak signal". + A wirebreak signal serves a practical purpose only in conjunction with a 6ES5 498-1AA11 through connection card. I t is not possible t o detect a wirebreak on the 6ES5 498-1AA41, -1AA51 or -1AA71 range cards, as the measuring inputs are terminated with low-resistance shunts. On all other range cards, a wirebreak signal results in an undefined reaction. CPU 945 Manual Analog Value Processing Wirebreak Signal in Conjunction w i t h Resistance Thermometers An interruption in the supply leads t o a resistance thermometer is reported as follows: Table 10.37 Wirebreak Signal in Conjunction w i t h Resistance Thermometers * M+ 010 1 1 M- 010 1 1 PT100 (resist.-type sensor) O*/O 0* 1 S+ 010 0 1 S- 010 0 1 On the 460 analog input module, the value "0" is also decoded for the unbroken PT 100 resistors and error bit F setto 0. The overflow bit is set separately for each channel in the case o f the 4601465-7LA12 modules. The S+lines t o the resistance thermometer can be monitored for a wirebreak on the 465 -7LA12 analog input module by setting switch 7 o f mode selector I t o "PT 100" (PT l 0 0 constant power supply). The error bit is also set t o flag a wirebreak in this line. Unused channels can be used t o measure voltages or currents when the current sourcing outputs (S+, S -) associated with the relevant measuring channel are short-circuited with a jumper. Without this jumper, the error bit would be set for this channel and the value "0" decoded. The S+lines are not monitored for wirebreak when mode selector I I is in the "Current or voltage measurement" position. In this case, the error bit is not set when a wirebreak occurs. This switch setting should be selected when onlyvoltages or currents are t o be measured (see Figure 10.7). The following general rule applies: When the wirebreak signal is t o be issued, the measuring circuit must have a low resistance ( < l kn). EWA 4NEB S1 1 61 50-02d CPU 945 Manual Analog Value Processing Sampling The 460 and 465 modules offer t w o methods of sampling the analog value: Cyclic sampling and Selective sampling The 463 module implements only cyclic sampling. The 466 module implements only cyclic sampling because o f i t s high speed. Cyclic Sampling The modules's processor decodes all inputs. However, there are differences between the individual modules. For example, the amount of time that elapses before a measured value is updated depends on the number o f input channels. The time required for decoding depends on the input value. In the case of the 460 analog input module, when VI=O V, decoding takes 40 ms; when V,= nominal value, decoding takes 60 ms. Table 10.38 Scan Times * Nominal value applied t o all inputs In the case o f the 4601465 modules, the digitized measured values are stored in the circulating buffer under the channel address (the high-order byte under address n, the low-order byte under address n + l), and can be read out from the buffer whenever required. Selective Sampling Selective sampling is not possible on the 463 and 466 modules. Double addressing cannot be used for selective sampling, i.e. an address cannot be assigned t o an analog output module and an analog input module. In the case o f the 460 and 465 modules, the initiative for decoding a measured value comes from the CPU when this function is used. The module must be accessed once with a Write command (T PW) under the relevant channel address; the data itself is o f no relevance. In this way, only the measured value o f the activated channel is decoded and the other channels are ignored. During decoding, an activity bit is set on the data bus (A= l, see also Section 10.7). The module sets the activity bit independently, i.e. if several channels are t o be decoded using selective sampling, the activity bit cannot be assigned t o one channel! The valid digitized measured value can be read out from t w o bytes once the activity bit has been reset (A=O, negative-going edge). EWA 4NEB 81 1 61 50-02d CPU 945 Manual Analog Value Processing Repeated scanning o f t h e activity b i t loads both t h e bus and t h e CPU. This results i n non-periodic measured value acquisition when different measured values are involved, and is therefore n o t desirable for PID control tasks. A better method is time-controlled program execution, i n which certain program sections, for instance FB13, are automatically inserted i n t o t h e program every 100 ms by a time-controlled block (OBI 3), thus producing a constant time base while offloading t h e bus and the CPU. The associated sample program is written as follows: :L PW128 READ ANALOG VALUE :T FW128 T R A N S F E R T O A U X I L I A R Y FLAG :A F 129.2 SCAN A C T I V I T Y B I T :J C =END I F = I , J U M P T O END :T FWlO I F = 0, :T PB128 I N I T I A T E SAMPLING T R A N S F E R MEASURED V A L . ( 1 S T VAL. 10.9 TO FW 1 0 I S I N V A L I D FOLLOWING R E S T A R T ) Analog Output Modules The CPU processes t h e digital values t h a t t h e analog output modules convert t o t h e required voltages or currents. Various floating modules cover individual voltage and current ranges. Signal Interchange between CPU and Module The CPU transfers a digital value t o the module's memory under a specified address.The user starts the transfer via FB251 or "TPY" or "TPW" operation. Block diagraml0.32 illustrates t h e principle o f operation o f t h e 470 analog output module. Analog Value Processing CPU 945 Manual CPU 4 I I Control signal Control signals Address bus S5 bus Data bus II I I v v v Address decoder - ) n Processor Clock pulse Circulating buffer Galvanic isolation .-----------------------------O_et_~co_~~le~----------------------------------. +24V t +16V +5.6V -7.2V A A Digital-analog converter 4 -7\ M UX 4 mode regulator A J. Sample and Hold J. 8X --------------- T A L tk t DI L+ MUX D/A L- V $ AO, AO, V/l converter Sample and Hold -4 T 41 - - - - - - -8-X- - - - - - - - - - - - Process signal output t DI v $ A7, A7, Multiplexer Digital-analog converter Figure 10.32 Block Diagram with Signal Interchange between CPU and a 470 Analog Output Module CPU 945 Manual Analog Value Processing 10.9.1 Connecting Loads to Analog Output Modules When loads are connected t o analog output modules, t h e voltage is measured directiy across the load via high-resistance sensing lines (S+/S -). The output voltage is then corrected so t h a t t h e load voltage is n o t falsified by voltage drops on t h e lines. In this way i t is possible t o compensate voltage drops o f up t o 3 V per line. Figure 10.33 shows t h e design o f this circuit. Load voltage QV (X) = Analog output voltage QI (X) = Analog output current S+ (X) = Sensing line+ S- (X) = Sensing line- (QV= Output voltage) (Q1 = Output current) (S+ =Sensing line+) Load current (S-=Sense line-) MANA X MANA Figure 10.33 Connecting Loads = Ground terminal of t h e analog component = Channel no. (0 t o 7) Analog Value Processing CPU 945 Manual Connecting Loads t o Current and Voltage Outputs Figure 10.34 shows h o w t o wire the analog output module. Figure 10.34 Connecting Loads to Current and Voltage Outputs Note If voltage outputs are not used, or if only current outputs are connected, jumpers must be inserted in the front connector for the unused voltage outputs. To do this, connect QV (X) t o S (X) and S - (X) t o MANA. Unused current outputs remain open. + EWA 4NEB 81 1 61 50-02d CPU 945 Manual Analog Value Processing 10.9.2 Digital Representation of an Analog Value The CPU uses t w o bytes t o represent the value o f an output channel. Figure 10.35 explains t h e individual bits: Byte No. Bit No. X represents an irrelevant b i t Figure 10.35 Representation of an Analog Output Signal in Digital Form Note For the two's complement, b i t 2" indicates t h e sign (0 equals a positive value, 1 a negative value). EWA 4NEB 81 1 61 50-02d CPU 945 Manual Analog Value Processing Table 10.39 lists the output voltages or currents of the individual 470- ... analog output modules. Table 10.39 Analog Output Signals 1 * The insignificant bits have been omitted 6.0 124.0 I 0 1 0 1 o 0 0 0 0 0 0 0 I Overrange Analog Value Processing CPU 945 Manual 10.10 Analog Value Matching Blocks These blocks match the nominal range o f an analog module t o a normalized range that you can specify. The CPU 945 has four analog value matching blocks which are assigned t o the various analog input modules m m m m For the 460 and 465 analog input modules: For the 463 analog input module: For the 464-8 (ET 1OOIET 200) analog input module: For the 466 analog input module: FB250 F6241 F8242 F B243 The FBs read an analog value from the analog input module assigned t o them and output a value XA as a 32-bit floating-point number in the scaled range specified. Define the desired range using the "upper limit" (OGR) and "lower limit" (UGR) parameters. Specify the type of analog value representation (channel type) in the KNKT parameter The BU parameter is set when the analog value exceeds the nominal range. Analog Value Processing 10.10.1 CPU 945 Manual FB25O-Reading and Scaling Analog Values of the 460 and 465 Analog Input Modules Call and Parameter Assignments KY= 2.1 28 t o 2.224 (2.240)* KT= Channel (nominal range 0 t o +2048) (norn. range -2048 t o * + 2048) 224for 16 channels 240 for 8 channels Selective Sampling FB 250 permits reading o f an analog value with selective sampling. Setting the "EINZ" parameter t o "1" causes the analog input module t o convert the analog value o f the selected channel t o a digital value immediately. During conversion (approximately 60 msec.), no further sampling operations involving this module may be initiated. Consequently, the function block that is presently active sets the TBlTto "1" until the converted value is read in. The TBlT is reset upon completion of selective sampling is terminated. Analog Value Processing CPU 945 Manual Scaling: Function block FB250 converts the value read lineariyto accord with the upper and lower limiting values using the following formula: For channel type 3 (absolute value 4 t o 20 mA): XA= + UGR a(2560-xe) OGR .be-512) 2048 For channel type 4 (unipolar representation): XA = For channel type 5 and 6 (bipolar representation): XA = Where XA xe + UGR -(2048-xe) OGR axe 2048 + UGR a(2048-xe) OGR .(xe+2048) 4096 is the value output by the FB and is the analog value read from the module. Figure 10.36 Schematic Representation of Conversion EWA 4NEB 81 1 61 50-O2d Analog Value Processing 10.10.2 CPU 945 Manual FB241-Reading and Scaling Analog Values of the 463 Analog Input Module Call and Parameter Assignments ..,... .................... .......... ................. ......................,...,, .... ......... .; .................. ;....... ,..... :.:.:~:::~~:::*::::::: .......................... ...................... m ..:S :.:.#&@@@g$ E$#SiftrnRtwm .......(.... ................................ ..........,,,, ..........,... (...(.............i__ $ $ l )&C*:':'...~*&ii'y:x::,:ll: i I ) i : , g ~ ~ j : j j j : j : j j*~:i:j:i:i:j:~*~<q:::;::;2222jjjj~~jI)i:~:~~~ j : ; ~ i j j j ~ ~ ~ ~ ~ ........ :i:g :::::.:;::::::::::::::::::.:.S.. .......'.'.....'.'... .....:...~ .:.:.:.:$ .:.:.:.:.:.:.:. jfgg@g. :.%$p4 ~&@lE*rg:::i:::::i::i::I:::I:i::i:I::~@~@$ ........................................ @ ........~.....~.....@ ........;...:....:....:...:.. ; ..:...: ..; .:..,.: : ; ~ ~ .A. ,;;;: :.L...:.. :,:,:,:,:,:,:~:,:,:~:~;~x,Z,Z,Z,:,:,:,:,:,:,:, ........................................................... BG :.:...:.:,:,:,:, ..m :::::::::::::::::*:.:.:,:,:,M 110 area and module address D ,,,, KY KY=O.I 28 t o 0.248 (P area) KY= l.O t o 1.248 (Q area) KY=2.0 t o 2.248 (IM3 area) KY= 3.0 t o 3.248 (1M4 area) NAME BG KNKT KNKT KN = Channel D KY Q BI ,, ,, : JU F B 241 : Al:463 : KY=x,y = O t o 3 (channel number) KD = Channel type BU Range violation EWA 4NEB 81 1 61 50-O2d CPU 945 Manual 10.10.3 Analog Value Processing FB242-Reading and Scaling Analog Values of the 464-8Mxxx Analog Input Module Call and Parameter Assignments BG I10 area and module address D KY KY=0.128 t o 0.254 (P area) KY= 1.O t o 1.254 (Q area) NAME : JUFB242 :Al:464 BG KNKT KN= Channel D KY KNKT KY=x,y KD= Channel type 7: fixed-point represent., bipolar (norn. range -200 t o + 1369) (norn. range -200 to + 1200) : CPU 945 Manual Analog Value Processing 10.10.4 FB243-Reading and Scaling Analog Values of the 466 Analog Input Module Call and Parameter Assignment BG I10 area and module address D KY KY =O.'128 t o 0.224 (P area) KY = 1.Q t o 1.224 (Q area) NAME : JU FB 243 :Al:466 BG KNKT KN= Channel KD = Channel type KNKT : CPU 945 Manual 10.10.5 Analog Value Processing Outputting an Analog Value -FB251- Use function block FB251 t o output analog values t o analog output modules. Specify the module's type of analog representation (channel type) in the KNKT parameter. Values from the range between the "lower limit" (UGR) and the "upper limit" (OGR) parameters are converted t o the nominal range o f the relevant module using the following formula: For channel type 0 (unipolar representation): xa = 1024 .(XE- UGR) OGR- UGR For channel type 1 (bipolar representation): xa = Where XE xa is the digital value specified in the function block and is the value output t o the module. Calling and Initializing -FB251- KD = Channel t y p e EWA 4NEB 81 1 61 50-02d 1024 .(2 0XE-OGR- UGR) OGR- UGR Analog Value Processing 10.10.6 CPU 945 Manual Extended Error Diagnostics with the Analog Value Matching Blocks Besides t h e FB a n d BU bits, t h e analog value matching blocks o f f e r further diagnostics facilities. As additional error diagnostics, t h e analog value matching blocks provide additional information in ACCU l - L and i n t h e RLO w h e n exiting t h e block: RLO is set, w h e n t h e FB o r BU b i t = " 1 " When FB = "O", t h e digital value read b y t h e analog i n p u t module o r w r i t t e n t o t h e analog o u t p u t module is available i n ACCU l-L. When FB = " 1 ",an error number describing t h e error f o u n d is available i n ACCU l - L (see Table 10.40). Table 10.40 Error Diaanostics with t h e Analoa Value Matchina Blc cks 0001, Parameter BG<128 i n P area Parameter BG<128 i n P area Parameter KN>3 Parameter KN>3 Sum o f parameter BG and 2Xparameter KN>255 Sum o f parameter BG and 2 X parameter KN>255 Parameter Parameter Parameter BG<128 i n P area Parameter BG<128 i n P, Q, IM3, I M 4 area Parameter BG<128inP, Q, IM3, I M 4 area Parameter KN>15 Parameter KN>7 Sum o f parameter BG and 2Xparameter KN >255 Sum o f parameter BG a n d 2Xparameter KN > 255 Sum o f parameter BG and 2Xparameter KN > 255 OGRSUGR OGRlUGR OGRSUGR Parameter BG:x,y w i t h x>l Parameter BG:x,y w i t h Parameter BG:x,y with x>3 Parameter KN>15 NAK NAK CPU 945 Manual 10.11 Analog Value Processing Example of Analog Value Processing Problem Definition: A closed container contains a liquid. I t should be possible t o read the current liquid level o n an indicating instrument whenever required. A flag is t o be set when t h e liquid level reaches a specified limiting value. A 0 - 20 m A transducer transmits t h e liquid level signal (between 0 and 10 m) t o a 6ES5 460-7LA12 (460 AI) analog input module. The analog input module converts t h e analog current values into digital units (0 - 2048 units), which can be postprocessed by t h e 55-1 15U's application program. The application program compares t h e values w i t h a limiting value (max. permissible liquid level), sets a flag if necessary, and sends these values t o a 6ES5 470-7LBll ( A 0 470) analog output module. The analog output module reconverts t h e values into voltages (0 - 10 V). In response t o these voltages, t h e needle on t h e analog display swings proportionally t o t h e liquid level. Figure 10.37 shows t h e system configuration. inlet pl: Pressure o f the filled container p2: Pressure generated by the current liquid level Application program module Figure 10.37 Example of Analog Value Processing EWA 4NEB 81 1 61 50-02d Analog Value Processing CPU 945 Manual Startup Procedures 460 Analog lnput Module: b Connect the transducer directly t o the front connector on the AI 460 (Terminals: MO+, MO -1. ) The transducer supplies values between 0 and 20 mA, 0 mA corresponding t o a liquid level o f 0.00 meters and 20 m A t o the maximum liquid level, which is 10.00 meters. Plug a f 20 mA range card (6ES5 498-1AA41) into the AI 460. A digital value between 0 and 2048 units, which is subsequently processed by the application program, is then present a t the output o f the analog input modules's internal ADC (see Figure 10.38). pressure Figure 10.38 Function of the 460 Analog lnput Module b Set the mode selectors at the rear of the module as follows (Figure 10.39): Switch I1 Switch I Cyclic sampling No wirebreak signal Abs. value and sign 500 mVI ... mA I I l l l l i l 1 2 3 4 5 6 I 5 0 H z system frequency No reference junction compensation Figure 10.39 Setting Mode Selectors I a n d II EWA 4NEB 81 1 61 50-O2d CPU 945 Manual Analog Value Processing 470 Analog Output Module: ) Connect the indicating instrument directly via the module's front connector (pins: QVO, S 0, S - 0, MAN*). The analog output modules outputs a voltage between 0 and 10 V t o the indicating instrument, thus making i t possible t o read the liquid level as an analog value (Figure 10.40). + From the application program Value between 0 and 1024 Figure 10.40 Function of the 470Analog Output Module Program Structure ) ) ) Call and parameterize "Read analog value" function block FB250 (for conversion t o a range of from 0 t o 1000 cm [XA parameter]). Generate the limiting value (PB9). A flag (F 14.6) is set when the liquid level exceeds 900 cm. Call and parameterize "Output analog value" function block FB251 (for conversion o f a value in the range from 0 t o l000 cm [XE parameter] into a value between 0 and 1024 units for the A 0 470). Integral function blocks FB250 and FB251 are discussed in detail in Sections 10.10.1 and 10.10.5. NAME :AI:460 BG :KY 0,128 MODULE STARTING ADDR: 128 (WHEN SLOT ADDRESSING IS FIXED: SLOT 0) CHANNEL NO.: 0; UNIPOLAR REPRESENTATION: 4 KNKT :KY OGR :KG UGR :KG 0,4 EINZ :F 14.0 (SET IN EXAMPLE FOR: CYCLIC SAMPLING) IN FD 10: XA VALUE O<XA<1000CM XA FB 10 14.1 RELEVANT ONLY WHEN SET FOR WIREBREAK SIGNAL IF LEVEL > 1000CM, BU = 1 . RELEVANT ONLY FOR SELECTIVE SAMPLING. :FD :F BU :F TBIT :F +1000000+04 +0000000+00 14.2 14.3 EWA 4NEB 81 1 61 50-O2d PHYSICAL MEASURING RANGE: O<XA<1000CM RELEVANT ONLY FOR SELECTIVE SAMPLING Analog Value Processing NAME CPU 945 Manual :J U P B 9 GENERATE L I M I T I N G VALUE : J U FB 2 5 1 OUTPUT ANALOG VALUE :RLG:AA XE ( F B 2 5 1 ) XE :FD 10 XA ( F B 2 5 0 ) HG :KY 0,160 MODULE S T A R T I N G A D D R . ; ADDRESSING: = 1 6 0 ( F I X E D SLOT SLOT l ) KNKD :KY 0,O CHANNEL N O . : OGR :KG t10000000+04 P H Y S I C A L MEASURING RANGE: UGR :KG +0000000+00 :F 14.4 BU :F 14.5 = 1 i n c a s e of p a r a r n e t e r i z a t i o n e r r o r o r NAK. WHEN XA<UGR OR XA>OGR, BU = 1. :BE :L KG + 9 0 0 0 0 0 0 + 0 3 MAX. V A L . FOR L I Q U I D L E V E L MEASURED VALUE :L FD 1 0 :=F 1 4 . 6 0 O<XA<lOOOCM FB FB 0 ; UNIPOLAR REPRESENTATION: MEASURED VALUE > 900 I F YES, = F 14.6 ? I N I T I A T E REACTION I N SAME PROGRAM C Y C L E . .................... 11.2 Setting the Addresses for the Parameter Error Code in DBI (An example of how t o set the parameters correctly) . . . . . . . . . . . . 2 ...................-......me. 4 1. 3 ........................... 11 . 4 11.3 How t o Assign Parameters in DB1 11.4 Rules for Setting Parameters in DBI 11.5 How t o Recognize and Correct Parameter Errors 11.6 Transferring the DB1 Parameters t o the PLC 11.7 Reference Table for Initializing DB1 EWA 4NEB 81 1 61 50-02d 1 1- ................ 11 . 5 .................... 11 . 9 ........................... 11 .10 11. l 11.2 Parameter Error Code . . . . . . . . . . . . . . . . . . . . . . ..... . . . . . . . . . .. . . .... DB1 with Parameter Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 - 6 8 EWA 4NEB 81 1 61 50-02d CPU 945 Manual 11 Pararneterization of CPU 945 w i t h DB 1 Parameterization of CPU 945 with DBI The CPU has functions which you can set t o your own requirement. For example, you can initialize the following: Integral hardware clock Data interchange over SINEC L1 Data interchange via 2nd interface (interface submodule) - ASClldriver - 3964 computer link Call interval fortime-controlled program execution (OBIO t o 13) System characteristics (e.g. scan time monitoring) Address for parameter error code. You can initialize these functions in data block DB1 11. l Configuration and Default Settings for DBI To make it easier for you t o assign parameters, data block 1 is already integrated in the programmable controller with preset values (default parameters). After performing an overall reset, you can load the default DBI from the programmable controller into your programmer and display it on the screen: $$$$$$2:;2222: ;$m!; R<<<::<?<;::::::: 0: KS = ' D B ~ :.:...,. % :...:............. ~ # & @ $ ~1 O0 0B ~ ~ 12: KS = ' WD 5 0 0 ; END '; .................... @$$## parameter block identifiers 19: This default DB1 contains one parameterblockeach f o r t h e following functions: Specifying the call interval for OB13; parameter block "TFB: ". System characteristics (scan time monitoring); parameter block "SDP: ". What Typifies a Parameter Block? A parameter block contains all the parameters of one function; it always starts with a block identifier followed by a colon. The colon must be followed by at least one space. The semicolon (;) indicates the end o f a parameter block. The parameters are contained between the block identifier and the semicolon (;). EWA 4NEB 81 1 61 50-02d Parameterization of CPU 945 with DB 1 11.2 CPU 945 Manual Setting the Addresses for the Parameter Error Code in DBI (An example of how to set the parameters correctly) We recommend that you use this example when you start setting your parameters. The following t w o reasons explain why. l . There are no default parameters in DBI for parameter block "ERT:". You must therefore enter this block complete. We will explain the entries step by step. In doing so, you will quickly learn the rules for initializing. 2. Properly entered, parameter block "ERT:" makes it easy for you t o correct parameter errors. For this reason, you should complete this block in DBI before changing or entering other parameters. To help find parameter errors easier and t o help correct them, you can ask the programmable controller t o output error messages in a coded form. All you have t o do is t o tell the programmable controller where it should store the error code. Make this input in parameter block "ERT:" of DBI. The error code can be stored in: flags/S flags or data blocks (DBIDX). The entire error code consists of 20 flag bytes or 10 data words. You only need t o indicate the start address for the error code in parameter block "ERT:". Procedure: Overall Reset has been performed on the CPU and the CPU is in the STOPstate. b b b Display default DBI on the programmer Position the cursor on the E o f the end identifier "END" at the end o f default DBI Now enter the shaded characters: The parameter error code is stored from flag b Use the following check l i s t t o make sure your entries are correct. Is the block ID "ERT:" terminated by a colon? Is at least 1 filler (a blank space) added after the colon? Is the parameter name ("ERR") entered correctly? - Does a t least 1 filler (a blank space) follow the parameter name? - Is the argument (for example "FYI ") entered correctly? - Does a t least 1 filler (a blank space) follow the argument? - Does a semicolon (;) indicate the block end? - The end ID "END" concludes DBI - EWA 4NEB 81 1 61 50-02d CPU 945 Manual ) ) Parameterization of CPU 945 with D6 1 Transferthe changed DBI t o the programmable controller. Switch the programmable controller from STOBto RUN. Changed DBI parameters are accepted. If you did not store the parameter block "ERT:" in DBl, you can localize the error in the ISTACK if there was an incorrect parameter setting. However, you will not know what type of error is present. The same thing applies if you made an error when you input the parameter block "ERT:". 11.3 How to Assign Parameters in DBI As illustrated in Section 11.2, you use the following steps t o change or expand the preset values o f DB1: ) ) ) ) ) Displaythe default DBl, with i t s parameter block "ERT:" on the programmer. Position the cursor on the desired parameter block. Change or expand the parameters. Transferthe changed DBI t o the programmable controller. Switch the programmable controller from STOP t o RUN. Changed DBI parameters are accepted. The following applies when initializing in DBI: Not all parameters o f a parameter block must be defined in DBI. If some parameters are not defined in DBI, the default setting of the relevant system data word automatically applies! If you delete a DBI in the PLC, the integral DBI is retrieved by an overall reset of the CPU. In addition t o DBxDWy arguments, DXaDWa arguments can be used, if you store the parameters in DX blocks. You can set parameters in either uppercase or lowercase. Note If the CPU detects a parameter error in DBI, the restart is interrupted on transition from STOP =+ RUN or after POWER ON and the CPU goes into STOP with the identifier SYSFE in the ISTACK. Parameterization of CPU 945 with DB 1 11.4 CPU 945 Manual Rules for Setting Parameters in DB1 DBI consists of the following: F Astart block ID .................... ........ . . .. . .... . . One or more parameter blocks ....................... : DBI e. g.: TFB: OB13 100 A parameter block consists of: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e. g.: TFB: -b A block ID + One or more parameters .................. e. g.: OB13 100 A parameter consists of: I-+ A parameter name One or more arguments A block end ID -b A block end symbol: ............. ........ e. g.: OB13 e. g.: 100 ............................... ..................................... : ; (Semicolon) END The following is a list of all the rules you must observe when changing parameters in DBI or when completing whole parameter blocks. If you do not observe these rules, the CPU cannot interpret your entries. The structure o f this DBI depends on whether interprocessor communication flags must be defined or not! 1. If interprocessor communication flags must be defined: DBI begins w i t h the definition o f the interprocessor communication flags as described in Section 12.2.1. The "DBI" start identifier for the other DBI parameters follows the interprocessor communication flag end identifier (EEEEH). The three characters must not be separated by spaces. The "DBI" start identifier must be followed by at least one space. If no interprocessor communication flags must be defined: DB1 begins w i t h the "DBI" start identifier. The three characters must not be separated by spaces. The "DBI" start identifier must be followed by at least one space. 2. The start identifier (including space) is followed by the block identifier of a parameter block. The parameter blocks can follow any order in DBI. The block identifier indicates a block o f related parameters. The block identifier "TFB" stands for "Timer Function Block" (time-controlled execution). The block identifier must be followed immediately by a colon (:). If the colon is missing, the CPU skips this block and outputs an error message. The block identifier and i t s colon must be followed by at least one space. 3. The parameter name comes next. Parameter names are names for single parameters within a parameter block. Within a block, the first four characters o f a parameter name must be different from each other. After the parameter name, you must add at least one filler. CPU 945 Manual 4. Parameterization of CPU 945 with 084 A t least one argument is attached t o each parameter name. An argument is either a number or a STEP-5 operand that you must enter. If several arguments belong t o a parameter name, then every argument must be followed by at least one filler (even the last one). 5. Use a semicolon (;) t o identify a block end. After the semicolon, you must enter at least one filler. Leaving out the semicolon leads t o misinterpretation in the programmable controller. 6. After the semicolon, additional parameter blocks can follow. (Use steps 2 through 5 t o create additional parameter blocks.) 7. After the end o f the last parameter block, you must enter the end ID "END". This identifies the end of DBI. If you forget t o enter an end ID, this leads t o errors in the programmable controller. Points 1 through 7 present the minimal requirements for setting the parameters. Beyond that, there are additional rules that make it easier for you t o assign parameters. For example: you have the ability t o add comments you can expand the mnemonics used as parameter names in plain text. Comments can be added anywhere a filler is allowed. The comment symbol is the pound (#) sign. The comment symbol must be placed at the beginning and at the end o f your comment. The text between t w o comment symbols may not contain an additional #. Example: #Comment# . A t least one filler must follow the # sign. In order t o make it easier t o read parameter names, you can add as many characters as you wish if you add an underscore () after the abbreviated parameter name. Example: SF becomes SF-SENDMAILBOX . At the end o f the input, you must add at least one filler. There is a rule o f thumb that will help you t o check DBI. You should include at least one filler in the following instances: afterthe start ID beforeandafterthe block ID, parameter name, argument, and semicolon 11.5 How to Recognize and Correct Parameter Errors Should an error occur while assigning parameters and the programmable controller does not go t o the RUN mode, you have t w o possibilities for recognizing errors: by using a parameter error code by using the analysis function "ISTACK" Both possibilities are described below. Scanning the Parameter Error Code If you have entered a start address f o r t h e parameter error code in parameter block "ERT:" o f DBI, then you can retrieve the cause o f the error, and the error location information at this address. EWA 4NEB 81 1 61 50-O2d CPU 945 Manual Parameterization o f CPU 945 w i t h DB 1 The entire error code occupies 10 data words or 20 flag bytes. In the following examples and tables, we assume that the error code is stored in a data block starting w i t h data word 0.The error code occupies DW 0 through DW 9. In the "Flag" operand area, this corresponds t o FW 0 through FW 18. Example: You entered the start address DB3 DW 0 in parameter block "ERT:". The parameters set in DB1 have already been transferred t o the programmable controller. Then you continue t o set parameters in DB1. While attempting t o transfer the changed DBI parameters t o the programmable controller, you find out that the programmable controller remains in the STOP mode. You suspect that the reason the programmable controller remains in the STOP mode is that there is a parameter error. To find the error, display DB3 on the programmer. The entire contents of DB3 appear on the screen. DW 0 through DW 9 contain the code for the parameter error. In the following figure, you see how your screen could look. The error code containing the cause or location of the error is listed in Tables 11.land 11.2. Screen display with parameter error codes ....- . .. - ....Cause o f error :. :Locationf: error Figure 1 l . 1 Parameter Error Code CPU 945 Manual Parameterization of CPU 945 with DBI Table 11.1 DBI Parameter Error Code: Cause of Error - Left Bvte in Data Word I 00 No error 01 End identifier (END) missing 02 Unterminated comment before END or semicolon missing before END or END identifier missing 03 Block identifier syntax error or identifier unknown 04 Parameter syntax error 05 Argument syntax error or overrange 06 Overrange in an argument 10 DB does not exist 11 Insufficient space (DSBIDXIMBISY) 12 Error in specifying weekday 71 73 75 I Error in the date I Error in time format I Error in hour format I Header or footer of ASCll driver too long 1 Control character o f ASCII driver faulty Parameter DB does not exist (computer link and ASCII driver) MEIML only alternatively possible (ASCII driver) Parameterization of CPU 945 w i t h DB 1 CPU 945 Manual Table 11.2 DBI Parameter Error Code: Error Location - Right Byte in Data Word I I SL1: SINEC L1 03 05 I Deactivation o f ASCll driver or computer link 3964driver CLP: Clock parameters 06 I I TF5: Timer function block 09 I I 13 I ERT: Error return I 99 I Error cannot be attributed t o a block F0 I I ASC: ASCll driver (2nd interface) 14 I I I SDP: System characteristics I RKT: Computer link (2nd interface) 11 I I Error cannot be attributed t o a block FF I Locating Parameter Errors in the ISTACK If the PLC detects a parameter error in DB1 during restart, the PLC remains in the STOP state and stores the asolute (error) address as well as the relative (error) address in the ISTACK. The STEP address counter (SAC) in the ISTACK then points either a t o the address that contains the wrong input or directly a in front of the address that contains the wrong input. The addresses are byte addresses. Example: You have entered D51 as follows; the shaded area represents an error. DBI T,FB~; :::::::0 ~ 1 3100 ; SDP ........ ........ WD g#$@; ................... ............ .... E R T : ERR MBI KS = KS =l KS = l ; I END'; :P I The decimal number at the beginning of each input line is the word address of the first userprogrammable character in that line. Each word consists of t w o characters (two bytes) Figure 11.2 D51 with Parameter Error EWA 4NEB 81 1 61 50-02d CPU 945 Manual Parameterization of CPU 945 with DBI The ISTACK indicates t h e following as a result o f this error: The absolute (error) address: AB1 4CH (absolute SAC) The relative (error) address: 001CH (relative SAC) To locate t h e error accurately in your DBI, you must convert t h e relative byte address given as a hexadecimal number into a decimal word address. The reason: The programmer counts the contents o f a DB decimaliy and in words. The SAC counts t h e contents o f a DB hexadecimally and i n bytes. 001CH - Hexadecimal byte address =D Decimal byte address 2 8 ~ : 2 ~ = 14D Decimal word address It follows that: The error is in w o r d address 14. In our example, address 14 (data word 14 and 15) is occupied by argument "3000". The entry "3000" is an error; reason: overrange. 11.6 Transferring the DBI Parameters to the PLC The CPU processes DBI only after manual cold restart or after automatic cold restart after power restore. You must perform a cold restart anytime you make changes t o DBI. You can perform a cold restart by switching from: POWER OFF t o POWER ON or f r o m STOPtoRUN The programmable controller accepts t h e parameters from DB1 and stores them i n t h e system data area. Note The programmable controller remains i n t h e STOP mode if a parameter assignment error is found during start-up. The red LED lights up on t h e operator panel and ISTACK displays a DBI addressing error. EWA 4NEB 811 61 50-O2d Parameterization o f CPU 945 with DB 1 CPU 945 Manual Reference Table for Initializing DB1 11.7 "0" = Master function for point-to-point link (at 2nd interface); Note: CBS and CBR are in a flag byte or in the high-order byte of the specified data word (DL)! * WD P p=ot02550 RDLY r r=Oto65535 RT YIN RC YIN RF YIN PROT YIN PIO YIN PII YIN RPIC S PPIT YIN s = o t o 255 "Watch-Dog" (scan time monitoring) can be set in milliseconds but only in steps o f 10 msec. "Run DeLaYs restart delay after POWER ON in msec. "Resident Timers" if "Y", all timers are retentive, if "Nu, only T 0 t o 63*. "Resident Counters" if "Y", all counters are retentive, if "NW,C 0 t o 63*. "Resident Flags" (if "Y", all flags1S flags are retentive, if "NW,only the first half are retentive)* "PROTection" activate software protection? (inputloutput of program no longer possible) "Process Image Output" disable output of process image? "Process Image Input" disable read in of process image? "Reduced Process Image Output Counter" counter for cycles w i t h reduced PIQ transfer "Parallel Process Image Transfer" If "NW,the sequential PI transfer is set, if "Y", the parallel PI transfer is set. Additionally, set switch f o r DefaultlOverall Reset on the control panel o f the CPU t o "RE" CPU 945 Manual Parameterization of CPU 945 with DB1 processed (time in milliseconds) None = no check EWA 4NEB 81 1 61 50-02d Parameterization o f CPU 945 w i t h DB 1 CPU 945 Manual = ODH = 1 3 ~ = OAH = 10D rinter control characters are entered as * - CR (Carriage Return) is automatically generated in the parameter DB at the end of the ASCII string (separation of lines). If HD 112, FT 112 are missing, only CR is stored (see Section 12.5) - To send the $ character, $$ must be entered. - To send the " character, $" must be entered. CPU 945 Manual Parameterization of CPU 945 with D5 1 set automatically. Position of the PARameter set "MODe number" 1 =no bsock check character 2=send with block check character m = 150,200, previously defined parameters for RKT or ASC are not transferred. Parameterization o f CPU 945 w i t h DB 1 CPU 945 Manual z=O t o 4094 Set clock time, date Weekday = Su t o Sa wd dd.mm.yy hh =lto12 24 hour mode "Timer interrupt Set" ~d dd.mm. hh:m:ss "Operation Hour counter Set" hhhhhh :m : s s 2 hhhhhh =000000 "Operation Hour counter Enable" "STOP" Update clock in STOP state "SAVe" Save clock time after last RUN+ STOP or ERR DBXDWY or X=O,2 t o 255 DXaDWy or y =0 t o 255 a=Oto 255 MBZ or SYP lERR~rs" Position of the error code z=Oto 236 p-Oto4076 If an argument (e.g. Weekday) is not t o be transferred, enter XX! The clock will then continue with the current value. If you specify A M or PM after the clock time, the clock will operate in the relevant 12-hour mode. If you omit this argument, the clockwill operate in 24-hr mode. 2 If an argument (e.g. minute) is not t o be transferred, enter XX! The clock will then continue with the current value. There exists no parameter block for the definiton of communication flags. If you require communication flags for the use of certain CPs, please proceed as described in Section 12.2.1. Only after the definition o f the communication flags, you start t o parameterize the functions described here. EWA 4NEB 81 1 6150-02d Parameterization of CPU 945 with DB7 CPU 945 Manual 11.8 DBI Programming Example The following example o f a DB1 program shows you the complete DB1 parameterization once again. The following have been parameterized: System characteristics Data interchange over SINEC L1 Time-driven processing ASCll driver RK 3964 computer link (is not activated in the example) Integral clock Address for parameter error code 36: KC ='RDLY-run delay 1000 48: KC='RT-resident-timersn 72: KC ='RF-resident-flags n 84: KC ='PROT-software 96: KC ='PIO-inhibit n KC ='PII-inhibit n protection n 108: 132: KC ='PPIT-parallel-PA 144: KC='; 180: KC ='PGN_PG-bus number 2 204: KC ='RM_rec. mlbx. DB60DWO '; Position of the receive mailbox 216: KC ='CBS-CB-send MB61 ; Coordination byte send 228: KC ='CBR-CB-rec. ; Coordination byte receive 240: 252: 264: KC = ' ; KC='#Time-drivenproc. # KC ='TFB: 276: KC ='OBlO_interval 400 288: n MB60 ; Block end identifier ; ; Comment Block identifier for time-controlled '; processing ; Call interval OB 10 KC ='OBll-interval 300 ; 300: KC ='OB12-interval 200 ; Call interval OB 11 Call interval OB 12 312: KC='OB13-interval100 ; Call interval OB 13 324: 336: KC = ' ; KC = ' # ASCII driver # ; Block end identifier ; 348: KC='ASC: ; Comment Block identifier for ASCII driver 360: KC =ISM Send mailbox DB203DWO ' ; Position of the send mailbox 372: 384: KC = ' R M rec. mailbox DB204DWO ' ; KC ='CBS CB send ME3200 ; Position of the receive mailbox Coordination byte send 396: KC ='CBR CB Receive MB201 ; Coordination byte receive 408: 420: KC ='PAR-Parameter DB202DWO KC ='MOD Mode No. 6 ; Position of the parameter DB '; Mode number Parameterization o f CPU 945 w i t h DBT KC ='BDR_Baudrate 9600 KC ='PRTY-Parity E KC ='DF_Data format 0 KC ='WCR_Wait-after-CR 0 KC ='WLF-Wait-after-LE 0 KC ='WEE-Wait-after-FF 0 KC ='ME_End charac. 0 4 KC ='SLFLSkip-LE n KC ='LM_Left_Marqin KC -'PN_Paqe-No U KC ='HDl-Header1 KC ='"$1B$38 LISTING C KC ='$3Ct' KC ='HD2-Header2 KC =Q============" KC =TTllFooterl KC ='**************<Page>****?; KC . . . . . . . . . . . . . . . . . . . . . . . . . . . . KC = l * * * * * * * * * * * * " KC ='FT2_Footer2 KC ='mple CPU945-ASCII driver'; KC = ' interface KC = ' # RKT: KC = ' CBS MBlOl MOD 2 KC ='BDR 9600 PRTY E KC ='DF 1 P R 1 h DT 220 KC ='TIO 2000 BWT 4000 KC ='TTE 6 TTS 6 KC='; # KC = ' S 2 T : DEAC n ; CPU 945 Manual CPU 945 Manual Parameterization o f CPU 945 with BB1 RC = ' C L P : KC ='SAV_Save_time y KC ='SET-set-clock-time KC ='02 05.04.93 02:00:00 pm ' ; KC ='TIS_set_time_int. KC =l02 05.04. 03:XX:XX pm '; 1116 : KC ='000010:10:00 t 1128: KC = l . ; Block end identifier 11-40: 1152: KC ='# ; Comment Block identifier for position of error DB DB for DB1 error # . KC = ' E R T : ; 1164 : KC ='ERR_error code DB DWO ; Position of error code area 1176 : KC > Block end identifier 1188: 1200: KC ; DB1 end identifier = 'END by t h e CPU 945 .............................................. Data lnterchange over t h e S5 Backplane Bus o f t h e Programmable Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.1 Data Interchange over Interprocessor Communication Flags . . . . . 12.2.2 Data Interchange over t h e I10 Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.3 Data Interchange over Data Handling Blocks FB244 t o FB249 . . . . . 12- 1 12.2 12121212- 5 5 12 12 12.3 SlNEC L1 Local Area Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12- 40 12.3.1 Connection o f t h e 55-11 5U PLCto t h e L1 Bus Cable . . . . . . . . . . . . . . 12- 40 12.3.2 Coordinating Data lnterchange by Connecting t h e CPU 945 t o t h e SINEC L1 Bus via One o f Its Serial Interfaces . . . . . . 12- 41 12.3.3 Assigning Parameters t o t h e 55-1 15U f o r Data Interchange via SINECLI .................................................... 12- 45 12.4 12.4.1 12.4.2 12.5 12.5.1 12.5.2 12.5.3 12.5.4 12.5.5 12.5.6 12.5.7 Point-To-Point Connection w i t h SINEC L1 Protocol . . . . . . . . . . . . . . Point-To-Point Connection o f a Communications Partner . . . . . . . . Parameter Assignment and Operation o f t h e Point-To-Point Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12- 51 .......................... ASCll Driver . . . . . . . . . . . . . . . . . . .. . . Data Traffic via t h e ASCll Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coordination Bytes of t h e ASCll Driver ......................... Specifying t h e Type of Data Traffic by Means o f M o d e Numbers . . ASCII Parameter Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Assigning Parameters t o t h e ASCll Driver . . . . . . . . . . . . . . . . . . . . . . . Program Example f o r ASCll Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ASCll Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1212121212121212- 12.6 Computer Link w i t h 3964(R) Transmission Protocol . . . . . . . . . . . . . . 12.6.1 3964(R) Transmission Protocol ................................ 12.6.2 Data lnterchange over t h e S1 2 Interface w i t h 3964(R) Transmission Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6.3 Coordination Bytes o f t h e 3964(R) Driver . . . . . . . . . . . . . . . . . . . . . . . 12.6.4 Parameter Set o f t h e 3964(R) Driver ........................... 12.6.5 Assigning Parameters t o t h e 3964(R) Driver ..................... 12.6.6 Program Example f o r Transmitting Data . . . . . . . . . . . . . . . . . . . . . . . 12.7 12.7.1 12.7.2 12.7.3 12.7.4 12.7.5 12.7.5 Interface Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmer Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V.24 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TTY Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RS422-Al485-Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SINEC L1 Module ............................................ Technical Specifications o f t h e Interface Modules ............... EWA 4NEB 811 61 50-02d 12- 51 12- 51 54 55 56 58 60 63 65 74 12- 75 12- 77 1212121212- 84 86 88 91 93 12- 97 12- 98 12-103 12-108 12-1 13 12-1 17 12-120 Interfacing Capabilities of Interface 1 of the CPU 945 . . . . . . . . . . . . . . . . . . . . Assignments of SI 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interfacing Capabilities of the Second Interface of the CPU 945 . . . . . . . . . . Principle o f Data Interchange between CPU and CPs . . . . . . . . . . . . . . . . . . . . lnterprocessor Communication Flag Areas Used for Signal Exchange with a CP (Example) ............................... 12.6 Interprocessor Communication Flag Areas when Several CPs Are Used .... .. . . . . . . . . . . . ... 12.7 Format o f the Job Status Word . . . . . . . . . . . . . . . . . . . . .. 12.8 Format o f the "PAFE" Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.9 Programmable Controllers Linked via the SlNEC L1 LAN . . . . . . . . . . . . . . . . . . . . .... 12.10 Data Transport via SlNEC L1 (Example) . . . . . . . . . . . . . . . . . . . . . . . . 12.1 1 Structure of the Send and Receive Mailboxes for SINEC L1 . . . . . . . . . . . . . . . 12.12 Example o f Data Transport (ASCII driver) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.13 Connector Pin Assignments o f the Cable Connecting the CPU 9451512 t o the Printer (DR 210 or DR 21 1 ; l T Y Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . 12.14 ASCll Driver Program Structure for RESTART . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1 5 Structure of the Cyclic ASCll Driver Program . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.16 Error-Free Send Procedure (Computer Link) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1 7 Error-Free Receive Procedure (Computer Link) . . . . . . . . . . . . . . . . . . . . . . . . . 12.18 Errors During Data Transmission (Computer Link) . . . . . . . . . . . . . . . . . . . . . . 12.19 Solving an Initiation Conflict (Computer Link) . . . . . . . . . . . . . . . . . . . . . . . . . . 12.20 Data Interchange overthe S12 Interface (Computer link) . . . . . . . . . . . . . . . . 12.21 Structure of the Send Mailbox (Computer Link) ........................ 12.22 Location o f the Interface Module in the CPU 945 . . . . . . . . . . . . . . . . . . . . . . . 12.23 Programmer Module: Direction of Loop Current ....................... 12.24 Programmer Module: Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.25 Programmer Module: Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.26 Programmer Module: Standard Connecting Cable . . . . . . . . . . . . . . . . . . . . . 12.27 Programmer Module: Connecting Cable for Point-To-Point Connection . . 12.28 Pin Assignments of the V.24 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.29 V.24 Module: Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.30 V.24 Module: Jumper Settings on Delivery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.31 V.24 Module: Cable for Connecting the CPU 945 and CP 525, CP 524, CPU 945, CPU 928B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.32 V.24 module: Cable Connecting the CPU 945 and the DR 2101211 ........ 12.33 TP/ Module: Current Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.34 TP/ Module: Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.35 TTY Module: Jumper Settings on Delivery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.36 TTY Module: Cable Connecting the CPU 945 and CP 524, CP 525, CPU 945, CPU 928B .................................................. 12.37 TTY Module: Cable Connecting the CPU 945 and the DR 210121 1 . . . . . . . . 12.38 Pin Assignments o f the RS422-AI485 Interface . . . . . . . . . . . . . . . . . . . . . . . . . 12.39 RS422-AI485 Module: Pin Assignments ................................ 12.40 RS422-AI485 Module: Jumper Settings on Delivery . . . . . . . . . . . . . . . . . . . . . 12.41 RS422-AI485 Module: Cable Connecting the CPU 945 and CP 524, CPU 945, CPU 928B .................................................. 12.42 SINEC L1 Module: Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.43 SINEC L1 Module: Jumper Settings .................................... 12.44 SINEC L1 Module: Connecting Cable for Point-To-Point Connection ...... 12.1 12.2 12.3 12.4 12.5 12121212- 3 3 4 5 12- 9 12- 11 12- 27 12- 31 12- 40 12- 41 12- 42 12- 55 12- 65 12- 67 12- 67 12- 80 12- 81 12- 82 12- 83 12- 84 12- 84 12- 97 12- 99 12- 99 12-100 12-101 12-102 12-103 12-104 12-105 12-106 12-107 12-108 12-109 12-110 12-111 12-112 12-113 12-114 12-115 12-116 12-117 12-118 12-119 Communications Capabilities with the Serial Interfaces of the CPU 945 . . . Definition of lnterprocessor Communication Flags when Two CPs Are Used (Example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3 List of Parameters Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4 QTYPIZTYP Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . ... . 12.5 Ready delay times o f the CPs and IPs . . . . . . . . . . . . . . . . . . . . . .. 12.6 Basic Format of the Doubleword for the Job Status . . . . . . . . . . . . . . . . . . . . . 12.7 Description of the Error Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.8 Meanings of bits 0 t o 7 in the job status word . . . . . . . . . . . . . . . . . . . . . . . . . . 12.9 Accessing the Length Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.10 Destination and Source Number Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . 12.11 Meanings o f the Individual Bits of the "Receive" Coordination Byte (CBR) forSINECL1 ....................................................... 12.1 2 Meanings o f the lndividual B i t s o f the "Send" Coordination Byte (CBS) forSINECL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.13 SINEC L1 Parameter Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.14 Data IDs o f the SINEC L1 Parameter Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1 5 Communications Partners (Slaves) for Point-to-point Connection . . . . . . . . 12.1 6 Meanings o f the lndividual Bits o f the Coordination Byte for "Receive" (CBR) in the Case o f a Point-To-Point Connection . . . . . . . . . . 12.17 Meanings o f the Individual Bits o f the Coordination Byte for "Send" (CBS) in the Case o f a Point-To-Point Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.18 DescriptionofSystemDataWord46(ASCIIDriver) ..................... 12.19 Meanings of the Individual Bits o f the Coordination Byte for "Send" (CBS) in the Case o f the ASCII Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.20 Meanings o f the lndividual Bits o f the Coordination Byte for "Receive" (CBR) in the Case of the ASCll Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.21 Description of the Mode Numbers (ASCII Driver) . . . . . . . . . . . . . . . . . . . . . . . 12.22 ASCll Parameter Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.23 Character Frame and Order o f Bits on the Line in the Case of ASCll Transmission (Depending on Word 2 o f the ASCll Parameter Set) ........ 12.24 ParameterBlockfortheASCIIDriver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.25 Data IDs o f the Parameter Block (ASCII Driver) . . . . . . . . . . . . . . . . . . . . . . . . . 12.26 ASCIICode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.27 Meaning o f System Data Word 46 (Computer Link) . . . . . . . . . . . . . . . . . . . . . 12.28 Meanings o f the lndividual Bits o f the "Send" Coordination Byte (CBS) inaComputerLink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.29 Meanings o f the Individual Bits o f the Coordination Byte for "Receive" (CBR) in a Computer Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.30 ParameterSet(ComputerLink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.31 Character Frame and Order o f Bits on the Line in the Case o f a Computer Link (Depending on Word 2 o f the Parameter Set) . . . . . . . . . . . . . . . . . . . . . . 12.32 Meanings o f the Mode Numbers (Computer Link) ...................... 12.33 Parameter Block for Computer Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.34 Data IDs o f the Parameter Block (Computer Link) . . . . . . . . . . . . . . . . . . . . . . . 12.35 Applications of the Interface Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.36 Technical Specifications o f the Interface Modules ...................... 12.1 12.2 12- 2 12- 12 12- 13 12- 17 12- 19 12- 26 12- 27 12- 28 12- 30 12- 42 12- 43 12- 44 12- 45 12- 46 12- 51 12- 52 12- 53 12- 54 12- 57 12- 57 12- 59 12- 61 12- 62 12-63 12- 64 12-74 12- 76 12- 86 12- 87 12-89 12- 90 12- 90 12- 91 12- 92 12- 98 12-120 CPU 945 Manual Communications Capabilities Communications Capabilities This chapter informs you of the various communications capabilities o f the CPU 945, the characteristics o f the various communications capabilities, the parameterization of the CPU for communications and "initiation" of communciations, special requirements t o be observed when using t w o interfaces, and the various interface modules that can be used in connection with the CPU 945. 12.1 Overview of the Communications Capabilities Offered by the CPU 945 The CPU 945 offers various possibilities for exchanging data with other modules1communications partners. Data is exchanged in t w o different ways: via the S5 backplane bus via the CPU interfaces (S1 1 and SI 2) Additional intelligent I10 modules (CPsIlPs) can be used in the 55-11 5U programmable controller. The CPU 945 communicates with these modules over the S5 backplane bus. The CPsIlPs can be used for a wide range o f applications, such as communications via different LAN types (SINEC L1, L2, HI, etc.), visualization, signal preprocessing. Depending on the IPsICPs used, the modules communicate in one of the following manners: via interprocessor communication flags via data handling blocks (page addressingldual-port RAM) via the I10 area The serial interfaces o f the CPU 945 provide additional communications facilities (see Table 12.1). In contrast t o CPUs 941 t o 944, the CPU 945 permits the connection of various interface modules as a second serial interface. Interface modules available: Programmer interface module (1 5-pole) TTY interface module (25-pole) V.24 interface module (25-pole) RS 422-AI485 interface module (1 5-pole) SINEC L1 interface module (1 5-pole) The SINEC L1 interface module is essential for a SINEC L1 or point-to-point link with S1 2. CPU 945 Manual Communications Capabilities Table 12.1 lists the various communications capabilities permitted by the t w o serial interfaces of the CPU 945. Table 12.1 Communications Capabilities w i t h the Serial Interfaces of the CPU 945 Programmer functions Yes Yes Programmer submodule V.24 submodule TTY submodule RS 422-AI485 submodule SINEC L1 submodule Communications via SINEC L1 LAN (as slave or as a slave partner in a point-to-point link) Yes Yes SINEC L1 submodule Yes SINEC L1 submodule Point-to-point connection (SINEC L1 protocol; master) Computer link using the 3964(R) transmission protocol ASCII driver Yes Programmer submodule V.24 submodule TPI submodule RS 422-AI485 submodule SINEC L1 submodule The communications capabilities communications via SINEC L1 LAN, point-to-point link (with SINEC L1 protocol), computer link with 3964(R) transmission protocol, ASClldriver can be activated through parameterization in the DBI or the respective defaults in the system data area. Advantages o f using a second serial interface: Programmerloperator panel and Programmerloperator panel, also connected t o CPU 945, can be operated in parallel; Programmerloperator panel and SINEC L1 (slave) can be connected t o the CPU 945 in parallel; Parallel operation o f programmerloperator panel and link with another partner possible via - point-to-point link (SINEC L1 protocol), - computer link with 3964(R) transmission protocol, - ASCll driver; Low-cost links with other PLCs (SIMATIC 55) via point-to-point link, e.g. CPU 945 with 55-100U (CPU 102), no CP required; Simple connection t o SIEMENS equipment via computer link, e.g. between CPU 945 and SICOMP PC; Simple connection t o third-party devices via ASCll driver, e.g. connection o f a barcode reader t o the CPU 945. CPU 945 Manual Communications Capabilities lnterfacing capabilities of the first serial interface of the CPU 945 The following table provides you with an overview of the communications methods available for the individual communications partners at the first serial interface of the CPU 945 and the deviceslsystems that can be linked with the CPU 945 via this interface. CPU 945 S1 l First serial interface -.-v Programmer functions (see Chapters 415) SINEC L1 (see Section 12.3) * Programmers for SIMATIC S5 Operator control and monitoring for SIMATIC S5 SINEC L1 LAN CPU 945 can be connected as slave in a SINEC L1 LAN* - PG 710 t o 770,S5-DOS V6.1 and higher - OP 393 - SS-90U, S5-95U S5-100U (CPU 1021103) S5-115U (CPU 941I94219431 9441945) - CP 521 S1 - CP530 A number of third-party devices feature interfacesfor SINEC L1 thanks to the wide-spread use of SINEC L1 Figure 12.1 Interfacing Capabilities o f Interface 1 o f the CPU 945 M ~ ~ r -RxD + 5.2 V + 24V M +TxD -TxD ME, RxD + M 24V 20 mA M 20 mA 5.2V M + 1 Internal circuitry I I L +- 3 4 5 o 7 8 n J 10 11 (a4 12 13 I K/(-$i I I I I I I I I I I I I I I I I I 14 I 15 --------------------------------A I Figure 12.2 Assignments of S1 1 Communications Capabilities CPU 945 Manual Interfacing capabilities of the second serial interface of the CPU 945 The following table provides you with an overview of the communications methods available for the individual communications partners at the second serial interface of the CPU 945 and the devices1systems that can be linked with the CPU 945 via this interface. CPU 945 SI 2 Interface module Programmer functions (see Chapters 415) SlNEC L1 (see Section 12.3) p Programmers for SIMATIC S5 - PG 710 t o 770,S5-DOS V6.1 and higher Operator control and monitoring systems for SlMATlC S5 - OP393 SINECLI LAN CPU 945 can be connected as master or slave in a SINEC L1 LAN* - S5-90U, 55-95U - 55-IOOU (CPU 1021103) - 55-115U (CPU 941I94219431 9441945) - CP521 S1 - CP530 Point-to point connection (see Section 12.4) Point-to-point link CPU 945 can be master or slave* ASCll driver (see Section 12.5) Devices that can receive1 send data without using a transmission protocol - Devices capable o f using the 3964(R) transmission protocol* - SICOMPPC Printers Terminals Barcode readers Modems p 396qR) computer link (see Section 12.6) - SICOMP M Teleperm M Mobyl - CP 523 - CP 524 (with special driver) - CP 525 (with special driver) p * A number of third-party devices feature interfaces for SlNEC L1 and the 3964(R) transmission protocol thanks t o the wide-spread use o f SlNEC L1. Figure 12.3 Interfacing Capabilities of the Second lnterface of the CPU 945 CPU 945 Manual 12.2 Communications Capabilities Data lnterchange over the S5 Backplane Bus of the Programmable Controller There are (in principle) three ways of organizing data interchange between the CPU 945 and the CPsIlPs via the backplane bus of an 55-115U programmable controller. Data interchange over interprocessor communication flags Data interchange over the I10 area Data interchange over data handling blocks (page addressing) These options are described in the following sections. 12.2.1 Data lnterchange over lnterprocessor Communication Flags lnterprocessor communication flags are used for transmitting binary signals between the CPU 945 and some types o f communications processors (e. g. CP 526). lnterprocessor communication flags are flag bytes that are read cyclically (input flags) or output (output flags) by the CPU. Unlike other flags, however, interprocessor communication flags are stored in a special memory area on one or more CPs. This memory area comprises 256 bytes between the addresses OF200, and OF2FFH. CPU CP 1 lnterprocessor Interprocessor communication flag area communication flag area CP 2 Interprocessor communication flag area indicates the interprocessor communication flag areas used Figure 12.4 Principle of Data lnterchange between CPU and CPs CPU 945 Manual Communications Capabilities The transfer of interprocessor communication flags is similar t o the transfer of inputs and outputs t o and from the process images. The procedure is as follows: The interprocessor communication input flags are read in and stored in the appropriate flag bytes prior t o cyclic program execution. interprocessor communication output flags are read in the relevant flag bytes and transferred t o the appropriate CPs at the end o f program execution. lnterprocessor communication output flags can be treated like normal flags. Interprocessor communication input flags should be scanned only, since the setting or resetting o f bits can be canceled during the next data transfer. The control program must identify interprocessor communication flags byte by byte in data block DBI as input flags or output flags. Definition of the lnterprocessor Communication Flags in DB1 You can program DBI in the following t w o ways: with the help o f a screen form on a programmer through direct input of data words Note If you are using interprocessor communication flags and you use DBI as parameter DB for internal functions (see Chapter 1l), then proceed as follows: ) ) ) ) Overall reset Transfer integrated DBI from the CPU 945 t o the programmer Insert interprocessor communication flag agreements (as described below) before the DBI parameters awaiting interpretation (see Chapter l I) Modify and expand the other DBI parameters (see Chapter l 1) Transfer the modified and expanded DBI to the PLC The first three data words form the header ID. Always program them as follows: After specifying an ID for the operand area, enter the numbers o f all flag bytes used. Conclude the interprocessor communication flag list with an end ID. The IDs are asfollows: KH = CEOO KH = CA00 KH = EEEE for for for interprocessor communication input flags interprocessor communication output flags end You can use a total o f 256 bytes as interprocessor communication flags. Number the bytes in relation t o the start address o f the interprocessor communication flag area (FY 0 t o FY 255). The end identifier can be followed by the DBI section in which internal functions are parameterized (see Chapter 11). CPU 945 Manual Example: Communications Capabilities Define flags bytes FY10, FY20, and FY30 as interprocessor communication input flags. Define flag bytes FYI 1 and FY22 as interprocessor communication output flags. Assign DBI as follows: DW 0 1 2 : : : KH KH KH = 4D41 = 534B = 3031 DW 3 4 : : : KH KF KF KF = CEOO = +l0 = +20 = +30 : 5 6 Header !D (KS = MASK 01) Interprocessor communication input flags DW 7 8 9 : : KH KF KF = CA00 = +l1 = +22 Interprocessor communication output flags DW 10 : KH = EEEE End ID The following points apply t o the assignment o f DBI : The interprocessor communication flag definitions must always start from DW 0 in DBI, i. e. they must precede the parameter data t o be interpreted. You can enter interprocessor communication flag areas in any order. You can enter the byte numbers for an area in any order. The CPU accepts the entries in DB1 only during Manual or Automatic Restart. You must therefore execute a program restart each time you modify DBI. Signal Exchange w i t h a CP Set jumpers on the CP t o enable the area as required by the interprocessor communication flag bytes. The jumpers divide the area between bytes 0 (OF2001 and 255 (OF2FF) into eight blocks of 32 bytes each. Normally the entire interprocessor communication flag area is enabled. Setting is necessary only when you use several CPs with interprocessor communication flags. Specify the desired interprocessor communication flags in DBI. The bytes must be in the set area. You can choose any bytes from this area. However, use only as many bytes as necessary t o keep the transfer time as short as possible. EWA 4NEB S1 1 61 50-02d Communications Capabilities Example: CPU 945 Manual 20 interprocessor communication flag bytes are needed for a signal exchange: 14 bytes t o transfer information t o the CP 6 bytes t o fetch information from the CP The jumper setting on the CP enables the area between byte 128 (OF280) and byte 159 (OF29F). The interprocessor communication flags are defined in DBI as follows: Outputs: Inputs: FY 128 ... 141 FY 142 ... 147 The words in the DB are assigned as follows: DW 0 1 2 : : : KH KH KH = 4D41 = 534B DW 3 4 5 6 : : : : KH KF KF KF = CEOO = +l42 = +l43 = 144 DW9 : KF = +l47 DW 18 11 12 : : : KH KF KF = CA00 = +l28 = 129 DW 25 : KH = EEEE Header ID = 3031 + + lnterprocessor communication input flags lnterprocessor communication output flags End ID CPU 945 Manual CPU lnterprocessor communication flag area Communications Capabilities CP Interprocessor communication flag area 1 Indicates the interprocessor communication flag areas used Figure 12.5 lnterprocessor Communication Flag Areas Used for Signal Exchange with a CP (Example) Special Points to Observe when Using the CP 525 and CP 526 in RESTART Mode Note If the CP 525 and CP 526 are used in the 55-115U, the interprocessor communication flag area enabled on the CPs should be reset on restart in connection with the following CP functions: CP 525 (6ES5 525-3UA11): Component: Event printer if group disable bits are used Component: Operator-process communication and visualization with the 3975 display unit if b i t set and reset commands are used Group disable bits should always be located in the interprogeneral: cessor communication flag area enabled per jumper setting. CP 526 (6ES5 526-~Lxxx): If bit set and reset commands are used Basic board: EWA 4NEB 81 1 61 50-02d Communications Capabilities CPU 945 Manual Before synchronizing the CPs, an FB should be called in OB21122. This FB should be programmed as shown in the following example: Example: Function block FBxxx (e.g. F B I 1) for resetting the interprocessor communication flag area on a CP. The communication flag areas enabled by jumpers on the CP can be reset w i t h the following block. This FB must be specified with i t s starting flag byte (V-FY) and end flag byte (B-FY) for each contiguous communication flag area. If a flag byte that does not define an area boundary is specified here, the entire area is still reset. V-FY B-FY FY 35 FY 165 : : (fro m) (to) This resets the communication flag area from flag byte FY 32 t o flag FY 191. This area must naturally have been enabled on the CP. DECL : V-FY DECL : B-FY I/Q/D/B/T/C: I BI/BY/W/D: BY : LW =B-FY L o a d relative e n d a d d r e s s : L KH OOEO R e f e r t o 3 2 - b y t e area : AW : ADD DH 0 0 0 0 F 2 1 C A d d t o s t a r t i n g address : T FW 2 5 2 + 2 8 f o r t h e I P C area and buffer result : LW =V-FY Relative end address : L KHOOEO R e f e r t o 3 2 - b y t e area : AW : ADD DH 0 0 0 0 F 2 0 0 Add t o s t a r t i n g a d d r e s s : JU =M002 o f I P C area Loop f o r d e l e t i n g the JPC f l a q M001: TAK : ADD KF + 4 L KB 0 M002 : : TAK : TDI A2 : L FW 2 5 2 : <D : JC : BE =M001 EWA 4NEB 81 1 61 50-02d CPU 945 Manual Communications Capabilities Signal Exchange w i t h Several CPs If one CPU addresses several CPs, one or more interprocessor communication flag areas must be enabled on each CP. When setting the jumpers on the CPs, please note the following points: The areas on the individual CPs must not overlap (to prevent duplicate address assignment). The areas on the individual CPs do not have t o be assigned consecutively. CPU interprocessor Communication Flag Area CP 1 lnterprocessor Communication Frag Area CP 2 l nterprocessor Communication Flag Area indicates the interprocessor communication flag areas used Figure 12.6 Interprocessor Communication Flag Areas when Several CPs Are Used EWA 4NEB 81 1 61 50-02d Communications Capabilities CPU 945 Manual Define the interprocessor communication flag bytes in data block DB1 as described above. Example: Use one CPU t o address t w o CPs. Table12.2 shows the flag bytes needed and possible numbering. Table 12.2 Definition of Interprocessor Communication Flags when Two CPs Are Used (Example) 12.2.2 Data lnterchange over the I/O Area Low-range signal-preprocessing IPs or CPs generally communicate via the standard 110 area for digital and analog 110: OF000, t o OFOFF, (also via the Q area). In these cases, the basic load and transfer operations, such as L PY, L PW, T PY, T PW are used for data interchange. 12.2.3 Data lnterchange over Data Handling Blocks F6244 to FB249 Complex functions are handled by those modules of the SlMATlC S5 system that can be programmed and parameterized (CPs and IPs). These modules incorporate a dual-port RAM (page) o f either 1 X 2K or 2 X 2K bytes for data interchange between CPU and CPIIP. In the CPU 945, this buffer area is assigned an address range (0000 F400, t o 0000 F7FFHor 0000 F400, t o 0000 FBFF,) which can be accessed via a page. Since all CPsIlPs use the same address range (0000 F400, t o 0000 FBFF,) for page addressing, the address range must be allocated t o a specific CPIIP with the aid of a particular page number (= interface number): The CPIIP is assigned an "address" by setting the interface number (0 t o 255). In the PLC program, the CPIIP is addressed via programmable "data handling blocks". The data handling blocks are used t o enter the desired interface number in the page select register (address: 0000 FEFF,) and then address the required CPIIP. They handle communication between the CPU and the CPIIP autonomously. Blocks FB244 t o FB249 permit the use o f communications processors and intelligent I10 modules. These so-called data handling blocks coordinate data interchange between the CPU and the page area o f these modules. Data handling blocks require neither program memory space nor flag, timer or counter areas. CPU 945 Manual Communications Capabilities Parameters The data handling blocks use the parameters listed in Table 92.3. The individual parameters are explained on the following pages. Table 12.3 List of Parameters Used Job number Job status word (double word) QTYPIZTYPl : Type o f data source or destination Data block number ' QLAEIZLAEl ' QANFIZANFl Relative start address for type Number of sourceldestination Parameter assignment error byte BLGR Frame size 1 If these parameters are not required for a call (e. g. ALL function), they can be skipped by means o f "CR" when initializing t h e block 2 Only direct parameterization possible Parameter Description The formal operands that you must supply when using data handling blocks are explained below. SSNR - Interface Number The SSNR parameter specifies the logical number of the interface (page) t o which a particular job refers. y=O t o 255 y=O t o 255 Direct parameterizing Interface number (page address) Indirect parameterization Data word number. The SSNR, A-NR, and ANZW parameters are stored beginning with the next data word in the current DB (or DX). Communications Capabilities CPU 945 Manual A-NR - Job Number The jobs for an interface are characterized by this number. Parameterx is ignored y= l to 223 "y" represents the job number. ALL function 1 Direct function Number of the job t o be executed. 2 1 The "ALL" function is not permitted forthe FETCH block. 2 Refer t o the SINEC L1 Local Area Network manual for an explanation of the individual job numbers. ANZW - Job Status Word Use this parameter t o specify the address of a double word ( D W n/DW n+ 1 or FW n and FW n + 2) that indicates the processing status of a particular job. Address o f the job status word for direct parameterization Permissible areas: FW 0 t o 252 DW 0 t o 255 * DW refers t o t h e current data block. CPU 945 Manual Commernications Capabilities QTYPIZTYP - Type o f Data Source o r Data Destination Assign these parameters ASCII characters t h a t specify t h e type o f data source (for SEND) o r d a t a destination (for RECEIVE or FETCH). KS= DB, DX, QB, IB, FY, TB, CB, AS, RS, PB (see Table 12.4) Direct parameterization: The specification o f t h e d a t a source (or d a t a destination) is specified directly i n t h e QTYPIZTYP, DBN R, QANFIZANF, QLAE, ZLAE parameters. N o parameter assignment: Data source (or data destination) specifications are located i n t h e j o b o n t h e CP. KS = RW, XX Indirect parameterization: Specifications f o r d a t a source (or d a t a destination) are located i n a data area specified b y t h e DBNR a n d QANFIZANF parameters. DBNR - Data Block Number If DB, DX, RW o r XX w e r e assigned t o t h e parameters QTYPIZTYP, t h e DBNR parameter must specify t h e number o f t h e required data block. y=O t o 255 EWA 4NEB 81 1 61 50-O2d Number o f t h e data block containing t h e CPU 945 Manual Communications Capabilities QANFIZANF - Start Address of the Source or Destination Data Block When parameterization is indirect (QTYP/ZTYP=RW or XX), specify the number of the DW at which the parameter block begins. When parameterization is direct, QANFIZANF refers t o the specified area. QLAEIZLAE - Length o f the Source or Destination Data Frame When parameterization is direct, the source or destination type specification is understood t o be the number of either bytes or words. Permissible range (see Table 12.4) The "joker length" - 1 means the following: for RECEIVE: As much data as the transmitter sends or as much as area limitations permit. for SEND: Data is transmitted until a particular area boundary is reached. l I I I EWA 4NEB 81 1 61 50-02d CPU 945 Manual Communications Capabilities Summary: Table 12.4 QTYPIZTYP Parameters parameters are stored in the data parameters begin DBNR and QANF). without data parameters begin data from/to the sourceldestination be read or written b e read or written be read or written 1) Assigning RWto ZTYP is not permitted for the RECEIVE block. EWA 4NEB 81 1 61 50-02d CPU 945 Manual Communications Capabilities Table 12.4 QTYPIZTYP Parameters (Continued) I Sourceldestination data fromlto the process input image - Sourceldestination data fromfto I10 modules. Source data from input modules. Destination data t o output modules Sourceldestination data fromlto counter locations Sourceldestination data fromlto timer locations I , -,-~~- L lrrerevanr ( Irrelevant Irrelevant Irrelevant Input byte number beginning with which the data is t o be read or written 0 t o 127 64K area address (page address) Length of the sourceldestination data in bytes Number of the counter location beginning with which the data is t o be read or written Length of the source or destination data in words (counter Number of the timer location beginning with which the data is t o be read or written Length of the source or destination data in words (timer location = 1 word) 0 t o 256 Offset address in the 64K area beginning with which the data is t o be read or written. (Must be specified in KF, interpreted as KH) 0to Sourceldestination data fromlto system data area or extended system data area Irrelevant Permissibleranges: 1: OOOOOHtoOFFFFH (S5 bus) 2: 2000OHto 205FFH (C, T, F, PII, PIQ) Length of the sourceldestination data block in words + 32767 Number of the system data word beginning with which the data is t o be read or written. Oto 2551BS 256to 511ABT * Oto 128 Peripheral byte number beginning with which the data is t o be read or written 0 t o 127 digital 110s 128 t o 255 analog 110s 0 t o 255 Sourceldestination data fromlto memory locations absolute-addressed I Length of the sourceldestination data in bytes Length of the sourceldestination data in words 0to512 3: 80000, to DFFFFH (program memory) 4: EOOOOHto E13FFH (S flags, BS and BT ranges) EWA 4NEB 81 1 61 50-02d CPU 945 Manual Communications Capabilities BLGR - Frame Size The BLGR parameter specifies t h e maximum size o f t h e data frame t h a t can be exchanged between a PLC and a CP during one pass o f t h e data handling block (applies only t o SYNCHRON). SENDIRECEIVE: t = 54ps+4Xready delay time ** Execution time including data transfer t = 1 0 7 G p t 3 0 X r e a d y d e l a y t i m e ** nX(2.5ps+ ready delay time **) + t= 128-+ 20Xready delay time ** + nX(5ps+ ready delay time **) with n being the minimum value for message frame length or frame size * ** The block uses the default parameter. (On the 55-1 15U, the frame size is set t o 64 bytes). SeeTable 12.5. Table 12.5 Readv delav times of the CPs and IPs Communications Capabilities - CPU 945 Manual PAFE - Parameter Assignment Error Byte For PAFE, specify a byte that is set i f the block detects a parameter assignment error. The following can be parameter assignment errors: No such interface. The QTYPIZTYP, QANFIZANF or QLAEIZLAE parameters were assigned incorrectly. Direct and Indirect Initialization of SSNR, ANR, ANZW or BLGR The high-order byte of the SSNR parameter is the selection criterion for direct or indirect parameterization: High-order byte o f SSNR=O means direct parameterization SSNR, A-NR, ANZW or BLGR are specified directly in the block. High-order byte of SSNR#O means indirect parameterization SSNR, A-NR and ANZWIBLGR are stored in the current data block (DB or DX), beginning with the data word specified in the loworder byte of the SSNR parameter. SSNR and A-NR have the same data format (KY) in both cases. Representation formats are different for the job status word. While the address of the job status word is specified directly when parameterization is direct (e.g. FW loo), a double word is used for indirect parameterization. The first data word specifies the data area in the KS data format (ASCII code). Meanings: FW DB DX Job status word is located in the flag area Job status word is located in the DB data block Job status word is located in the DX data block The second data word includes the ANZW address in the KY data format and, if the job status word is located in a DBIDX, additionally the block number (in the first byte o f the KY format). EWA 4NEB 81 1 61 50-02d CPU 945 Manual Communications Capabilities Examples: Direct parameter assignment of SSNR, A-NR and ANZW Jobstatuswordasflag :JU FB 2 4 5 NAME :RECEIVE SSNR : KY 0 , 3 I n t e r f a c e is a s s i g n e d number 3 A-NR : KY 0 , 1 0 0 The j o b number is 1 0 0 ANZW : FW 2 4 0 F l a g w o r d s 2 4 0 a n d 2 4 2 are u s e d a s j o b s t a t u s words. Job status word in a data block : J U FB 2 4 7 NAME :CONTROL SSNR : K Y 0,3 T h e i n t e r f a c e n u m b e r is 3 A-NR : KY 0 , 1 0 0 The j o b number is 100 ANZW : DW 4 0 D a t a w o r d s 4 0 a n d 4 1 i n DB47 a r e u s e d a s j o b EWA 4NEB 81 1 61 50-02d CPU 945 Manual Communications Capabilities Indirect Initialization of SSNR, A-NR and ANZW Job status word as flag NAME :C DB 4 4 :JU FB 2 4 4 Open DB44 :SEND KY 2 5 5 , 1 SSNR : ID for indirect parameterization The data area for pararneterization begins with DW 1 . KY DW2: KY=0,31 The job number is 3 1 . DW 3: KS = FW The job status word is in the flag area. DW 4 : KY = 0,200 T h e job status word is represented in flag words = 0,1 The interface number is 1 DW 1 : F W 2 0 0 and FW 2 0 2 . Job status word in a data block NAME :C DB 2 4 :JU FB 2 4 4 Open DB24 :S END SSNR : KY 2 5 5 , l I D for indirect pararneterization The data area for parameterization begins with DW 1. A-NR: KY0,O Irrelevant ANZW FW 0 Irrelevant : DB24 DW1: KY=O,l The interface number is 1 . DW2: KY=0,31 The job number is 3 1 . DW 3 : KS = DB The job status word is in a data block. DW 4 : KY = 222,lO Address of the ANZW (DW 1 0 and DW 11 in D B 2 2 2 ) DB2 2 2 DW 1 0 DW 11 Job status word CPU 945 Manual Communications Capabilities Indirect Initialization of SSNR and BLGR (SYNCHRON) NAME :C DB 4 9 :JU FB 2 4 9 Open DB49 : SYNCHRON SSNR : KY 2 5 5 , 1 0 0 ID for indirect parameterization The data area for parameterization begins with DW 1 0 0 . BI,GR: Irrelevant KY0,O DB4 9 DW 1 0 0 : KY = 0,10 The interface number is 1 0 . DW 1 0 1 : KY = 0,6 The block size is set at 5 1 2 bytes. Direct and indirect parameterization of QTYPIZTYP, DBNR, QANFIZANF and QLAEIZLAE When direct parameterization is selected, the data handling block processes the source and destination parameters (including QTYPIZTYP, DBNR; QANFIZANF and QLAEIZLAE) stated in the block call directly. In the case o f indirect parameterization, the block parameters point at a parameter area in a data block which contains the actual source or destination parameters. For indirect parameterization of the source and destination parameters, "XX or "RW" (KS data format) is t o be used for the type of data source or data destination. For DBNR, the number of the DB or DX data block must be specified in the low-order byte. If the high-order byte is equal t o 0, the data handling block expects t o find the parameter l i s t in a DB data block; otherwise (highorder byte not equal t o 0), in a DX data block. The relative start address for a type (QANFIZANF) contains the word number where the parameter list starts. QLAEIZLAE are irrelevant. For operations w i t h type of data source "AS" (=absolute addressing of memory locations), the DBNR parameter is used t o define the required 64K memory area via the four most significant add ress bits. In this case, the QANFIZANF parameter describes the least significant (1 6-bit) portion o f the 20-bit address. CPU 945 Manual Communications Capabilities When XX is used for indirect parameterization, enter the following data in the data block specified by the formal operand "DBNR" : 0,Ot o 0,255* 0 t o 2047* +3 * KF 1 t o 2848* (-1 =joker length) estlnatlon type destination area QANFIZANF Length o f the source or destination area Only if "DBIDX" was previously assigned (otherwise according t o type of data, see Table 12.4) For indirect parameterization with RW, the data in the block with the "DBNR" number must contain the following information: 0,Ot o 0,255* 0 t o 2047* Destination type specification 0,O t o 0,255* 0,O t o 2047* * Only if "DBIDX" was previously assigned (otherwise according t o type of data, see Table 12.4) CPU 945 Manual Communications Capabilities Examples: SSNR: KY 0,21 A-NR: KY 0,33 ANZW: FW QTYP: DBNR: KS QANF: K!? 100 XX 0,25 11 KY Indirect parameterization Parameters are in DB 25 from DW 11 onwards Irrelevant DB 25 DW 11: KS DB Parameter QTYP = DW12: KY 0,17 Parameter DBNR = DB 17 DW 13: KF + 3 Parameter QANF = 3 DW 14: KF + 5 EWA 4NEB 81 1 61 50-02d (QDB= DB17 from DW3) CPU 945 Manual Communications Capabilities Absolute addressing, AS Absolute address (hexadecimal) - 64K area address - Least significant part of address (hexadecimal): or as f ixed-point number: E 0200 E ( a s decimal number: 14) 0200 512 SSNR: KY A-NR: KY 0.21 0,33 ANZW: FW 100 QTYP: KS AS DBNR: KY 0,14 6 4 K area: 1 4 QANF: KF +512 Least significant part of address 512 2 200H QLAE: KF +200 PAFE: FY 13 Operation with AS Format and Meaning of the Job Status Word The job status word is used t o store information on the status of jobs. Specify the address of the job status word when assigning parameters. Starting at this address, information can be read out and processed further. Assign parameters t o the ANZW such that a separate job status word is addressed for each job defined. The job status word is part o f a double word that is addressed by the ANZW parameter. Table 12.6 Basic Format of the Double Word for the Job Status n+l Length word EWA 4NEB 81 1 61 50-02d CPU 945 Manual Communications Capabilities Job Status Word The job status word is divided into four parts. Figure 12.7 explains the individual bits. ; S ! 1 1 ; I 1 I ; Y I 1 S I 1 1 I I f l 1 I l 1 1 I l I l 1 I l 1 1 I l 1 I I ' I I I : ' I ! ; I I , I job i n progress I Job terminated (without error) Jobterminated (with error) I I Data transferldata receive i n progress 1 ; I I I bata transfer completed I Data receive completed I I Data transferldata receive disabled Figure 12.7 Format of the l o b Status Word Description of the Error Bits: Error bits in the job status word are valid only if the "Job terminated with error" bit (bit 3) is set. Table 12.7 lists the possible errors. Table 12.7 Description of the Error Bits No error If the "Job terminated w i t h error" bit is set nonetheless, this means that the CP has set up the job again after a Cold Restart or a RESET. PLC error, error code the same as in PAFE 6toF EWA 4NEB 81 1 61 50-02d CP error CP-specific errors. Use the appropriate CP manual t o determine the cause o f the error. I Communications Capabilities CPU 945 Manual Description o f t h e Status and Data Management Bits The status bits and t h e data management bits can be setlreset and evaluated both by t h e user and via data handling blocks. The table below shows t h e situations i n which these bits are set or reset. Table 12.8 Meanings o f bits 0 t o 7 in the job status w o r d w i t h t h e CP is initiated). (Scan t o see i f there is a frame). 1 SENDIFETCH job running DHB (as soon as t h e CP receives a job request) DHB (when t h e CP serviced t h e job request) SENDIFETCH block (A new job is sent only after t h e old job has been processed). User (Scan t o see if a new job is t o be initiated). 2 Job complet e d (without error) DHB (if t h e job was completed w i t h o u t error) DHB ( i f t h e job is reinitiated) User (Scan t o see if t h e job was completed w i t h o u t error). User (Scan t o see if t h e job was completed w i t h o u t error). 3 Job complet e d (with error) DHB DHB (if t h e job termi- (if t h e job is nated w i t h error). (The cause o f t h e error is stored i n the high-order byte o f t h e j o b status word). reinitiated) CPU 945 Manual Communications Capabilities Table 12.8 Meanings of bits 0 t o 7 i n the job status w o r d (continued) t o see if the data frame has initiation w i t h DIRECT function but exchange via ALL function 5 Data transfer completed SEND block (if data has been transferred for a job) SEND block (if data transfer has been started for a new job) User (if an evaluation was made) User (Scan t o see if the dataset for a job has already been transferred t o the CP and when a new dataset can be made available for a current job). 6 RECEIVE block (if data reception has been concluded for a job) RECEIVE block (if data transfer has been started for a new job) User (if an evaluation was made) User (Scan t o see i f the data frame of a new job has already been transferred t o the PLC and when a new data frame was transferred t o the PLC for a job currently in progress). Data reception completed 7 Data transfer/ reception blocked 1 User (Access o f t h e SEND and RECEIVE blocks t o an area is prevented at the first data frame. Jobs already started are terminated). User (The relevant data area is enabled). SEND-RECEIVE block (If the b i t is set, the blocks d o n o t execute any data traffic. Instead, they report an e r r o r t o the CP). During data transfer between the CP and PLC, you can no longer modify the data for a job. This fact is not critical fa small data packets since, in this case, data exchange can be handled in one block pass. However, large amounts of dat can be transferred in blocks only. Consequently, data exchange can stretch over several program scans, depending o the frame size specified in the SYNCHRON block. Communications Capabilities CPU 945 Manual Meaning o f the job status word for SEND ALL and RECEIVE ALL For the ALL functions, the SEND and RECEIVE blocks enter the job number for which they were active in the current pass in the low-order byte. Job number " 0 " (empty run) means that no job was processed. Length Word: In the length word, the SEND and RECEIVE data handling blocks enter the amount o f data (in bytes) already transferred for a particular job. Table 12.9 shows how the length word is acted upon. Table 12.9 Accessing the Length Word HTBISEND, RECEIVE (during data exchange) The contents are calculated from the current number of transfers plus the quantity o f (blocked) data already exchanged. HTB/SEND,RECEIVE FETCH by overwriting during the next job. User (If bit 2, 5, or 6 is set in the job status word, the current source or destination length is in the length word. If bit 3 is set, the length word contains the amount of data transferred prior t o detection o f an error). "Parameter Assignment Error" (PAFE) Byte Only a flag byte is suitable as a condition code byte. Various parameter assignment errors are reported in the PAFE byte (in the high-order tetrad). When assigning parameters, specify the address under which this information can be accessed. Figure 12.8 describes the individual bits. EWA 4NEB 81 1 61 50-O2d CPU 945 Manual Communications Capabilities 7 L Q ------ Bit No. I L-,---- 'f ! 0 1 2 3 4 5 6 7 8 9 A B C D E F 1 Q Error Noerror No error Incorrect ORG format, QTYPIZTYP illegal (PLC or CP) Area not available (no DB or illegal DB) Area too small Time-out (QVZ)/no access possible Wrong job status word No source or destination parameters for SENDIRECEIVE ALL (system error) No such interface lnterface not ready lnterface overloaded Unassigned Illegal A-NR No acknowledgement or negative acknowledgement from the interface (CP) ParameterIBLGR illegal (first byte) Unassigned unassigned Figure 12.8 Format of the "PAFE" Byte The SEND block - FB 244 The FB 244 requests that data be sent t o a module with page addressing. Adistinction is made between t w o function modes: SEND ALL In this mode, the function block is used for so-called background communications and can transfer data t o a CPIIP if requested by the same. SEND DIRECT Aspecific send request can be initiated and the required data transmitted at the same time. Communications Capabilities CPU 945 Manual Calling Function Block FB244 (Example: SEND DIRECT) NAME FB 244 :SEND SSNR : KY 0,10 A-NR KY 0 , 3 2 : - SEND SSNR ANZW : FW 1 4 QTYP : K S DB DBNR: KY0,lO QTYP QANF : K F +l DBNR QLAE: KF+33 - - PAFE - A-NR ANZW QANF QLAE Description of the SEND ALL Function For the SEND ALL function, the block requires the following parameters: SSNR A-NR ANZW PAFE - interface number job number (assign " 0 " ) jobstatusword parameter assignment error byte All other parameters are irrelevant for this job. The CP uses the communications area t o provide the following information: address o f the job status word type o f data amount o f data start address o f the data area The following bits are evaluated or setlreset in the job status word f o r t h e pertinent job: data transfer disabled data transfer completed data transfer in progress The SEND block enters the number o f bytes transferred in the data word that follows the job status word of the SEND DlRECTjob. The SEND block must be called in the control program in "ALL" mode at least once per interface if the CP can request data from a PLC on i t s own initiative, e.g., the CP 526 for display output or the CP 143 w i t h the job mode "READ PASSIVE". a CP job is initiated with SEND DIRECT, but the CP asks the PLC for the data for this job via "background communications". the amount of data t o be transmitted t o the CP with SEND DIRECT is greater than the specified frame size. EWA 4NEB 81 1 61 50-02d CPU 945 Manual Communications Capabilities Description of the SEND DIRECT Function The SEND DIRECT function works with the following parameters: SSNR A-NR ANZW PAFE QTYP DBNR QANF QLAE - - interface number job number (assign ";to") job status word parameter assignment error byte source type data block number so U rce start add ress amount of source data Normally, the SEND DIRECT function is called in the cyclic part of the control program. The block can be invoked in an interrupt program (see Section 2.8.4),but the job status word would not be updated cyclically in this case. This task must then be performed by the CONTROL block. The following t w o conditions must be met t o transfer data or t o activate a SEND job: RLO "1 " was forwarded t o the function block The CP enabled the job. (The "SENDIFETCH in progress" bit of the condition code word is "0"). If RLO "0" is forwarded (empty run), only the job status word i s updated. If "NN" is entered in the QTYP parameter, the source parameters have t o be stored in the CP. If not, the job is aborted with error. Data interchange can proceed as follows: The requested data is transferred directly t o the CP. The CP asks only for the job parameters. The amount o f data t o be transmitted is too large. The block transfers the parameters and the first data block t o the CP. Then the CP requests the remaining data or an additional data frame from the PLC via the SEND ALLfunction. For the block user, the operator interface is the same in all initiation modes. However, in the last t w o cases, the instant of data transfer is postponed by at least one program cycle. Description of the WRITE Function If "RW" i s entered in the QTYP parameter, the block transfers the indirectly specified source and destination parameters t o the CP. Then the destination parameters are sent along with the useful data (requested via the SEND ALLfunction) t o the communications partner (WRITE function). CPU 945 Manual Communications Capabilities The RECEIVE Block - FB245 - FB245 requests reception o f data f r o m a module w i t h page addressing. A distinction is made between t w o function modes: RECEIVE ALL Data can be received f o r any job. In this mode, t h e function block is used for so-called background communications and can request any data a CPIIP is prepared t o transfer t o t h e CPU. RECEIVE DIRECT Data is received f o r a specific job. Calling Function Block FB245 (Example) FB 2 4 5 NAME : R E C E I V E SSNR: KY0,lO A-NR KY 0 , 1 0 1 : ANZW : FW 2 4 ZTYP KS DB : - RECEIVE SSNR A-NR ANZW DBNR : KY 0 , 1 0 ZTYP ZANF : KF +l00 DBNR ZLAE : KF -1 PAFE : FY 23 ZANF -' ZLAE PAFE - Description o f the RECEIVE ALL Function The block needs t h e following parameters in RECEIVE ALL mode: a SSNR A-NR ANZW PAFE - interface number job number (assign " 0 " ) jobstatusword parameter assignment error byte All other parameters are irrelevant f o r this job. The CP provides t h e following information via t h e communications area: a address o f t h e job status w o r d type o f data amount o f data start address o f t h e data area The following bits are evaluated or setlreset i n t h e status w o r d f o r t h e pertinent job: 0 data transfer disabled data transfer completed data transfer i n progress The block enters t h e amount o f data transferred f o r a j o b i n t h e data w o r d t h a t follows the job status w o r d o f t h e associated RECEIVE DlRECTjob. EWA 4NEB 81 1 61 50-02d CPU 945 Manual Communications Capabilities The RECEIVE block must be called in the control program in "ALL" mode at least once per interface if the CP wants t o give data t o the PLC on i t s own initiative. the amount of data t o be received with RECEIVE DIRECT exceeds the specified frame size. the CP uses RECEIVE DIRECT only t o enable receive data, and transfers data t o the PLC via "background communications". You can call FB245 in RECEIVE ALL mode in the cyclic program (e.g., in OBI) the service routine for timed interrupts (e.g. prompter block) the service routine for process interrupts (see section 2.8.4) Description of the RECEIVE DIRECT Function The RECEIVE DIRECTfunction works with the following parameters: SSNR A-NR ANZW PAFE ZTY P DBNR ZANF ZLAE - - interface number job number (assign " S O " ) job status word parameter assignment error byte destination type data block number destination start address amount of destination data Normally, the RECEIVE DIRECT function is called in the cyclic part of the control program. This block can also be called in an interrupt program (see Section 2.8.4), but the job status word is not updated cyclically in this case. The CONTROL block must then perform this task. The RECEIVE block communicates with the CP on a handshaking basis under the following conditions only: RLO "1 " has been forwarded t o the function block. The CP has enabled the job. (The "RECEIVE ready" bit in the job status word is set). When RLO "0" is forwarded (empty run), only the job status word is updated. If "NN" is assigned t o the ZTYP parameter, the CP must provide the destination parameters. Otherwise, the job is aborted with an error. If the CP provides the destination parameters, when ZTYP is not "NN", only the parameter specifications in the block are noted. Large amounts o f data can be received in the form o f frames only. Only one data frame can be received at a time with RECEIVE DIRECT. The remaining data or additional data frames must therefore be transferred t o the PLC with RECEIVE ALL. Communications Capabilities CPU 945 Manua! The FETCH Block - FE1246 FB246 requests t h a t data can be fetched from a communications partner over a CP. The data is received via function block FB245 in RECEIVE ALL mode. You can use the FETCH block only t o fetch data for a specific job (FETCH DlRECTfunction). Calling the FETCH Block (Example) F P 246 NAME :FETCH SSNR : KY 0 , 1 0 A-NR KY 0 , 1 0 1 : ANZW: FW9 ZTYP : KS DB DBNR : KY 0 , 4 6 ZANF : KF ZLAE : KF + 2 0 PAFE : FY 1 4 + 5 - FETCH SSNR PAFE - A-NR ANZW ZTYP DBNR ZANF -, ZLAE Description of the FETCH Function All parameters must be assigned f o r the FETCH function. The destination parameters (ANZW, ZTYP, DBNR, ZANF, ZLAE) are passed t o t h e CP during handshaking. As soon as t h e requested data arrives, t h e CP provides t h e RECEIVE ALL block w i t h both parameters and data. The FETCH block itself does n o t transfer o r receive data. The FETCH job is activated under the following conditions: RLO "1 " has been forwarded t o the function block. The CP has enabled the function. (The "SENDIFETCH in progress" b i t is "0"). If RLO= 0 (empty run), only the job status word is updated. If "RW" is assigned t o t h e ZTYP parameter, the FETCH block transfers the source and destination parameters and the address o f the job status word t o the CP. FETCH can be invoked in t h e cyclic program or in an interrupt service routine (see Section 2.8.4). The FETCH or CONTROL block updates t h e job status word. EWA 4NEB 81 1 61 50-02d CPU 945 Manual Communications Capabilities The CONTROL Block - FB247 FB247 updates the job status word for a specific job or indicates which job is currently in progress. Calling FB247 (Example) FB 247 NAME :CONTROL SSNR : KY 0,10 A-NK : KY 0,101 ANZW : FW 20 PAFE : FY 22 CONTROL - SSNR A-NR ANZ,W Description of the CONTROL Function The CONTROL function requires the following parameters: SSNR A-NR ANZW PAFE - interface number number of the job t o be monitored job status word where the result is t o be stored parameter assignment error byte The CONTROL block implements different functions depending on the job number. The CP is asked which job is currently in progress. The CP writes the number of the current job in the low-order byte o f the job status word when the CONTROL block is being processed. A-NR # "0" The block executes in CONTROL DIRECT mode: The status of a specific job is interrogated. The job status word is updated. Processing o f this block does not depend on the RLO. However, FB247 should be called in the cyclic part o f the control program. CPU 945 Manual Communications Capabilities - The RESET Block FB248 FB248 resets a job executing over the specified interface. RESET can execute in t w o different modes: RESETALL If you assign "0" as the job number, all jobs for the specified interface are reset. RESET DIRECT If you assign a number "#O" as the job number, only the specified job is reset. Calling FB 248 (Example) CSFtLAD STL - I :JU F B 248 NAME :RESET SSNR KY 0,l : A-NR: KY0,O PAFE: FY111 . *** Parameter Description FB248 requires the following parameters: SSNR A-NR PAFE - - interface number number of the job that is t o be reset parameter assignment error byte RESET Function Description In both modes, jobs are reset in the following way: the job data are deleted. active jobs are aborted. FB248 executes dependent on the RLO, and can be invoked in both the cyclic program and in an interrupt service routine (see Section 2.8.4). EWA 4NEB 81 1 61 50-02d CPU 945 Manual Communications Capabilities - The SYNCHRON Block FB249 - Each time the PLC is restarted, FB249 parameterizes the interface on a module with page addressing for communication with the control program. This synchronization is essential for proper execution o f the data handling blocks. Calling FB249 (Example) FB 2 4 9 SSNR : K Y 0,l BLGR : KY 0 , 5 PAFE : F Y 100 Parameter Description FB249 requires the following parameters: SSNR BLGR PAFE - interface number framesize parameter assignment error byte SYNCHRON Function Description After you enter the desired frame size for the BLGR parameter, the CP checks this value according t o module-specific criteria and determines the final frame size. In certain cases, this means that the frame size specified in the parameter is invalid. The final frame size specifies how much data (bytes) can be transferred directly when the SEND and RECEIVE blocks are called. For larger amounts of data, continuation frames are generated and transferred with the ALL functions o f these blocks. FB249 synchronizes the PLC and the CP on each PLC restart. Consequently, FB249 should be called in RESTART blocks OB21 and OB22. Communications Capabilities 12.3 CPU 945 Manual SINEC L1 Local Area Network The SINEC L2 local area network is used for networking SlMATlC S5 programmable controllers o f the U range; it works according t o the master-slave principle. One master and up t o 30 slaves can be connected t o the SINEC L1 bus. The master is always a CP 530. I t handles all communication and monitoring tasks in conjunction with data communications via the LAN. Slaves can either be - CP 530 communications processors or - CPUs w i t h L1 slave interface (e.g. 51 1 of the CPU 945 can be directly connected; S1 2 via SINEC L1 interface module only). "Data handling blocks" which support communications with the CP 530 are integrated in the central processing units o f the 55-115U (see Section 12.2.3). 12.3.1 Connection of the SS-l 15U PLC to the L1 Bus Cable Each node, master or slave, needs a BT 777 transceiver as level converter. The BT777 can be connected t o the slave's programmer interface (CPU 945: S1 2 with SINEC L1 interface module only); in this case, the data is t o be interchanged via sendlreceive mailboxes as described in the following or t o the SINEC L1 interface of the CP 530 - either as master or slave. (In this case, proceed as described in the "SINEC L1 Local Area Network"; 6ES5 998-7LA21. Data is exchanged via data handling blocks.) Data is transferred over a 4-wire shielded cable that interconnects the various transceivers. Master CP 530 -----55-1 15 PLC SIMATIC S5 115U 150U 135U 155U BT 777 transceiver \ CPU 941 to 945 - Figure 12.9 Programmable Controllers Linked via the SlNEC L1 LAN CPU 945 Manual Communications Capabilities You can transfer data over the SINEC L1 local area network i n the following t w o ways: from one node t o another - master + slave - slave + master - slave + slave from one node t o all other nodes simultaneously (broadcasting). Besides data, you can also transmit programmer functions on t h e SINEC L1 local area network. A programmer t h a t is connected t o the master's CP 530 can address individual slaves (see SINEC L1 manual 6ES5 998-7LA21). 12.3.2 Coordinating Data Interchange by Connecting the CPU 945 to the SINEC L1 Bus via One of Its Serial Interfaces Aslave needs t h e following t o interchange data: aslavenumber(lto30) a Send mailbox (SF) a Receive mailbox (EF) a coordination byte f o r "send" a coordination byte f o r "receive" Transmitter (Source) Receiver (Destination) I I I I Receive mailbox mailbox mailbox A Figure 12.10 Data Transport via SINEC L1 (Example) EWA 4NEB 81 1 61 50-02d Communications Capabilities CPU 945 Manual Send and Receive Mailboxes The Send and Receive mailboxes contain send and receive data. They can hold u p t o 64 bytes o f information. They also contain t h e following: Length o f t h e data packet (1 t o 64 bytes) L1 address o f t h e sender (receive mailbox) - t h e receive mailbox contains the source number L1 address o f t h e receiver (send mailbox) - t h e destination number is specified i n the send mailbox. Send Mailbox Receive Mailbox Data packet length Byte l Data packet length Destination number Byte 2 Source number Byte 3 Data (max. 64 bytes) Data (max. 64 bytes) Byte 66 Figure 12. I I Structure of the Send and Receive Mailboxes for SINEC L1 The source or destination number indicates the "L1 node" w i t h which you w a n t t o communicate. Refer t o Table 12.10 f o r t h e meaning o f these numbers. Table 12.10 Destination and Source Number Assisnment Master 0 Slave 1 t o 30 I Broadcasting I Use t h e control program t o access the mailboxes. The location o f t h e mailboxes can be parameterized. You can define t h e starting addresses o f t h e mailboxes i n either o f t h e following ways: Specify a data block (DBIDX) and a data word. Specify a flag byte (FY, SY). CPU 945 Manual Communications Capabilities Coordination bytes for "Send" and "Receive" The coordination bytes form the interface t o the operating system o f the CPU 945. The control programs of the slaves use these bytes t o track and manipulate the data traffic via the LAN. The following table describes the meanings o f the individual bits of the "Receive'\oordination byte (CBR). The "Receive" coordination byte can either be a flag byte (FY, SY) or the high-order byte of a data word (DL in DBIDX). Table 12.1 1 Meanings of the Individual Bits of the 'Receive'"Coordination Byte (CBR) for SlNEC L 1 2 Yes LAN RUN 0: LAN i s in the STOP mode 1: LAN is in the RUN mode 3 Yes PG bit 0: Programmer does not request LAN access 1: Programmer requests LAN access 4 Yes Interrupt 0 : No signal 1: Data packet is sent as express transmission The control program may only read the bits. The operating system sets and resets the bits. 5 Insignificant 6 7 NO REC-PERM 0: Program can fetch data from the Receive mailbox. The operating system has no access t o the data. 1: The data in the REC mailbox may not be evaluated by the program. The operating system can receive data from the LAN via the Receive mailbox. If REC-PERM = "l ",the operating system f i l l s the Receive mailbox with data. Then the operating system resets REC-PERM t o "0". Bit is set by the control program. Bit is reset by the operating system. Communications Capabilities CPU 945 Manual The following table describes the meanings o f the individual bits of the "Send" coordination byte (CBS). The "Send" coordination byte can either be a flag byte (FY, SY) or the high-order byte of a data word (DL in DBJDX). No Error during last data transfer 0: No error 1 : Error detected -I Insignificant Yes Interrupt 0: Normal message 1: Slave wants t o send an express transmission or overwrite the old message. 1 The bit is set and reset by the operating system. The bit is set and reset by the control program. The bit is reset by the operating system. Insignificant SEND-PERM 0: Program can process the Send mailbox. Operating system has no access t o data. 1: Program is not allowed t o alter data in the Send mailbox. Send mailbox is enabled for transmission via the bus. SEND-PERM = " 1" causes the operating system t o transmit the contents o f the Send mailbox. Then the operating system resets the SEND-PERM bit t o "0". The bit is set by the control program. The bit is reset by the operating system. Note The bits in the coordination bytes can be set or reset by the operating system after any operation and irrespective o f the PLC cycle. This means that a multiple scan of a coordination byte within one program cycle can have different results (This must be taken into consideration for an edge evaluation!). 12-44 EWA 4NEB 81 1 61 50-O2d CPU 945 Manual Communications Capabilities 12.3.3 Assigning Parameters to the 55-115U for Data interchange via SINEC L1 When using SINEC Ll, t h e following must always be specified: local slave number data or flag areas assigned for t h e Send and Receive mailboxes location o f t h e coordination bytes (CBR and CBS) If necessary, you can also specify your o w n programmer number f o r programmer bus functions. The parameter assignments can be made either in DB 1 (see Chapter Il ) or in a function block which is called by one o f t h e t w o restart organization blocks (OB21 or OB22). Table 12.13 lists the parameters t h a t are stored from system data word 57 onwards in t h e system data area o f the CPU 945. Table 12.13 SINEC L1 Parameter Block order part o f t h e S flag I * ** *** I I 1 A programmer number is required if programmer functions are t o betransmitted via the SINEC L1 LAN. Note carefully that slave number = 0 in the low-order byte indicates the master function. In this case, no programmerlOP functions are possible via the S1 2 interface of the CPU! The programmer number i s retained in the case of an overall reset of the CPU via the programmer bus. Slave number = "0": master function (see Section 12.4) seeTable 12.14 Specify t h e location o f t h e coordination bytes and start addresses o f t h e Send and Receive mailboxes w i t h three bytes each. EWA 4NEB 81 1 6150-02d Communications Capabilities CPU 945 Manual Table 12.14 Data IDs o f the SlNEC L1 Parameter Block --- S flag** 5 3 ~ S S flag byte number: 0 t o 4095 Data (DB) 4 4 ~ D DB No.: 0 t o 255 Data w o r d No.: 0 t o 255 Data (DX) 5 8 ~ X DX No.: 0 t o 255 Data w o r d No.: 0 t o 255 * Specifies the start addresses of the memory areas for the Send and Receive mailboxes ** High-order part of the S flag number: OOH t o OFH; low-order part of the S flag number: OOH t o FFH Overflow - w h e n receiving If t h e length o f a data packet received exceeds t h e length o f the Receive mailbox, t h e data received is rejected and t h e error b i t (bit 0 in CBR) is set. The transmitting node receives a negative acknowledgement. - w h e n sending If more data than t h e amount o f data available i n the Send mailbox are t o be transmitted (Send mailbox t o o small), t h e send error b i t (bit 0 i n CBS) is set and t h e data is n o t transmitted. The end o f t h e receive area is marked by flag byte 255 in t h e flag area, 4095 i n t h e S flag area or the last available data w o r d (in t h e data block). EWA 4NEB 81 1 61 50-02d CPU 945 Manual Communications Capabilities Example of SlNEC L1 Parameter Assignment: Set parameters i n OB22 (OB21). FB 255 is used t o handle parameter entries. The formal operands indicate t h e type and number o f the coordination bytes (CBR, CBS) and o f the data mailboxes (RMB, SMB), e.g., TCBR is the type o f "receive" coordination byte. NAME : L1 PARAM CBR : flag area CBS : flag area SMB : d a t a block D R 2 beg. with DWI RMB : d a t a block D B 2 b e g . with DW40 I I Parameter description: SLNO: PG bus addressldata slave address (KY a, b): a) PG bus address b) Data slave number TCBRINCBR: Type o f COOR byte f o r Optionsare FY SY DW G XW RECEIVEISEND (KS): Flag byte Sflag byte Data w o r d (left) i n DB Data word (left) i n DX NCBRINCBS: Number or address o f COOR byte f o r RECEIVEISEND (KY a, b): a) FortypeFY N u m b e r o f t h e f l a g byte For type SY 5 High-order part o f t h e S flag address For type D W Number o f t h e data block (DB) For type XW Number o f t h e data block (DX) b) For type FY "0" For type SY Low-order part o f t h e S flag address For type DB 2 Number o f t h e data word (left; DB) For type DX A Number o f t h e data w o r d (left; DX) TSMBITRMB: Type o f SENDIRECEIVE MAILBOX (KS): Optionsare FY Flag byte SY A Sflagbyte DB Data w o r d (left; DB) XB Data w o r d (left; DX) I Communications Capabilities CPU 945 Manual NSMBINRMB: Number o f SENDIRECEIVE MAILBOX (KY a, b): a) Type FY A Number o f t h e f l a g byte f r o m which t h e sendlreceive mailbox starts Type SY 4 High-order p a r t o f t h e S f l a g address Type DB + Number o f t h e DB data block Type DX Number o f t h e DX data block b) Type FY "0" Type SY A Low-order p a r t o f t h e S f l a g address Number o f t h e data w o r d i n t h e DB f r o m which t h e sendlreceive Type DB mailbox starts Type DX --' Number o f t h e data w o r d i n t h e DX f r o m which t h e sendlreceive mailbox starts Example of type SY: SY 258 (=l X256+2X1) and TCBRITCBS o r TSMBlTRMB=SY +NCBRlNCBS= 1,2 CPU 945 Manual NAME DECL DECL DECL DECL DECL DECL DECL DECL DECL :L1 PARAM :SLNO I/Q/D/B/T/C: :TCBR I/Q/D/B/T/C: :NCBR I/Q/D/B/T/C: :TCBS I/Q/D/B/T/C: :NCBS I/Q/D/B/T/C: :TSMB I/Q/D/B/T/C: :NSMB I/Q/D/B/T/C: :TRMB I/Q/D/B/T/C: :NRMB I/Q/D/B/T/C: =SLNO :LW :T FW 200 CommunicationsCapabilities D D D D D D D D D KY KS KM/KH/KY/KS/KF/KT/KC/KG: KY KM/KH/KY/KS/KF/KT/KC/KG: KS KM/KH/KY/KS/KF/KT/KC/KG: KY KM/KH/KY/KS/KF/KT/KC/KG: KS KM/KH/KY/KS/KF/KT/KC/KG: KY KM/KH/KY/KS/KF/KT/KC/KG: KS KM/KH/KY/KS/KF/KT/KC/KG: KY L1-PG-bus/Ll-data bus slave No. KM/KH/KY/KS/KF/KT/KC/KG: KM/KH/KY/KS/KF/KT/KC/KG: :T =TCBR FW202 Type of coordination byte "R" (Receive) :LW :T =NCBR FW 203 Address of the CBR :LW :LW =TCBS :T FW 205 Type of coordination byte "S" ( Send ) :LW =NCBS :T FW 206 Address of the CBS :LW :T :LW :T :LW :T :LW :T Type of send mailbox =TSMB FW 208 =NSMB FW 209 =TRMB FW 211 =NRMB FW 212 Address of send mailbox Type of receive mailbox Address of receive mailbox :L DH 000204D5 :L DH 000E107F :TNB 14 Transfer from flag area to system data area :L :T :T :T :T Reset scratch flag words KBO FD 200 FD 204 FD 208 FW 212 : BE EWA 4NE8 81 1 6150-02e Communications Capabilities CPU 945 Manual Use the following example t o parameterize an 55-1 4 5U as PG bus node, i.e. without SINEC L1 parameter assignment: Example: Initializing an CPU 945 connected only as programmer bus node t o the SINEC L1 LAN. The function block for programmer address assignments (FBI) is invoked in the restart OBs (OB21 and OB22). :JU NAME : PGAD : FB 1 PG-ADR KY 1 , O Call FB 1 for programmer bus address assignments Programmer bus address of the CPU is 1 (perrn.values: 1 to 30) NAME DECL : PG -ADR :L : PGAD RS57 I/Q/D/B/T/C : D KM/KH/KY/KS/KF/KT/KC/KG Load system data word 57 :L KH OOFF Delete old PG N o . :LW =PGAD Load PG bus address RS 57 and PG bus address are ored, :T RS 57 write result of OR operation back to RS 57 : KY The low-order byte of RS 57 remains unchanged CPU 945 Manual 12.4 Communications Capabilities Point-To-Point Connection with SINEC L1 Protocol A point-to-point connection is a SINIEC L1 link between onlytwo communications partners: CPU 945 (only with SINEC L1 interface module) as master and communications partner connected as slave (see Table 12.1 5). Data, control information and data protection information can be transmitted via this link. Table 12.1 5 Communications Partners (Slaves) for Point-to-point Connection 12.4.1 Point-To-Point Connection of a Communications Partner You can establish connections in either o f the t w o following ways: via a bus w i t h transceivers (BT 777) 0r via a direct line (a direct line connection is possible only when the controllers are no further apart than 1000 m.) Use a four-wire, shielded cable with a cross-section o f at least 0.14 mm2 (26 AWG). SIMATIC cable 6ES5 707-1AA00 is recommended. The transceiver or direct line is connected t o the SINEC L1 interface module of S1 2. For the connector pin assignments o f the t w o 15-pole Cannon connectors for the direct line, refer t o Section 12.7 "Interface Modules". 12.4.2 Parameter Assignment and Operation of the Point-To-Point Connection Use the SINEC L1 parameter block t o parameterize the interface on the CPU (see Section 12.3.3). For a point-to-point connection, assign " 0 " as the slave number for the CPU 945 (master function only possible at S1 2). The communications partner is always addressed as slave 1. A point-to-point connection can be established only i f neither an ASCll driver nor any computer link is parameterized (see Sections 12.5 and 12.6). As long as interface S1 2 has been parameterized for point-to-point connection, no programmer or OP can be operated over this connector. EWA 4NEB 81 1 61 50-02d Communications Capabilities CPU 945 Manual Note Neither broadcasting nor interrupt traffic is possible over point-to-point connections. As w i t h the SINEC L1 local area network, data is exchanged via Send and Receive mailboxes t h a t the control program accesses w i t h load and transfer operations. The CPU operating system controls data transfer and stores t h e information i n t w o coordination bytes. The control program can read and evaluate b o t h bytes. The following tables explain t h e bits in t h e coordination bytes. Acoordination byte can either be a flag byte (FYISY) or t h e high-order byte in a data word (DBIDX) Table 12.16 Meanings o f the Individual Bits o f the Coordination Byte f o r "Receive" (CBR) i n the Case o f a Point-To-Point Connection 0: Noerror 0: Normal operation 1 : Communications partner failure 2 Yes Control program may only read t h e Bit may only be set and reset by t h e operating system. LAN RUN 0: SINEC L1 LAN is i n t h e STOP mode 1: SINEC L1 LAN is i n t h e RUN mode 3 4 insignificant 5 6 7 No REC-PERM 0: Program can fetch data f r o m the Receive mailbox The operating system has n o access t o t h e data. 1: Program is n o t allowed t o evaluate receive data. Operating system may transfer data from t h e bus into t h e Receive mailbox. The b i t is set by t h e control program. The b i t is reset by t h e operating system. CPU 945 Manual Table 12.17 Communications Capabilities Meanings of the Individual Bits of the Coordination Byte for "Send" (CBS) in the Case of a Point-To-Point Connection Bit is set and reset by the operating system. Insignificant L 6 7 No SEND-PERM 0: Program can process Send mailbox. Operating system has no access. 1: Operating system sends data from the Send mailbox t o the bus. Program is not allowed t o alter any send data. Bit is set by the control program. Bit is reset by the operating system. Note The bits of the coordination bytes can be set or reset by the operating system after any operation and irrespective o f the PLC cycle. This means that a multiple scan o f a coordination byte within one program cycle can have different results (This must be taken into consideration for an edge evaluation!). The location of the coordination bytes, and the Send and Receive mailboxes can be parameterized (as for SINEC L1) in a function block (see Section 12.3.3). If the amount o f data t o be transferred exceeds a certain limit, the reaction is the same as for "Overflow" in the SINEC L1 LAN. Differences between Point-to-point Connection and CP 530 In a point-to-point connection, data is written directly into the CPU's program memory. The control program can therefore access this area only between the time the data has been received and the next frame enabled. These steps must be coordinated over the control program. When using a CP 530, the data in a frame is initiallystored in a CP 530 buffer. The control program triggers data transfer t o the appropriate DBs. Only one read operation is needed for this transfer. While the control program is processing the DBs, the CP 530 can receive the next frame. EWA 4NEB 81 1 61 50-02d CPU 945 Manual Communications Capabilities 12.5 ASCll Driver The CPU 945 provides an ASCII driver for the second interface. The ASCll driver permits open communications with other communications partners, such as printers, terminals, etc. The ASCll driver operates only under the following conditions: Initialization as described in Sections 12.5.4 and 12.5.5 and activation by setting RS 46 (E 105CH)accordingly. The ASCll driver can also be parameterized and activated by means of DB 4 (see Chapter 11). Any error flags concerning CBR and CBS are entered in the low-order byte of RS 46 after activation of the ASCll driver. Note No other functions are possible at the second interface (e.g. programmer/OP, SINEC L l , point-to-point connection) when the ASCII driver is activated. Table 12.18 Description of System Data Word 46 (ASCII Driver) 00, * High-order byte ProgrammerIOP and SINEC L1 operation - ASCll driver 01, Errw C h ~ k a &Stgnds Low-order byte I OOH Default value (after overall reset) No error with regard t o CBS and CBR 01H Invalid driver number 1OH No CBS 20, No CBR 4 0 ~ * 1 No CBS and no CBR I Comm un ications Capabilities CPU 945 Manual 12.5.1 Data Traffic via the ASCll Driver Figure 12.1 2 shows h o w t h e ASCII driver functions. Program memory Operating system +(1Input buffer 024 bytes) Peripheral device +Output buffer (l 024 bytes) +- * I Figure 12-12 Example of Data Transport (ASCII driver) Data traffic is bidirectional: Send The ASCll driver processes data i n the program memory (e.g. t h e contents o f a data block) and outputs it a t t h e second interface. Receive A peripheral device sends data i n ASCll code t o t h e second interface. The ASCll driver processes t h e data and stores it in t h e program memory. The t w o memory areas in internal RAM i n which t h e send and receive data are stored are called the Send mailbox (SMB) and t h e Receive mailbox (RMB). The data can be stored either i n a data block (DBIDX) or i n t h e flag area (FYISY). You must enter t h e relevant information i n t h e parameter block (see Table 12.24) or parameterize them i n DBI (see Chapter 11). Communications Capabilities CPU 945 Manual Send and Receive mailboxes have the following properties: 1024 bytes of input buffer are available in all modes. Up t o 100 message frames can be stored. In modes where characters are interpreted when received (e.g. XON, XOFF), the ASCll driver can still receive data or message frames even if it has already sent XOFF t o the communications partner. In this case, the ASCll driver receives data until the input buffer is full, or it receives message frames until the maximum possible number of frames has been reached. Example o f "borderline case": If a received message frame is 1024 bytes song and the ASCll driver then sends XOFF, there is no way o f buffering characters received from the communications partner after sending XOFF. In mode 1, 7 or 8 (see Section 12.5.3), you must enter in the first word of the send mailbox the number o f bytes o f data t o be sent. 12.5.2 Coordination Bytes of the ASCll Driver The ASCll driver monitors data communications by means of the coordination byte for "Send" (CBS) and the coordination byte for "Receive" (CBR). The ASCll driver sets status and error flags in these bytes. Coordination bytes can either be flag bytes (FYISY) or high-order bytes in the data words (DBIDX). Tables 12.19 and 12.20 describe the meanings o f the coordination bytes. Note The bits o f the coordination bytes can be set or reset by the operating system after any operation and irrespective of the PLC cycle. This means that a multiple scan o f a coordination byte within one program cycle can have different results (This must be taken into consideration for an edge evaluation!). CPU 945 Manual Communications Capabilities Table 12.19 Meanings of the Individual Bits of the Coordination Byte for "Send" (CBS) in the Case o f t h e ASCll Driver I 0 to 6 I Hex code l Description 0 7 ~ Output buffer full ODH Parameter assignment error 1 1 ~ I I No Send mailbox 13H Frame is too long 1BH Break (in modes 6 and 7 only) 7 Reaction Data is rejected Send permitted This b i t is set by the user and reset by the ASCll driver when the send procedure is terminated, no matter i f with or without error. The send procedure is initiated by a positive-going edge at bit 7. The send data and the location of the Send mailbox must not be modified as long asthis b i t is " 1 ". Table 12.20 Meanings of the Individual Bits of the Coordination Byte for "Receive" (CBR) in the Case of the ASCll Driver I Hexcode OIH I I I Description Character delay time exceeded 0 3 ~ Parity error 07H Input buffer full OgH I Too many frames received I Reaction Data is valid until time is exceeded Data is rejected 1 Data is valid. subsequent frames are OBH Frame larger than Receive mailbox OFH No Receive mailbox 1 9 ~ Framing error lBH Break Data is rejected Receive permitted 1: The bit is set by the user and reset by the ASCll driver after transferring a message frame received from the input buffer t o the Receive mailbox or setting an error flag in the CBR. The receive data and the location o f the Receive mailbox must not be modified as long as this bit is " 1 ". 0: As long as bit 7 is "OM,the user has access t o the Receive mailbox. When the input buffer is not yet full, message frames are entered there instead o f being written into the Receive mailbox. Up t o 100 message frames can be stored in the input buffer. EWA 4NEB 811 61 50-02d Communications Capabilities CPU 945 Manual 12.5.3 Specifying the Type of Data Traffic by Means of Mode Numbers You can use mode numbers (1 t o 8 ) t o specify t h e type o f data traffic. There are t w o types o f protocol: Non-interpreting mode (mode numbers 1,2,3) No control characters (XON, XOFF) are used i n t h e send and receive modes. However, modes 2 and 3 interpret end-of-frame characters. Interpreting mode (mode numbers 4 and 8) An XONIXOFF protocol is used f o r data interchange. When t h e signal state o f t h e "receive permitted" b i t changes, t h e ASCII driver sends t h e following control characters: - XOFF f o r negative-going edge - XON f o r positive-going edge. EWA 4NEB 81 1 61 50-02d CPU 945 Manual Communications Capabilities Mode number The table below explains the mode numbers. The default refers t o word 7 in the ASCll parameter set (see Table 12.22). The mode numbers must be defined in system data word 55 (see Section 12.5.5) or parameterized in D B I (see Chapter 11). Table 12.21 DeScri~tion of the Mode Numbers (ASCII Driver) pecified in the ASCll parameter set and is then <CR> <LF> End o f text is recognized only when the character defined in the T> : delete last character <CR> <LF> Send n bytes; n must be specified in the first word of the Send mail- As in mode l;the following ASCll characters are also interpreted when received <RUB OUT> * : delete last character <XON> : continue t o send <XOFF> : abort send and wait for XON * If a received message frame of m bytes contains a RUB OUT, correspondingly less data is entered in the Receive mailbox and the character delay time responds -+ error 01 in CBR. EWA 4NEB 81 1 61 50-02d Communications Capabilities CPU 945 Manual ASCII Codes and Corresponding Hexadecimal Numbers: RUBOUT + XON + + XOFF 7FH 11, 13, CR LF FF ODH OAH OC, + + EOT ETX + + 04, 03, 12.5.4 ASCll Parameter Set The ASCll parameter set is used t o define t h e functions o f t h e ASCll driver (see Table 12.22). Depending o n t h e mode selected, t h e individual parameters are preset. The defaults in modes 6 and 7 apply t o t h e DR 21 1 printer. The meaning o f w o r d 7 i n t h e ASCll parameter set depends o n t h e mode number (see Table 12.21). The ASCll driver can also be parameterized i n DBI (see Chapter 11); i n this case, t h e ASCll parameter set is generated accordingly. (The area t o which t h e parameter set is t o be transferred must already exist.) The parameter set is read when activating t h e ASCll driver or after a mode change. Data trafficvia t h e interface must first be terminated (i.e. b i t 7 o f CBR=O and b i t 7 or CBS =O); t h e parameter set is transferred after POWER ON o f t h e PLC if t h e ASCll driver was previously activated. Note The default values are used only if t h e parameter set does n o t exist or cannot be interpreted. EWA 4NEB 81 1 61 50-02d CPU 945 Manual Communications Capabilities Table 12.22 ASCII Parameter Set 4 600 baud 4 Waiting time LF ** 0 t o OOFFHX1Oms X X X X X 0 0 X 5 Waiting time FF ** 0 t o OOFFHX10ms X X X X X 0 0 X 6 Character delay time (receive only) End-of-text characters1 N umber of characters received 1 t o FFFF,XlOms 10 10 10 10 10 X X 10 7 According t o mode number (see Table 12.21) 8 Suppress LF 011 yeslno X X X X X 0 0 X 9 Lines per page 1 t o 255 X X X X X 72 72 X 10 Leftmargin 0 t o 255 blanks X X X X X 10 10 X 11 Page number o/u toplbottom X X X X X U U X 12 Header1Footer*** Header l Header 2 Footer l Footer 2 X X X X X CR CR CR CR CR CR CR CR X X = irrelevant * ** *** See Table 12.23 for the meaning of data formats 0 t o 8 When sending The contents of each header and footer (rnax. 120 characters each) must be separated by CR. Communications Capabilities CPU 945 Manual The character delay time (word 6 of the ASCll parameter set) must conform t o the following formula: Character delay time 2 100 Baud rate Example: 1 4800-5 Baud rate= * Character delay time 1 100 4800 S =+ Word 6 in the ASCll parameter set = 2 Data Format and Character Frame Table 12.23 Character Frame and Order of Bits on the Line in the Case of ASCll Transmission (De~endinaon Word 2 of the ASCII Parameter Setl I 1 1 start bit, 7 data bits, 1 parity bit, 2 stop bits 1 1 bits 1 start bit, 8 data bits, 1 parity bit, 1 stor, bit 1 1 start bit, 8 data bits, 2 stop bits 1 1 bits Setting 1 10 bits 0 I 10 bits I 7 8 - * I 1 bits As data format 0 As data format l see Table 12.22 1 1 bits Setting 1 start bit, 7 data bits, 2 stop bits 1 start bit, 7 data bits, 1 parity bit, 1 stor, bit 1 start bit, 8 data bits, 1 stop b i t 1 start bit, 7 data bits, 1 parity bit, 2 stor, bits 1 start bit, 8 data bits, 1 parity bit, 1 stop bit CPU 945 Manual Communications Capabilities 12.5.5 Assigning Parameters to the ASCll Driver With the help o f the control program, you must define the position o f the ASCll parameter set, the send and receive mailboxes and the coordination byte in a parameter block (see Table 12.24) located in the system data area o f the CPU 945; you also specify the mode number there. The ASCll driver can also be parameterized in DBI (see Chapter 11). :I1Driver * RS 48 OE 1060 OE 1061 ASCll parameter set Data ID ASCll parameter set DBIDX or flag byte number or high-order part of Sflag add ress RS 49 OE 1062 OE 1063 ASCll parameter set Data word number or loworder part o f S flag address Send mailbox Data ID RS 50 OE 1064 OE 1065 Send mailbox DBIDX or flag byte number or high-order part o f S flag address Send mailbox Data word number or low-order part of S flag add ress RS 51 OE 1066 OE 1067 Receive mailbox Data ID Receive mailbox DBIDX or flag byte number or high-order part of S flag add ress RS 52 OE 1068 OE 1069 Receive mailbox Data word number or loworder part o f S flag address CBS Data ID RS 53 OE 106A OE 106B CBS DBIDX or flag byte number or high-order part of S flag address CBS Data word number or low-order part o f the S flag add ress RS 54 OE 106C OE 106D CB R Data ID CBR DBIDX or flag byte number or high-order part of the S flag address RS 55 OE 106E OE 106F CB R Data word number or loworder part o f the S flag address Mode number * If no valid mode number is entered in RS 55, the default value "1" is used. Communications Capabilities CPU 945 Manual The data IDs of the parameter block are described in the following table. Table 12.25 Data IDs of the Parameter Block (ASCII Driver) * Flag 4 D ~ M Flag byte number: 0 to 255 --- S flag 5 3 ~ S Sflagbytenumber:Oto4095** --- Data (DB) 4 4 ~ D DB No.: 0 to 255 Data word number: 0 to 255 Data (DX) 5 8 ~ X DX No.: 0 to 255 Data word number: 0 to 255 The start addresses of the memory areas are specified for the ASCll parameter set and the send and receive addresses. * * High-order part of S flag numbers OOH to OFH, low-order part of S flag numbers OOH t o FFH CPU 945 Manual Communications Capabilities 12.5.6 Program Example for ASCll Driver This section describes the structure of a control program for the ASCII driver. Example: The program on hand generates a log which is output t o the DR 211 printer. I t initiates an automatic printout in a two-second interval. Proceed as follows: ) Connect the DR 21 1 printer t o S12 o f the CPU 945 (programmer module) via the respective cable. CPU 945 (programmer module) 4 5-pole Cannon connector Sender Receiver DR 21 1 printer 25-pole Cannon connector 6 a2 21 7 b2 18 9 al 10 2 bl 9 1 1 Sender Receiver Figure 12.13 Connector Pin Assignments o f the Cable Connecting the CPU 945/Sl2 to the Printer (DR 210 or DR 211; 77YInterface) ) Switch on the printer and assign the relevant parameters via the menu on the printer itself. The following list contains only those printer parameter blocks (bold type) in which the defaults have t o be changed; the parameters t o be set are printed in italics: Communications Capabilities CPU 945 Manual INTERNAL SETTINGS: LlNE FEED CONTROL PAPER FEED LINE OVERFLOW CR LF INTERFACE SETTING SERIAL INTERFACE RECEIVE BUFFER DATA BITS PARITY STOP BITS BAUD RATE POWER-ON STATE ESCAPE CHARACTER VERTICAL SPACING VERTICAL SPACING USER-SPECIFIC SETTINGS PAPER FEED CR LF CR +LF LF + + CR 17 KB 7 BITS EVEN 2 STOP BITS 9600 ON LINE ESC LANGUAGE MENU LANGUAGE GERMAN PRINT DENSITY CHARACTER PITCH SPACED PRINT 10 CPI NO CHARACTER SET COUNTRY 0 (for ASCII) VERTICAL LINE SPACING 6 LP1 PAPER FORMAT FORM LENGTH (INCH) LINE LENGTH (1 I 10 INCH) 12 136 1/72 INCH b Switch t h e printer t o on-line m o d e (you are guided b y t h e printer menu). b Switch o n t h e CPU 945 a n d initiate a n overall reset o f t h e PLC (CPU mode: STOP). b Program t h e individual blocks as described below. b Transfer t h e control program t o t h e CPU 945. b Switch t h e m o d e selector switch o f t h e CPU t o RUN. CPU 945 Manual Communications Capabilities The structure o f the sample program is shown in Figures 12.14 and 12.1 5. ASCll parameter Send mailbox Figure 12.14 ASCll Driver Program Structure for RESTART FBI b Output o f OB1 various messages t o t h e printer F B I is invoked every t w o seconds 4 Send mailbox (message texts for printer output) FB4 Binary-to-ASCII conversion f o r output t o printer l Figure 12.15 Structure of the Cyclic ASCll Driver Program EWA 4NEB 81 1 61 50-02d Communications Capabilities CPU 945 Manual ASCII parameter FB call :JU FB 230 NAME :ASCII-PA TPAR : KS DB KY 202,O NPAR : TSMR : KS DB Data type of ASCII parameter set Is in DB202 and begins with DWO. The Send mailbox is located in NSMB: TRMB : KY203,O KS XX NRMB: TCBS : KY0,O Not required KS FY The Send coordination byte NCBS TCBR NCBR : KY 200,O KS FY is FY200. The receive coordination byte : KY 201,O is FY201. MODE : KF +6 ASCII driver mode number 6 : DB203 beginning at DWO. Not required : BE ...... NAME :ASCII-PA I/Q/D/B/T/C: DECL :TPAR Initialize ASCII parameter list KS D KM/KH/KY/KS/KF/KT/KC/KG: DECL DECL : NPAR I/Q/D/B/T/C: D KM/KH/KY/KS/KF/KT/KC/KG: KY : TSMB I/Q/D/B/T/C: D KM/KH/KY/KS/KF/KT/KC/KG: KS DECL : NSMB DECL :TRMB I/Q/D/B/T/C: I/Q/D/B/T/C: D D KM/KH/KY/KS/KF/KT/KC/KG: KM/KH/KY/KS/KF/KT/KC/KG: KY KS DECL :NRMB : TCBS I/Q/D/B/T/C: I/Q/D/B/T/C: D D KM/KH/KY/KS/KF/KT/KC/KG: DECL DECL KM/KH/KY/KS/KF/KT/KC/KG: KY KS : NCBS I/Q/D/B/T/C: D KM/KH/KY/KS/KF/KT/KC/KG: KY DECL : TCBR I/Q/D/B/T/C: D KM/KH/KY/KS/KF/KT/KC/KG: KS DECL DECL :NCBR I/Q/D/B/T/C: I/Q/D/B/T/C: D D KM/KH/KY/KS/KF/KT/KC/KG: KY KF :MODE KM/KH/KY/KS/KF/KT/KC/KG: CPU 945 Manual Communications Capabilities :L KH 0100 ID for activation :T :L :T FW 200 RS47 FW 202 ASCII driver Do not change RS 47, since it is used by the operating system :LW =TPAR :T FW 204 :LW =NPAR Type of parameter list Address of parameter list FW 205 :LW =TSMP Type of send mailbox :T :T :LW :T :LW :T FW 207 =NSMP FW 208 = T W FW 210 :LW =NRMB :T Type of receive mailbox Address of receive mailbox FW 211 :LW =TCBS :T FW 213 :LW =NKRS :T :LW :T :LW Address of send mailbox Type of "Send" coordination byte Address of "Send" coordination byte FW 214 =TCBS FW 216 Type of "Receive" coordination byte =NCBR FW 217 Address of "Receive" coordination byte :LW =MODE Specification of driver mode number :T :L L FY 219 DH 000204DB DH 000E106F Absolute address of FY 219 :T :TNB :L :T :T :T :T :T 20 KBO Address of system data 55 (low-order byte) Initialize ASCII driver and enter in RS 46 to 55 Delete flag area used FD 200 FD 204 FD 208 FD 212 FD 216 Note with TPAR, TSMB, TRMB, TCBS, TCBR: Specify XB parameter for DX blocks Specify SY parameter for S flags Note with NPAR, NSMB, NRMB, NCBS, NCBR: Specify flag number in KY in the case of S flags Example: SY 258 Parameter = 1,2 (A1X 2 5 6 + 2 X 1 ) EWA 4NEB 81 1 61 50-02d Communications Capabilities :AN F :L KT 2 0 0 . 0 CPU 945 Manual 0.0 :SD T 0 :A T 0 . F 0.0 C a l l FBI e v e r y 2 s e c o n d s :J C F B 1 NAME :DRUCKEN Sample function block F B I is used t o print out message texts stored in send data block DB203. Output t o printer is initiated each time the function block is invoked and the send trigger bit (CBS bit 7) reset. Each time F B I is invoked, the number output in the message text is incremented by 1. Function block FB4 converts the message number from binary t o ASCII. :C DB 2 0 3 C a l l s e n d m a i l b o x DB :A F CBS b i t : 200.7 "SEND" (PRINT) : J C =ENDE L FW 2 0 2 Increment message o u t p u t number F o r e x a m p l e by 1 :ADD K F + l :T FW 2 0 2 :J U FB 4 C a l l c o n v e r s i o n FB NAME : D U > A S C I I DUAL : FW 2 0 2 A-TH : DW 2 1 A S C I I R e p r e s . TH/H ( D a t a w o r d s t o be A-ZE : DW 2 2 ASCII Repres. u p d a t e d i n s e n d DB) :L FW 2 0 4 :ADD K F + 2 :T FW 2 0 4 S o u r c e n u m b e r (BINARY) Tens/ones I n c r e m e n t error t e x t n u m b e r f o r e x a m p l e by 2 CPU 945 Manual :J U Communications Capabilities FB 4 C a l l c o n v e r s i o n FB NAME :DU>ASCII DUAL : FW 2 0 4 A-TH : DW 4 5 D a t a w o r d s t o be u p d a t e d A-ZE : DW 4 6 i n s e n d DB :AN F 200.7 CBS b i t 7 :S F 200.7 Initiate printing END :BE DECL : DUAL I/Q/D/B/T/C: I BI/BY/W/D: W DECL :A-TH I/Q/D/B/T/C: Q BI/BY/W/D: W DECL : A - ZE I/Q/D/B/T/C: Q BI/BY/W/D: W :L KBO :T FW 2 4 0 :T FW242 :T FW244 Remainder r e g . :L =DUAL Load b i n a r y number ( v a l . r a n g e 0 - 9 9 9 9 ) :L KF + g 9 9 9 SUBT : L KF + l 0 0 0 Evaluate thousands place =TAUS Jump t o p r o c e s s t h o u s a n d s p l a c e KF + l 0 0 Evaluate hundreds p l a c e =HUND Jump t o p r o c e s s h u n d r e d s p l a c e KF + l 0 Evaluate tens place :J C SUBH : L :J C Clear auxiliary req. :TAK SUBZ :L : >=f :JC =ZEHN Jump t o p r o c e s s t e n s p l a c e :JU =EINE Jump t o process o n e s p l a c e TAUS : - F :T FW244 :L FY240 :ADD KF +l :T :TAK FY 2 4 0 Increment counting reg. f o r thousands Communications Capabilities :JU HUND =SUBT CPU 945 Manual Jump to process thousands place : -F :T FW 244 :L FY 241 :ADD KF +l FY 241 :T :JU =SUBH Increment counting req. for hundreds Jump to process hundreds place ZEHN :-F :T FW 244 :E FY 242 :ADD KF +l :T FY 242 Increment counting req. for tens =SUBZ Jump to process tens place : TAK : JU EINE :TAK :T FY 243 :L KH 3030 :L FW 240 Describe counting req. for ones :OW :T =A-TH :TAK :L : OW FW 242 :T =A-ZE : BE ASCII Driver Parameter Data Block DB202 for Sample Program KF KH KH KH 13: 12-72 = = = = 100007; 0000; Waiting time after CR: (none) 0000; 0000; Waiting time after LE: (none) Waiting time after FE: (none) KH = 000A; Delay time between 2 char.: A KH = 0004; End-of-text char.: "EOT" KH = 0001; Suppress LE: NO KF = 100066; Lines/paqe: 66 KF = +00000; Page number at bottom of page KH Spaced print ON = 1B38; 100 ms Left margin: 0 characters KS = ' U'; KS = ' MESSAGE LOG: CPU945 = Header line 1 I EWA 4NEB 81 1 61 50-02d CPU 945 Manual Communications Capabilities 25 : 33 : KS ='ASCII DRIVER ' ; KH = 1B3C; Spaced print OFF 34 : KH KS CR / LE Header 2 = ODOA; 35 : 47: KS 59: KS ............................ 71: KS ='========l. 75 : 76: KH KS 88: KS ='**********<page>********'; ............................ ............................ = CR / LF Footer 1 ODOA; ............................ 100 : KS 112: 116: KS = ' * * * * * * * * ' KH = ODOA; 117: KS = ' 129: KS ='ple for CPU945 ASCII drip; 141: KS ='ver interface 151: KH .............................. = ; CR / LF Exam ' ; Footer 2 t . CR / LF ODOA; 152 : Send Data Block DB203 for Sample Printer Output Program K11 = 3477; KS ='age NO.: ' : KH = 1B30; Control char.:Underline ON Text message number (is used by FB4) KS ='0000'; KH = 1B39; KS = ' * * * KH = Control char.:Underline OFF Message text > F ; 1B30; Control char. :Underline ON KS=' C A U T I O N B U R N ' ; KS='ER 0000 H A S F A ' ; Message text Message text and message number 53: 60 : KS ='I L E D ! KH = 1B39; Message text 61: 62: KS = ' < ' ; KH = 2000; Message text SPACE and CR Activate control char. 1 . Control char.:Underline OFF 63 : KH = 1B5B; 64 : KH = 3177; for pitch 1/10 65 : KH = OA04; End-of-text char. is EOT (see PAR-DB202) 66: KH = 0000; 67: EWA 4NEB 81 1 61 50-02d Communications Capabilities CPU 945 Manual 12.5.7 ASCII Code Table 12.26 ASCII Code CPU 945 Manual 12.6 Communications Capabilities Computer Link with 3964(R) Transmission Protocol The CPU 945 permits data interchange with the 3964(R) transmission protocol via i t s second interface. Data can be exchanged between t w o programmable controllers (two CPUs) or a programmable controller and another commlsnications partner Possible communications partners for the CPU 945 (512) using the 3964(R) transmission protocol: CPU945(S12) CPU944(S12) CP523 CP 5241525 (e.g. with S5 R006 special driver "Programmable computer link with 3964(R) protocol without reaction message frame". (Order No.: 6ES5 897-2AB11-03)) Other communications partners (with 3964(R) transmission protocol) e.g.: - SICOMP PC - Teleperm M - Moby l The control program on the CPU initiates the data interchange. The transmission procedure controls the exchange. The transmission procedure permits t w o types o f data communications: Data interchange with block check character (BCC): Data interchange without block check character: 3964R procedure 3964 procedure The block check character generates the vertical parity (exclusive OR operation) of all the bytes o f a block that have been transmitted. EWA 4NEB 81 1 61 50-02d CPU 945 Manual Communications Capabilities Data can be interchanged by means of the 3964(R) transmission procedure only if the parameters have been assigned according t o Sections 12.6.4 and 12.6.5 and the computer link has been activated by the corresponding entry in the high-order byte of RS 46 (E 105CH). The ASCll driver can also be parameterized and activated by parameterizing DBI accordingly (see Chapter ll ) . After activation o f the computer link, any error flags concerning the CBR or CBS are set in the loworder byte of RS 46. Note When the computer link is activated, S12 is no longer available for any other functions (e.g. programmerIOP, SINEC L1, point-to-point connection). Table 12.27 Meaning o f System Data Word 46 (Computer Link) High-order byte OOH* ProgrammerIOP and SINEC L1 operation 02, Driver for 3964(R) computer link active 01H Invalid driver number 1OH CBS not available 20, CBR not available 4 0 ~ * CBS and CBR not available Default value (preset value) after overall reset The communications partners are linked via a direct line. Cable requirements: 4-core Shielded Cross-section r 0.14 mm2(26 AWG) The SIMATIC cable 6ES5 707-1AA00 is recommended. For connector pin assignments, refer t o Section 12.7 "Interface Modules" CPU 945 Manual Communications Capabilities 12.6.1 3964(R) Transmission Protocol This section describes the 3964(R) transmission protocol. The parameter assignments and activation o f t h e computer link are explained in Sections 12.6.4 and 12.6.5. The 3964(R) driver ensures relatively safe data transmission since the receiver must first send a ready signal t o the transmitter (connection buildup) and acknowledge the reception o f data after the data interchange. The block check character transmitted i n addition t o t h e data also enhances data security. The 3964(R) driver interprets the following control characters: m m m m DLE STX NAK ETX (10,) (02,) (15,) (03,) Data Link Escape Start o f Text Negative Acknowledgement End o f Text Transmission Procedure Control characters and useful data are transmitted b i t by bit. When mode 2 is selected, t h e data unit transmitted, also called message frame, is followed by a block check character. Like all other data bytes, t h e BCC is protected by t h e relevant parity check and transmitted a t t h e end o f t h e message frame. Mode 2 must be set in system data w o r d 55 (see Section 12.6.4). Prior t o a transmission, t h e data is buffered in a 1024-byte output buffer. If t h e amount o f data t o be transmitted is t o o large f o r t h e output buffer, an error b i t is set (see Section 12.6.3). The data received is first entered i n t h e 1024-byte input buffer o f t h e receiver before t h e user program initiates the transfer t o the receive mailbox o f the CPU. Communications Capabilities CPU 945 Manual SendingIReceiving w i t h the 396413964R Line Procedure in Detail Connection Buildup The 3964(R) line procedure executes the following steps automatically. Tra nsmitter Receiver When there is no Send order t o process, the 3964(R) driverwaits forthe peer in the l i n k t o establish a connection. STX is a control character (02,) which initiates connection buildup. Receiver acknowledges with DLE (10,) prior t o time-out (QVZ). Connection buildup was successful; the transmitter sends the first character from the send buffer. (QVZ: Word 5 in the parameter list) Receiver acknowledges with a character other than DLE or STX prior t o time-out (QVz) or receiver does not acknowledge prior t o time-out Connection buildup was initially unsuccessful; the transmitter makes another attempt t o establish a connection. (Number of attempts t o establish a connection: Word 7 in the parameter list). If the last attempt also proves unsuccessful, the transmitter enters a code in the Send coordination byte (CBS). Receivertransmits an STX control character prior t o time-out (QVZ) Initiation conflict, i.e. both peers in the link want t o transmit. The peer with the lower prioritysends DLE, thus enabling the higher-priority node t o transmit first; the lower-priority node then transmits its data. The t w o peers must never have the same priority! (Priority: Word 3 in the parameter set) CPU 945 Manual Communications Capabilities Sending and Receiving Frames Each character whose value is 10H (DLE) i s transmitted twice in succession ss that the receiver does not interpret it as the control character for connection buildup. The receiver enters only one of the t w o characters in i t s Receive buffer. The receiver monitors the time that elapses between transmission o f t w o consecutive characters. If it exceeds the specified character delay time (ZVZ), the receiver sends a NAK and waits the amount of time defined in word 6 of the parameter list for the frame t o be retransmitted. (Character delay time: Word 3 in the parameter list). The following occurs when the receiver's Receive buffer is full before the transmitter has initiated a connection cleardown: - receiving continues until the connection has been cleared down - the receiver subsequent~ytransmitsthe NAK control character - the error is flagged in the CBR. If the receiver sends a NAK character t o the transmitter while transmission is in progress, the transmitter aborts the data transfer and retransmits the entire frame, beginning with the first character. If the receiver sends a character other than NAK while transmission is in progress, the transmitter ignores it and continues i t s transmission. The receiver reacts t o a transmission error (character lost, bad frame, parity error, BCC error) as follows: - Reception continues until the connection is cleared down - NAK is then transmitted - If an attempt t o transmit is s t i l l possible (word 8 of the parameter list), the receiver waits for the frame t o be retried. How long the receiver waits depends on the frame delay time (word 6 in the parameter list). The receiver aborts transmission and reports an error in CBR if the data block could not be received at the last send attempt or - if the sender does not start sending within the block waiting time. - The "BREAK" signal causes the transmitter t o abort the current transmission - send NAK - flag an error in the CBS. - If a message frame is not accepted (no positive acknowledgement) after the set number o f attempts t o establish a connection or transmit, the sender responds by sending a NAK. Communications Capabilities CPU 945 Manual Connection Cleardown When all characters in the Send buffer have been transmitted, the transmitter initiates connection cleardown by transmitting in succession the control characters DLE (Ion), ETX (03n) and, i f specified, BCC (block check character for 3964R). -+ (BCC) 4 ETX -,DLE -+ Receiver sends a DLE control character prior t o time-out (QVZ) The frame was received without error and the connection cleared down. Receiver sends a NAK control character or any If the specified number o f transmission attempts is greater than l,the frame is retransother character (except DLE !) prior t o mitted (number of attempts: word 8 in the time-out parameter list). If the last attempt is unor successful, the transmitter aborts the transthe receiver does not send any character prior mission and flags an error in the CBS. t o time-out Example of an Error-Free Send Procedure CPU 945 w i t h 3964R line procedure Communications partner F[- nth char. DLE (10,) - DLE (10,) DLE (10), * with 3964R transmission protocol only Figure 12.16 Error-Free Send Procedure (Computer Link) CPU 945 Manual Communications Capabilities Example of an Error-Free Send Procedure: CPU 945 3964(R) driver Communications partner STX 4 DLE W 1st character 4 4 4 4 nth character 4 DLE 4 BCC * f DLE * Connection cleardown W BCC for 3964R transmission protocol only Figure 12.17 Error-Free Receive Procedure (Computer Link) EWA 4NEB 81 1 61 50-O2d CPU 945 Manual Communications Capabilities Examples of Errors During Data Transmission: CPU 945 3964(R) driver Low priority Communications partner High priority Correct connection Renewed connection buildup t o repeat transmission of * BCC for 3964R transmission protocol only Figure 12.18 Errors During Data Transmission (Computer Link) EWA 4NEB 81 l 61 50-O2d CPU 945 Manual Communications Capabilities Example of H o w t o Solve an Initiation Conflict Communications partner, low priority CPU 945 with 3964R driver, high priority (02,) ___, STX(O2") DLE (10,) 1st character Initiation conflict - Partner with low priority leaves permission t o send t o partner with high priority -b ___, ___+ nth character DLE (10,) ETX (03,) BCC d DLE (10,) sTX(02~) DLE (10,) - Partner with low priority begins t o send B Figure 12.19 Solving an Initiation Conflict (Computer Link) CPU 945 Manual Communications Capabilities 12.6.2 Data lnterchange over the S12 Interface with 3964(R) Transmission Protocol The data t o be transferred must be entered in an area of memory designated as the "Send mailbox". Conversely, the data t o be received requires a "Receive mailbox", and an area in memory must therefore also be designated for this purpose (detailed information is presented in the next section). The data is stored temporarily in interface 512's input or output buffer. Figure 12.20 illustrates the procedures involved in data interchange. Operating system Program memory P 1, +(1Input buffer 024 bytes) Peripheral device l Receive mailbox +Output buffer (1024 bytes) + , Send mailbox Figure 12.20 Data lnterchange over the S12 Interface (Computer link) Transmitting Data The length o f the frame t o be transmitted (in bytes) must be entered in the first word of the Send mailbox. Send mailbox Frame length Word 1 Word 2 Data Word n Figure 12.21 Structure of the Send Mailbox (Computer Link) The data t o be transmitted must be entered in the remaining words of the Send mailbox. Set bit 7 in the CBS (a rising edge triggers the transmission). The computer link resets this bit when transmission has been completed. The bit is reset irrespectively of whether the send procedure was correct or errored. If an error occurred during data transmission, an error code is entered in bits 0 t o 6 o f the CBS which describes the type of error (see Section 12.6.3). EWA 4NEB 81 1 61 50-02d CPU 945 Manual Communications Capabilities Receiving data Receive data (message frames) are automatically written in the input buffer o f the computer link (buffer size: 1024 bytes) if there is sufficient space or less than 100 message frames are i n t h e buffer. Otherwise, an error flag is written i n t h e input buffer and can be evaluated i n t h e CBR. The error flag is not stored i n t h e input buffer if it has been stored there immediately before (see Section 12.6.3). In order t o transfer this data t o t h e receive mailbox, b i t 7 must be set i n the CBR by t h e control program. The computer link automatically enters t h e number o f bytes received i n the first word o f the receive mailbox. When t h e data o f a message received is stored i n the receive mailbox, t h e computer link resets b i t 7 o f t h e CBR. If t h e data was n o t correctly received, an error code is written i n bits 0 t o 6 o f t h e CBR and b i t 7 o f t h e CBR is reset (see Section 12.6.3). Since various errors can occur i n one receive request, the computer link assigns priorities t o t h e individual errors. The CBR always contains t h e error t h a t had the highest priority during t h e last attempt t o receive. 0 indicates t h e highest priority, 6 t h e lowest. Communications Capabilities CPU 945 Manual 12.6.3 Coordination Bytes of the 3964(R) Driver The 3964(R) driver monitors data communications via the coordination byte for "Send" (CBS) and the coordination byte for "Receive" (CBR). The 3964(R) driver enters status and error messages in these bytes. A coordination byte can either be a flag byte (FYISY) or a high-order byte in a data word (DBIDX) Tables 12.28 and 12.29 describe the meanings o f the individual bits of the coordination byte. Table 12.28 Meanings of the Individual Bits of the "Send" Coordination Byte (CBS) in a Computer Link Permission t o send The bit is set by the control program and reset by the 3964(R) driver irrespective o f whether the send procedure is terminated with or without error. The transmission is initiated by a positive-going edge at bit 7. The send data and the location o f the send mailbox must not be modified as long as this bit is "1". CPU 945 Manual Table 12.29 Communications Capabilities Meanings of the Individual Bits of the Coordination Byte for "Receive" (CBR) in a Computer Link Permission t o receive The bit is set by the user and reset by the 3964(R) driver when a frame received has been transferred from the input buffer t o the Receive mailbox or an error flag has been set in the CBR. As long as the bit is "l", the receive data and the location of the receive mailbox must not be modified. As long as the bit is "O",the user must not access the receive mailbox. As long as the input buffer is not full, the messages are stored there and are not entered in the Receive mailbox. U p t o 100 message frames can be entered in the receive buffer. * ** DLE and ETX are control characters for connection buildup and connection cleardown (DLE=Data Link escape, ETX= End o f Text). The line procedure automatically doubles a byte o f data that has t h e same code as a control character (DLE i n this case) i n o r d e r t o be able t o distinguish the data from the control character. DLE-ETX is a fixed sequence that is required for error-free connection buildup/cleardown. STX is t h e control character which establishes the connection t o t h e communications partner (STX = start of text) Note The bits in the coordination bytes can be set or reset by the operating system after any operation and irrespective of the PLC cycle. This means that a multiple scan of a coordination byte within one program cycle can have different results (This must be taken into consideration for an edge evaluation!) EWA 4NEB 81 1 61 50-02d Communications Capabilities CPU 945 Manual 12.6.4 Parameter Set of the 3964(R) Driver The parameter set contains t h e defaults necessary f o r a data interchange. The location o f t h e parameter set is defined by system data w o r d 48 (or b o t h 48 and 49) (see Table 12.33). For permissible parameter settings and defaults, refer t o Table 12.30. The 3964(R) driver can also b e parameterized i n DB 1 (see Chapter 11). Note The default values are used only if t h e parameter set is n o t available o r cannot be interpreted. EWA 4NEB 81 1 61 50-02d CPU 945 Manual Communications Capabilities Table 12.30 Parameter Set (Com~uterLink) l Baud rate 9 150 baud 200 baud 300 baud 600 baud 1200 baud 2400 baud 4800 baud 9600 baud 19200baud 0 1 2 3 4 even odd mark (filler bit high) space (filler bit low) nocheck 2 3 4 5 6 7 8 Parity Data format* Priority lot08 lo 1 high low 1 to65535X10 ms Character delay time (The max. amount of timewhich may elapse between transmission of t w o consecutive characters) 1 t o 65535x10 ms Acknowledgement delay-time (ti me-out) (The time within which a request-to-send or a complete frame (DLE, ETX) must be acknowledged) 1 to65535X10 ms Frame delay time (If the character delay time is exceeded, the complete retransmitted frame must arrive in the receiver before the frame delay time is exceeded) 1 t o 255 Connection buildup attempts (Maximum number of attempts that may be made t o build up a connection) Number o f transmission attempts (Maximum number of attempts that may be made t o transmit a block) * 1 t o 255 I Meaning of word 2 (data format) see Table 12.31 The parameter set is read at activation o f the computer link or after a mode change; data traffic at the interface must have previously been terminated, however (bit 7 in CBR and and bit 7 in CBS=O). The parameter set is also transferred after PLC POWER ON if the computer link had been previously activated. The parameter settings on the CPU and in the communications partner must be identical t o word 3 (priority). The opposite priority must be the default in the communications partner so that a parameterization conflict can be resolved. Communications Capabilities CPU 945 Manual Please note these time relationships when setting the following: Character delaytime < timeout < block waiting time! The send or receive process can be initiated when these defaults have been completed. Table 12.31 * Character Frame and Order o f Bits on t h e Line i n the Case o f a Computer Link 7 As data format 0 11 bits 0 t o 4* 7 1 start bit, 7 data bits, 1 parity bit, 2 stop bits 8 As data format 1 11 bits 0 t o 4* 8 1 start bit, 8 data bits, 1 parity bit, 1 stop b i t seeTable 12.30 Assigning a M o d e Number (System Data 55) Data can be transmitted i n t w o different modes. The mode selected, i.e. i t s number, is t o be entered i n t h e low-order byte o f system data w o r d 55 (OE 106E,) (see Table 12.33). Refer t o Table 12.32 f o r t h e mode types. Table 12.32 Meanings o f t h e Mode Numbers (Computer Link) I 1 2 I No block check character (BCC) is transmitted a t t h e end o f a frame (3964) A block check character (BCC) is transmitted a t t h e end o f each frame (3964R) I CPU 945 Manual Communications Capabilities 12.6.5 Assigning Parameters to the 3964(R) Driver The location o f t h e parameter set, o f t h e send and receive mailboxes, the coordination bytes and the mode number are t o be defined by means o f t h e control program in a parameter block (see Table 12.33) in t h e system data area o f t h e CPU 945. Parameters can also be assigned i n DBI (see Chapter 11). Table 12.33 Parameter Block f o r Computer Link Send mailbox Data word No. or low- * high-order part o f S flag address order part o f S flag address RS 54 CB R Data ID CB R DBIDX- or flag byte, or high-order part o f S flag address OE 106C OE 106D RS 55 CB R Data w o r d No. or low-order part o f S flag address Mode number* OE 106E OE 106F If no valid mode number is entered, thedefault number is "1 ". CPU 945 Manual Communications Capabilities The data IDs of the parameter block are described in the following table. Table 12.34 Data IDs of the Parameter Block (Com~uterLink) S flag** I * S 53H I S flag byte NO.: o t o 4095 DB NO.: 0 t o 255 DX No.: O I I Data (DB) 4 4 ~ D Data (DX) 58~ X --- 255 Data word NO.: 0 t o 255 Data word No.: 0 t o 255 The start addresses of the relevant memory areas, both for the parameter set of the computer link and for the send and receive addresses, are stated here. * * High-order part of S flag numbers OOH ...OFH; low-order part of Sflag numbers OOH ... FFH EWA 4NEB 81 1 61 50-02d CPU 945 Manual Communications Capabilities 12.6.6 Program Example for Transmitting Data During restart, the relevant computer link parameters are assigned t o system data words 46 t o 55 and the computer link is activated. For this purpose, a programmable function block (FB220) is used. The parameters for the communications link are as follows: Parameter set in DB202, beginning with DW 0 Send mailbox in DB203, beginning with DW 0 Receive mailbox in DB204, beginning with DW 0 The CBS is flag byte FY 100 The CBR is flag byte FY 101 The mode setting is: Mode 2 (with BCC) The data t o be transferred is in data words DW 1 t o DW 5 o f DB203. The frame length specification must therefore be 10 bytes. The example describes the program of the communications partner. I t can be used analogously for a CPU 945 which acts as a communications partner i f the priority (DB202, DW 3) is changed t o "low priority". : J U FB 2 2 0 NAME : P A - 3 9 6 4 TPAR : KS DB NPAR : KY 2 0 2 , O is located in D B 2 0 2 beginning DWO TSMB : KS DB The send mailbox is located in NSMB: KY203,O D B 2 0 3 beginning DWO TRMB KS DB The receive mailbox is located in NRMB : KY 2 0 4 , O D B 2 0 4 beginning DWO TCBS : KS FY The coordination byte for NCBS KY 1 0 0 , O send is flag byte FYlOO KS FY The coordination byte for : : TCBR : Parameter set for communications link NCBR : KY 1 0 1 , O receive is flag byte F Y l O l MODE : KF + 2 Mode number: 2 (with BCC) :AN F 101.7 :S F 101.7 Receive enable :BE Notes for TPAR, TSMB, TRMB, TCBS, TCBR: For DX blocks +Specify "XB" parameter For S flags + Specify "SY" parameter Notes for NPAR, NSMB, NRMB, NCBS, NCBR: For S flags Example: SY 258 Parameter=1.2 (S1 X256+2X1) EWA 4NEB 81 1 61 50-02d +Specify S flag No. in KY Communications Capabilities CPU 945 Manual DECL DECL : TPAR I/Q/D/B/T/C: D KM/KH/KY/KS/KF/KT/KC/KG: : NPAR I/Q/D/B/T/C: D KM/KH/KY/KS/KF/KT/KC/KG: KY DECL : TSMB I/Q/D/B/T/C: D KM/KH/KY/KS/KF/KT/KC/KG: KS DECL DECL DECL : NSMB I/Q/D/B/T/C: D KM/KH/KY/KS/KF/KT/KC/KG: KY :TRMB : TCBS D D D KM/KH/KY/KS/KF/KT/KC/KG: DECL I/Q/D/B/T/C: I/Q/D/B/T/C: I/Q/D/B/T/C: KM/KH/KY/KS/KF/KT/KC/KG: KM/KH/KY/KS/KF/KT/KC/KG: KS KY KS DECL :NCBS I/Q/D/B/T/C: D KM/KH/KY/KS/KF/KT/KC/KG: KY : TCBR I/Q/D/B/T/C: I/Q/D/B/T/C: I/Q/D/B/T/C: D D D KM/KH/KY/KS/KF/KT/KC/KG: KS KY KF DECL : NRMB DECL : NCBR DECL :MODE KM/KH/KY/KS/KF/KT/KC/KG: KM/KH/KY/KS/KF/KT/KC/KG: KS Preset system data area :L KH 0200 :T FW 200 :L :T RS47 FW202 :LW =TPAR :T FW204 :LW =NPAR :T FW205 :LW =TSMB :T FW 207 :LW =NSMB Driver number for computer link Retain entry in RS 47 Data type of parameter set Address of parameter set Type of Send mailbox Address of Send mailbox :T FW 208 :LW =TRMB :T FW 210 Type of Receive mailbox :LW =NRMB Address of Receive mailbox :T :LW :T FW 211 =TCBS Type of CBS :LW =NCBS FW 213 :T FW 214 :LW =TCBR :T FW 216 :LW =NCBR :T FW 217 :LW =MODE :T :L FY 219 DH 000204DB :L : TNB :L :T :T :T :T :T :BE DH 000E106F 20 KBO Address of CBS Type of CBR Address of CBR Mode Abs. address of FY219 (source) SD55 address (low-order byte)(dest.) Enter computer link parameter in RS 46 to 55 Reset flag area FD 200 FD 204 FD 208 FD 212 FD 216 EWA 4NEB 81 1 61 50-02d CPU 945 Manual :JU NAME Communications Capabilities FB 1 :SEND :JU FB 2 NAME :RECEIVE :C :O DB 203 F 100.7 :ON I 0.0 Open Send mailbox Go to end when send in progress or when no send request is pending (enable send with I 0.0) :A : JC F PB 100.0 ERROR during last SEND? Then evaluate error in PB1 1 Load data into Send mailbox :L KF +l0 10 bytes are to be transferred :T DW 0 (first word in Send mailbox) :L DW 1 Modify send data :ADD KF + l :T DW 1 :AN :S F F 100.7 100.7 :BE EWA 4NEB 81 1 61 50-02d Initiate send CPU 945 Manual Communications Capabilities NAME :RECEIVE :C DB 2 0 4 Open Receive mailbox :A F 101.7 END if no data were received. :A F 101.0 Receive ERROR? :JC PB :A F 101.0 :BEC 2 Then evaluate error jn PB2 If errors occured, re-enable Receive mailbox and do not evaluate data F101.7 Evaluate Receive mailbox Evaluate number of bytes recelved :T DW QW DW QW :AN F 101.7 :S F 101.7 :S : BEC :L :T :L 0 0 1 Evaluate data received 2 Re-enable Receive mailbox :BE KF = +00008; Baud rate KF = +00000; Even parity KF = +00001; Data format 1 KF = +00001; KF = +00022; High priority Character delay time KF = +00200; Acknowledgement delay KF = +00400; Frame delay time KF = +00006; Max. number of conn. buildup attempts KF = +00006; Max. number of attempts to send = 9 6 0 0 baud = 4 2 2 0 ms = = 2 s S CPU 945 Manual 12.7 Communications Capabilities lnterface Modules This section describes the interface modules that can be used in conjunction with the CPU 945. Furthermore, the functions of the individual interface modules are explained. Besides the first serial interface (SII), the CPU 945 offers a receptacle for an interface module which serves as the second serial interface (512). The following interface modules can be inserted in the CPU 945: Programmer module (1 5-pole) V.24 module (25-pole) TTY module (25-pole) RS 422-AI485 module (1 5-pole) SINEC L1 module (l 5-pole) 6ES5 752-OM52 6ES5 752-OM22 6ES5 752-OM4 2 6ES5 752-OLA42 6ES5 752-OLA62 lnterface module Figure 12.22 Location of the Interface Module in the CPU 945 Communications Capabilities CPU 945 Manual Inserting the lnterface Module in the CPU 945 Warning The interface module can only be inserted or withdrawn at POWER-OFF. Proceed as follows when connecting an interface module t o 512: F F b Unscrew the cover plate of the interface module receptacle and remove it from the housing o f the CPU 945. Insert the interface module in the receptacle. Fix the interface module by means of the screws. The following table shows which interface modules can be used for the various types of links. Table 12.35 Applications of the lnterface Modules Programmer interface * X X* X X X SlNEC L1 X Point-to-point connection (SINEC L1 protocol) X Computer link 3964(R) X X* X X X ASCll driver X X* X X X Only V.24 signals RxD and TxD are supported. 12.7.1 Programmer Module The programmer module permits the connection of programmers and operator panels t o the second serial interface in addition t o those connected t o the first interface o f the CPU 945. Other permissible links: ASClldriver Computer link The maximum permissible transmission rate is 9600 baud. The programmer functions are limited if they are requested simultaneously at the first interface and at the programmer module. Depending on the functions activated at one interface, certain requests cannot be made by a programmer1OP connected t o the other interface. If a function requested at one interface clashes with the function initiated at the other interface, the operating system o f the CPU interrupts this function and issues an error message t o tell the operator that the interface function is disabled. CPU 945 Manual Cornrnunications Capabilities The programmer module incorporates both a transmitter and a receiver for 20 mA current-loop signals. The loop current is always fed from the programmer if a PG 7xx programmer is connected. The following diagram shows the connection o f the loop current signals. 4Receiver - - Transmitter + - - Transmitter + CPU 945 Programmer - Receiver PG Current direction P P P - - P P P - - Figure 12.23 Programmer Module: Direction of Loop Current Data is generally transmitted via the programmer interface at a rate of 9600 baud. The following Figure shows the connector pin assignments of the 15-pole Cannon socket in the front plate o f the programmer module (corresponds t o assignments of 511): Figure 12.24 Programmer Module: Pin Assignments Communications Capabilities CPU 945 Manual Jumper settings on the programmer module The programmer module is supplied with the jumper settings shown in Figure 12.25. The module is thus ready for use. CPU 945 Figure 12.25 Programmer Module: Jumper Settings CPU 945 Manual Communications Capabilities Standard connecting cables for the programmer module Standard connecting cables with lengths up to 1000 m (3300 ft) are available for linking the programmer module in the CPU 945 t o the programmer. CPU 945lprogrammer connecting cable CPU 945 S1 lor S12 with programmer module Programmer/programmer adapter (PG 7xx) K2 4 K3 3 4 4B 2 U Jl- JlBaud rate setting Figure 12.26 Programmer Module: Standard Connecting Cable Note Incorrect wiring can cause destruction of the optical couplers in the interface. Communications Capabilities CPU 945 Manual Connecting cable for point-to-point connection (programmer module) The following Figure shows the assignments of the connecting cable for point-to-point connections. ASCII driver (see Section 12.5) Computer link (see Section 12.6) CPU 945 e.g. CPU 943 t o 945,928B, s5-95U Figure 12.27 Programmer Module: Connecting Cable for Point-To-Point Connection EWA 4NEB 81 1 61 50-02d CPU 945 Manual Communications Capabilities 12.7.2 V.24 Module The V.24 module can be used for the following types of link: Data link with 396413964R procedure Data link with ASCll driver Programmer interface The following Figure shows the pin assignments o f the V.24 interface (send and receive lines): Device 2 Device 1 GND GND TXD TX D RXD RXD Shield Shield Figure 12.28 Pin Assignments of the V.24 Interface Besides send and receive lines, the V.24 module incorporates a number o f control and signal lines complying with the CClTT recommendation for V.24lV.28. Neither the 396413964R standard procedures nor the ASCll driver use these signals. Voltage ranges for V.24 signals: Logic " 0 " corresponds t o a voltage of Logic " 1 " corresponds t o a voltage of + V 1 3V V 5 -3 V If you assemble the connecting cables t o suit your own requirements, note that unassigned inputs of the partner must possibly be connected t o an open-circuit potential. For detailed information, refer t o the relevant manuals and the CClTT recommendations for V.24 or V.28. Note For data transmission via the V.24 module, baud rates up t o 19,200 baud are permissible. Communications Capabilities CPU 945 Manual The following Figure shows the connector pin assignments of the 25-pole Cannon socket in the front plate of the V.24 module: * Not supported by drivers. Figure 12.29 V.24 Module: Pin Assignments The signal numbers are specified in accordance with DIN 66020 (V.24lRS 2 3 2 0 , the signal designations comply with the international standards (RS 2 3 2 0 . CPU 945 Manual Communications Capabilities Jumper settings on the V.24 module The V.24 module is supplied w i t h the jumper settings shown in Figure 12.30. The V.24 module is thus ready f o r use. Front connector 25-pole sub D socket 1 2 3 00 Module connector l0 Figure 12.30 V.24 Module: Jumper Settings on Delivery Jumpers 3 and 5 are used f o r reversing t h e polarity of the send and receive data. Send data w i t h normal polarity Negated send data Receive data w i t h normal polarity Negated receive data CPU 945 Manual Communications Capabilities Jumper 6 can b e used t o switch all V.24 receivers i n such a w a y t h a t t h e y need only t h e positive voltage range. ~ u m 3 2 1 p e r All signals received must have a V.24-specific m signal level 6 signal range Jumper 9 can b e used t o connect CTS permanently t o a n open-circuit potential o r t o b e connected directly t o t h e f r o n t connector. 1. l rem pu~ CTS connected t o open-circuit potential a Standard connecting cables f o r V.24 module Standard connecting cables are available a t d i f f e r e n t lengths u p t o 16 m (52 f t ) f o r linking t h e V.24 module of t h e CPU 945 t o t h e partner. Cable f o r connecting t h e CPU 945 a n d CP 525, CP 524, CPU 945, CPU 928B CP 525, CP 524, CPU 945, CPU 928B CPU 945 Transmitter Receiver -0 n)-- 3 j\ .. ! ! ! ! ! Transmitter 7 ! ! ! ! ! !! . . ! ! ! ! ! I ; TXD ! ! ! ! ! I ; RXD ! ! I I i i ! ! I I i i !! !! 2 ;; Receiver 3 7 m 3 ! ! ! ! r Y ---"'--l I1 Housing, g r o u n d n a RXD a++-- -----Shield 1 Housing, g r o u n d Figure 12.31 V.24 Module: Cable for Connecting the CPU 945 and CP 525, CP 524, CPU 945, CPU 9288 CPU 945 Manual Communications Capabilities Figure 12.32 V.24 module: Cable Connecting the CPU 945and the DR 210/211 Communications Capabilities CPU 945 Manual 12.7.3 TTY Module The TTY module can be used for the following types o f link: Data link with 396413964R procedure Data link with ASCll driver As programmer interface The TTY module incorporates a transmitter and a receiver for 20 mA current-loop signals. The Figure below illustrates a typical connection of the current-loop signals. Device 1 Transmitter r i-, Device 2 Receiver Current direction Figure 12.33 TTY Module: Current Direction The loop current can be fed both from the TTY module and the partner. Only the device that supplies the power must be non-floating. A Caution For greater cable lengths, the lines should be connected in such a way that the transmitter always supplies the power. The l T Y module supplies the current (20 mA) via jumpers in the connector of the standard connecting cable. The 24 V required for generating the loop current are provided by the power supply unit o f the PLC. A current of 20 mA (logic " 1") flows in the inactive state o f a correct current-loop circuit. An open circuit is indicated by a logic " 0". Meanings o f the TPI signals: Logic " 0 " : No current Logic " 1 ": Current (20 mA) EWA 4NEB 81 1 61 50-02d Communications Capabilitl'es CPU 945 Manual Note The maximum permissible transmission rate for a data link with the TTY module is 9600 baud. The l T Y module complies with DIN 66 258, Part 1. Figure 12.34 shows the pin assignments of the 25-pole Cannon socket in the front plate of the TTY module: Figure 12.34 TTY Module: Pin Assignments Communications Capabilities CPU 945 Manual Jumper settings on the TTY module The TTY module is supplied w i t h the jumper settings shown i n Figure 12.35. In this way, the TTY module is ready f o r use. Figure 12.35 77YModule: Jumper Settings on Delivery Jumpers 1 and 2 are used f o r reversing t h e polarity o f t h e send and receive data: Jumper 1 Negated send data Send data w i t h normal polarity Jumper 2 Receive data w i t h normal polarity Negated receive data CPU 945 Manual Communications Capabllities Jumper 3 can be used t o route the 24 Vsource voltage for generating the loop current: 24 V are connected t o pin 9 of the sub D socket in the front plate 24 24 are the module connector (internal) Jumper 3 [F] Standard connecting cables for the TTY module Standard connecting cables are available in various lengths up t o l000 m (3300ft) for linking the TTY module in the CPU 945 with the partner. Cable connecting the CPU 945 and CP 524, CP 525, CPU 945, CPU 928B CD1 I CP 524. CP 525. CPU 945, CPU 9288 OAK Transmitter 'A 'A I f- - - - - ?---F+ 1 Housing, ground Shield -+t-(-- I ' . . Mext 1 1 Housing, ground Me, Figure 12.36 T7-Y Module: Cable Connecting the CPU 945and CP 524, CP 525, CPU 945, CPU 928B Note Incorrect wiring can cause destruction of the optical couplers in the interface. EWA 4NEB 81 1 61 50-O2d Communications Capabilities CPU 945 Manual Cable connecting the CPU 945 and the DR 210lDR 21 1 This connecting cable can be used for both the TTY and the V.24 module. Make sure you have selected the same interface types in the CPU 945 and the printer. DR 210IDR 21 1 CPU 945 V.24 assignments V.24 assignments Housing, Ground Figure 12.37 TTY Module: Cable Connecting the CPU 945and the DR 210/211 Note - Incorrect wiring can cause destruction o f the optical couplers in the interface. CPU 945 Manual 12.7.4 Communications Capabilities RS 422-AI485 Module The RS 422-AI485 module can only be used in the RS 422-A mode in a 3964(R) link, with the ASCll driver, as programmer interface. RS422-A mode means that the module incorporates the necessary hardware components for fullduplex mode according t o the EIAstandard RS422-A (CCITT recommendation V.ll). The following Figure shows the pin assignments of the RS422-AI485 interface (send and receive lines): Device 2 Device 1 GND . GND T(A) T(A) T(B) T(B) R(A) NB) Shield . R(A) R@) Shield Figure 12.38 Pin Assignments of the RS422-A/485 Interface Besides the send and receive lines, the RS422-AI485 module has a number of control and signal lines conforming t o the CCITT recommendation X.24 and IS0 8481. However, the abovementioned links neither require nor use these signals. Therefore the relevant pins need not be assigned. The RS422-AI485 interface operates on the differential voltage principle and therefore has a higher degree o f interference immunitythan a TTY or V.24 interface. The following applies t o the signals complying with the EIAstandard RS 422-A (V.ll): Logic "0" (ON) corresponds to: VA > VB Logic "1 " (OFF) corresponds to: VA < VB In the RS422-AI485 module, the interface signals are electrically isolated from the supply voltage of the PLC. EWA 4NEB 81 1 61 50-02d Communications Capabilities CPU 945 Manual The following Figure shows the pin assignments of the 15-pole Cannon socket in the front plate of the RS422-AI485 module: Figure 12.39 RS422-A/485 Module: Pin Assignments CPU 945 Manual Communications Capabilities Jumper settings on the RS422-AI485 module These jumpers are inserted as shown in Figure 12.40 when the module is supplied. In this way the RS422-AI485 module is ready for immediate use. Front connector 15-pole sub D socket - I X3 I7 Q ------- 3 Module connector IQ Figure 12.40 RS422-A/485 Module: Jumper Settings on Delivery EWA 4NEB 81 1 61 50-02d Communications Capabilities CPU 945 Manual Jumpers X10 and X1 1 can be used t o change the default f o r the two-wire line R, which enables t h e detection o f a wire break. 1 2 a a a No presetting f o r t w o - w i r e line R; the break cannot be detected definitely Presetting for detecting a wire break on the two-wire line R. All other jumper settings must n o t be changed. Standard connecting cables f o r RS422-A1485 module Standard connecting cables w i t h lengths o f up t o 1200 m (3900 f t ) are available for linking the RS422-AI485 module i n t h e CPU 945 and t h e partner. Standard cables connecting the CPU 945 and CP 524, CPU 945 and CPU 928B CPU 945 CP 524, CPU 945, CPU 928B I I I I I I I I I Housing, g r o u n d L - - - - - - Figure 12.4 1 RS422-AI485 Module: Cable Connecting the CPU 945 and CP 524, CPU 945, CPU 9286 CPU 945 Manual Communications Capabilities 12.7.5 SINEC L1 Module The SINEC L1 module enables the connection o f the CPU 945 t o the SINEC L1 LAN via i t s second interface. Other links permitted by the SINEC L1 module: Connection o f a programmer Point-to-point connection (with SINEC L1 protocol) ASClldriver Computer link The maximum permissible transmission rate is 9600 baud. The Figure below shows the connector pin assignments of the 15-pole Cannon connector in the front plate o f the SINEC L1 module (it corresponds t o the assignments of 511): M 12 13 14 + 2 0 mA -l-5.2 V 15 M Current source Figure 12.42 SlNEC L1 Module: Pin Assignments CPU 945 Manual Communications Capabilities Jumper settings on the SINEC L1 module The SINEC L1 module is supplied with the jumper settings shown in Figure 12.43. In this way, the SINEC L1 module is ready for use. r Front connector 15-pole sub D socket Figure 12.43 SINEC L1 Module: Jumper Settings CPU 945 Manual Communications Capabilities Connecting cable for point-to-point connection (SINEC L1 module) The following Figure shows the connecting cable for point-to-point links. Point-to-point connection (see Section 12.4) ASCII driver (see Section 12.5) Computer link (see Section 12.6) CPU 945 e.g. CPU 941 ... 945,9288, 102,103, S5-9OUl95U Figure 12.44 SINEC L1 Module: Connecting Cable for Point-To-Point Connection Use of programmer interface If you connect a programmer t o the SINEC L1 module, the same requirements and restrictions as for the programmer module are valid (see Section 12.7.1). EWA 4NEB 81 1 61 50-02d CPU 945 Manual Communications Capabilities 12.7.6 Technical Specifications of the interface Modules Table 12.36 Technical Specifications of the Interface Modules Degree of protection Ambient temperature Relative humidity Altitude Supply voltage as for CPU 945 (see Section 15) Transmission rate Programmer module V.24 module TTY module RS422-AI485 module SINEC L1 module Fixed 9 600 bitls max. 19 200 bitls max. 9 600 bitls max. 19 200 bitls max. 9 600 bitls Front socket connector Programmer module RS422-AI485 module V.24 module TTY module SINEC L1 module 15-pin Cannon 15-pin Cannon 25-pin Cannon 25-pin Cannon 15-pin Cannon Connecting cable Shielded four-wire cable (five-wire cable for RS422-A) with braided screen and metal connector housing; must be earthed at both ends) Cable lengths Programmer module max. RS422-AI485 module max. max. RS422-AI485 module max. 100 mA max. 500 mA 1 000 m 16m 1 000 m 1 200 m (3300ft) (52ft) (3300ft) (3900ft) 16.1 mm X 68.4 mm X 102.7 mm ........................... 13.2 Structure o f the Clock Data Area 13.3 Structure o f the Status Word 13.4 Backup of the Clock EWA 4NEB 81 1 61 50-O2d ............................... 13- 6 .................................. 13- 10 .......................................... 13- 12 ............... ......................... ........................................ 13.3 13.4 13.5 13.6 13.7 Clock Data Definition Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Meaning of the Clock Flags (Bits O,1, 2 and 3 of the Status Word) . . . . . . . . Meaning of Bits 4and 5 of the Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . Meaning of the Operating Hours Counter Flags (Bits 8, 9 and 10 of the Status Word) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Meaning of the Alarm Clock Flags (Bits 12, 13 and 14 of the Status Word) . 13- 8 13- 11 13- 11 13- 12 13- 12 EWA 4NEB 81 1 61 50-02d CPU 945 Manual Real-Time Clock Real-Time Clock The real-time clock offers the following methods of controlling the process: Alarm clock function e.g. for monitoring the duration of a process Operating hours counter e.g. for monitoring inspection intervals Real-time clock function e.g. for establishing the time at which the CPU stopped in the event of a fault The clock has an accuracy of k 2 seconds per day at a temperature o f 15 "C. This accuracy changes with temperature according t o the following formula: Temperature dependency (Tambin "C): At in ms/day= k2siday- 3.5 . (Tamb- 15)2 mslday Example: Tolerance at 40 " C: 13.1 k 2 siday - 3.5 - (40 - 15)2 msiday +ca. 0 t o 4 slday. Parameterizing the Real-Time Clock The real-time clock cannot be used unless you initialize a clock data area and a status word. The parameters can be assigned either in DBI (+ see Capter 11) or in system data 8 t o 10. The following information must be parameterized in system data 8 t o 10: Location o f the clock data area Location o f the status word Proceed as follows for parameterizing the clock: Initialization o f the real-time clock in the system data area The clock is initialized in a function block that you first have t o program. In this function block, you can store parameters in the relevant system data by means of transfer operations (e.g. "T RS, TNB"). It is advisable t o call the function block in the restart organization blocks OB 21 and OB 22. The location o f the clock data area and the status word is stored in system data words 8 t o 10. In these system data words, you can determine whether the area concerned is a flag/S flag area or a data block (DBIDX) and the exact location within the defined area. EWA 4NEB 811 61 50-02d Real-Time Clock CPU 945 Manual The operating system makes no standard assignments i n these system data cells so t h a t clock can only be accessed if t h e necessary parameters have been entered. Table 13.1 describes the meanings o f the individual bytes o f system data words 8 t o 10. System data 12 w i l l be explained subsequent toTable 13.1 and t h e following example. Table 13.1 System Data Area of the Clock 1 Operand area o f the clock ASCll characters: data Initial clock data address Operand area D Operand area X Operand area M Operand area S D f o r DB area X f o r DX area F f o r flag area S for S flag area DB number (DBO t o DB255) DX number (DXO t o DX 255) Flag byte number High-order part o f S flag number Initial clock data address (only relevant for operand Data word number D W 0 t o D W 255 areas D, X and S) For S: Low-order part o f S flag number I wOperand area o f t h e status ord ASCll characters: D f o r DB area X for DX area F f o r flag area S for S flag area I 10 1 Status word address I I Operand area D Operand area X Operand area M Operand area S I DB number (DBO t o DB255) DX number (DXO t o DX255) Flag word number High-order part o f S flag number Status word add ress (only relevant for operand Data word number D W 0 t o D W 255 areas D, X and S) For S: Low-order part o f S flag number Startup check o f t h e clock block 11 12 I Correction value* I * Checked and proc !ssed only once per hour Bits 0 and 1 are set when t h e clock is running CPU 945 Manual Real-Time Clock Parameterizing the clock Example: NAME Parameterizing the clock during restart of the PLC (OB21 and OB22) The clock data are t o be stored in DB2 from DWO. The status word is entered in flag word 10. :UHR-INIT TUDA : KS DR C l o c k d a t a a r e a is i n DR. NUDA : KY 2 , O H e r e : DB2 f r o m DWO TUSW : KS FW S t a t u s w o r d o f c l o c k i s a n FW NUSW : KY 1 0 , O Here: KF-l2 Correction value :L KM 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 P r e s e t s t a t u s word :T FW CORR: FWl0 (Here , e . g . 10 enabled, operating hours counter l a s t RUN-STOP c h a n g e s t o r e d , c l o c k t i m e u p d a t e d d u r i n g CPU S T O P ) Programming note: For dataarea DX + KSXB For5 flag area + DCSY NUDAINUSW: State the S flag number in the KY format (Example: 1,2 for 1 x 256 2 x 1 = 258) when using the S flag area TUDAITUSW: + EWA 4NEB 811 61 50-02d CPU 945 Manual Rea /-Time Clock DECL : TUDA I/Q/D/B/T/C: D KM/KH/KY/KS/KF/KT/KC/KG: KS DECL DECL : NUDA I/Q/D/B/T/C: D KM/KH/KY/KS/KF/KT/KC/KG: KY : TUSW : NUSW D D D KM/KH/KY/KS/KF/KT/KC/KG: DECL DECL I/Q/D/B/T/C: I/Q/D/B/T/C: I/Q/D/B/T/C: KS KY : CORR KM/KH/KY/KS/KF/KT/KC/KG: KM/KH/KY/KS/KF/KT/KC/KG: KF Operand area type for :LW :T :LW :T =TUDA FW 250 :LW =TUSW Operand area type for :T FW 253 :LW :T =NUSW FW 254 status word Address of status word L DH 0002 04FE DH OOOE 1014 :L =NUDA FW 251 : TNW 3 :LW =KORR :T RS12 :L KB +O :T :T MD 250 FW 254 : BE clock data Start address of clock data area Final address of source area (FW254) End address target area (RS10) FY 250-255 in RS 8 to 10 transfer. Enter correction value Delete scratch flag CPU 945 Manual Real-Time Clock KH = 0003; --,WEEKDAY KH = 1402; DAY, MONTH //Current time HOUR + AM/PM b i t KH = 8908; YEAR, KH = 0000; MINUTE, KH = 0102; LEAP YEAR, W E E K D A Y / / S e t t i n q KH = 0504; DAY, MONTH SECOND clock HOUR + AM/PM b i t KH = 9308; YEAR, KH = 0000; MINUTE, KH = 0002; --,WEEKDAY KH = 0504; DAY, KH = 0009; --,HOUR KH = 0000; MINUTE,SECOND SECOND //Prompt time (setting) MONTH + AM/PM b i t 12: KH = 0000; -,SECONDS / / C u r r e n t 1 3: KH = 0001; MINUTES, operating hours 1 4: KH = 0000; 1 5: KH = 0000; HOURS X 1 0 0 , HOURS X 1 0 0 0 0 - - ,SECONDS / / O p e r a t i n g hours s e t t i n g 16: KH = 0012; MINUTES, 17: KH = 0000; HOURS X 1 0 0 , HOURS X 1 0 0 0 0 18: KH = 0000; --,WEEKDAY 19: KH = 0000; DAY, MONTH 20: KH = 0000; YEAR, HOUR 21: KH = 0000; MINUTE, SECOND HOURS HOURS // C l o c k a f t e r STP/RUN 22: Correction Value To compensate for clock inaccuracy due t o the effect o f temperature, you can enter a correction value in system data word (RS) 12 (E 1018,). The correction value (in seconds) is based on an operating time o f 30 days, i.e. if you see that the clock o f the CPU has lost, say, 20 seconds in 30 days, the correction value is 20. Internally, the operating system corrects the clock every hour by a value smaller than one second. This ensures that the clock does not "jump" a second (the correction value is read and checked only once per hour). This compensation is unaffected by the mode selected, i.e. it functions in both STOP and RUN mode. Correction value range: - 400 t o 0 to+400 (no correction at "0"). You must specify the correction value in "KF" format. Following an OVERALL RESET, the default value "0" is in RS 12. + If a nonvalid correction value is used, the operating system sets b i t No.15 in RS 11; in this case, the correction value is "0". The time is not corrected on POWER OFF. On POWER-UP, the time correction is updated if the CPU had battery backup during this time. Real-Time Clock 13.2 CPU 945 Manuad Structure of the Clock Data Area The location o f the clock data area must be stored in system data words 8 and 9. Data is always exchanged between the control program and the integrated clock via the clock data area. The integral clock stores current values o f clock time, date and operating hours counter in the clock data area (flag1S flag area or data block (DBIDX)) and, in this same clock data area, the control program stores settings for prompting times and operating hours counters. The control program can only read or write t o the clock data area, but can never access the clock direct. Figure 13.1 illustrates this relationship. Read clock data with load operations Transfer variables with transfer operations *-- Clock writes clock data t o the clock data area Clock accepts settings from --+the clock data area Figure 13.1 Control Program and Clock Access to the Clock Data Area When setting the clock, you need only transfer the data required for implementing the function in question. For example, if you only want t o change the data for the clock function, you need not specify the data for the prompter function or for the operating hours counter. Table 13.2 gives information on the location of certain clock data within the clock data area, regardless of the memory area selected (DBIDX area or flag1S flag area). You will find explanations of the entries in the clock data area following Table 13.2. CPU 945 Manual Real-Time Clock Table 13.2 Clock Data in the Clock Data Area 21 RUNISTOP change or POWER OFF (only if bit No. 5 in the status word = 1) Please note the following: Entries in the clock data area must be in BCD. EWA 4NEB 81 1 61 50-02d Minute Second Real-Time Clock CPU 945 Manual By changing bit No. 1 in the status word, you can select the 12-hour or 24-hour mode for the clock (see Section 13.3) The AMIPM flag (0 = AM; 1 = PM) is only o f significance if the hardware clock is operating in 12-hour mode. It corresponds t o bit 7 o f the following words: - Word 2 - Word6 - Word l 0 - Word 20. In this mode, the hours and the AMIPM flag cannot be set independently o f each other when specifying the settings o f the clock and the prompting time. If an AMIPM flag is set in 24-hour mode, this is recognized when the settings for the clock and prompting time are entered and the relevant error bit is set. Settings must lie within the definition ranges given in Table 13.4: ta Definition .,...,.......,.,.,.,.,.,.,.,.,.......,...,.,...,.. .,.,.,.,.,.,.,...,... Seconds Minutes Hours Weekday 0 t o 59 0 t o 59 in 24-hour mode: 0 t o 23 in 12-hour mode: f o r A M lt o 1 2 (12 00.00 hours) for PM 81 t o 92 (92 noon if AMIPM bit set) 0 t o 99 i f operating hour counter specified 1t o 7 l=Sunday 2 = Monday 3 =Tuesday 4= Wednesday 5=Thursday 6 = Friday 7 =Saturday Day Month Year Leap year 1 t o 31 1 t o 12 0 t o 99 0to3 0 = Leap year is current year 1 =Leap year was last year 2 = Leap year was t w o years ago 3 = Leap year was three years ago Any other entries will lead t o operating system error messages which are flagged in the status word. If the settings are within the definition range, error bits in the status word are reset by the operating system the next time the clock, the prompting time or the operating hours counter is set. If a setting (prompting time or operating hours counter) is not t o be transferred t o the clock or if the current value is not t o be changed on entry o f the setting, enter "FF" (hexadecimal) for this variable. CPU 945 Manual Real-Time Clock If t h e clock data area is located at the end o f t h e individual areas (flags, data block) and if there is insufficient space for the clock data area, only t h e actual clock data transferred will be accomodated in this area. Settings outside t h e range are ignored. If t h e clock data is in t h e nonretentive flag area or nonretentive S flag area, all settings and t h e time o f t h e last RUNISTOP change w i l l be lost after POWER OFF or COLD RESTART! Please remember t h a t you can define t h e location o f t h e clock data area and t h a t the word numbers in Table 13.2 are relative. - If your data w o r d area is in a data block (DBIDX) and if it does n o t begin w i t h DW 0 b u t D W X, you must add t h e value X t o t h e w o r d number in Table 13.2. Example: Your clock data area begins a t DW 124. The data for clock timeldate are stored from DW 124 t o DW 127. - If you store the clock data area i n t h e flag area from flag w o r d 0, you must multiply t h e w o r d number given i n Table 13.2 b y a factor o f 2 i n order t o obtain t h e corresponding w o r d address. Example: Store t h e clock data area in t h e flags operand area from FW 0 onward. The operating hours counter data is stored from address FW 244 onward. If your clock data area does n o t begin a t flag word 0, you must add this value. Real-Time Clock 13.3 CPU 945 Manual Structure of the Status Word The status word can be scanned t o detect, for example, errors in the entry of clock settings, or alternatively, specific bits can be changed in the status word t o disable or enable transfer or read operations. The response o f the CPU when changing from RUN t o STOP or during POWER OFF can be determined with the bits (flags) reserved for this purpose. m The status word can be located in the flag area/S flag area or in a data block (DBIDX). The location must be defined in system data words 9 and 10. The clock runs independently of the mode set. Updating of the clock data area is dependent on the mode set and the states o f bits 4 and 5 o f the status word. You can set or reset these bits with "S" or "R" operations in the control program. When monitoring the program with an operator panel (e.g. the OP 396),it is advantageous t o have the CPU update the clock (current date) also in STOP mode. The "Transfer settings" bits (bits 2, 10 and 44 in the status word) are reset by the operating system i f - the settings have been transferred - the settings have not been transferred because they were outside the permissible range. In this case, the relevant error is set (bits 0,8 and 12 o f the status word). The "Transfer settings" bits (bits 2,10 and 14 of the status word) are not reset by the operating system if - the system data for the clock are incorrect or not available - the clock data area is too small The bits o f the status word are divided into - clock flags - operating system flags - operating hours counter flags - prompting time flags. EWA 4NEB 81 1 61 50-02d CPU 945 Manual Real-Time Clock Tables 13.4 t o 13.7 contain information on the meaning of the signal states of the flags. Clock Flags Table 13.4 Meaning of the Clock Flags (Bits 8,1,2 and 3 of the Status Word) 0 1 3 1 Error when entering settings 0 No error when entering settings 1 12-hour representation (clock mode) 0 24-hour representation (clock mode) 1 Transfer settings 0 Do not transfer settinqs 1 Clock time can be read 0 Clock time cannot be read Operating System Flags Table 13.5 Meaning of Bits 4and 5 of the Status Word STOP The clock updates only words 0 t o 3 in the clock area (current clock time1 current date). The clock can be set with the "FORCE VAR" programmer function. The clock does not update the clock data area. Word 0 t o 3 contain the time o f the last RUNISTOP change. Words 18 t o 21 contain the time of the last RUNISTOP change o r t h e time o f the last POWER OFF i f bit 4 is also set. Words 18 t o 21 are not used. RUN The clock updates the clock data area continuously (words 0 t o 17). Words 18 t o 21 contain the time of the last RUNISTOP change or the time o f the last POWER OFF. Words 18 t o 21 are not used. Real-Time Clock CPU 945 Manual Operating Hours Counter Flags Table 13.6 Meaning of the Operating Hours Counter Flags (Bits 8,9 and 10 of the Status VVord) :;:;:;:;:>;:;:;:;:;~@.~:j:~;:j:;:X;:;:;:~jjjj~::::~:::~:j::::::~:~:~j:j:>~*:I:;: ; @ J @ : ~ ~ @ ~ M : @ # $ g ~ ~ $ $ $ $ ~ ~ $ ........ ........................... .... ..... ...,.,. .. ..... .. .. Error when entering settings . .. . :.j::::::::::j::::::::::::::::::j::::s:::::r.g.p . . ..... .... ..... ........................................................................................................................... 1 8 9 10 0 No error when entering settings 1 0 Enable operating hours counter 1 0 Transfer settings Disable operating hours counter Do not transfer settings Alarm Clock Flags Table 13.7 Meaning of the Alarm Clock Flags (Bits 12.13 and 14 of the Status Word) l II 1 l2 I3 3d a- Error when entering settings 1 0 1 0 I 1 0 No error when entering settings Set prompting time reached I I Set prompting time not reached Transfer settings Do not transfer settings Bits 6,7,11and 15 are required by the operating system, and cannot be used by the user. 13.4 Backup of the Clock With battery backup, the clock will continue t o operate even after "POWER OFF". If the PLC does not have battery backup, the clock will show the settings 01 .01.93 12.00.00,Weekday: 6 when the clock is initialized following "POWER ON". The 24-hour mode is set as default. Batteries should therefore only be changed while the power is on, otherwise the clock data will be lost. CPU 945 Manual '13.5 ReaLTime Clock Programming the Clock Transferring Settings t o the Clock Settings are stored in the clock data area with Transfer operations (see Table 13.2). The AMIPM flag (bit No. 7) is onlysignificant in 12-hour mode. Bit7-1 +PM Bit7=O+AM Clock data must be transferred in BCD. If a setting is not t o be transferred, identify the corresponding byte with the number "255," "FF,". The value of this variable in the clock is then retained when the clock is set. or Once you have transferred the settings t o the clock data area, you must set bit 2 o f the status word before the clock can accept the clock data. After completing the transfer of clock data t o the clock, bit 2 o f the status word is reset. Incorrect settings are flagged in the status word by setting bit 0. The clock continues t o operate with old values. Example: Transferring new settings (clock timeldate) t o the clock, using the programmer. The clock is t o be set with the following data: MO 05.04.93; 12:OO:OO. The status word is assigned t o flag word 10 and the clock data is stored in DB2 from data word 0. The settings for the clock data are transferred: With the "FORCE VAR" programmer function i f the PLC is in RUN Mode With the "FORCE VAR" programmer function if the PLC is in STOP mode and status word bit4-1. Note When using the "FORCE VAR" function, you must enter the clock data first and then the status word. 7 EWA 4NEB 81 1 61 50-02d Rea /-Time Clock CPU 945 Manual Leap year was last year and weekday (MO) Date (05) and month (04) Year (93) and hour (12) Minute (00) and second (00) Bit 4= 1: Clock data area is updated during Bit 2= 1: Transfer settings or KM = 0000 0000 0000 04 00 FW 10 In "RUN" mode only: Bit 4=0: Clock data are not updated during "STOP". Bit 2 = 1: Transfer settings A. Example: Program for setting clock time and date. Settings for clock time and date are transferred depending on the signal state at input 12.1. These settings must be transferred t o flag bytes 120 and 127 before setting input 12.1 (cf. OBI). Values which are not t o be changed must be preset with FFH. Clock mode can be defined with input 14.0 (1 = 12-hour mode). Input 13.0 is the AMIPM bit for 12-hour mode. The clock data area is in DB2 from DW 0, and the status word is FW 10. S E T T I N G CLOCK TIME AND DATE LOAD time and date values into FY 1 2 0 t o FY 1 2 7 first! :A I 12.1 clock setting triggered :S F 20.0 by setting F 2 0 . 0 :JU FB 10 (reset in FB 1 0 ) NAME :SETCLK LPYR : FY 1 2 0 LEAP YEAR WDAY: FY121 WEEKDAY DAY : FY122 MON : FY123 YEAR : FY 1 2 4 HOUR : FY 1 2 5 AMPM: I MIN : FY 1 2 6 SEC : FY127 SECONDS ERR : F 12.1 ERROR B I T MODE : I 14.0 1 2 - H R MODE: I 1 4 . 0 :BE 13.0 AMPM B I T (ONLY IMPORTANT I N 1 2 - H R MODE) = 1 Real-Time Clock CPU 945 Manual DECL DECL DECL :LPYR :WDAY :DAY DECL DECL DECL : MON :YEAR :HOUR DECL :AMPM DECL DECL DECL DECL I/Q/D/B/T/C: I BI/BY/W/D: BY I/Q/D/B/T/C: I/Q/D/B/T/C: I I BI/BY/W/D: BI/BY/W/D: BY BY I/Q/D/B/T/C: I BI/BY/W/D: BY I/Q/D/B/T/C: I BI/BY/W/D: B1 :MIN I/Q/D/B/T/C: I BI/BY/W/D: BY :SEC :ERR :MODE I/Q/D/B/T/C: I/Q/D/B/T/C: I/Q/D/B/T/C: I Q I BI/BY/W/D: BI/BY/W/D: BI/BY/W/D: BY B1 B1 :A . =MODE F 11.1 :AN F 20.0 24-HR mode = 0, 12-HR mode read i n t o clock data a r e a :C DB Clock d a t a a r e a :L =LPYR :T DL :L =WDAY :T DR :L :T :L =DAY DL 5 S t o r e v a l u e f o r DAY =MON S t o r e v a l u e f o r MONTH :T DR :L =YEAR S t o r e v a l u e f o r YEAR :T :L DL 6 =HOUR S t o r e v a l u e f o r hour S t o r e v a l u e f o r LEAP YEAR 4 S t o r e v a l u e f o r WEEKDAY 4 5 :ON =AMPM I F 12-HR mode i s s e t , and :ON AMPM b i t =MODE :JC =MORN :L KH 0080 MORN :T DR :T :L DL 7 =SEC :T DR :L :SV M001 :A l (afternoon), t h e S t o r e v a l u e f o r MINUTES =MIN :S = r e l e v a n t b i t i n t h e clock a r e a 6 :L :AN F l Flag is r e s e t i f s e t t i n g s a l r e a d y :JC =M001 :R F 20.0 2 = ( c l o c k mode s t a t u s word b i t I ) S t o r e v a l u e f o r SECONDS 7 11.2 Transfer s e t t i n g s 11.2 KT 020.1 S t a r t monitoring time T T BEC, i f m o n i t o r i n g t i m e F ( S t a t u s word i s FW10) 10 10 not y e t elapsed Real-Time Clock CPU 945 Manual :AN F :JC =M002 if Y E S , :AN F Error when entering settings? :RB =ERR 11.2 Have settings been Transferred? 11.0 j u m p to M002 Reset error bit if NO BEC if no error M002 :S =ERR Set error bit if error Reading the Current TimeIDate Current data is stored in the first four data words o f the clock data area. This data can be read out from there with Load operations. To be able t o read a correct time, bit 3 o f the status word must be set in the control program before the read access. The clock data area is no longer updated when bit 3 is set. You must reset this bit after reading the clock. Setting bit 3 in the status word I Reading the time from the clock data area Resetting bit 3 in the status word Figure 13.2 Procedure for Reading the Current Date/Time CPU 945 Manual Example: Real-Time Clock Reading the time and the date. The time is stored i n flag bytes 30 t o 36 depending o n an external event, simulated here by a positive edge a t input 12.0. Flag 13.1 indicates which mode t h e clock is operating in. Flag 13.0 is the AM/PM b i t in 12-hour mode. The clock data area is i n DB2 from DW 0 onwards, and t h e status word is FW 10. READING TIME AND DATE -------------------------------- ----P--------------------------- :A I 12.0 :AN F 0.1 T i m e and d a t e a r e t o be s t o r e d i n FY 3 0 to FY 3 6 i n the c a s e of p o s i t i v e edqe a t I 1 2 . 0 (external event). : J C FB 13 NAME :READCL WDAY : FY 30 DAY : FY 31 MON : FY 32 WEEKDAY YEAR: FY 33 HOUR : FY 34 HOUR AMPM: F 13.0 F13.0=1, M I N : F Y 3 5 MINUTES SEC FY 36 SECONDS F 13.1 F13.1=1, I F 12.0 0.1 : MODE: :A .= :BE a f t e r n o o n i n 1 2 - H R mode i n 1 2 - H R mode CPU 945 Manual Real-Time Clock NAME :READCL READING THE CLOCK DECL :WDAY DECL :DAY DECL :MON DECL :YEAR Q BI/BY/W/D: BI/BY/W/D: BY BY I/Q/D/B/T/C: Q BI/BY/W/D: BY Q DECL :HOUR I/Q/D/B/T/C: I/Q/D/B/T/C: BI/BY/W/D: BI/BY/W/D: BY BY DECL :AMPM DECL :MIN I/Q/D/B/T/C: I/Q/D/B/T/C: Q Q BI/BY/W/D: BI/BY/W/D: B1 BY DECL :SEC DECL :MODE I/Q/D/B/T/C: Q BI/BY/W/D: BY :SU F I/Q/D/B/T/C: I/Q/D/B/T/C: Q 11.3 :C :L DB DR :T =WDAY :L DL 1 =DAY DR 1 :T :L 0 =MON L DL :T =YEAR DR 2 KH 007F 2 :A =HOUR D 2.7 :L DL :T :L =MIN DR 3 :T =SEC :RU :A F F :T Time can be read (set bit 3 in the status word) 2 :T :L :L Q Erase AMPM bit (only relevant in 12-HR mode) DPsplay AMPM bit (only relevant in 12-HR mode) 3 11.3 11.1 time is updated again Display clock mode MODE = 1, IN 12-HR mode CPU 945 Manual Real-Time Clock Storing the Current TimeIDate After a RUNISTOP Change Note This clock data area is only written t o if b i t 5 in t h e status word is set t o "1 " a RUNISTOP change or a POWER OFF has taken place t h e necessary memoryspace is available i n t h e operand area This enables you t o detect a RUNISTOP change or a POWER OFF even if the PC has since gone back t o RUN mode. The time and date o f t h e last RUNISTOP change or POWER OFF are i n words 18 t o 21 (see Table 13.2). If several RUNISTOP changes have occurred before you read o u t this clock data area, you will only be able t o determine t h e time o f t h e last change. If you d o n o t have sufficient memory f o r this clock data area, you cannot use this area or only part o f it. This has no other effects. Programming t h e Prompt Function Transferring Settings t o the Clock The settings are stored i n t h e clock data area using Transfer operations (4see Table 13.2). The AMIPM flag (bit No. 7) is only significant i n 12-hour mode Bit7=1+PM Bit 7=O-+AM The clock data must be transferred i n BCD. If you enter t h e number "255," or "FFHWi n a byte i n t h e prompting time, this byte w i l l be ignored w h e n evaluating "Prompt time reached". This makes it easy t o program, f o r example, a prompt which is repeated daily by entering t h e value "255, or FFH" in the "Weekday", "Date" and "Month" variables. ~ - Transfer o f t h e prompt function settings t o t h e clock is initiated by b i t 14 i n the status word. Incorrect settings are flagged by b i t 12 i n t h e status word. CPU 945 Manual Real-Time Clock Prompter Time Sequence B i t 13 in the status word is set after the prompter time has elapsed. B i t 13 remains set until you reset it in the control program. The prompting time can be read at any time. /I\ Caution If the prompting time is reached in STOP mode or in POWER OFF, the prompting time bit is not set. Example: Setting and evaluating the prompting time. In the example program, the settings for the prompting time are transferred as a function of the state o f input 12.2. You must transfer the settings t o flag bytes 130 and 135 before setting input 12.2. Values that are not t o be changed must be preset with FFH. The clock mode is set with input 14.0. Use input 13.0 t o set the AMIPM bit for 12-hour mode. Flag 13.2 is set when the preset prompting time has been reached. Any errors made when entering the promptertime are flagged in F 12.2. The clock data is stored in DB2 from DW 0 onwards, and the status word is FW 10. ......................................... ......................................... SETTING AND EVALUATING THE PROMPTING TIME ......................................... Load values into FY130 to FY135 :A I 12.2 :S F 20.1 :JU FB 11 NAME :WECKZ-ST WDAY : FY 130 DAY : MON : HOUR: AMPM: FY131 FY 132 FY133 MIN SEC : FY134 FY135 ERR : : ALRM: MODE : I F F I first! Initiate setting of prompting time by setting F 20.1 (reset in FB11). 13.0 12.2 13.2 14.0 WEEKDAY DAY MONTH HOUR AMPM-BIT (only important in 12-HR mode) MINUTES SECONDS Error bit Flag for prompting time reached 12-HR-mod: I 14.0 = 1 :BE EWA 4NEB 81 1 61 50-02d CPU 945 Manual Real-Time Clock NAME DECL DECL :WECKZ-ST :WKDAY I/Q/D/B/T/C: I BI/BY/W/D: SETTING THE PROMPTING TIME BY : DAY I/Q/D/B/T/C: I BI/BY/W/D: BY DECL :MON I/Q/D/B/T/C: I BI/BY/W/D: BY DECL DECL DECL DECL :HOUR : AMPM I/Q/D/B/T/C: I/Q/D/B/T/C: I I BI/BY/W/D: BI/BY/W/D: BY B1 : MIN :SEC I/Q/D/B/T/C: I BI/BY/W/D: BY I/Q/D/B/T/C: I BI/BY/W/D: BY DECL DECL :ERR :ALRM I/Q/D/B/T/C: I/Q/D/B/T/C: Q Q BI/BY/W/D: BI/BY/W/D: B1 B1 DECL :MODE I/Q/D/B/T/C: I BI/BY/W/D: B1 24-HR mode = 0, 12-HR mode (Set clock mode) 1 :A =MODE . :A :S F 11.1 F 10.5 =ALRM Display prompting time reached :R F 10.5 Reset bit after evaluation :AN F 20.1 :JC =M001 = (Bit 13 in the status word) Flag is reset if settings have been read into the clock data :R F :C :L DB :T DR :L :T =DAY DL 9 Store value for DAY :L =MON Store value for MONTH :T DR 20.1 2 =WKDAY area Clock data area Store value for WEEKDAY 8 9 Real-Time Clock - :ON =AMPM if AMPM :ON =MODE 12-HR mode are set, the :JC =MORN KH 0080 data area will be set :L MORN CPU 945 Manual :T DR :L =MIN l (afternoon) arid corresponding bit on the clock 10 Store value for MINUTES DL l 1 :L =SEC :T DR l1 :SU F 10.6 Transfer settings :L Start monitoring time :T Store value for SECONDS (Bit 14 in status word FW 10) KT 020.1 11 :SE T MOO1 :A T 11 F 10.6 : BEC :A BEC if monitoring time not yet elapsed Have settings been transferred? :JC =M002 If NO, jump to M002 :AN F Error when entering settings? :RB 10.4 =ERR if NO, reset error bit BEC if no errors =ERR If error, set error bit :BEC M002:S :BE - Programming t h e Operating Hours Counter The operating hours counter is enabled w i t h b i t 9 o f t h e status word. This allows you t o establish, f o r example, t h e number o f hours a m o t o r has been i n operation. The operating hours counter is only active i n RUN mode. Transferring Settings t o t h e Operating Hours Counter Y o u can preset t h e operating hours counter t o a specific initial value (e.g. after change o f CPU). The clock data must b e transferred i n BCD. Real-Time Clock CPU 945 Manual If a variable is not t o be transferred when you are entering settings for the operating hours counter, identify the relevant byte with the number "255," or "FF,". The value of this variable in the operating hours counter will then be retained when setting the counter. After you have transferred the settings t o the clock data area, you must set bit 10 of the status word t o have the clock data area accepted by the clock. Incorrect settings are flagged by bit 8 in the status word. Example: Setting the operating hours counter Transferring the settings for the operating hours counter is a function of the state of input 12.3. You must transfer these values t o flag bytes 136 t o 140 before setting input 12.3 (not implemented in the example program). Values that are not t o be changed should be preset with FFH. Incorrect settings are flagged in F 12.3. The clock data area is in DB2 from DW 0 onwards, and the status word in FW 10. S E T T I N G THE OPERATING HOURS COUNTER ................................... ................................... Load v a l u e s i n t o FY 1 3 6 t o FY 1 4 0 :A 1 12.3 I n i t i a t e t r a n s f e r of s e t t i n g s f o r :S F 20.2 o p e r a t i n g h o u r s c o u n t e r by s e t t i n g :JU FB 12 NAME :BETRST- S SEC : MIN : FY 1 3 6 FY 1 3 7 HOURO: FY 1 3 8 HOURS HOUR2: FY 1 3 9 HOURS X 1 0 0 HOUR4 : FY 1 4 0 HOURS X 1 0 0 0 0 ERR F ERROR B I T : :BE 12.3 Real-Time Clock CPU 945 Manual DECL : S E C DECL :M1 N I/Q/D/B/T/C: I BI/BY/W/D: DECL :HOUR0 I/Q/D/B/T/C: I BI/BY/W/D: BY DECL :HOUR2 I/Q/D/B/T/C: I BI/BY/W/D: BY DECL :HOUR4 I/Q/D/B/T/C: I BI/BY/W/D: BY DECL :ERR I/Q/D/B/T/C: Q BI/BY/W/D: B1 :AN F :JC =M001 :R F :C DB :L =SEC :T DR :L =MIN :T DL 20.2 BY F l a g i s reset i f s e t t i n g s h a v e a l r e a d y b e e n read i n t o t h e 20.2 2 c l o c k d a t a area C l o c k d a t a area S t o r e v a l u e for SECONDS 15 S t o r e v a l u e f o r MlNUTES 16 :L =HOUR0 :T DR S t o r e v a l u e f o r HOURS 16 :L =HOUR2 :T DL S t o r e v a l u e f o r HOURS X 1 0 0 17 :L =HOUR4 T DR 1 7 S t o r e v a l u e f o r HOURS X 1 0 0 0 0 :AN F 10.2 :S F 10.2 ( B i t 1 0 i n s t a t u s w o r d FW 1 0 ) :S F 10.1 Enable operating hours counter :L KT 0 2 0 . 1 :SE T 12 T 12 BEC i f m o n i t o r i n g t i m e n o t y e t :AN F 10.2 Have s e t t i n g s b e e n t r a n s f e r r e d ? :JC =M002 :AN F :RB =ERR Transfer settings i f not already enabled M001 :A 10.0 start m o n i t o r i n g t i m e i f NO, j u m p t o M002 E r r o r when e n t e r i n g s e t t i n g s ? i f NO, reset e r r o r b i t BEC i f n o error M002:S =ERR i f error, s e t e r r o r b i t EWA 4NEB 81 1 61 50-02d CPU 945 Manual Real-Time C/ock Reading the Current Operating Hours The current data is stored in words 12 t o 94 of the clock data area. The data can be read from there with Load operations. Bit 9 in the status word of the control program must be reset before the read access in order t o be able t o read the operating hours counter correctly. The clock data area is no longer updated when bit 9 is reset. You must set this bit again after reading the clock. the status word Read the operating hours from the clock data area Set b i t 9 in the Figure 13.3 Procedure for Reading the Operating Hours Counter Example: Reading the operating hours counter A machine is t o be switched o f f after 300 hours of operation for inspection purposes. Flag 12.4 is set when the machine is switched off. After 300 hours of operation, a jump is made t o PB5 t o switch the machine off (not programmed in the example). The clock data area is in DB2 from FW 0 onwards, and the status word is FW 10. NAME : BETR-LES Real-Time Clock NAME CPU 945 Manual :B E T R - L E S :A F READING T H E O P E R A T I N G HOURS COUNTER 12.4 I f a u x i l i a r y f l a g 1 2 . 4 is s e t , t h e m a c h i n e is a l r e a d y off. 10.1 :RU F :C DB 2 :L DL 14 :SU F 10.1 :T, KB003 --> block END Disable operating hours counter ( B i t 9 i n t h e s t a t u s word) DB c o n t a i n i n g c l o c k d a t a . L o a d HOUR VALUE x 1 0 0 i n t o Enable operating hours counter Compare w i t h 3 (= 300 h o u r s ) END i f :S F :JU PB 12.4 5 300 h o u r s n o t y e t Set auxiliary flag Jump t o P B 5 when 300 o p e r a t i n g hours reached :BE 14.1 Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . * * . * . . . . . 14.1.1 Failure Characteristics of Electronic Devices . . . . . . . . . . . . . . . . . . . . . 14.1.2 Reliability of SlMATlC S5 Programmable Controllers and Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.1.3 Failure Distribution . . . . . . . . . . . . . . . . . . .. . . .. . . . . . . . . . . . m m 14.2 Availability 1414- 2 3 14- 4 -. ......................... ............................................. .............................................. 14- 5 14- 5 14- 6 ...................ooo Summary 1 2 .................................................. 14.3 Safety 14.3.1 TypesofFailures 14.3.2 SafetyMeasures 14.4 1414- .................... . . m m ......................... 14- 7 . ble Controllers O ~ ~ . . ~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14- S Reliability#Availability and Safety of Electronic Control Equipment CPU 945 Manual 14 Reliability, Availability and Safety of Electronic Control Equipment The terms reliability, availability and safety o f electronic control equipment are n o t always clear and sometimes even misinterpreted. This can be explained on the one hand by t h e different failure characteristics o f electronic control systems compared w i t h conventional systems. On t h e other hand, some o f t h e safety regulations have been made considerably more stringent i n a number o f application areas i n t h e course o f t h e last f e w years. The following chapter is intended t o familiarize t h e large number o f users o f SlMATlC electronic control systems w i t h t h e basics o f this problem complex. The information given is o f a predominantly fundamental nature and applies regardless o f t h e type o f electronic control system and its manufacturer. 14.1 Reliability Reliability is the capability o f an electronic control system t o satisfy, over a specified period and within t h e specified limits (i.e. technical data), t h e requirements placed upon it by i t s application. Despite all t h e measures taken t o prevent failures, there is no such thing as 100 % reliability. The failure rate A is a measure o f t h e reliability: A= n No X t EWA 4NEB 81 1 61 50-02d and n = Number o f failures during time t No= Remaining components CPU 945 Manual Reliability, Availability and Safety o f Electronic Control Equipment 14.1. l Failure Characteristics of Electronic Devices The failure-rate-versus-time curve can be broken down roughly into three periods of time. A I Early Failures A (1 I I I I I I I I I I I Random Failures (2) I I I I I I I I I I I I I I I I S I I I I I I I I I I I I I I I I I I I I I I I I 0 104 (3) I I I I I I I Wear-out Failures 1O6 b tin h p Figure 14.1 Failure Characteristics of Electronic Devices ("Bathtub" Curve) (1) Early failures are caused by material and manufacturing defects and the failure rate falls steeply during the initial period of operation. (2) The random failure phase is characterized by a constant failure rate. Provided the systems are used in accordance with the specifications, only random failures occur during this period. This period covers the normal behaviour o f system components and is the basis for the calculation o f all reliability parameters. (3) The failure rate increases with time. Wear-out failures become more frequent, indicating that the end o f the useful life is approaching. The transition t o this phase is gradual. There is no sudden increase in the failure rate. 14.1.2 Reliability of SlMATlC S5 Programmable Controllers and Components A very high degree of reliability can be achieved by taking the following extensive and costintensive measures during the development and manufacture of SIMATIC S5 systems: The use o f high-quality components; Worst-case design of all circuits; Systematic and computer-controlled testing o f all components supplied by subcontractors; Burn-in o f all LSI circuits (e.g. processors, memories etc.); Measures t o prevent static charge building up when handling MOS ICs; Visual checks at different stages of manufacture; In-circuit testing o f all components, i.e. computer-aided testing of all components and their interaction w i t h other components in the circuit; Continuous heat-run test at elevated ambient temperature over a period o f several days; Careful computer-controlled final testing; Statistical evaluation of all failures during testing t o enable the immediate initation o f suitable corrective measures. Reliability, Availabilityand Safety of Electronic Control Equipment CPU 945 Manual 14.1.3 Failure Distribution Despite the extensive measures described above, one must s t i l l reckon with the occurence of failures. Experience has shown that, in installations with programmable controllers, failures can be distributed approximately as follows: Enhancement of availability by programmed diagnostic functions ! S I Processor I I I I ) Memory I I l I I + I ~failures nternad A Failures = - 5% 95 % functions 10 % each 25 % B us system 90 % InputIOutput modules p External failures Plant Control system Central unit Figure 14.2 Distribution of Failure Occurrences in lnstallations Incorporating Programmable Controllers Meaning o f error distribution: Only a small number (approx. 5 %) of failures occur inside the electronic control system. These can be broken down as follows: - CPU failures (about 10 %, i.e. only 0.5 % o f all failures); these failures are evenly divided among the processor, memory, bus system and power supply- I10 module failures (about 90 %, i.e. only 4.5 % of all failures) The highest number o f all failures (about 95 %) occur in the sensors, actuators, drives, cabling etc. EWA 4NEB 81 1 61 50-02d Reliability, Availability and Safety of Electronic Control Equipment 14.2 CPU 945 Manual Availability Availability "V" is the probability o f finding a system in a functional state at a specified point in time. V= MTBF MTBF + MTTR MTBF= MTTR= Mean Time Between Failures; Mean Time To Repair; Ideal availability, i.e. V = l , can never be attained owing t o the residual failure probability that always exists. However, it is possible t o get near this ideal state by using, for example, voter systems. Such systems include the following: Standby sytems 2-out-of-3 voter systems Multi-channel voter systems with mutual check functions (for maximum safety requirements). Availability can also be enhanced by reducing the mean time t o repair. Such measures include, for instance: the stocking o f spare parts the training o f operating personnel fault indicators on the devices higher memory and software overhead for implementing programmed diagnostic functions. CPU 945 Manual 14.3 Reliability, Availability and Safety o f Electronic Control Equipment Safety 14.3.1 Types of Failures The nature o f a failure is decided by t h e effect it has. A distinction is made between active and passive failures, as well as fatal and non-fatal failures. Example: Control o f function "F," Schematic circuit diagram: Pushbutton T Enabling signals a b C l 1 1 r Input Control System Output 0 1 No fault No output command Output command 0 1 Active failure Passive failure Output command No output command 1' Figure 14.3 Control of Function "F," Depending o n t h e job a control system has t o do, active or passive failures can also be fatal faults. Examples: In a drive control system, an active failure results i n t h e unauthorized starting o f t h e drive. In an indicating system, a passive fault can be fatal since it blocks t h e indication o f a dangerous operating state. In all cases where t h e occurence o f failures can result in severe material damage or even injury t o persons, i.e. where t h e failure may be dangerous or fatal, measures must b e taken t o enhance the safety o f t h e control system. In this connection, t h e relevant regulations and specifications must be observed. Reliability, Availability and Safety of Electronic Control Equipment CPU 945 Manual 14.3.2 Safety Measures Single-Channel Configurations In the case of single-channel programmable controllers, the means available for enhancing safety are limited: Programs or parts can be stored and executed more than once. Outputs can be monitored per software by parallel feedback t o inputs o f the same device. Diagnostic functions within the programmable control system, which bring the output of the controller into a defined state (generally the FF state) when a failure occurs. Failure characteristics of electromechanical and electronic control systems: Relays and contactors pick up only if a voltage is applied t o the coil. With such a control element, therefore, active failures are less probable than passive failures. In electronic control systems, however, the probability of both types of failure occurring (active and passive) is approximately equal. The failing o f an output transistor, for instance, may cause this transistor t o become either continuously non-conducting or continuously conducting. The safety o f electronic control systems can therefore be enhanced as follows. All functions not relevant t o the safety of the plant are controlled electronically. Functions that are relevant t o the safety of the plant are implemented with conventional control elements. Multi-Channel Configurations If the measures taken t o improve safety in single-channel control systems are not sufficient t o satisfy safety requirements, electronic control systems should be designed as redundant, i.e. multichannel, systems. Two-channel control systems Both "channels" monitor each other mutually and the output commands are evaluated on a "l-out-of-2" or "2-out-of-2" basis. Typical PLC: 55-115F This programmable controller consists o f t w o submits that are identically programmed and operate in clock synchronism; monitoring is implemented via t w o comparator modules. Failures are displayed and the corresponding safety functions initiated. Multi-channel control systems Further voter systems (e.g. on the 2-out-of-3 principie) can be implemented by adding further "channels". CPU 945 Manual 14.4 Reliability, Availability and Safety of Electronic Control Equipment Summary In electronic control systems, failures o f any kind can occur a t any point in t h e system. Even when t h e greatest efforts are made t o obtain maximum reliability, t h e probability o f such a failure occurring can never be zero. The dollowing is decisive for t h e effects o f such failures: depending on t h e j o b a control system has t o do, active or passive failures may be fatal or non-fatal. When safety requirements are very high, fatal failures must be recognized by taking additional measures and prevented f r o m affecting other parts o f the system. In t h e case o f single-channel systems, t h e means available t o do this are relatively limited. For this reason, safety-oriented functions should generally be implemented outside the electronics by interposing conventional components. In order t o satisfy safety functions, electronic control systems should be o f t h e multi-channel (redundant) type. These fundamental considerations are independent o f - t h e type o f control systems (hard-wired or programmable) - t h e vendor - t h e country o f origin (Europe, US, etc.). EWA 4NEB 81 1 61 50-02d 15.1 General Technical Specifications .............................. 15.2 Description of Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.1 Mounting Racks (CRs. ERs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.2 Power Supply Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.3 CentralProcessingUnits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.4 Digital input Modules . . . . . . . . . . . . . . . . . . . . . . . . . .. ... . . .. . . . . .. 15.2.5 Digital Output Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.6 Digital InputIOutput Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.7 Analog Input Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.8 Analog Output Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.9 Signal Preprocessing Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.10 Communications Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.1 1 Interface Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.12 The 313 Watchdog Module . . . . . . . . . . . . . . . . . . . . . . . . . ... . ...... 15.3 Accessories EWA 4NEB 81 1 61 50-02d .......................... 15- 1 15- 5 15- 5 15- 10 15-15 15- 16 15- 26 15- 39 15- 40 15- 45 15- 51 15- 52 15- 53 15- 55 15.1 15.2 15.3 Overview of Signal Preprocessing Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview of Communications Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ijbersicht uber die Anschaltungsbaugruppen . . . . . . . . . . . . . . . . . . . . . . . . . . 15- 51 15- 52 15- 53 EWA 4NEB 81 1 61 50-02d CPU 945 Manual Technical Specifications Technical Specifications 15.1 General Technical Specifications The general technical specifications include standards and test specifications which the 55-115U meets and fulfills and which were used during testing of the 55-115U. ULICSA Approbations The following approbations have been granted for the 55-115U: UL-Recognition Mark Underwriters Laboratories (UL) t o ULstandard 508, Report 116536 CSA Certification Mark Canadian standard Association (CSA) t o C22.2 standard No. 142, Report LR 48323 CE-Marking Our products meet the requirements of EU directive 89/336/EEC "Electromagnetic Compatibility" and the harmonized European standards (EN) listed therein. <f In accordance with the above-mentioned EU directive, Article 10, the EU declarations of conformity are held at the disposal of the competent authorities at the address below: Siemens Aktiengesellschaft Bereich Automatisierungstechnik AUTE 14 Postfach 1963 D-92209 Amberg Federal Republic o f Germany Area of Application SIMATIC products have been designed for use in the industrial area. With individual approval, SIMATIC products can also be used in the domestic environment (household, business and trade area, small plants). You must acquire the individual approval from the respective national authority or testing board. Individual approval I EN 50082-1 : 1992 I Observing the Installation Guidelines S5 modules meet the requirements if you observe the installation guidelines described in the manuals when installing and operating the equipment (-+ Section 3). EWA 4NEB 81 1 61 50-02d Technical Specifications CPU 945 Manual Notes for the Machine Manufacturer The SlMATlC programmable controller system is not a machine as defined in the EU Machinery Directive. There is therefore no declaration of conformity for SlMATlC with regard t o the EU Machinery Directive 891392lEEC. The EU Machinery Directive 891392lEEC regulates requirements relating t o machinery. A machine is defined here as an assembly o f linked parts or components (see also EN 292-1, Paragraph 3.1). SIMATC is part o f the electrical equipment o f a machine and must therefore be included by the machine manufacturer in the declaration of conformity procedure. The EN 60204-1 standard (Safety of Machinery, Electrical Equipment o f Machines, Part 1, Specification for General Requirements) applies f o r t h e electrical equipment of machinery. The table below i s designed t o help you with the declaration o f conformity and t o show which criteria applyto SIMATIC according t o EN 60204-1 (as at June 1993) > j ~ < < : j : j < : j : j < : j : j : j : s ~ : j : j : j : j : j : ~ ~ : j : j j j ~ j j j j j j j j j j j j j j j j j $ i i g : ~ j j j j j : : : : : : : : j ~ ~ . ~ ~ : j j j j : ~ j j : ~ ~ < : j < : j : j : j : j : j : j : j : j : j < : ~ : j : j : j : s :::::::::j:j:j:j:j:j:j:j:j:j8>j:sgj~j~:j:j:j:j:j:j$,$,~j<:j:j:j:j<:::j:j:j:j:j:j:j:~<:j<:j:j:j:j:j:j:j:>j:j:j:~j:~j m&g@kI#a$Q#gq~ir,#mi h 3- j..,...,......... j@ & #&&$$$ $ S............................................. ........................................................................................ ...................................................................................................................................................................................................... jjjj ..,.,. .................................................................. ..... ...........,.... ...........,.,.,.,.,.,.,.,.,. ,.,.......,., .................................,.,.,., .,.,.........,.....,.,.,.,.,.,.,.,.,...............,.,.,.,.......,...............................,.,.,.. .....................................................,...........................................,...........,.,.,.,.......................,.,.,...................................... ......,..... ....m ..... ...,....... ......( ...(............................,.,.,.,.,. .............,.,..,....... Paragraph 4 General requirements Requirements are met in the devices are mountedlinstalled in accordance with the installation guidelines. Please observe the explanations in "Notes on CE Marking o f SlMATlC 55". Paragraph 11.2 Digital inputloutput interfaces Requirements are met. Paragraph 12.3 Programmable equipment Requirements are met if the devices for protection o f memory contents against change by unauthorized persons are installed in locked cabinets. Paragraph 20.4 Voltage tests Requirements are met. CPU 945 Manual Technical Specifications - tested to IEC 68-2-6 10 Hz 5 f 57 Hz S f (measured at the bottom of the modules) Oto+55"C - Cabinet design Mode of vibration loss depends on the type of construction, the ambient temperature, and the arrangement of the devices.) Air intake temperature (measured a t t h e bottom of the modules) Oto+55"C StorageIShipping < 57 Hz, < 150 Hz, Constant amplitude 0,075 mm Constant acceleration 1 g Frequencysweeps with sweep rate of 1 oktavelmin. each of the 3 axes vertical to each -Operation conditions in accordance with IEC 1131-2 - tested t o IEC 68-2-27 -40to+70C Temperature change maximum 10 Klh maximum 20 Klh 2 shocks in each o f t h e 3 axes vertical t o each other Relative Humidity 595 % (according t o - storagelshipping - tested to IEC 68-2-3 595 % (noncondensing) Height of fall l m Atmospheric Pressure - operation - storagelshipping Pollutants - SO, - H2S 1 860to 1060 h ~ a ' 660 t o 1060 h Pa ' S0.5 ppm, (rel. humidity 5 6 0 %, noncondensing) 50.1 ppm, (rel. humidity 5 6 0 %, noncondensing) For use under 900 hPa (= 1000 m above sea level), check with the manufacturer on the cooling requirements. EWA 4NEB 81 1 6150-02d * Vibrations and shocks persisting f o r a prolonged period at the maximum values stated above and continuous shocks should be avoided by taking the appropriate measures. CPU 945 Manual Technical Specifications IEC I VDE Safety Information Electromagnetic Compatibility (EMC) Noise Immunity Immunity t o static electrical discharge -tested in accordance with EN 61000-4-2 - Discharge t o air 8 kV - Discharge on contact 4 kV Degree of Protection - Type - Class according t o IEC 529 IP 20 I according to IEC 536 Immunity t o electromagnetic fields - tested in accordance with EN V 50140 Isolation Rating 80to l000MHz 10VIm 80 % AM (1 kHz) - tested in accordance with EN V 50204 (pulse-modulated HF) 900 MHz 10VIm 50 % ED, 200 Hz repetition frequency - between electrically (amplitued-modulated HF) independent circuits and with circuits connected by a central grounding point according t o VDE 0160 - between all Immunity t o fast transient bursts - tested in accordance with EN 61000-4-4 - Supply lines for 1201230VAC 2 kV - Supply lines for 24V DC 2 kV - Signal lines (110 and bus lines) 2 kV* circuits and central grounding point (standard mounting rail) according t o VDE 0160 Immunity t o high frequency - tested in accordance with EN V 50141 0.1 5 to 80 MHz 10V 80 % A M (1 kHz) Source impedance 150R Test Voltage for a rated voltage V, of the circuits (ACIDC) V,=Oto 50V Ve=50to 125V V,= 125 t o 250 V Sine, 50 Hz Impulse voltage for a rated voltage V, of the circuits (ACIDC) V,=Oto 50V Ve=50to 125V V, = 125 t o 250 V according t o IEC 255-4 500 V DC 1250VAC 1500V AC Emitted interference - tested in accordance with EN 5501 1 - Emmission of electromagnetic fields - Emitted interference over supply cable Damped Oscillatory WaveTest - AC power supply modules DC power supply modules output 24 V DC input 1151230 VAC - digital inputloutput modules - analog inputloutput modules - communications interfaces Limit value class A, Group 1 Limit value class A, Group 1 according t o IEC 255-4 2.5 kV IkV IkV 2.5 kV 2.5 kV 1 kV IkV *Signal lines that are not used for process control, for example, connections t o external printers: 1 kV 1 kV, 1.2150 psec. 1 kV, 1.2150 p e c . 3 kV, 1.2150 p e c . CPU 945 Manual 15.2 Technical Specifications Description of Modules 15.2.1 Mounting Racks (CRs, ERs) Mounting Rack CR 700-0 for Central Controller 0 Technical Specifications Number of inputloutput modules that can be plugged in maximum 4 Number of expansion units that can be connected - central maximum 3 Dimensions W x h x d (mm) 353 X 303 X 47 Weight 4 kg (8.82 lb.) Mounting Rack CR 700-0 for Central Controller 0 (6ES5 700-OLB 11) Technical Specifications Number of inputloutput modules that can be plugged in * see Section 3.3.2 maximum 6 Number of expansion units that can be connected -central maximum -distributed * maximum 3 63 Dimensions W X h X d (mm) 353 X 303 X 47 Weight 4 kg (8.82 lb.) Technical Specifications CPU 945 Manual Mounting Rack CR 700-1 for Central Controller 1 (6ES5 700-1LA12) Technical Specifications Number of inputloutput modules that can be plugged in maximum 7 Number of expansion units that can be connected central maximum 3 - Dimensions W X h X d (mm) 483 X 303 X 47 (18.84 in. X 11.82 in. X l.83 in.) Weight S kg (1 1.02 lb.) Mounting Rack CR 700-2 for Central Controller 2 (6ES5 700-2LA12) Technical Specifications Number of inputloutput modules that can be plugged in maximum Number of expansion units that can be connected -central maximum maximum -distributed * * Dimensions W X h X d (mm) 483x303~47 (18.84 in. X 11.82 in. X l.83 in.) Weight 5 kg see Section 3.3.2 EWA 4NEB 81 1 61 50-02d CPU 945 Manual Technical Specifications (6ES5 700-3LA12) Mounting Rack CR 700-3 for Central Controller 3 Number of inputloutput modules that can be maximum 11 Number of expansion units that can be connected - central connection maximum - distributed * maximum 3 63 Dimensions W X h X d (mm) 483 X 303 X 47 (18.84 in.xI1.82 Weight * see Section 3.3.2 Mounting Rack ER 701-0 for Expansion Unit 0 Technical Specifications Number of inputloutput modules that can be plugged in maximum 6 Interface module - central connection IM 305lIM 306 Interrupt evaluation not possible Dimensions W X h X d (mm) 353x303~47 Weight 4 kg (11.02 lb.) EWA 4NEB 81 1 61 50-02d Technical Specifications CPU 945 Manual Mounting Rack ER 701-1 for Expansion Unit 1 (6ES5 701-1LA12) Technical Specifications Number of inputloutput modules that can be maximum 9 interface module - L central connection IM 305lIM 306 Interrupt evaluation not possible Dimensions W X h X d (mm) 483 X 303 X 47 (18.84 in. X 11.82 in. X 1.83 in.) Weight 5 kg (11.02 lb.) I Mounting Rack ER 701-2 for Expansion Unit 2 (6ES5 701-2LA12) Technical Specifications Number of inputloutput modules that can be plugged in maximum 7 lnterface module - central connection - distributed connection I M 306 AS 3101AS 311 I M 314lIM 3171 IM 318 Interrupt evaluation not possible Dimensions W X h X d (mm) 483 X 303 X 47 (18.84 in. X 11.82 in. X 1.83 in.) Weight 5 kg (11.02 lb.) CPU 945 Manual Technical Specifications Mounting Rack ER 701-3 for Expansion Unit 3 (6ES5 701-3LA12) Technical Specifications Number of inputloutput modules that can be that can be plugged in maximum Interface module II o o o o o o o n n connection l -- central distributed connection Interrupt evaluation possible with I M 3071317 Dimensions W X h X d (mm) (18.84 in. X 11.82 in. X 1.83 in.) Weight 5 kg (1 1.02 lb.) CPU 945 Manual Technical Specifications 15.2.2 Power Supply Modules Power Supply Module PS 951 1201230 VAC; 5 V, 3 A Technical specifications SIEMENS lnput voltage L1 Rated value Permissible range 0 - SIMATIC S5 PS 3A 1 FE 1 1201230 VAC 94to132V/187to 264 V Line frequency - Rated value - Permissible range 50 Hz 47 t o 63 Hz Input current at 1201230 V 3.4~15~h - Rated value - Inrush current - 12t Replace by trained personnel only! max. Outputconsumption Power voltage (active power) 44.8 W 0 3.4...9v &9.5% V 5 -Output Tolerance Ratedcurrent value without fan RESET INTDC POWER 3A 3A 0.3Ato3A - Rated value w i t h fan - Permissible range 5.2~ DC 24v DC 0.5510.33 A 1 5 ~ 1 ~ 0.1 35 A2s Output voltage (PGIOP) } I - Rated value - Tolerance Q 5.2 V 1.5% max. 1 A + Output current Output voltage (auxiliary voltage) - Rated value - Tolerance VOLTAGE SELECTOR r 24 V k 5% max. 0.2 A Output current Backup battery @ L1 - @ N Backup time min. Mains buffering (at L1,in) min. @@ 120123OVAC @m Battery Lithium battery, size C (3.6 V15 Ah) 1 year (at 0.3 mA, 25C and uninterrupted backup) 20 ms Short-circuit protection Electronic Fault indicator No Fuse (primary circuit) Integral Galvanic isolation Yes Isolation rating - Tested w i t h Safe electrical isolation according t o VDE 0160 2700 V DC Initial discharge current t o VDE 0160 at 230 VAC 2.6 rnA CPU BATT LOW RESET 5v 5.2 V 24 V 5v EXT. BATT 24 V M L1 N PE 4 1 2 3 Chopper controller Linearcontroller Linear controller 4 5 6 7 Simplified schematic Control electronics Rectifier Radio interference suppression filter Monitoring electronics RI specifications A according t o VDE 0871 19.8 W Power losses of the module typ. Weight approx. 1.6 kg (3.53 lb.) CPU 945 Manual Technical Specifications Power Supply Module PS 951 I201230 VAC; 5 V, 7115 A (6ES5 951-7LD21) Technical specifications I lnput voltage L1 - 1201230 V A C 94to132V 187 t o 2 6 4 V Rated value - Permissible range n Line frequency - Rated value - Permissible range BATT1-BATT2 3.4Vi2Ah lnput current a t 1201230 V Rated value Inrush current - Replace by trained personnel only! max. 12t 1.410.8 A 1 5 ~ 1 ~ 1.8 A ~ s Power consumption (active power) Output voltage - Rated value - Tolerance Output current - Rated value w i t h o u t f a n - Rated value w i t h fan - Permissible range Output voltage (PGIOP) - Rated value - Tolerance 5.2 V +1.5% max. 2.5 A Output current - Backup time min. 2 lithium batteries, size AA (3.6 V12x1.75 Ah) 1 year (at 0.3 mA, 2 5C and uninterrupted backup) Mains buffering (at L1,in) min. 20 ms Backup battery Output voltage (auxiliary voltage) Rated value - Tolerance Output current - Batterv CPU -T LOW RESET 5v 5.2V 24 V -.BATT 24 V f5% max. 0.35 A Short-circuit protection Electronic Fault indicator No Fuse (primary circuit) Integral Class of protection Class 1 5v 5.2 V Galvanic isolation Yes 24 V Isolation rating Safe electrical isolation according t o VDE 0160 2700 V DC M L1 N - Tested w i t h 1 2 3 Chopper controller Linearcontroller Linear controller Simplified schematic 4 5 6 7 Control electronics Rectifier Radio interference suppression filter Monitoring electronics initial discharge current t o VDE 0160 a t 230 V A C A according t o VDE 0871 RI specifications Power losses o f t h e module typ. Weight approx. 1.9 k g (4.1 9 lb.) 36 W Technical Specifications CPU 945 Manual Power Supply Module PS 951 24V DC; 5 V, 3 A (6ES5 951-7NB21) Technical specifications SIEMENS lnput voltage L+ @ - Rated value 24 V DC 19.2 t o 30 V - Permissible range n S l M A T l C S5 PS 3A lnput current a t 24 V - Rated value - Inrush current - I2t Batt. 3.4VI5Ah max. Power consumption Replace by trained personnel only! 36.2 W Output voltage - Rated value - Tolerance Output current - Rated value w i t h o u t fan - Rated value w i t h f a n - Permissible range 3.4 ...9 v 1.51 A 1 5 ~ 1 ~ 0.4 A ~ s 5V 2 1.5% 3A 3A 0.3 t o 3 A BATT LOW Output voltage (PGIOP) - Rated value RESET 5.2 V 2 1.5% max. 1 A - Tolerance Output current 5.2V DC 24V DC INTDC POWER ) I) Backup battery @ @ L+ - Backup time min. Mains buffering (at L+ ,in) min. Lithium battery, size C (3.6 V15 Ah) 1 year (at 0.3 mA, 25C and uninterrupted backup) 20 ms Output voltage (auxiliary voltage) @M - Rated value - Tolerance @@ Output current 24 V k 5% max. 0.2 A Short-circuit protection Electronic Fault indicator No Fuse (primary circuit) Integral Class o f protection Class 1 5V Galvanic isolation No 5.2V 24 V RI specifications A according t o VDE 0871 24VDC Battery CPU BATT LOW RESET 5v 5.2 V 24 V EXT.BATT M L+ M PE 4 1 2 3 Chopper controller Chopper controller Linear controller Simplified schematic 4 5 6 Control electronics Radio interference suppression filter Monitoring electronics Power losses o f t h e module typ. 11.2 W Weight approx. 1.6 k g (3.53 lb.) CPU 945 Manual Technical Specifications Power Supply Module PS 951 24V DC; 5 V, 7115 A (6ES5 951-7ND51) Technical specifications Input voltage L + - Rated value - Permissible range 24VDC 49.2 t o 30 V input current a t 2 4 V - Rated value - Inrush current - I2t max. Power consumption 5.04 A 15xiN 16 A2s 120.5 W Output voitage - Rated value - Tolerance 5V k 4.5% Output current - Rated value w i t h o u t f a n - Rated value w i t h f a n - Permissible range 7A 15 A 0.3 t o 15 A Output voltage (PGIOP) - Rated value - Tolerance 5.2 V +1.5% max. 2.5 A Output current Backup battery - Backup time min. 2 lithium batteries, size AA (3.6 V/ 2 X 1.75Ah) 1 year (at 0.3 mA, 25"Cand uninterrupted backup) Mains buffering (at L+ ,in) min. 20 ms Output voltage (auxiliary voltage) - Rated value - Tolerance Output current 24 V ? 5% max. 0.35 A Short-circuit protection Electronic Fault indicator No Fuse (primary circuit) Integral Class o f protection Class 1 Galvanic isolation No RI specifications according t o VDE A according t o VDE 0871 Battery 0 CPU BATT LOW RESET 5v 5.2 V 24 V EXT.BATT 5V 5.2 V 24v L+ M M Power losses o f the module typ. 24.1 W Weight approx. 1.7 k g (3.75 lb.) PE 4 1 2 3 Chopper controller Chopper controller Linear controller Simplified schematic 4 5 6 Control electronics Radiointerference suppression filter Monitoring electronics CPU 945 Manual Technical Specifications (6ES5 951-7ND41) Power Supply Module PS 951 24V DC; 5 V. 7115 A - Permissible range 19.2 to 30V 3.4Vl2Ah Replace by trained personnel only! Power consumption - Rated value - Rated value w i t h fan Permissible range 0.3to15A Output voltage (PGIOP) - Rated value batteries, size AA (3.6 V12 X 1.75 Ah) min. 20ms Output voltage (auxiliary voltage) - Rated value max. 0.35 A Short-circuit protection Fault indicator Fuse (primary circuit) Class of protection - Tested with 1 2 3 Chopper controller Linearcontroller Linear controller Simplified schematic 4 5 6 7 Control electronics Rectifier Radio interference suppression filter Monitoringelectronics Power losses of the module typ. 38W approx. l.7 kg (3.75 lb.) Technical Specifics tions CPU 945 Manual 15.2.3 Central Processing Units Central P r o c e s s i n g Unit CPU 941 Technical Specifications Memory capacity (total) maxim. internal memory maxim. memorysubmodule (Flash-EPROM) maxim. - Execution time per operation approx. Flags ? 2s /day -3.5 X (Tarn,,-l 5)2 ms /day k 2 s - 3.5 X (40 -15)2 mslday approx. 0 t o -4s Iday 500 msec. (can be modified) 2048; optionally half or all retentive 1 32768; optionally half or all retentive 1 S flags Timers - number - I2812561384Kbyte approx. 0.1 ps - 1.35 ps Clock -Accuracy t, - Temperature dependency, , t (ambient temperature Tamb in "C) - e. g. Tolerance at 40C Scan time monitoring 2561384 Kbyte 2561384 Kbyte 256; optionally half or T 0 t o 63 retentive1 0.01 t o 9990 sec. range Counter - number 256; optionally half or C 0 t o 63 retentive l 0 t o 999 (up, down) - range Digital inputs Digital outputs - total maxim. 8192 Analog inputs Analog outputs -total maxim. 256 Organization blocks Pro ram blocks F u n k o n blocks (FBIFX) maxim. maxim. maxim. Sequence blocks Data bocks (DBIDX) maxim. maxim. 256 256 512 (can be assigned parameters) 256 512 Operation set approx. 270 operations Required backup current from the backup battery at power off - internal RAM approx. 100pA Current consuption (without interface module) - from 5 V (internal) typically 0.5 A from 24 V 0.06 A - Power losses of the module (without interface module) typically 4.2 W Weight 1 If backup battery used approx. 0.8 kg (1.7 Ib) CPU 945 Manual Technical Specifications 15.2.4 Digital lnput Modules Digital lnput Module 32 X 2 4 V DC, Nonfloating Technical Specifications Number of inputs Floating lnput voltage L - rated value - for "0" signal - for "l" signal 32 no + 24VDC -3Oto+SV 13to30V lnput current - for "l" signal typically 8.5 mA Response time - from "0" t o "l" - from "l " t o "0" Cable length shielded unshielded - 1.4 t o 5 msec. 1.4 to 5 msec. maximum 1000 m maximum 600m Isolation rating according to VDE 0160 Connection of 2-wire BERO proximity switches - leakage (quiescent) current possible 51.5 mA Current consumption - from 5 V (internal) 5 5 mA Power losses of the module typically 6.5 W Weight approx. 0.7 kg (1.54 lb.) INPUT 32x24VDC Terminal Assignment a - PE = M int. L g L+l M ext. External connection Simplified Schematic EWA 4NEB 81 1 61 50-02d Technical Specifics tions CPU 945 Manual Digital Input Module 32 X 2 4 V DC, Floating (6ES5 430-7LA12) Number of inputs yes (optocoupler) lnput voltage L - rated value + 24 V DC -30 to95V 13 t o 30V - f o r "0" signal - for "l" signal Response time - f o r "l" signal typically Response time from "0" t o "l" typically maximum t o "0" typically -from "l" maximum - - unshielded 8.5 mA 2.6 msec.; 5.5 msec. 2.3 msec.; 5 msec. maximum 1000 m (3281 ft.) maximum 600 m (1969 ft.) Isolation rating according t o VDE 0160 Rated isolation voltage (between groups) - isolation group -tested with Rated isolation voltage -tested with Connection of 2-wire BERO proximity switches quiescent current - 51.5 rnA Current consumption -from 5 V (internal) Terminal Assignment L + - s M ext. Simplified Schematic EWA 4NEB 81 1 61 50-02d Power losses of the module typically 6.5 W Weight approx. 0.7 kg (1.54 lb.) Technical Specifications CPU 945 Manual Digital Input Module 16 X 24 to 48 V UC (6ES5431-7LA11) Technical Specifications Number of inputs Floating - in groups of 16 yes (optocoupler) 4 lnput voltage L + -rated value -frequency - f o r "0" signal - f o r "l" signal 24 to 48 V UC 0 to63 Hz Oto5V 13to60V input current at "l " signal -for24VAC -for24VDC - f o r 48VAC -fsr48VDC typically typically typically typically Response time -from "0" to "1" " to "0" -from "l Cable length -shielded - unshielded 2 t o 13 msec. 10 t o 25 msec. maximum 1000m maximum 600 m Isolation rating according toVDE 0160 Rated isolation voltage 1 (between groups) - isolation group -tested with 60V C 500 V Rated isolation voltage (Ll t o & ) isolation group -tested with 250V C 1500 V Connection of 2-wire BERO proximity switches -quiescent current possible 2 mA - B DIGITAL INPUT 16x24-48VUC Terminal Assignment -from 5 consumption Current V (internal) Power losses of the module - 8.5 mA 9.0 mA 10.5 mA 10.5 mA $5 r n ~ typically 9W approx. 0.7 kg (1.54 lb.) B = us Simplified Schematic - Connection of different phases is not permissible. CPU 945 Manual Technical Specifications Digital Input Module 16 X 48 to 6 0 V UC, Floating (6ES5 432-7LA11) Technical Specifications Number o f inputs Floating - i n groups o f 16 yes (optocoupler) 4 lnput voltage L1 - rated value - frequency - for "0"' signal - for " l " signal lnput current a t "1" signal - %or48 V A C 150 Hz - for48VDC - for 60 V A C I50 Hz - for 60 V DC 48 t o 60 V UC 0 t o 63 Hz 0 to IOV 30 t o 72 V typically typically typically typically 8.5 m A 9.5 m A 9.5 m A 10.0mA Response time - from "0" t o " l " - from "l" t o "0" Cable length - shielded - unshielded 2 t o 13 msec. 10 t o 25 msec. maximum 1000 m (3281 ft.) maximum 600 m (1969 ft.) isolation rating according t o VDE 0160 Rated isolation voltage1 (between groups) - isolation group - tested w i t h 250 V C 1500 V Rated isolation voltage (L1 t o ) - isolation group tested w i t h - 250 V C 1500 V Connection o f 2-wire BERO proximity switches -quiescent current possible 5 5 mA Current consumption from 5 V (internal) 5 5 mA & DIGITAL INPUT Terminal Assignment Simplified Schematic - Power losses o f the module typically 10 W Weight approx. 0.7 k g (1 .54 lb.) 1 Connection o f different phases is n o t permissible. Technical Specifications CPU 945 Manual (6ES5434-7LAl2) Digital Input Module 8 X 2 4 V DC (with P Interrupt). Floating Technical Specifications Number of inputs Floating - in groups of lnput voltage L -rated value - f o r "0" signal - f o r "l" signal 8 yes (optocoupler) 1 + lnput current at "1" signal for 24 V DC - 24 V DC -30to +5V 13to30V typically Response time -from "0" t o "1 " -from "l " t o "0" 0.5 t o 1.5 msec. 0.5 t o 1.5 msec. Interrupt signal (external) latching relay contact (permissible load: max. 0.2 A 50 V DC switching capacity max. 20 W or 35 VA) Interrupt signal (internal) via bus line PRAL-N Acknowledgement external via input reset 24 V DC Cable length -shielded - unshielded maximum 1000 m (3281 ft.) maximum 600 m (1969 ft.) lsolation rating according to VDE 0160 Rated isolation voltage (between groups) -isolation group tested with - 30V C 500 V Rated isolation voltage &) isolation group - tested with 30 V C 500 V Connection of 2-wire BERO proximity switches possible (L+ t o DIGITAL INPUT Terminal Assignment -quiescent current maximum 51.5 mA Current Consumption -from 5 V(interna1) Interrupt logic U S - - 41 b" 2 24 V M ext. Simplified Schematic - 8.5 mA <70 mA Power losses of the module typically 2W Weight approx. 0.7 kg (1.54 lb.) CPU 945 Manual Technical Specifications Digital Input Module 16 X 115 V UC, Floating (6ES5 435-7LA11) Technical Specifications Number of inputs Floating - in groups o f 46 yes (optocoupler) 4 lnput voltage L1 -rated value -frequency - f o r "0" signal - f o r "l" signal d15VUC 47 t o 63 Hz Oto40V 85to135V lnput current at "l " signal - f o r AC, 50 Hz - f o r DC Response time -from "0" t o "l" -from "1 " t o "0" 2 t o 13 msec. l 0 t o 25 msec. Cable length -shielded unshielded - 1000 m (3281 ft.) 600 m (1969 ft.) Isolation rating according t o VDE 0160 Rated isolation voltage 1 (between groups) -isolation group -tested w i t h 250 V C 1500 V Rated isolation voltage (L1 t o ) isolation group -tested w i t h 250 V C 1500 V Connection of 2-wire BERO proximity switches -quiescent current possible 1 5 mA Current consumption -from 5 V(interna1) 5 5 mA Simultaneity factor (per group, L1 =l 35 V) -at25OC 100 % -& - B DIGITAL INPUT 16x115VAC Terminal Assignment -- -F% U s - Simplified Schematic typically 15 mA typically 6 mA -at55OC Power losses of the module 75 % typically 11 W Weight approx. 0.7 kg (1.54 lb.) L1 (L+) - Connection of different phases is permissible. Technical Specifications CPU 945 Manual Digital Input Module 16 X 115 V UC (6ES5 435-7LBl1) -, Technical Specifications Number o f inputs Floating i n goups o f - 16 yes (optocoupler) 2 lnput voltage L1 -rated value -frequency - f o r "0" signal -forn7"signal 115VUC 47 t o 63 Hz Oto40V 85to135V lnput current a t "l" signal - for AC, 50 Hz - f o r DC Response time - f r o m "0" t o "l " - f r o m "1 " t o "0" 2 t o 13 msec. 1 0 t o 25 msec. Cable length -shielded - unshielded 1000 m (3281 ft.) 600 m (1969 ft.) Isolation rating according t o VDE 0160 Rated isolation voltage l (between groups) - isolation group -tested w i t h 250 V C 1 500 V Rated isolation voltage (L1 t o & ) - isolation group -tested w i t h 250 V C 1500 V Connection o f 2-wire BERO proximity switches -quiescent current possible 5 5mA Current consumption - f r o m 5 V (internal) 5 5mA Simultaneity factor (per group, L1 = 135 V) -at25OC -at55'C Power losses o f B DIGITAL INPUT 16x1 15VAC Terminal Assignment typically 1 0 mA typically 6 m A 100 % 75 % the module typically 11 W Weight approx. 0.7 k g (1-54 lb.) L1 (L+) - Simplified Schematic 1 Connection o f different phases is permissible. CPU 945 Manual Technical Specifications (6ES5 436-7LA11) Digital Input Module 16 X 230 V UC, Floating Technical Specificat~ons Number of inputs Floating in groups of 16 yes (optocoupler) 4 - lnput voltage L1 - rated value 230 V UC 47 t o 63 Hz Oto70V 170 t o 264 V -frequency - f o r "0" signal - f o r "l" signal lnput current at "l" signal - f o r AC, 50 Hz - f o r DC E 3 DIGITAL INPUT 16~2201240VAC Terminal Assignment B E u- typically 15 mA typically 2.2 mA Response time -from "0" to "l" -from "l" to "0" 2 t o 13 msec. 10 t o 35 msee. Cable length -shielded - unshielded 1000 m (3281 ft.) 600 m (1969 ft.) Isolation rating according t o VDE 0160 Rated isolation voltage l) (between groups) - isolation group -tested with 250 V C 1500 VAC Rated isolation voltage (L1 t o & ) - isolation group -tested with 250 V C 1500 V AC Connection of 2-wire BERO proximity switches -quiescent current possible 5 3 mA Current consumption -from 5 V (internal) 5 5 mA Simultaneity factor (per group, for L1=264 V) -at25OC -at55'C 100 % 75 % the Power module losses of typically 11 W Weight approx. 0.7 kg (1.54 lb.) L1 (L+) - s - Simplified Schematic EWA 4NEB 81 1 61 50-02d 1 Connection o f different phases is not permissible. Technical Specifications CPU 945 Manual Digital Input Module 16 X 230 V UC (6ES5 436-7LBl1) Technical Specifications Number of inputs Floating in groups of - 16 yes (optocoupler) 2 lnput voltage L l -rated value -frequency - f o r "0" signal - f o r "l" signal 230 V UC 47 t o 63 Hz Oto70V 170to264V lnput current at "l" signal - f o r AC, 50 Hz - f o r DC typically 15mA typically 2.2 mA Response time -from "0" to "l" -from "l" to "0" 2 t o 13 msec. 10 t o 35 msec. Cable length -shielded unshielded - 1000 m (3281 ft.) 600 m (1969 ft.) Isolation rating according t o VDE 0160 Rated isolation voltage 1 (between groups) - isolation group -tested w i t h B DIGITAL INPUT 16x23OVAC 250V C 1500 V Rated isolation voltage (L1 t o ) - isolation group - tested w i t h 250 V C 1 500 V Connection of 2-wire BERO proximity switches -quiescent current possible 5 3 mA Current consumption -from 5 V (internal) 5 5mA Simultaneity factor (per group, for L1=264 V) -at25OC - a t 55OC 100 % 75 % the Power module losses of typically 11 W Terminal Assignment Weight approx. 0.7 kg (1.54 lb.) L1 (L+) Tk U S Simplified Schematic 1 Connection of different phases is not permissible. Technical Specifications CPU 945 Manual Digital Input Module 8 X 230 V U C (6ES5 436-7LC11) Technical Specifications Number o f inputs Floating - i n groups o f 8 yes (optocoupler) 1 Input voltage L1 -rated value -frequency - f o r "0" signal - f o r "l" signal lnput current a t "l " signal AC DC E 3 DIGITAL INPUT 8x230VAC 230 V UC 47 t o 63 Hz Oto400V 170 t o 264 V typically 1 6 m A typically 2.2 m A Response time - f r o m "W t o "1 " t o "0" - f r o m "l" 2 t o 13 msec. l 0 t o 25 msec. Cable length -shielded - unshielded 1000 m (3281 ft.) 600 m (1969 ft.) Isolation rating according t o VDE 0160 Rated isolation voltage (between groups) - isolation group -tested w i t h 250 V C 2700 V Rated isolation voltage (L1 t o ) - isolation group -tested w i t h 250 V C 2700 V Connection o f 2-wire BERO proximity switches -quiescent current possible 5 5 mA Current consumption - f r o m 5 V(interna1) 5 5 mA Power losses o f the module typically 5 W Weight approx. 0.7 k g (1.54 lb.) Terminal Assignment - - L1 (L+) - Simplified Schematic Connection o f different phases is n o t permissible. Technical Specifications CPU 945 Manual 15.2.5 Digital Output Modules Digital Output Module 32 X 24V DC; 0.5 A, Nonfloating Number of outputs + Load voltage L -rated value -permissible range -surge voltage at t 50.5 sec. 20to30V minimum L+-2.5V maximum 5W maximum ImA Output current -rated value Permissibletotal current lOO%at25OCand 50 % at 55 O C (related t o the sum Short circuit protection Limitation of the voltage induced on circuit interruption - 15 V Switching frequency - inductive load - resistive load maximum maximum 0.5 Hz 100Hz - unshielded maximum maximum 1000m(3281ft.) 600 m (1969 ft.) VDE 0160 Terminal Assignment - Simplified Schematic Current consumption -from 5V(internal) -from L+(without load) 17 mAlper group Power losses of the module typically 20 W Weight approx. 0.7 k g (1.54 lb.) CPU 945 Manual Technical Specifications Digital Output Modules 32 X 2 4 V DC; 0.5 A, Floating (6ES5 451-7LA12) Technical Specifications Number of outputs Floating - i n groups of 32 yes (optocoupler) 8 Load voltage L+ -rated value -permissible range -surge voltage at t 50.5 sec. 24 V DC 20 to 30 V 35 V Output voltage - a t "l" signal minimum L+- 2.5V Output current for "l " signal -rated value - lamp load 0.5 A maximum 5 W Leakage current at "0" signal maximum 1 mA Parallel connection of outputs not possible Permissible total current of outputs Short circuit protection 100% at25OCand 50 % at 55 O C (related t o the sum of currents) electronic Limitation of thevoltage induced on circuit interruption -15V Switching frequency - inductive load - resistive load DIGITAL OUTPUT Terminal Assignment maximum 0.5 Hz maximum 100 Hz Cable length -shielded unshielded - 1000 m (3281 ft.) 600 m (1969 ft.) isolation rating according toVDE 0160 Rated isolation voltage (between groups) -isolation group -tested w i t h 30 V DC C 500 VAC Rated isolation voltage (L+ t o ) isolation group -tested w i t h 30 V DC C 500 V AC - ; Current consumption Simplified Schematic -from 5V(internal) -from L+(without load) l 0 0 mA 17 mAlper group Power losses of the module typically 20 W Weight approx. 0.7 kg (1.54 lb.) Technical Specifications CPU 945 Manual Digital Output Module 32 X 2 4 V DC; 0.5 A, Floating Number of outputs Load voltage L 9 - rated value - permissible range - surge voltage at t 50.5 sec. 24 V DC 20 t o 30 V 35 V Output voltage - for "l " signal minimum L+-2.5V maximum 5 W Leakage current maximum 1 mA Parallel connection of l 0 0 % at25OCand 50 % at 55 O C (related t o the sum of currents) Short circuit protection Short circuit indicator electronic V23042 B201 B101 30V DC; 0.1 A 3Wor6VA - switching capacity Limitation of the voltage induced on circuit interruption Switching frequency - inductive load -resistive load - maximum 0.5 Hz maximum 100 Hz 1000 m (3281 ft.) 600 m (1969 ft.) unshielded according toVDE 0160 - tested w i t h Rated isolation voltage Current consumption - from 5 V (internal) - from L + (without load) 17 mAlper group Power losses of the module typically 20 W approx. 0.7 k g (1.54 lb.) CPU 945 Manual Technical Specifications Digital Output Module 16 X 24 t o 60 V DC; 0.5 A, Floating (6ES5 453-7LA11) yes (optocoupler) + Load voltage L -rated value -permissible range -surge voltage at t 50.5 sec. Ouput voltage signal - f o r "I" 24 to 60 V DC 20 to 75 V 87 V maximum L + - 2.5V maximum 5 W maximum 1 mA Permissible total current of outputs, per group Short circuit protection Short circuit indicator electronic red LED (each group) V23042 B201 B101 60 V DC; 0.2 A 20Wor35VA 24 t o 60 V DC Limitation of thevoltage induced on circuit interruption Switching frequency Terminal Assignment - inductive load - resistive load maximum 0.5 Hz maximum 100 Hz - unshielded maximum 1000 m (3281 ft.) maximum 600 m (1969 ft.) according t o VDE 0160 Isolation rating Rated isolation voltage (between groups) 500 V AC Current consumption -from 5 V (internal) - from L+ (without load) + 50 mAlper group Power losses of Simplified Schematic typically 14W approx. 0.7 kg (1.54 lb.) Technical Specifications CPU 945 Manual Digital Output Module 16 X 24V DC; 2 A, (6ES5 454-7LA12) Floating Technical Specifications Number of outputs Floating - i n groups o f 16 yes (optocoupler) 4 + Load voltage L -rated value -permissible range -surge voltage at t 50.5 sec. 24 V DC 20 to 30V 35 V Output voltage signal - f o r "l" minimum L+- 3 V Output current at"1" signal -rated value - lamp load 2A maximum 10 W Leakage current at "0" signal maximum 1 mA Parallel connection of outputs not possible Permissible total current of outputs, per group Short circuit protection 50 % (related t o the sum of the currents of a group) electronic Limitation of the voltage induced on circuit interruption -15 V Switching frequency - inductive load OUTPUT 1 6 x 2 4 ZA ~ ~ ~ Terminal Assignment -resistive load maximum 0.27 Hz maximum 100 Hz Cable length -shielded - unshielded maximum 1000 m (3281 ft.) maximum 600m(1969ft.) Isolation rating according t o VDE 0160 Rated isolation voltage (between groups) -isolation group -tested w i t h 30 V DC C 500 V AC Rated isolation voltage (L+to -isolation group -tested w i t h 30 V DC C 500 V AC Current consumption -from 5 V (internal) -from L+ (without load) 50 mA 8.5 mAlper group Power losses of the module typically 20 W Weight approx. 1.l kg (2.43 lb.) h) Simplified Schematic - CPU 945 Manual Digital Output Module 8 X 24V DC; 2 A, Technical Specifications (6ES5 454-7LBl1) Floating yes (optocoupler) Load voltage L+ -rated value - permissible range -surge voltage at t 50.5 sec. Output voltage for "l" signal - 24V DC 20 t o 30 V 35 V minimum L+- 3 V Output current -rated value maximum 10 W Leakage current maximum 1 mA Parallel connection of Permissible total current of outputs, per group Short circuit protection (for each group) lOO%at25OCand 50 % at 55 O C (related to the sum of the currents w i t h F 2.5 A fuse (e.g. Wickmann 19340) Limitation of the voltage induced on circuit interruption 23 V typically - Switching frequency - inductive load - resistive load maximum 0.27 Hz maximum 100 Hz - unshielded maximum 1000 m (3281 ft.) maximum 600 m (1969 ft.) according t o VDE 0160 Terminal Assignment Rated isolation voltage (between groups) isolation group -tested w i t h - 500 V AC Rated isolation voltage 500 V AC Current consumption -from 5 V (internal) maximum 50 mA + Power losses of Simplified Schematic EWA 4NEB 81 1 61 50-O2d typically 20 W approx. 0.8 kg (1.76 lb.) CPU 945 Manual Technical Specifications Digital Output Module 16 x 48 to 115 VAC;2 A, Floating (6ES5 455-7LA1 l) Technical Specifications Number of outputs Floating in groups of - 16 yes (optocoupler) 2 Load voltage L4 -rated value -frequency -permissible range 4811 15 VAC 47 t o 63 Hz 40to140V Output voltage - f o r "l" signal minimum L1 - 7 V Output current signal at "l" -rated value permissible range lamp load - 2 Alper group 40mAto2A maximum 501100 Wiper group Leakage current at "0" signal maximum 113 mA Parallel connection of outputs not possible Making capacity depends on the size of the fuse Permissibletotal current of outputs 100 % Short circuit protection (for each group) w i t h Gould GAB4 fuse or Bussmann ABC4 Fault indication (red LED for each group) defective fuse Switching frequency maximum 10 Hz Cable length -shielded - unshielded OUTPUT 16x48- 11 SVAC 2A Terminal Assignment maximum 1000 m (3281 ft.) maximum 300 m (984ft.) Isolation rating according to VDE 0160 Rated isolation voltage (between groups) - isolation group -tested w i t h 250 VAC C 1500 VAC Rated isolation voltage (L1 t o & ) -isolation group -tested w i t h 250 VAC C 1500 V AC Current consumption -from 5 V (internal) maximum 175 mA Simplified Schematic Power losses of the module typically 16W Weight approx. 1.l kg (2.43 lb.) CPU 945 Manual Technical Specifications Digital Output Module 16 X 115 to 230 VAC; 1 A, Floating (6ES5 456-7LA11) Technical Specifications 16 yes (optocoupler) 4 Number of outputs Floating in groups of - Load voltage L1 -rated value -frequency -permissible range Output voltage - a t "l " signal minimum L1 - 7 V Output current signal at "l" -rated value -permissible range lamp Poad lA 40mAto1 A 25/50 W - Leakage current at "0" signal typically Parallel connection of outputs not possible Making capacity DIGITAL OUTPUT Terminal Assignment depends on the size of the fuse Permissibletotal current of outputs 100 % Short circuit protection (for each group) fuse(10AFF) (e.g. Wickmann 19231) Fault indication (red LED for each group) defective fuse Switching frequency l 315 mA maximum 10 Hz Cable length -shielded - unshielded 1000 m (3281 ft.) 300 m (984 ft.) isolation rating according t o VDE 0160 Rated isolation voltage (between groups) - isolation groups -tested w i t h 250V AC C 1500 VAC Rated isolation voltage (L1 t o ) - isolation groups -tested w i t h 250 V AC C 1500 V AC l Current consumption - from 5 V (internal) maximum 70 mA Power losses of the module Simplified Schematic EWA 4NEB 81 1 61 50-02d -& 1 typically 16 W approx. kg (2.43 lb.) 1.l Please note the max. dropout capacity of the load connected (contactors of the 3TJ1 to 3TJ5 series and contactors of the SIMICOMTseries cannot be triggered)! Technical Specifications CPU 945 Manual (6ES5 456-7LB11 Digital Output Module 8 X 115 to 230 VAC; 2 A Technical Specifications Number o f outputs Floating i n groups o f 8 yes (optocoupler) - 1 Load voltage L1 -rated value -frequency permissible range 115to230VAC 47 t o 63 Hz 89 t o 264 V - Output voltage - a t "l " signal minimum L1 - 7 V Output current signal a t "l" -rated value -permissible range - lamp load Output current at "0" signal typically Parallel connection o f outputs depends o n the size o f the fuse Permissible total current o f outputs 100 % Short circuit protection (for each group) fuse (6.3 A FF) (e.g. Wickmann 19231) Fault indication (red LED f o r each group) defective fuse Switching frequency maximum 1 0 Hz Cable length -shielded - unshielded l000 m 300 m Isolation rating according t o VDE 0160 Rated isolation voltage (between groups) isolation group -tested w i t h 250 V A C C 2700 V A C Rated isolation voltage (L1 t o & ) - isolation group -tested w i t h 250 V A C C 2700VAC - Terminal Assignment 1 n o t possible Making capacity DIGITAL OUTPUT 3 t o 5 mA Current consumption - f r o m 5 V(interna1) maximum 35 m A 'A Simplified Schematic Power losses o f the module typically 16W Weight approx. 1.l k g (2.43 lb.) 1 Please note t h e max. dropout capacity o f t h e load connected (contactors o f t h e 3TJl t o 3TJ5 series and contactors o f t h e SIMlCOMTseries cannot be triggered)! Technical Specifications CPU 945 Manual Digital Output Module 32 X 5 to 24 V DC; 0.7 A, Floating (6ES5 457-7LA11) Technical Specifications Number of outputs Floating in groups of 32 yes (optocoupler) 8 - Load voltage L1 - rated value -permissible range 5to24VDC 4.75 to 30 V Output voltage TTL compatible Output current for "l" signal maximum 100 mA Parallel connection of outputs possible Permissibletotal current of outputs aoo 76 Short circuit protection not available Limitation of the voltage induced on circuit interruption (for Vp = 30 V) -lOV Switching frequency - inductive load - resistive load 2 Hz 10 Hz Cable length -shielded - unshielded 1000 m (3281 ft.) 300 m (984 ft.) Isolation rating according t o VDE 0160 Rated isolation voltage (between groups) - isolation group -tested w i t h OUTPUT 32x5VDC 0.1A 30 V C 500 V Rated isolation voltage (5Vto ) -isolation group -tested with 30 V C 500 V Current consumption Terminal Assignment - Simplified Schematic - from 5 V(interna1) - from L1 (without load) maximum 100 mA maximum 4 mA Power losses of the module typically 6W Weight approx. 0.7 kg (1.54 lb.) 1 Transistor w i t h open collector - current sinking Technical Specifications CPU 945 Manual Relay Output Module for Measuring Currents 16 X 2 4 V DC (6ES5 458-7LA11) Number of outputs -contact bridge -galvanic isolation 3700-2501-011 Parallel connection of Permissibletotal current Switching frequency - resistive load - inductive load Switching voltage Switching capacity of the contacts - resistive load - inductive load maximum 60 Hz not permissible maximum 30 V DC 10Wat0.5A; not permissible Number of contact operating cycles according t o VD 0660, Supply voltage L+ -permissible range 20 t o 30 V maximum 3.6V Terminal Assignment - unshielded 1000 m (3281 ft.) 300 m (984 ft.) Isolation rating according t o VDE 0160 Rated isolation voltage (between contacts) - isolation group -tested w i t h Rated isolation voltage (contacts t o L ) isolation group -tested w i t h 500 V AC Rated isolation voltage (contacts t o & ) -isolation group -tested w i t h 30 V DC C 500 VAC - Simplified Schematic + Current consumption from 5 V (internal) fromL+ (for relay) - maximum 50 mA 240 mA Power losses of the module typically 5W Weight approx. 0.8 kg (1.76 lb.) CPU 945 Manual Technical Specifications Relay Output Module 8 X 30 V DCf230 V AC (6ES5458-7LB11) Technical Specifications Number of outputs -contact bridge 8 varistor SIOV-507-K275 Yes 1 V23057-A006-A402 (Siemens) -floating - i n groups of - relay type Limiting continuous current per contact 5A Parallel connection of outputs possible Permissibletotal current of outputs 400 % Switching capacity of the contacts - resistive load 5Aat250VAC 2.5Aat30VDC 1.5Aat250VAC 0.5 A a t 30 V DC - inductive load Switching frequency maximum 10 Hz Number of contact operating cycles according t o VDE 0660, Part 200 - AC11 - DC11 Supply voltage L+ (for relay) -rated value -permissible range -surge voltage at t -ripple DIGITAL OUTPUT Terminal Assignment ) 24 V DC 20 t o 30 V 0.5 sec. 35 V maximum 3.6V Isolation rating according to VDE 0160 Rated isolation voltage (between contacts) -isolation group -tested w i t h 250 VAC C 1500 VAC Rated isolation voltage (between contacts L + ) -isolation group -tested with 250 VAC C 1500 VAC Rated isolation voltaae (between contacts ) -isolation group -tested w i t h 250V AC C 1500VAC h Current consumption - f r o m 5V(internal) maximum 50 mA -from L+ (for relay) 200 mA Simplified Schematic Power losses of the module typically 4W Weight approx. 0.8 k g (1.76 lb.) CPU 945 Manual Technical Specifications Relav Output Module 16 X 230 V UC Technical Specifications Number o f outputs -contact bridge 16 varistor SIOV-507-K275 Yes 4 outputs MSR V23061-B1007-A401 -galvanic isolation - i n groups o f - relay type Switching capacity o f the contacts - resistive load 5.0 A a t 250 V A C 5.0 A a t 30 V DC 0.4AatllOVDC 1.5Aat250VAC l.OAat30VDC 0.08AatllOVDC - inductive load Switching frequency - resistive load - inductive load maximum Current load o f t h e relay contacts - o n e relay per r o o t - t w o relays " " -three " " " -four " " " 5 Alcontact 4 Alcontact 2.5 Alcontact 2 Alcontact Number o f contact operating cycles according t o VDE 0660, Part 200 - DC 1 4 Supply voltage L + /L- (for relay) - rated value -permissible range -surge voltage a t tS0.5 sec. -ripple maximum I OUTPUT 16x230 UC Relay I Cable length -shielded - unshielded 1000 m (3281 ft.) 300 m (984 ft.) Isolation rating according t o VDE 0160 Rated isolation voltage (contacts t o L ) - isolation group -tested w i t h 250VAC C 1500 V A C Rated isolation voltage ) (contacts t o isolation group -tested w i t h 250 V A C C 1500 V AC + Terminal assignment - Current consumption - from 5 V (internal) 2 mA(+4mAper active channel) 16 m A per active channel - f r o m L+(for relay) Power losses o f the module typically Weight approx. CPU 945 Manual Technical Specifications 15.2.6 Digital InputIOutput Module Digital Input/Output Module 32 X 2 4 V DC; 0.5 A Number of inputs -rated value The technical specifications for the inputs correspond t o those of the 6ES5 430-7LA11 digital input module. Number of outputs yes (optocoupler) Output current -rated value The technical specifications for the outputs correspond t o those of the 6ES5 451-7LA11 digital output module. Outputs 0 t o 3 and 4 t o 7 8tolland12to15 can be connected in parallel Parallel current Permissiblecurrent l 0 0 % at 35OCand 50 % at 55 O C (related t o the sum of the currents Current consumption -from 5V(internal) maximum 50 mA Power loss Setting on I M 306 INPUTIOUTPUT 3 2 x 2 4 ~ ~ ~ Terminal Assignment typically 18 W approx. 0.7 kg (1.54 lb.) 16-channel The inputs and outputs are referenced under the same address (e.g. 10.0 t o 11.7 and Q 0.0 t o Q 1.7). Example: Addressing must be as follows for module start address "0": EWA 4NEB 81 1 61 50-02d 15-39 Technical Specifications CPU 945 Manual 15.2.7 Analog lnput Modules Analog lnput Module 8 X I/V/PT 100, Floating Number of inputs channels at a time PT100: 2 1 0 M Q +IV:90kn;2% k5V: 5 0 k ~ ; 2 % k50mV k500mV : k2% : k4.5% 12 bits plus sign or 13 bits two's k50mV : ?5% Measuring principle integrating Conversion principle voltage-time conversion (dual-slope) k20mA :+6.7%0 + 4 t o 2 0 m A : k6.79b Integration time (adjustable for optimum noise suppression) 20 msec. at 50 Hz 16.6 msec. a t 60 Hz k 2 0 m A : 25Q; 1 %O k 4 t o 20 mA:31.25 Q; Two-wire connection: four-wire connection for PT 100 Coding time (Single coding for 2048 units) maximum 60 msec. at 50 Hz 50 msec. at 60 Hz Cycle time for - 8 inputs 0.48 sec. at 50 Hz maximum 18 Vor 75Vfor Permissible voltage max. 1 msec. and between inputs and a duty cycle 1 : 20 between inputs and central grounding point (destruction limit) maximum 75 V DC 160 VAC Permissiblevoltage between the reference potential of a nonfloating sensor and the central grounding point Cable length -shielded maximum 200 m (656 ft.); 5 0 m f o r k 50mV Front connector 46 pins Isolation rating according toVDE 0160 Rated isolation voltage (channel to channel) -tested w i t h 500 V Rated isolation voltage (channel t o ) -tested w i t h 500 V Current consumption - rated value - ripple Vpp - permissible range (including ripple) 24VDC 3.6 V 20 t o 30 V Current consumption - from 5 V (internal) typically 0.1 5 A 0.1 A - from 24V (external) typically Power losses of the module typically 3 W Weight approx. 0.4 kg (0.88 lb.) EWA 4NEB 81 1 6150-02d CPU 945 Manual Technical Specifications Analog Input Module 8 X IIVIPT 100, (6ES5 460-7LA13) Floating Technical Specifications Number of inputs Floating lnput ranges (rated values) 8 voltagelcurrent inputs or 8 inputs for PT 100 Yes 2 50 mV; 4 500 mV; PT100; k 1 V: 4 5 V ; k10V; 4 2 0 m ~ ; 4 t o 20 mA (can be selected for four channels at a time using range cards) + Disconnectablewirebreak test current Noise suppression forf=nx (50160 Hzk 4 %) n=1.2, -Common mode noise min. BV,<l V) -Series mode noise min. (peak noise value < rated value of range) Configurable ... Basic error limits lnput resistance Operational error limits (0C t o 55OC) Type of connection for sensors Two-wire connection; four-wire connection for PT100 Digital representation of the input signal 12 bits sign or 13 bits two's complement (2048 units= rated value) Measuring principle integrating Conversion principle Voltage-timeconversion Integration time (adjustable for optimum noise suppression) 20 ms at 50 Hz 16.6 ms at 60 Hz Coding time (Single coding for 2048 units) I + Cycle time for - 8 inputs max. 60 ms at 50 Hz 50 ms at 60 Hz Permissiblevoltage max. 75 V DC160 VAC Error indication for EWA 4NEB 81 1 61 50-02d Cable length max. yes (exceeding 4095 units) Configurable in the range 50 mV, 500 mV and PT100 (only measuring leads) 200111; 5 0 m a t k 50mV Front connector 46-pole Isolation rating to VDE 0160 Rated isolation voltage &) (channel t o - tested with 500 V 0.48 s a t 50 Hz max. 18 V o r 75 V f o r max. 1 ms and a duty cycle of 1 : 20 -wire break of sensor line + + - shielded Permissible voltage between inputs and central grounding point (destruction limit) - overranging PT100 climatic measuring range Measuring range incl. override range approx. -100C t o 100C -Resolution 0.025 "C per unit - Basic error at T= 25C max. 1- 0.2 C ' -Operational error limit atT=O to65"C max. +l0.5 C ' -Range card 6ES5 498-1AAA11 - Current consumption -Rated value -Ripple Vpp -Permissible range (including ripple) 24 V DC 3.6 V 20 to30 V Current consumption -from 5 V (internal) -from 24V (external) typ. typ. 70 mA 50 mA Power losses of the module typ. 3W Weight approx. 0.7 kg (1.54 Ib) 1 5-41 Technical Specifications CPU 945 Manual Analog Input Module 4 X IIV, Floating + -0.05 to 1V -0.5 t o 10V -1 t o 20 mA 4 t o 20 mA for 2-wire transducer 4 t o 20 mA for 4-wire transducer + + + + (6ES5 463-4UAl 11-4UA121-4UB11/-4UB12) Max. permissible input voltage without causing k 30V; 75Vfor max. 1 ms 0 and a duty cycle of 1 :l Number of inputs Noise suppression -Common mode noise > 80dB(f=O to50kHz) > 40 dB (VSs0.1X UN) 100% (at full accuracy) -Temperature error Error message at overflow 0.6 X IO~IK yes (from 50 % override Inputs against earthing Measuring principle Conversion principle Voltage-frequency conversion against one another Permissible potential difference between the reference potentials of sensors and the module (VcM)and between the sensors (channels) Current consumption -Digital section of system bus -Analog section of load voltage -Enabling of module F IF- + max.25VAC!60VDC 5Vf. 5%; typ. 150 mA 24V; approx. 150 mA 24V; approx. 7 mA Integration time - 463-4UA111-4UA12 - 463-4UBl ll-4UB12 20 ms at 50 Hz 16 213ms at 60 Hz Coding time per measuring value - 463-4UA111-4UA12 - 463-4UBl lI-4UB12 20 ms at 50 Hz 162I3msat60Hz Cycle time for 4 measuring values (max. delay for measuring value acquisition) - 463-4UAl ll-4UA12 20 ms at 50 Hz - 463-4UBl ll-4UB12 162I3msat60Hz Inputs against L-: Vs = lkV; 1.2150 ps CPU 945 Manual Technical Specifications (6ES5 465-7eA13) Analog Input Module l 6 X IIV or 8 xPT 100. Nonfloating 1 Technical Specifications Noise suppression forf=nx(50/60 H z k I % ) n = l , 2. ... - common mode min. noise (Vp< lV) ? 50 mV; k 500 mV; - series mode noise min. PT100; k 1 V; k 5 V ; (peak noise value +10V; k20mA; < rated value of 4 t o 20 mA (can be selec. the range) ted for four channels at a time using range cards) Number of inputs 16 voltagelcurrent inputs or 8 inputsfor PT100 no Floating lnput ranges (rated values) + Input resistance I k50mV: zIOMQ k500 mV: 2 1 0 MQ PT100: 2 1 0 MQ ?1V:90k~:2% k 5 V : 5 0 k ~ ;2% k10V: 5 0 k ~ ; 2 % k20mA:25Q;II % ? 4 t o 20 mA:31.25 Q; 1% Type of connection for sensors Two-wire connection; four-wire connection for PT100 Digital representation of the input signal 12 bits sign or 13 bits two's complement (2048 units =rated value) + Measuring principle integrating Conversion principle voltage-time conversion (dual-slope) Integration time (adjustable for optimum noise suppression) Coding time (single coding for 2048 units) 20 msec. at 50 Hz 16.6 msec. at 60 Hz maximum 60 msec. a t 50 Hz 50 msec. at 60 Hz - 16 inputs Cable length -shielded I maximum 200 m; 50 m f o r k 50 mV Front connector 46 pin Power supply - rated value - ripple Vpp - permissible range (including ripple) 24VDC 3.6 V 20 t o 30 V Current consumption typically 0.1 5 A from 24 V maximum 20 mAltransd ucer - from 5 V (internal) - Coding time - 8 inputs Operational error limits (OC t o 55OC) 0.48 sec. at 50 Hz 0.96 sec. at 50 Hz Permissiblevoltage maximum l 8 V or 75 V f o r max. 1 msec. and a duty between inputs and cycle o f 1 : 20 between inputs and central grounding point (destruction limit) Power losses of the module typically 0.75 W Weight approx. 0.4 kg (0.88 lb.) Permissiblevoltage maximum k 1 V between the reference potential of a nonfloating sensor and the central grounding point Error indication for - overranging -wire break of the sensor line Wire break test current disconnectable yes (exceeding 4095 units) can be designed for the ranges 50 mV, 500 mV (PT 100) configurable 1 only required for two-wire transducers or for disconnecting the wire break test current I Technical Specifications CPU 945 Manual Analog lnput Module 16 X IIV or 8 X IIV, Floating Technical Specifications Number o f inputs 1 6 individual or 8 differential inputs i n groups o f 4 o r 2 channels (switchable) voltage measurement o r current measurement Floating Yes Input ranges 0 t o 20 mA, 4 t o 20 mA, k20mA,Oto1.25V, Oto2.5V,Oto5V.1 t o 5 V . O t o l O V , k1.25V. k2.5V. k5V. k 1 0 V Input resistance -Voltage measuring range 2 1 0 M Q -Current measuring range 125 Q Type o f connection for sensors Two-wire connection Digital representation o f t h e input signal any o f the following representations - 12 bits two's complement - 11 bits sign - 12 bits binary + Measuring principle Momentary value decoding Conversion principle successive approximation Conversion time typically 25 psec. (per channel) Coding time (per measured value) Duration o f cyclic sampling (scan time) - f o r 8 measured values - f o r 8 measured values maximum 2 msec. maximum 4 msec. maximum k 30V (static) or k 75V (Pulse for max. 1 msec. and a d u t y cycle 1:20) Permissible isolation voltage between t h e reference potential and the central grounding p o i n t maximum 60 V AC175 V DC Noise suppression common mode noise (Vpp= 1 V) Operational error limits (0 "C t o 60 OC) -Voltage ranges 0.2 % outside 0 t o 1.25 V, + 1.25 V -Current ranges 0.2 % andOto1.25V. +1.25V Individual errors -Linearity -Tolerance -Polarity error 0.02 % 0.05 % 0.05 % Temperature error 0.005 %/K Cable length -shielded maximum 200 m (656 ft.) Front connector 43 pins Isolation rating t o VDE 0160 Rated isolation voltage (channels t o grounding point) tested w i t h 500 V Supply voltage -internal - external +5V+/-5% none Internal current consumption typically 0.7 A Power losses o f t h e module typically 3.5 W Weight approx. 0.4 k g Design ES 902 250 psec. Max. permissible input voltage (without destruction) Error indication f o r - Overflow - Internal errors Basic error limits -Voltage ranges 0.1 % outside 0 t o 1.25 V, + 1.25 V -Current ranges 0.2 % andOto1.25V. +1.25V yes (overflow b i t set) yes (error b i t (= E bit) set) minimum 70 dB Technical Specifications CPU 945 Manual 15.2.8 Analog Output Modules MANA = QVx Q1 X S+x S-X = = = = common reference point of all current and voltage channels voltage output channel X current output channel X sensor line+ channel X sensor Dine - channel X Technical Specifications CPU 945 Manual Analog Output Module 8 x k 10V; 0 t o 20 mA; Floating (6ES5 470-7LA12) Technical Specifications 8 voltage and current outputs floating (not between the Number o f outputs Type of outputs _+ Output ranges (rated values) Load resistance - for voltage outputs - for current outputs 10V; to 20 minimum 3.3 k a maximum 300 a Load connection Load to MANAterminal Digital representation of the output signal 11 bits plus sign (1024 units= rated value) Conversion time Imsec. Permissibleoverload capability approx. Short circuit protection Power supply - rated value - ripple Vpp permissiblerange (ripple included) Current consumption -from 5 V (internal) - from 24 V (external) typically 0.25 A typically 0.3 A Power losses of the module typically 8.5 W Weight approx. 0.4 kg (0.88 lb.) 25 % (up t o 1280 units ) Yes Short circuit current approx. 25 rnA(for a voltage output) Open circuit voltage approx. 18 V (for current output) Voltage between the reference potential (MANA terminal) and maximum 60 VAC175 V DC Linearity in the rated range ? 2.5 46o k 3 units maximum 200 m (656 ft.) Front connector max. 1 pF (per channel) EWA 4NEB 81 1 61 50-02d CPU 945 Manual Technical Specifications Analog Output Module 8 X ? IOV; Floating Terminal Assignment of the Front Connector Channel 0 Channel l Channel 2 Channel 3 Channel 4 Channel 5 36 MANA 37 38 39 40 . A X A A EWA 4NEB 81 1 61 50-02d MANA = QVx S+x S- X = = = QV 6 S+6 5-6 41 42 43 QV 7 44 s+7 45 5-7 46 47 L-ov - Channel 6 Channel 7 common reference point of all current and voltage channels voltage output channel X sensor line channel X sensor line - channel X + Technical Specifications CPU 945 Manual Analog Output Module 8 x k 10V; Floating (6ES5 470-7LB12) Number o f outputs - rated value (ripple included) Load resistance minimum 3.3 k n Current consumption -from 5 V(interna1) -from 24V(external) typically 0.25 A typically 0.3 A Load t o MANA-terminal Load connection Power losses of Digital representation of the output signal typically 8.5 W approx. 0.4 kg (0.88 lb.) 25 % (up t o 1280 Short circuit protection approx. 25 mA Voltage between the reference Linearity in the rated range &2,5%0 k 3 units maximum 200 m (656 ft.) Front connector according t o VDE 0160 Capacitive load of max. lpF (per channel) Technical Specifications CPU 945 Manual Analog Output Module 8 X + 1 to 5 V; + 4 to 20 mA; Floating (6ES5 470-7LC12) CPU 945 Manual Technical Specifications Analog Output Module 8 X + 1 to 5 V; + 4 to 20 mA; Floating Number of outputs (6ES5 470-7LC12) - rated value - permissible range +l to5V; + 4 t o Current consumption Load resistance - for voltage outputs minimum 3.3 k n for current outputs maximum 300 n - - from 5 V (internal) - from 24 V (external) typically 0.25 A typically 0.3 A Power losses of typically 8.5 W Load connection Load t o MANA-terminal approx. 0.4 kg (0.88 lb.) Digital representation of the output signal Conversion time Permissible overload approx. 25 % (up t o 1280 units) Short circuit protection Voltage between the reference Linearity i n the rated range k 2.5 96o 5 3 units maximum 200 m (656 ft.) Front connector according t o VDE 0160 max. 1 p F (per channel) EWA 4NEB 81 1 61 50-02d CPU 945 Manual 15.2.9 Technical Specifications Signal Preprocessing Modules The following Signal Preprocessing Modules can be used in the 55-1 15U programmable controller with CPU 945. Table 15.1 Overview of Signal Preprocessing Modules l IP 240 Counter and pos. decoder mod. IP 241 Digital position decoder module 1.2A Yes Yes Ultrasonic pos. decoder mod. IP 242B Counter module IP 243 Analog module Yes 1.2 A No Yes 0.8 A No Yes Temperature control module IP 246 Positioning module I Yes I Yes I IP 247-4UA11 IP 247-4UA21 Positioning module I No 2.3 A IP 281 Counter module 0.6 A No Yes IP 288 Positioning module1 Cam controller 0.8 A No Yes WF 705 Position decoder 0.5 A No Yes WF 706 Positioning module 0.75 A (3-channel) 1.5 A (6-channel) No Yes WF 707 Cam controller WF 721 Positioning module Positioning module * ** I IP 252 Closed-loop control module For Order Nos. of the modules or relevant Manuals, please refer t o the Catalog Without sensor power supply Technical Specifications CPU 945 Manual 15.2.1 0 Communications Processors The following communications processors can be used in the 55-115U programmable controller with CPU 945: Table 15.2 Overview of Communications Processors CP 516 0.8 A No Yes 1.5 A Yes Yes 1.8A Yes Yes 2.2 A Yes Yes 1.0A Yes Yes 1.0A No No 0.45 A No' Yes Memory module CP 5241544 Computer link CP 525 Listinglcomputer link CP 526 Listinglcomputer link CP 530A Configuring a SlNEC L1 LAN CP 530 Configuring a SlNEC L1 LAN CP 543015431 Configuring a SlNEC L2 LAN CP 143-OAB.. Configuring a SlNEC H1 LAN - for monochrome VDUs - f o r colour VDUs Diagnostics processor * ** 1 2 3 For Order Nos. of the modules and the relevant manuals, please referto the Catalog Basic board see Section 3 "Installation Guidelines" can only be plugged in with adapter casing 6ES5 491-OLC11 can only be plugged in with adapter casing 6ES5 491-OLD1 1 can only be plugged in with adapter casing 6ES5 491-OLD1 1 (if required) CPU 945 Manual 15.2.1 1 Technical Specifications lnterface Modules The following interface modules can be used in the 55-115U programmable controller: Table 15.3 Overview of lnterface Modules a central controller (CC) (see expansion units (EUs) over a distance o f max. 600 m (1900 ft) a central controller (CC) in a distributed configuration (see Section 3.3). Adapter casing Terminator for IM 314 721 connecting cable (see Catalog ST 52.3) 6ES5 491-0LB12 6ES5 760-1AA11 Technical Specifications CPU 945 Manual Table 15.3 Overview of Interface Modules (Continued) 317 interface module forthe distributed connection of expantroller (CC) via fiber optic cables. 6ES5 491-0LB12 (6ES5 3173UA11) IM 308 (6ES5 3083UA12) used in connection with the [ M 307 interface module for the distributed connection of expansion units (EUs) t o a central controller (CC) via fiber optic cables. (5 V; internal requirement) lA Weight approx. 0.4 kg Accessories Adapter casing 722 connecting cable (see Katalog ST 52.3) The IM 308-B interface module is Current consumption (5 V; internal requirement) max. used for linking the ET 100 with 0.5 A Weight approx. 0.4 kg the 55-155U programmable controller. Accessories Adapter casing IM 308-B (6ES5 3083UBl l ) (6ES5 3183UA11) 6ES5 491-0LB12 The IM 308-8 interface module is Current consumption used for connecting the 55-1 15U (5 V; internal requirement) max. 0.6 A programmable controller t o the Weight approx. 0.5 kg SINEC L2 LAN (with DP protocol) Accessories Adapter casing IM 318 6ES5 491-OLB12 The IM 318 interface module is used in connection w i t h the IM 308 interface module f o r t h e distributed connection - over max. 3000 m (9900 ft) o f expansion units (EUs) t o a central controller (CC) . 6ES5 491-0LB12 Current consumption (5 V; internal requirement) max. 0.3A Weight approx.0.34 kg Accessories Adapter casing 6ES5 491-OLBI 2 CPU 945 Manual 15.2.12 Technical Specifications The 313 Watchdog Module (6ES5 313-3AA11) (6ES5 313-3AA11T) 313 Watchdog Module The 313 Watchdog module monitors signals on the S5 bus. It can be used t o check the connection between a central controller and an expansion unit for open circuits and short circuits. Technical Specifications Current consumption (at 5 V) maximum 0,4 A For further technical specifications see Manual C 79 000-B85000-C266-1 Accessories Adapter casing EWA 4NEB 81 1 61 50-02d 6ES5 494-OLAI 2 Technical Specifications 15.3 CPU 945 Manual Accessories Adapter Casing for Two Printed Circuit Boards (6ES5 491-OLB12) Technical Specifications Dimensions ( w X h X d ) in mm 43 X 303 X 187 Even modules which are not of the block type can be used in the 55-115U, provided an adapter casing is available. The adapter casing can take one module or, in the case o f the CR 700-3 subrack, t w o modules, but only one double-width module IP241, IP 245, IP 246 and IP 247 (self-ventilated model) IP 252 and CP 535. Adapter Casing for SIMATIC S5 CP 5801581 or for up t o 4 Printed Circuit Boards Technical Specifications Dimensions (wX h X d ) in mm Weight 86x 303 X 187 approx. 0,8 kg ( l .8 lb.) Even modules which are not o f the block type can be used in the 55-115U, provided an adapter casing is available. The adapter casing can take t w o double-width or 4 single-width modules; the SIMATIC S5 CP 5801581 can be used in the 55-115U programmable controller with the help of this adapter casing. EWA 4NEB 81 1 61 50-02d CPU 945 Manual Technical Specifications Adapter Casing for CP 551 Bulk Storage Memory or for up t o 6 Printed Circuit Boards (6ES5 491-OLCI 1) I 1 Technical Specifications Dimensions (wX h X d ) in mm Weight 129x 303 X 187 approx. 1.8 kg (3.97 Even modules which are not of the block type can be used in the 55-115U, provided an adapter casing is available. The adapter casing can take three double-width or six single-width modules; the CP 551 hard diskdrive can also be used in the 55-115U subracks with the help of this adapter casing. 490 Front Connector Screw terminals Crimpsnap-in Springloaded connectors Technical Specifications see Catalog ST 52.3 490 Front Connector 24-pole 46-pole 46-pole 46-pole - for screw-type terminals - 24-pole - 46-pole 763 jumper comb (for use with screw-terminal front connectors) 6ES5 490-7LB11 6ES5 490-7LB21 6ES5 763-7LA11 - for crimp snap-in connections 46-pole - without crimp contacts - with 50 crimp contacts Crimp contacts (250) Crimping tool for crimping the crimp contacts Extraction tool for crimp contacts 6ES5 490-7LA21 6ES5 490-7LA11 6XX3 070 6XX3 07 1 6ES5 497-8MA11 - for spring-loaded connectors - 46-pole 6ES5 490-7LC11 Technical Specifications CPU 945 Manual Simulator Technical Specifications see Catalog ST 52.3 Sirnusator - 32 switches/buttons 24 V DC can be plugged into - 16 switcheslbuttons 24/48/60 V AC/DC can be plugged into Fan Subassemblv If the 6ES5 951-7LD11 or 6ES5 951-7ND14 power supply modules carry a load o f more than 7 A, or if modules w i t h a high power consumption are used, a fan subassembly is necessary. ' Technical Specifications (6ES5 981-OHA11 and 6ES5 981-OHB11) Fan 6ES5 981-OHAI 1 6ES5 981-OHBI 1 23011 15 VAC - 10 % to+10 % 23011 15 VAC -IO%to+lO% Input voltage - rated value - tolerance Network frequency - Rated value 50160 Hz Input current typically 420 mA typically 420 mA 5.OA at 1.5A at 5.0 A 2.5A 1.5A 0.5A Contact rating - w i t h ohmic load 2.5 A - w i t h inductive load 0.5 A - Life span Operating cycles at 230 VAC 30 V DC at 230VAC 30 V DC 1.5~106AC11 at at at at 230 VAC 30 V DC 230 VAC 30V DC 1.5~106ACl1 EWA 4NEB 81 1 61 50-02d CPU 945 Manual Technical Specifications Fan Subassembly (Continued) Technical Specifications (6ES5 981-OHA21 and 6ES5 981-OHB21) Fan 6ES5 981-OHA21 6ES5 981-OHB21 Degree o f protection Radio interference suppression level lP2O t o DIN 40 050 lP2O t o DIN 40 050 A t o VDE 0871 A t o VDE 0871 Dimensions wxhxd(mm) Weight 423x110~135 16.6 X 3.93 X 5.31 in. 1.5 kg (3.3 lb.) 294x 11Ox 135 11.5 X 3.93 X 5.31 in. 1.4 kg (3 lb.) 6ES5 981-OGAI 1 6ES5 981-OJAI 1 6ES5 981-OGBI 1 6ES5 981-OJBl1 24 V DC +20Vto+30V 24 V DC +20Vto+30V typically 800 mA typically 800 mA 5.0A at 2.5A at 1.5A at 0.5Aat 5.0A at 2.5 A a t 1.5A at 0.5Aat Accessories Installation parts Filter mat unit Input voltage - rated value - permissible range (including ripple) Input current Contact rating - w i t h ohmic load -withinductiveload 230VAC 30VDC 230VAC 30VDC 230 VAC 30 V DC 230VAC 30VDC - Life span Operating cycles 1.5-106 DC11 1.5-106 DC11 Degree o f protection Radio interference suppression level IP20 t o DIN 40 050 IP20 t o DIN 40 050 A t o VDE 087 1 A t o VDE 0871 Dimensions wxhxd(mm) Weight 423x110~135 16.6~ 3 . 9 3 ~5.31 in. 1.5 kg (3.3 lb.) 294x110~135 1 1 . 5 ~ 3 . 9 3 ~ 5 . 3in. 1 1.4 kg (3 Ib.) 6ES5 981-OGAI 1 6ES5 981-OJAI 1 6ES5 981-OGBI 1 6ES5 981-0JB11 Accessories Installation parts Filter mat unit EWA 4NEB 81 1 61 50-02d Technical Specifications CPU 945 Manual Back-up Battery (6EW1 000-7AA) Technical Specifications Lithium battery (3.4 Vl5.2 Ah) - back-up time (at 25 "C and constant backup o f the CPU with memory submodule) - service life (at 25 "C) - external battery backup approx. approx. 2 years 5 years 3.4 t o 9 V Types of Fuses Wickmann 19231 2,5 A FF 4AFF 10 A FF I Gould GAB4 Types of Relays Siemens V23042 B201 B101 Gunther 3700-2501-011 Siemens V231 57-006-A402 6ES5 980-3BC21 6ES5 980-3BC51 6ES5 980-3BC41 Appendix A Appendix B Appendix C . . Dimension Drawings . . . Maintenance . . . Guidelines for Handling ElectrostaticSensitive Devices (ESD) A.2 Dimension Drawings of the Subracks . . . . . . .. . . . . . . . . . . . . . . . . . . A - 2 A.l A.2 A.3 Dimensions o f the Modules .......................................... Dimension Drawings o f the Subracks ................................ Dimensions for Installation in a 19-Inch Cabinet . . . . . . . . . . . . . . . . . . . . . . . A.l Module Dimensions ................................................ A . 1 A . 2 A . 3 A . 1 CPU 945 Manual Dimension Drawings A Dimension Drawings A.l Dimensions of the Modules 1 Operator control and display elements (e.g. when using a n adapter casing) protrude from the front (e.g. CP 525) Figure A.1 Dimension Drawings of the Modules Table A.l Module Dimensions .............................................................................................................................. ............................................................................................................................................................................................................... m , b m zmM&gg#$fggm@mgi ........................ Power Supply Module Central Processing Unit ;;;:;;;gw$jg$& ~~W:;~X~;:!:!:::;:;:;:;~;~~:~>>>:~>>>~.:~;:::::::::~:~: .............................. .................-. --187 (7.29) 65 (2.54) --187 (7.29) 4 3 (1.68) built in Digital and Analog Modules Adapter Casing Interface Module b EWA 4NEB 81 1 61 50-02d 25 (0.98) 133 (5.1 9) --- Dim ension Drawings A.2 CPU 945 Manual Dimension Drawings of the Subracks Figure A.2 Dimension Drawings of the Subracks CPU 945 Manual A.3 Dimension Drawings Dimension Drawings for Cabinet Installation Figure A.3 Dimensions for Installation in a 19-Inch Cabinet Important The 533.4 (20.80) spacing must be maintained even if no fan is used. B.2 B.2.1 B.2.2 B.2.3 Installing or Changing Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Removing the Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . InstallingtheBattery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Battery Disposal ............................................. B B B B . . . . 1 2 2 3 B.3 Changingthe Fan Filter . . . . . . . . . . . . . . . . . . . . . . . . .. . .... . . . .. . B . 3 CPU 945 Manual Maintenance Maintenance Proper functioning of the programmable controller can only be guaranteed if the electronic components have not been interfered with. This appendix describes the maintenance jobs you can perform on your programmable controller. These are Changing the fuses Installing and changing the batteries Changing the fan filter Replacing the fan motor B.l Changing Fuses For the output modules with red LED indicators for fuse failure, you can remove the fuses with a screwdriver (maximum width 3 mm). Swing the front connectors out t o access the fuses. Fuse specifications are noted on the inside o f the front doors. B.2 Installing or Changing Battery The power supply modules 6ES5 951-7LB2117NB21 are provided with a backup battery. Use a 3.4 V 1 5 Ah lithium battery (Order No. 6EW1 000-7AA; size C) for backup in those power supply modules. Its service life for continuous backup is a t least t w o years (one year when using CPs). The power supply modules 6ES5 951-7LD21/7ND41/7ND51 are provided with t w o backup batteries. Use a 3.6 V 1 1.75 Ah lithium battery each (Order No. 6ES5 980-OAE11; size AA) for backup in those power supply modules. Its service life for continuous backup is at least one year. Changing Battery in Power Supply Modules with 2 Backup Batteries Since the second battery takes over the backup function you can change the discharged battery without any problems. After changing of the battery, the backup function remains with the second battery. Only when this battery is discharged, the new battery takes over the backup functions. Note If you install or change a battery when the PLC is shut o f f and there is no external voltage supply, perform an Overall Reset on the CPU afterwards. Otherwise, the CPU cannot go into the RUN mode. Maintenance B.2.1 CPU 945 Manual Removing the Battery Proceed as follows: 1. Open the battery compartment as follows (see Figure B.1) O Press the slide down. O Swing the battery compartment door out and down. 2. Removing the battery Remove the battery by pulling the end of the plastic ribbon out. The battery slides out of i t s clamp and falls out. 3. Closing the battery compartment door Close the battery compartment door by swinging it back into place. Latch it with the slide. Figure B. 1 Opening the Battery Compartment B.2.2 Installing the Battery To install a battery, proceed as described below: 1. Open the battery compartment door (see Figure B.l) O Press the slide down and O swing the battery compartment door out and down. Install the battery after noting the following points: The poles are indicated on the back o f the battery compartment. The plastic ribbon should be t o the left o f the battery so that i t s end stays in a freely accessible position. Before using a lithium battery, you should depassivate it by loading it with 100 ohms for t w o hours. 2. Install the battery 3. Close the battery compartment door. Close the door o f the battery compartment by swinging it back into place. Latch it with the slide. EWA 4NEB 81 1 61 50-02d CPU 945 Manual B.2.3 Maintenance Battery Disposal Note the warning below and dispose of used batteries carefully! /I\ Warning Improper handling can cause a lithium battery t o catch fire and explode. Do not recharge or disassemble a lithium battery. Keep it away from water and open flame. Do not expose it t o temperatures greater than 100 " C! B.3 Changing the Fan Filter Under the fan is a filter (Order No. 6ES5 981-0JA11) t o keep the electronic components and the printed circuit boards in the modules clean. As preventive maintenance, change this filter regularly according t o the degree of air pollution in the PLC's environment. To change the filter, proceed as described below (see Figure B.2): 1. Pull out the dirty filter using the two handles O. 2. Place the new filter in the guide tracks O and push it back. Note You can change the filterwhile the PLC is operating. Figure B.2 Changing the Fan Filter EWA 4NEB 81 1 61 50-02d Maintenance B.4 CPU 945 Manual Replacing the Fan Motor The fan motors can be exchanged in all fan subassemblies of the S5-115U programmabie controller. For this purpose, Siemens offers a fan replacement package (Order No. 6ES5 988-7NA11). This package contains the following: Fan motor Plug-in connector Repair instructions Since the repair instructions form part of the fan replacement package, the removal and installation o f the fan motor is not described in this section. EWA 4NEB 81 1 61 50-02d CPU 945 Manual C Guidelines f o r Handling Electrostatic Sensitive Devices (ESD) Guidelines for Handling Electrostatic Sensitive Devices (ESD) What is ESD? All electronic modules are equipped with large-scale integrated ICs or components. Due t o their design, these electronic elements are very sensitive t o overvoltages and thus t o any electrostatic discharge. These Electrostatic Senstive Devices are commonly referred t o by the abbreviation ESD. Electrostatic sensitive devices are labelled with the following symbol Caution Electrostatic sensitive devices are subject t o voltages that are far below the voltage values that can s t i l l be perceived by human beings. These voltages are present i f you touch a component or module without previously being electrostatically discharged. In most cases, the damage caused by an overvoltage is not immediately noticeable and results in total damage only after a prolonged period o f operation. EWA 4NEB 81 1 61 50-02d Guidelines for Handling Electrostatic Sensitive Devices (ESD) CPU 945 Manual Electrostatic charging of objects and persons Every object with no conductive connection t o the electrical potential of i t s surroundings can be charged electrostatically. In this way, voltages up t o 15000 V can build up whereas minor charges, i.e. u p t o 100 V, are not relevant. Examples: Plastic covers Plastic cups Plastic-bound books and notebooks Desoldering device with plastic parts Walking on plastic flooring Sitting on a padded chair Walking on a carpet (synthetic) up t o 5000 V up t o 5000 V up t o 8000 V up t o 8000 V up t o 12000 V up t o 15000 V up t o 15000 V Limits for perceiving electrostatic discharges An electrostatic discharge is perceptible from 3500 V audible from 4500 V visible from 5000 V Afraction of these voltages is capable o f destroying or damaging electronic devices. Carefully note and apply the protective measures described below t o protect and prolong the life of your modules and components. General protective measures against electrostatic discharge damage Keep plastics away from sensitive devices. Most plastic materials have a tendency t o build up electrostatic charges easily. Make sure that the personnel, working surfaces and packaging are sufficiently grounded when handling electrostatic sensitive devices. If possible, avoid any contact with electrostatic sensitive devices. Hold modules without touching the pins o f components or printed conductors. In this way, the discharged energy cannot affect the sensitive devices. CPU 945 Manual Guidelines for Handling Electrostatic Sensitive Devices (ESD) Additional precautions for modules without housings Note the following measures that have t o be taken for modules that are not protected against accidental contact: Touch electrostatical sensitive devices only - if you wear a wristband complying with ESD specifications or - if you use special ESD footwear or ground straps when walking on an ESD floor. Persons working on electronic devices should first discharge their bodies by touching grounded metallic parts (e.g. bare metal parts of switchgear cabinets, water pipes, etc.). Protect the modules against contact with chargeable and highly insulating materials, such as plastic foils, insulating table tops or clothes made of plastic fibres. Place electrostatic sensitive devices only on conductive surfaces: - Tables w i t h ESD surface - Conductive ESD foam plastic (ESD foam plastic is mostly coloured black) - ESD bags Avoid direct contact of electrostatic sensitive devices with visual display units, monitors or TV sets (minimum distance t o screen > 10 cm). EWA 4NEB 811 61 50-O2d Guidelines for Handling Electrostatic Sensitive Devices (ESD) CPU 945 Manual The following Figure once again illustrates the precautions for handling electrostatically sensitive devices. a b c d e f g Conductive flooring material Table with conductive, grounded surface ESD footwear ESDsmock Grounded ESD wristband Ground connection o f switchgear cabinet Grounded chair Figure C.l ESD Measures Taking measurements and working on ESD modules Measurements may be taken on electrostatic sensitive devices only if the measuring device i s grounded (e.g. via protective conductor) or the t i p o f the isolated measuring tool has previously been discharged (e.g. by briefly touching grounded metal parts). EWA 4NEB 81 1 61 50-02d EWA 4NEB 81 1 61 50-02d List o f Abbreviations CPU 945 Manual List of Abbreviations List of Abbreviations Abbreviation Explanation ACCU l Accumulator 1 ACCU 2 Accumulator 2 AI Analog input module AQ Analog output module ASCll American Standard Code for Information interchange RASP Command output disable BR Base address register CBR "Receive" coordination byte CBS "Send" coordination byte CC 0 /CC 1 Condition code b i t 0 1 condition code bit 1 CP Communications processor CPU Central processing unit CSF STEP 5 control system flowchart method of representation DB Data block DBL Length register of data block DBS Start address register of data block DX Data block (extension) EMC Electromagnetic compatibility FB Function block FX Function block (extension) IP Intelligent I10 LAD STEP 5 ladder diagram method of representation NST Nesting stack NSTP 1 Nesting stack pointer OB Organization block 0P Operator panel OS Latching overflow, overflow flag ov Overflow, overflow flag PB Program block PG Programmer PIIIPII' Process image of the inputs PIQIPIQ' Process image of the outputs PLC Programmable controller PS Power supply List of Abbreviations ist o f Abbreviations Abbreviation Qvz I Explanation Timeout SB I Il I I 5TL 1 STEP 5 statement l i s t method of representation RL 0 RS RT SAC Result of logic operation System data area Extended system data area Step address counter sequence block CPU 945 Manual EWA 4 N E 81 1 61 50-02d Index CPU 945 Index A Block Access t o DBS and DEL registers - change Accessing - t h e PI1 - t h e PIQ - end -end - conditional - operations - parameter ACC U Actual operands Adapter casing Addition Addresses -analog modules -digital modules Address allocation - on the CPU Address field Addressing - 0 area Alarm clock function Analog input modules Analog modules - addresses -connecting Analog output modules -wire Analog value matching blocks - error diagnostics -stack -structure -types Blockaddress l i s t -cancel block - regenerating Block identifier -change Boolean logic operation BSTACK C Calculating interrupt response times Call -data block -function block Causes of malfunction CE-Marking Central controller Analog value processing -example Arithmetic operations ASCll code Centralized configuration Centralized configuration ASCll driver ASCll parameter set Availability Changing the fan filter Clock data area Clock function Code block call operation Back-up battery Base address register Cold restart characteristics Cold restart routine Collision of t w o timed-interrupts - response t o Basic operations Battery Binary logic operation Bit setting operation B i t test operation Central processing units Communications -capabilities - processor -system B i t s for the "receive" coordination Comparison operation byte (CBR) in a computer link Bits of the "receive" coordination byte (CBR) for SINEC L1 Compensating box Compressing Compressing the program memory Computer link Condition code generation Conditional block end CPU 945 Index Connecting -analog modules Data area -floating modules - nonfloating modules -thermocouples -copying Data Block - (DBIDX) - call operation Connecting digital modules -floating - non-floating -duplicate -generating - length register Connection - point-to-point -start address register Connection of measuring transducers A1 460 -transferring t o flag area Data IDs of the parameter block Connection of measuring transducers A1 463 -ASCII driver Data IDs o f t h e parameter block Connection of measuring transducers -computer link A1 465 Connection-sensors Data IDs of the SlNEC L1 parameter Control panel of the CPU Data interchange (computer link) Control power supply Data interchange block Control system flowchart (CSF) -data handling bocks Conversion operation - interprocessor communication Coordination byte for "receive" flags - l10 area (CB R) - ASCII driver - S5 backplane bus -computer link Data traffic - point-to-point connection - SlNEC L1 Data transport - ASCII driver - SlNEC L1 Coordination byte for "send" (CBS) - ASCII driver DB 1 -computer link - configuration - point-to-point connection - SlNEC L1 -default settings Correction value Count Count down Counter Counter operation Counting up CPU CSA Approbation Current counter status Cyclic program execution - initializing - parameter error code - parameterizing DEL register - access - read and write DES register - access - read and write Decrement Deleting a data block Digital input modules Digital inputloutput module Digital logic operations Cyclicsampling Digital modules -addresses Digital output -disable and enable Digital output modules Digital representation of an analog value Index CPU 945 Dimension drawings - cabinet installation -modules - subracks Display generation operation Distributed configuration Division A- 3 A- l A-2 8-28 3-11, 3-14,1-5 8-20 E Generating a data block GRAPH 5 Grounding Guidelines for handling electrostatic sensitive devices (ESD) Handling the process signals Electrical installation Enable operation Equipotential bonding I Error - response Indexed access t o DX 110 error - address indexed access t o FX -analysis -diagnostics -signalling input module Installing Error diagnostics with the analog value matching blocks Expansion units Extended error diagnostics -analog value matching blocks Extended pulse Extensionfor sign -fan - f a n subassernbly 3-4 -front connector - moduY es 10-74 8-12 2-76 -system Integral blocks Intelligent module - inputloutput module Interface module F Failure characteristics Fan - installing - subassembly Field transfer Fixed slot address assignment Fixed-point comparison operation -technical specification 6-2 8-18 Fixed-point double-word comparision Interference voltage operations 8-19 Flag 2-6,6-15 -transferring to data block 2-69 Floating-point comparison operations 8-19 Floating-point numbers 7-23.8-44 FORCE 44 FORCE VAR 4-4 Formal operand 7-14 Front connectors 3-23,15-57 Function block - (FBIFX) - parameters Fuse Interfacing capabilities -first serial interface -second serial interface 7-9,7-13.7-16 Interference-free design Interference-free operation Interprocessor communication flag area lnterrupt -analysis - characteristics -disable -enable - selectively disabled -selectively enabled -stack Interrupt-driven program processing Interrupt mask lnterrupt 0 8 8-24 7-6 3-28,3-36 C-l Index CPU 945 Interrupt processing Operating modes lnterrupt response -after timeout I10 access without QVZ Isolated transducers -changing - "RUN" - "STOP" Operating system services -disable digital outputs - interrupt response after J Job status word Jump operation timeout - PI0 access without QVZ - page access - read and write DBL registers L - read and write DBS registers Lightning protection Linear programming Line group Loading - register contents Load operation Operation type Operator functions of the CPU Organization block (00) Output modules Overall reset Load power supply Load power supply unit P Page Page access without QVZ Parameter block -computer link - ASCII Driver M Maintenance Machinery Directive Parameter set (computer link) PID control algorithm Pin assignments Measuring range module Measuring the scan time Mechanical installation Mechanical slot coding Memory submodule - A1 460 - A1 463 - A1 465 Methods of representation Mode number PLC malfunctions Point-to-point connection Power supply - ASCII driver -computer link Power supply module Process interrupt Process 110 image transfer Modifying blocks Modifying the program Module-interrupt-initialing Mounting racks -changing Processing an arithmetic operation Processing operation Program block (PE) Multiplication N Nesting depth Nesting stack 7-9 7-5 Nesting stack pointer New PT100 climatic measuring range Non-isolated transducers Number representation 7-5 10-15 10-5 7-21 0 Off-delay Program - error -execution - execution level - memory -test -trace Programmable controllers linked via the SlNEC L1 LAN On-delay Operand EWA 4NEB 81 1 6150-02d Index CPU 945 Programmer interface Programmer module Sampling Programming device Scaling Programming error Programming interrupt blocks Scan monitoring time Scan time Programm processing - time-controlled PT100 climatic measuring range - basis for calculating - breakdown -estimating - measuring Pulse Scan time triggering R Schematic of the CPU Range card Schematic representation of Ready delay Real-time clock conversion Selective sampling - parameterizing - programming Send mailbox for SlNEC L4 Sequence block (SE) Receive mailboxes for SlNEC L1 Sequential process 110 image transfer Registers Serial interface Setlreset operation Relays -output module Reliability Representation of the digital input Setting a counter Setting addresses - AS 463 value Setting of measuring range - 460,465,466 - 463 Setting up data blocks Resetting a counter Resistancethermometers - connecting t o 6ES5 460 - connecting t o AI 465 Response the substitution error Response time - parallel process 110 image transfer - sequential process I10 image transfer - 463 Shielding devices Shift operation Simulator SINEC L1 - module - parameter block - parameter assignment Slot coding element Software protection Response t o timeout Start a timer Starting the control program Response t o transfer error Startu p Restart -delay - A1 460 - A I 463 Restart characteristicsof the CPU - A I 465 Retentive feature - A1 466 Rotate operation Statement l i s t (STL) RS422-AI485 module STATUS RUN mode STATUS register STATUS VAR STEP address counter STEP 5 blocks Index CPU 945 Stored on-delay and reset U Structure -address UL Approbation Unconditional block end USTACK - block - w i t h floating modules v - w i t h non-floating modules Structured programming Structure of the clock data area Substitution operation V.24 module Variable time loop Subtraction System -data -error W Watchdog module Wiring -analog output module Wirebreak signal - resistancethermometers Wiring - error level -operation T Technical specification Testing the control program Thermocouples - connecting 41 10-7, 10-20 Time base Time value Time-controlled program execution 8-9 8-9.8-58 2-28 Timed-interrupt OB Timed-interrupt-driven program processing TIMEOUT - response t o 2-28 2-35 Timer operation Timers 8-8,s-58 2-6.6- 15 Transducer - connecting 2-34 10-5 10-11,lO-22 Transducer wiring - A1 460 Transfer operation Transferring -data (computer link) - t h e program 12-84 47 - t o the system data area Transferring register contents Transmission protoco[ 3964(R) 8-67 8-65 12-77 TTY module Types of representation of the digital input value - A I 460,465,466 12-108 10-45 Types of representation of the digital input value - AI 463 10-53 EWA 4NEB 81 1 6150-02d