June 2008
EB12_02.4
LatticeXP™ Standard Evaluation Board
User’s Guide
2
LatticeXP Standard Evaluation Board
Lattice Semiconductor User’s Guide
Introduction
The LatticeXP Standard Evaluation Board provides a convenient platform to evaluate, test and debug user designs.
The board consists of a LatticeXP-10 FPGA in a 256 fpBGA package, power input jacks, a clock oscillator (33MHz)
and I/O connections. The LatticeXP I/Os are connected to a rich variety of interfaces including switches (momen-
tary and ON/OFF), LEDs, SMA pads, RJ45, 0.10” headers and PCB test points.
The information in this document pertains to boards marked as ‘Rev. A’ and ‘Rev. B’. This marking is located on the
front of the board, beneath the Lattice logo. Any information that only applies to either the ‘Rev. A’ or ‘Rev.B’ board
will be explicitly stated as such.
Features
Included
• LatticeXP FPGA: LFXP10C-5F256C or LFXP10E-5F256C
• On-board power supply (rev. B only)
• Prototyping area
• 188 user I/Os, grouped in eight I/O banks
• Independent voltage control for core, I/O and clock voltages
• 33MHz on-board oscillator
• Status LEDs, input switches
• Lattice ispDOWNLOAD cable
• AC adapter (rev. B only)
Optional
• Optional SMA connectors (up to 16) for high-speed clock and data interfacing. The board includes pads for these
connectors. The SMA connectors must be procured and installed separately by the user.
Software Support
• To target your HDL design to the LatticeXP device, use the ispLEVER
®
design software. You can learn more
about ispLEVER on the Lattice web site at: www.latticesemi.com/software.
• To download your program to the LatticeXP device, use the ispVM
®
System software. ispVM System can be
downloaded from the Lattice web site at: www.latticesemi.com/ispvm.
• ispTRACY™ in-system logic analysis support (ispTRACY is included with the ispLEVER design software)
3
LatticeXP Standard Evaluation Board
Lattice Semiconductor User’s Guide
Figure 1. LatticeXP Standard Evaluation Board
Electrical, Mechanical and Environmental Specifications
The nominal board dimensions are 7 inches by 3.9 inches. The environmental specifications are as follows:
• Operating temperature: 0ºC to 55ºC
• Storage temperature: -40ºC to 75ºC
• Humidity: < 95% without condensation
• VDC input (+/- 10%) up to 4A
Additional Resources
Additional resources related to this board can be downloaded from the web at www.latticesemi.com/boards. Click
on the appropriate evaluation board, then follow the appropriate links for items such as updated documentation,
software, sample designs, IP evaluation bitstreams, and more.
LatticeXP Device
This board features a LatticeXP FPGA with either a 3.3V or a 1.2V DC core. The board is populated with a Lat-
ticeXP-10 device in plastic 256-ball fpBGA (1mm pitch) package. Density migration is possible for Lattice XP
devices in the 256 fpBGA package. A complete description of this device can be found in the LatticeXP Family Data
Sheet on the Lattice web site at www.latticesemi.com.
Device Core and I/O Voltage
Boards shipping with a 3.3V DC core device will allow operation of the core between 1.8V and 3.3V DC. Jumpers
(JP4, JP5 and JP6) are available to switch between 3.3V, 1.2V and an adjustable supply between the other two
voltages. Boards shipping with a 1.2V core device will not have headers installed for core voltage selection. JP4 will
be shorted on the board. Figure 2 shows the core voltage selection jumpers.
4
LatticeXP Standard Evaluation Board
Lattice Semiconductor User’s Guide
Figure 2. Core Voltage Select Jumpers
The LatticeXP device has eight sysIO™ buffer banks; each is capable of supporting multiple I/O standards. Each
sysIO bank has its own I/O supply voltage (VCCIO) and two voltage reference resources, VREF1 and VREF2, that
allow each bank to be completely independent from the others.
Please refer to the LatticeXP Family Data Sheet for additional information about supported I/O standards. This data
sheet can be downloaded from www.latticesemi.com.
The LatticeXP Standard Evaluation Board provides individual control of each I/O bank capable of supporting
VCCIO between 1.2V and 3.3V. The board provides jumper blocks which allow the end user to select 1.2V, 3.3V or
an adjustable voltage between these two voltages. Figure 3 shows a typical layout for a VCCIO select jumper block.
Table 1 details the VCCIO bank selection connectors.
Figure 3. VCCIO Jumper Block
Table 1. VCCIO Connectors
Device Clocks
The LatticeXP Standard Evaluation Board provides a variety of ways to input clock signals to the LatticeXP device.
These include an on-board crystal oscillator, SMA connectors and 0.1” header pins. Clock inputs connect to pri-
VCCIO Bank Connector Number
VCCIO0 JP1
VCCIO1 JP2
VCCIO2 JP3
VCCIO3 JP10
VCCIO4 JP11
VCCIO5 JP12
VCCIO6 JP13
VCCIO7 JP14
3.3V
ADJ
1.2V
VCC_CORE
JP4
JP5
JP6
1.2V
ADJ
3.3V
VCCIO
5
LatticeXP Standard Evaluation Board
Lattice Semiconductor User’s Guide
mary clock inputs and device PLL inputs. Clock outputs connect to PLL outputs and external feedback pins. Table
describes the clock connections to the LatticeXP device.
The oscillator socket accepts both full-size and half-size oscillators and can route to different clock inputs, depend-
ing on installation of several 0
Ω
resistors. The oscillator has a 22
Ω
series termination resistor at the oscillator out-
put. These inputs correspond with PCLKT0, RLM0_PLLT_IN_A and RUM0_PLLT_IN_A. The oscillator supply
voltage is changeable, via the VCC_OSC header, located at JP9. The onboard oscillator operates at 3.3V. It is pos-
sible to power this socket from the following supplies: 3.3V, VCCIO0, VCCIO2 or VCCIO3, depending on the I/O
bank being used and the operating conditions for the chosen oscillator.
Table 2. Lattice XP-10 Clock Pins and Connections
XP-10 Pin Number XP Pin Label PCB Connection
1
On-Board OSC.
Resistor
2
Buffered (Y/N)
3
N16 RLM0_PLLT_IN_A J23-15 R89 Y
M16 RLM0_PLLC_IN_A J23-16 N/A N
L13 RLM0_PLLT_OUT_A J23-9 N/A N
M14 RLM0_PLLC_OUT_A J23-10 N/A N
N15 RLM0_PLLT_FB_A J23-17 N/A N
P15 RLM0_PLLC_FB_A J23-18 N/A N
F16 RUM0_PLLT_IN_A J24-7 R90 Y
G16 RUM0_PLLC_IN_A J24-8 N/A N
F13 RUM0_PLLT_OUT_A J24-17 N/A N
G12 RUM0_PLLC_OUT_A J24-18 N/A N
C15 RUM0_PLLT_FB_A J24-3 N/A N
D15 RUM0_PLLC_FB_A J-24-4 N/A N
M1 LLM0_PLLT_IN_A SMA J12 N/A N
M2 LLM0_PLLC_IN_A SMA J14 N/A N
K4 LLM0_PLLT_OUT_A SMA J16 N/A N
K5 LLM0_PLLC_OUT_A SMA J18 N/A N
L5 LLM0_PLLT_FB_A SMA J20 N/A N
M6 LLM0_PLLC_FB_A SMA J22 N/A N
G3 LUM0_PLLT_IN_A SMA J19 N/A N
G2 LUM0_PLLC_IN_A SMA J21 N/A N
E3 LUM0_PLLT_OUT_A SMA J15 N/A N
F4 LUM0_PLLC_OUT_A SMA J17 N/A N
D2 LUM0_PLLT_FB_A SMA J7 N/A N
D3 LUM0_PLLC_FB_A SMA J9 N/A N
A7 PCLKT0_0 OSC R104 N
A8 PCLKC0_0 Test Point N/A N
H16 PCLKT2_0 J24-9 N/A N
J16 PCLKC2_0 J24-10 N/A N
T10 PCLKT4_0 Test Pad N/A N
T11 PCLKC4_0 Test Pad N/A N
K1 PCLKT6_0 SMA J8 N/A N
K2 PCLKC6_0 SMA J10 N/A N
1. Check the schematic pages for termination resistors connected to these pins.
2. 0_ resistor connecting to on-board oscillator.
3. Indicates a non-inverting buffer between the oscillator and pin.
6
LatticeXP Standard Evaluation Board
Lattice Semiconductor User’s Guide
Figure 4 shows the layout and connections for JP9. There is also an optional 10K pull-up (R91) connect to pins 1
and 4 of the oscillator socket, in the event a oscillator with enable is required. The oscillator is also connected to
J24-26, for use as a clock input to a logic analyzer.
Figure 4. VCC_OSC Jumper Block
VCCIO0
VCCIO2
VCCIO3
JP9
3.3V
VCC_OSC
7
LatticeXP Standard Evaluation Board
Lattice Semiconductor User’s Guide
Device I/O Banks 0 and 1
I/O banks 0 and 1 represent general purpose I/O banks, which connect to a combination of test pads, switches,
LEDs and an RJ45 connector. The switches consist of two user defined push-button switches and an 8-position
DIP switch. Both types of switches are pulled up to the associated VCCIO voltage with 10K
Ω
resistors and con-
nected to GND when activated (pushed or levered in the down position). LEDs are active (lit) when the device I/O is
low. The RJ-45 connector is connected using paired I/O connections. Table 3 details the I/O banks 0 and 1 connec-
tions. Unlisted pins in banks 0 and 1are connected to test pads on the board.
Table 3. Banks 0 and 1 I/O Connections
I/O Bank
XP-10 Pin
Number Connection
0 C5 LED D8
0 F5 LED D9
0 B1 LED D10
0 A2 LED D11
0 B2 LED D12
0 B3 LED D13
0 A3 LED D14
0 D5 LED D15
0 D6 RJ-45 J25-1
0 E6 RJ-45 J25-2
0 B6 RJ-45 J25-3
0 A4 RJ-45 J25-4
0 B5 RJ-45 J25-5
0 A5 RJ-45 J25-6
0 D7 RJ-45 J25-7
0 E7 RJ-45 J25-8
0 C6 Switch SW7 1
0 A6 Switch SW7 2
0 D8 Switch SW7 3
0 E8 Switch SW7 4
0 C7 Switch SW7 5
0 B7 Switch SW7 6
0 B8 Switch SW7 7
0 E9 Switch SW7 8
1 C8 Pushbutton SW0
1 C9 Pushbutton SW1
8
LatticeXP Standard Evaluation Board
Lattice Semiconductor User’s Guide
Device I/O Banks 2 and 3
I/O banks 2 and 3 contain general purpose I/Os with LVDS transmit/receive pairs. These I/O pairs are connected to
two 0.1” headers suitable for connecting to a logic analyzer or ribbon cable. Table 4 details the I/O banks 2 and 3
connections.
Table 4. Banks 2 and 3 I/O Connections
Each I/O pair is connected to a resistor termination network, and the trace lengths are matched. Figure 5 shows
the termination network for these differential pairs. These resistors are not installed, and the series resistors use a
trace between the resistor pads. This trace can be cut to allow the installation of a series termination resistor. The
series resistors are 0805 size and the parallel resistors are 0603 size. Figure 5 shows this trace in relation to the
resistor pads.
Figure 5. Differential I/O Termination Network
I/O Bank
LatticeXP-10 Pin Number Connection
Positive Negative
1
Positive Negative
1
2 C15 D15 J24-3 J24-4
2 E14 F14 J24-1 J24-2
2 E15 F15 J24-19 J24-20
2 C16 B16 J24-5 J24-6
2 F13 G12 J24-17 J24-18
2 F16 G16 J24-7 J24-8
2 G14 G15 J24-13 J24-14
2 H14 H15 J24-21 J24-22
2 H12 H13 J24-15 J24-16
2 H16 J16 J24-9 J24-10
2 G13 J24-25
3 J14 J15 J23-1 J23-2
3 K16 L16 J23-3 J23-4
3 K13 K12 J23-13 J23-14
3 K15 K14 J23-5 J23-6
3 N16 M16 J23-15 J23-16
3 L14 L15 J23-7 J23-8
3 L13 M14 J23-9 J23-10
3 N14 M15 J23-21 J23-22
3 R16 P16 J23-19 J23-20
3 N15 P15 J23-17 J23-18
3 L12 SW4
1. Blank cell indicated pin with no negative paired pin.
Connector
XP-10 A Pad
XP-10 B Pad
9
LatticeXP Standard Evaluation Board
Lattice Semiconductor User’s Guide
Figure 6. Close-up of Series/Passthrough
Device I/O Banks 4 and 5
I/O banks 4 and 5 consist of general purpose I/O pins. These pins connect to test pads on the board. The test pads
are paired with a ground pad, which are spaced on 0.1” centers. In addition to the test pads, these I/O banks are
connected to a pull-up, pull-down and series resistor network. The resistor network is not populated. The series
resistors are 0805 size, and the pull-up/pull-down resistors are 0603 size. Figure 7 shows the schematic for the
individual I/O termination network.
Table 5. Banks 4 and 5 I/O Connections
Position Pin Number GND Row Pin Number GND Row
1T3 GND P5 GND
2 R3 GND R1 GND
3 N5 GND R2 GND
4 R4 GND T2 GND
5 T5 GND R5 GND
6 P6 GND T4 GND
7 N6 GND T6 GND
8 M7 GND R6 GND
9 N7 GND T8 GND
10 M8 GND P8 GND
11 R8 GND N8 GND
12 T9 GND P7 GND
13 T7 GND R9 GND
14 R7 GND P9 GND
15 T11 GND N9 GND
16 T10 GND M9 GND
17 P13 GND T13 GND
18 R13 GND P14 GND
19 M11 GND N10 GND
20 N11 GND M10 GND
21 R10 GND P11 GND
22 P10 GND N12 GND
23 R12 GND R11 GND
24 T12 GND P12 GND
25 T15 GND T14 GND
26 R15 GND R14 GND
Resistor Pads
Cut trace to
install resistor
10
LatticeXP Standard Evaluation Board
Lattice Semiconductor User’s Guide
Figure 7. Banks 4 and 5 I/O Termination Network
Device I/O Banks 6 and 7
I/O banks 6 and 7 contain general purpose I/Os with LVDS transmit/receive pairs. The I/O pairs in these banks
have been routed to test pads on the PCB and eight pairs have been routed to SMA connectors. Table 6 details the
I/O bank 6 and 7 SMA connections. Unlisted pins are connected to test pads on the board.
Table 6. Bank 6 and 7 I/O Connections
Pairs routed to SMA connectors are connected with series and parallel termination resistors, similar to the network
shown in Figure 5 (see Bank 2 and 3 description). The SMA connectors are not included with the LatticeXP-Stan-
dard board, and must be procured and installed separately. AMP SMA connector 221780-1 or similar is recom-
mended.
I/O Bank
LatticeXP-10 Pin Number SMA Connection
Positive Negative
1
Positive Negative
1
6 K1 K2 J8 J10
6 M1 M2 J12 J14
6 K4 K5 J16 J18
6 L5 M6 J20 J22
7 D2 D3 J7 J9
7 E1 F1 J11 J13
7 E3 F4 J15 J17
7 G3 G2 J19 J21
Test Points XP-10 A Pad
VCCIO
11
LatticeXP Standard Evaluation Board
Lattice Semiconductor User’s Guide
Programming Headers
Two programming headers are provided on the evaluation board, providing access to the LatticeXP JTAG port.
Both 1x10 and 2x5 formats are available for compatibility with all Lattice ispDOWNLOAD
®
cables. The pinouts for
the headers are provided in Tables 6 and 7.
Important Note:
The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWN-
LOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any other JTAG
pins. Failure to follow these procedures can in result in damage to the LatticeXP FPGA device and render the
board inoperable.
Table 7. JTAG Programming Headers Function JP8 (2x5)
Table 8. JTAG Programming Headers Function JP7 (1x10)
Power Supply
Power can be supplied to the LatticeXP Standard Evaluation Board via the banana jacks (J1, 2, 5, 6 – all PCB revi-
sions), or a coaxial DC connector (J3 – Rev. B PCB only), which receive power from either a bench power supply or
a brick style power supply.
[Rev. B Only] The output from the DC system is controlled by switch SW1. This is a small surface mount switch that
enables and disables the LTC1775 DC-DC conversion chip. The output voltages from the power supply are enabled
when the switch is in the left position.
[Rev. B Only] The 5.0V to 28.0V DC input voltage (input to either J2 or J3) is converted by DC-DC converters and
switching power supplies to provide 3.3V, 1.2V, and an adjustable DC source on the board. The output from these
JTAG Programming Function JP8 Pin Number (2x5)
TCK 1
GND 2
TMS 3
GND 4
TDI 5
VCC (3.3V) 6
TDO 7
GND 8
TRST 9
PROGRAM 10
JTAG Programming Function JP7 Pin Number (1x10)
VCC (3.3V) 1
TDO 2
TDI 3
PROGRAM 4
TRST 5
TMS 6
GND 7
TCK 8
DONE 9
INIT 10
12
LatticeXP Standard Evaluation Board
Lattice Semiconductor User’s Guide
supplies travels through surface mounted fuse holders. Fuses are supplied and prevent over-current conditions
from damaging the components on the board (vendor: Littlefuse, make: Nano SMF Very Fast Acting, 1.5A or 3A).
Both Rev. A and Rev. B boards may be supplied with DC voltage through the banana plug connector. On both
boards, J4 is the GROUND connection point, J1 is the +3.3V input, J6 is the +1.2V input and J5 is the input for the
Adjustable rail. J2 connects to the VIN input of the on-board power supply of the Rev. B board. J2 is unconnected
on the Rev. A board. To directly connect power to the banana jacks on the Rev. B board, the SMT fuses must be
removed. SMT fuses are not installed on Rev. A boards.
Ordering Information
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: techsupport@latticesemi.com
Internet: www.latticesemi.com
Revision History
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.
Description Ordering Part Number
China RoHS Environment-
Friendly Use Period (EFUP)
LatticeXP10C Evaluation Board - Standard (upper voltage) LFXP10C-L-EV
LatticeXP10C Evaluation Board - Standard (lower voltage) LFXP10E-L-EV
ispLEVER Base with LatticeXP10 Standard Development Kit LS-XP10-BASE-PC-N
Date Version Change Summary
— —
Previous Lattice releases.
August 2006 02.1
Changes to I/O Bank column of Bank 6 and 7 I/O Connections table.
March 2007 02.2
Added Ordering Information section.
April 2007 02.3
Added important information for proper connection of ispDOWNLOAD
(Programming) Cables.
June 2008 02.4
Updated schematic.
10
13
LatticeXP Standard Evaluation Board
Lattice Semiconductor User’s Guide
Appendix A. Schematic
Figure 8. LatticeXP Evaluation Board
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
AA
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LatticeXP Evaluation Board
A
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18Wednesday, September 07, 2005
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18Wednesday, September 07, 2005
Bank 0
Bank 3
FPGA
Bank 6
Bank 5
Bank 7
Bank 1
Bank 2
Bank 4
XP
Lattice Semiconductor Corporation
Prototype
Area
SMAs for Testing
Differential or
Single Ended
High-speed Signals
Diffferential
Signals and
Logic
Analyzer
Headers
Single Ended Signal
Testing
Page 2
Page 3
Page 4
Page 6
Page 5
Programming
Interfaces Power Supplies
Page 7
14
LatticeXP Standard Evaluation Board
Lattice Semiconductor User’s Guide
Figure 9. JTAG and FPGA Programming
5
5
4
4
3
3
2
2
1
1
DD
C C
B B
A A
TCK
TDO
TDI
TCK
TDO
CFG0
CFG1
CFG0
TCK
TMS
TDI
TDI
TDO
INITN
INITN
PROGRAMN
PROGRAMN
PROGRAMN
PROGRAMN
DONE
DONE
TRST
DONE
CFG1
VCC_3.3V
INITN
TCK
TRST
PROGRAMN
TDI
TDO
VCC_3.3V
VCC_3.3V
VCC_3.3V
VCC_3.3V
TMS
TMS
TMS
DONE
VCC_3.3V
VCC_CORE
VCCM_3.3V
Title
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JTAG and FPGA Programming
Custom
28Tuesday, June 17, 2008
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JTAG and FPGA Programming
Custom
28Tuesday, June 17, 2008
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JTAG and FPGA Programming
Custom
28Tuesday, June 17, 2008
TDO
PROGRAMN
DONE
TDI
TMS
TCK
INITN
Download Cable Header
Input
Input
Output
Output
Output
Output
ispJTAG Download
Cable Headers
[7]
[7]
Down = 0, Up = 1
Input
CFG1 CFG0 Description
0 0 Slave Serial, External Device
0 1 Master Serial, External Device
1 0 Slave Parallel, External Device
1 1 I nternal Flash
Gate Source
Drain
SOT-23
[7]
PLANES FOR VCC and GND should be
seperate. These are to isolate /
filter noise to PLL power
Silk Screened 8 pin SOIC
package with X through it.
Printing to say no PROM
needed.
MT2MT2
1
C46
10uF
SizeC
C46
10uF
SizeC
FD1FD1
1
C41
0.1uF
CC0402
C41
0.1uF
CC0402
JP8
HEADER5X2
hdr5x2_100mil
JP8
HEADER5X2
hdr5x2_100mil
2
4
6
8
10
1
3
5
7
9
MT3MT3
1
D6
YELLOW_LED
CR0603
D6
YELLOW_LED
CR0603
C30
0.1uF
CC0402
C30
0.1uF
CC0402
MT1MT1
1
C36
0.1uF
CC0402
C36
0.1uF
CC0402
C23
0.1uF
CC0402
C23
0.1uF
CC0402
C25
0.1uF
CC0402
C25
0.1uF
CC0402
FD2FD2
1
C43
10uF
SizeC
C43
10uF
SizeC
C40
0.1uF
CC0402
C40
0.1uF
CC0402
L4 INDUCTORL4 INDUCTOR
1 2
R39
4.7K
CR0603
R39
4.7K
CR0603
SW2
SW DIP-2
261milX425mil
SW2
SW DIP-2
261milX425mil
1
2
3
4
Q7
BSS138LT1
Q7
BSS138LT1
D7
GREEN_LED
CR0603
D7
GREEN_LED
CR0603
C24
10uF
SizeC
C24
10uF
SizeC
FD3FD3
1
MT4MT4
1
R40
470
CR0603
R40
470
CR0603
C35
0.01uF
CC0402
C35
0.01uF
CC0402
R41 0 CR0603R41 0 CR0603
C44
0.01uF
CC0402
C44
0.01uF
CC0402
C31
10uF
SizeC
C31
10uF
SizeC
C39
0.01uF
CC0402
C39
0.01uF
CC0402
JP7
HEADER1X10
JP7
HEADER1X10
1
2
3
4
5
6
7
8
9
10
R36 10K CR0603R36 10K CR0603
TP2
CCLK
TP2
CCLK
C27
0.1uF
CC0402
C27
0.1uF
CC0402
LFXP10E (fpBGA256)
(5 OF 5)
U4E
LFXP10E-5F256C
LFXP10E (fpBGA256)
(5 OF 5)
U4E
LFXP10E-5F256C
GNDH8
GNDH9
GNDH10
GNDJ7
GNDJ8
GNDJ9
GNDJ10
GNDK7
GNDK8
GNDK9
GNDK10
GNDL6
GNDL11
GNDT1
GNDT16
GNDA1
GNDA16
GNDF6
GNDF11
GNDG7
GNDG8
GNDG9
GNDG10
GNDH7
VCC
D4
VCC
D13
VCC
E5
VCC
E12
VCC
M5
VCC
M12
VCC
N4
VCC
N13
VCCAUX
E4
VCCAUX
E13
VCCAUX
M4
VCCAUX
M13
TDI
D14
TMS
C14
TCK
B14
TDO
E16
VCCJ
D16
CFG0 C4
CFG1 B4
DONEC3
PROGRAMNC2
INITNP3
CCLK C1
VCCP0
H4
VCCP1
J12 GNDP0 H5
GNDP1 J13
L5 INDUCTORL5 INDUCTOR
1 2
FD4FD4
1
C45
10uF
SizeC
C45
10uF
SizeC
TP1
TRST
TP1
TRST
C34
0.1uF
CC0402
C34
0.1uF
CC0402
R38
470
CR0603
R38
470
CR0603
C32
0.1uF
CC0402
C32
0.1uF
CC0402
C26
10uF
SizeC
C26
10uF
SizeC
C38
0.1uF
CC0402
C38
0.1uF
CC0402
C28
0.1uF
CC0402
C28
0.1uF
CC0402
FD5FD5
1
C47
0.01uF
CC0402
C47
0.01uF
CC0402
C42
10uF
SizeC
C42
10uF
SizeC
SW3
SW PUSHBUTTON
4.7mmX3.5mm
SW3
SW PUSHBUTTON
4.7mmX3.5mm
1 2
R37 10K CR0603R37 10K CR0603
C33
0.01uF
CC0402
C33
0.01uF
CC0402
FD6FD6
1
C29
0.1uF
CC0402
C29
0.1uF
CC0402
C37
0.01uF
CC0402
C37
0.01uF
CC0402
15
LatticeXP Standard Evaluation Board
Lattice Semiconductor User’s Guide
Figure 10. Banks 3 and 4
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
OSC_CLK
VCCIO_3
VCC_3.3V
GSRN
OSC_CLK
VCCIO_2
VCCIO_0
VCCIO_3
VCCIO_2
VCC_3.3V
OSC_CLK
GSRN
VCCIO_0
Title
veR
rebmuN
tnemu
c
oD
e
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<Doc> A
Banks 3 and 4
B
38
Tuesday, June 17, 2008
Title
v
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r
eb
mu
N tn
emucoD
eziS
teeh
S
:etaD of
<Doc> A
Banks 3 and 4
B
38
Tuesday, June 17, 2008
Title
v
eR
r
eb
mu
N tn
emucoD
eziS
teeh
S
:etaD of
<Doc> A
Banks 3 and 4
B
38
Tuesday, June 17, 2008
[7]
Oscillator
14x2 Header
Top View
1
2
27 28
[4]
[7]
[7]
Routing to Connector for pairs needs to be matched
Routing to Connector for pairs needs to be matched
[4]
R67 0R67 0
R820R820
R79 DNSR79 DNS
R74 DNSR74 DNS
C49
10uF
SizeC
C49
10uF
SizeC
R60 0R60 0
R89
0
DNS
R89
0
DNS
R77 0R77 0
JP9
HEADER 4X2
JP9
HEADER 4X2
12
3 4
5 6
78
R61 0R61 0
R73 DNSR73 DNS
R52 0R52 0
R47 0R47 0
R63 DNSR63 DNS
J23
HEADER 14x2
J23
HEADER 14x2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
C48
0.1uF
CC0603
C48
0.1uF
CC0603
R76 0R76 0
C51
0.01uF
CC0402
C51
0.01uF
CC0402
R62 DNSR62 DNS
R54 0R54 0
R90
0
DNS
R90
0
DNS
R51 DNSR51 DNS
Y1
33MHz
DIP14
Y1
33MHz
DIP14
1
1
2
2
3
3
4
4
5
5
6
6
7
788
99
10 10
11 11
12 12
13 13
14 14
R70 0R70 0
R55 0R55 0
R46 0R46 0
R870R870
R91
10K
CR0603
R91
10K
CR0603
R50 DNSR50 DNS
R71 0R71 0
R840R840
C52
10uF
SizeC
C52
10uF
SizeC
C54
0.01uF
CC0402
C54
0.01uF
CC0402
R85DNSR85DNS
R80DNSR80DNS
R64 0R64 0
R810R810
R49 0R49 0
R42 0R42 0
R65 0R65 0
U6
SN74AUP1G34
U6
SN74AUP1G34
NC
1
A
2
GND
3
VCC 5
Y4
R69 DNSR69 DNS
R780R780
C50
0.1uF
CC0402
C50
0.1uF
CC0402
R580R580
C53
0.1uF
CC0402
C53
0.1uF
CC0402
R68DNSR68DNS
R75 0R75 0
R57 DNSR57 DNS
R43 0R43 0
R59 0R59 0
R480R480
BANK 2BANK 3
LFXP10E (fpBGA256)
(3 OF 5)
U4C
LFXP10E-5F256C
BANK 2BANK 3
LFXP10E (fpBGA256)
(3 OF 5)
U4C
LFXP10E-5F256C
PR34B / RLM0_PLLC_FB_A
P15
PR33B
P16
PR34A / RLM0_PLLT_FB_A
N15
PR32B / RLM0_PLL_RST
M15
PR33A / RDQS33
R16
PR31A / VREF0_3
N14
PR29B / RLM0_PLLC_OUT_A
M14 PR29A / RLM0_PLLT_OUT_A
L13
PR28B
L15 PR28A
L14
PR26A
L12
PR25B / RLM0_PLLC_IN_A
M16 PR25A / RLM0_PLLT_IN_A
N16
PR24B
K14 PR24A / RDQS24
K15
PR23B
K12 PR22A / VREF1_3
K13
PR21B
L16 PR21A
K16
PR19B
J15 PR19A
J14
PCLKC2_0 / PR17B J16
PR16B H13
PCLKT2_0 / PR17A H16
RUM0_PLL_RST / PR15B H15
RDQS16 / PR16A H12
VREF0_2 / PR14A H14
PR13B G15
PR13A G14
RUM0_PLLC_IN_A / PR12B G16
RUM0_PLLT_IN_A / PR12A F16
PR11B G13
RUM0_PLLC_OUT_A / PR8BG12
RUM0_PLLT_OUT_A / PR8AF13
PR7B B16
RDQS7 / PR7A C16
PR6B F15
VREF1_2 / PR5A E15
PR4B F14
PR4A E14
RUM0_PLLC_FB_A / PR3B D15
RUM0_PLLT_FB_A / PR3A C15
VCCIO2_G11 G11
VCCIO2_H11 H11
VCCIO3_J11
J11
VCCIO3_K11
K11
R44 DNSR44 DNS
R72 0R72 0
R56 DNSR56 DNS
R88 0R88 0
R269 0R269 0
R45 DNSR45 DNS
J24
HEADER14x2
J24
HEADER14x2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
R66 0R66 0
R86DNSR86DNS
R830R830
R53 0R53 0
U7
SN74AUP1G34
U7
SN74AUP1G34
NC
1
A
2
GND
3
VCC 5
Y4
R92 22R92 22
16
LatticeXP Standard Evaluation Board
Lattice Semiconductor User’s Guide
Figure 11. Banks 0 and 1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SW1
GSRN
SW0
RJ6
RJ7
VCCIO_0
VCCIO_0
RJ0
RJ1
RJ2
RJ3
RJ4
RJ5
RJ0
RJ2
RJ4
RJ6
RJ1
RJ3
RJ5
RJ7
VCCIO_0
SW0
SW1
VCCIO_1
VCCIO_0
OSC_CLK
VCCIO_1
GSRN
Title
ve
R
re
b
muN
tne
mu
co
D
ez
iS
t
eehS
:
etaD of
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Banks 0 and 1
B
48
Tuesday, June 17, 2008
Title
v
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mu
N tn
emucoD
eziS
teeh
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:etaD of
<Doc> A
Banks 0 and 1
B
48
Tuesday, June 17, 2008
Title
v
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r
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mu
N tn
emucoD
eziS
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:etaD of
<Doc> AB
48
Tuesday, June 17, 2008
[7]
Global Reset
or User
Defined
[7]
[3]
[3]
TP_15TP_15
TP_B13TP_B13
TP_B15TP_B15
TP_A5TP_A5
R96
220
CR0603
R96
220
CR0603
C58
0.01uF
CC0402
C58
0.01uF
CC0402
SW7
SW DIP-8
861milX425mil
SW7
SW DIP-8
861milX425mil
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
R107
10K
CR0603
R107
10K
CR0603
SW4SW PUSHBUTTON
4.7mmX3.5mm
SW4SW PUSHBUTTON
4.7mmX3.5mm
1 2
R97
220
CR0603
R97
220
CR0603
C59
0.1uF
CC0402
C59
0.1uF
CC0402
TP_C9TP_C9
R98
220
CR0603
R98
220
CR0603
D10
GREEN_LED
CR0603
D10
GREEN_LED
CR0603
TP_A10TP_A10
C57
0.1uF
CC0402
C57
0.1uF
CC0402
TP_A4TP_A4
D14
GREEN_LED
CR0603
D14
GREEN_LED
CR0603
TP_B11TP_B11
SW6SW PUSHBUTTON
4.7mmX3.5mm
SW6SW PUSHBUTTON
4.7mmX3.5mm
1 2
TP_9TP_9
R99
220
CR0603
R99
220
CR0603
TP_A13TP_A13
R112
10K
CR0603
R112
10K
CR0603
TP_16TP_16
R106
10K
CR0603
R106
10K
CR0603
TP_A14TP_A14
TP_14TP_14
TP_A15TP_A15
TP_C8TP_C8
C62
0.01uF
CC0402
C62
0.01uF
CC0402
TP_E6TP_E6
TP_A7TP_A7
TP_A9TP_A9
R111
10K
CR0603
R111
10K
CR0603
BANK 0
BANK 1
LFXP10E (fpBGA256)
(4 OF 5)
U4D
LFXP10E-5F256C
BANK 0
BANK 1
LFXP10E (fpBGA256)
(4 OF 5)
U4D
LFXP10E-5F256C
PT35B
A15 PT35A
B15
PT34B / VREF0_1
D12 PT34A / TDQS34
C11
PT33B
A14 PT32A
B13
PT31B
F12 PT31A
E11
PT30B
A13 PT30A / D0
C13
PT29B / D1
C10 PT29A / VREF1_1
E10
PT28B
A12 PT28A / D2
B12
PT27B / D3
C12 PT27A
A11
PT26B
B11 PT26A / TDQS26
D11
PT25B
B9 PT24A / D4
D9
PT23B
A10 PT23A / D5
B10
PT22B / D0 (MSB)
D10 PT22A
A9
PT21B/D7(LSB)
C9 PT21A
C8
BUSY / PT20B E9
CS1N / PT20A B8
PCLKC0_0 / PT19B A8
PCLKT0_0 / PT19A A7
PT18BB7
TDQS18 / PT18AC7
PT17B E8
PT16A D8
DOUT / PT15B A6
WRITEN / PT15A C6
PT14B E7
VREF0_0 / PT14A D7
PT13B A5
DI / PT13A B5
PT12B A4
CSN / PT12A B6
PT11B E6
PT11A D6
VREF1_0 / PT10B D5
TDQS10 / PT10A A3
PT9B B3
PT8AB2
PT7B A2
PT7A B1
PT6B F5
PT6A C5
VCCIO0_F7 F7
VCCIO0_F8F8
VCCIO1_F9
F9
VCCIO1_F10
F10
D11
GREEN_LED
CR0603
D11
GREEN_LED
CR0603
TP_D9TP_D9
R103
10K
CR0603
R103
10K
CR0603
D15
GREEN_LED
CR0603
D15
GREEN_LED
CR0603
TP_C10TP_C10
D16
RED_LED
CR0603
D16
RED_LED
CR0603
C56
10uF
SizeC
C56
10uF
SizeC
TP_10TP_10
R105
10K
CR0603
R105
10K
CR0603
TP_E11TP_E11
TP_17TP_17
TP_C11TP_C11
TP_B12TP_B12
TP_6TP_6
R110
10K
CR0603
R110
10K
CR0603
TP_13TP_13
TP_D7TP_D7
TP_B5TP_B5
D8
GREEN_LED
CR0603
D8
GREEN_LED
CR0603
TP_D10TP_D10
TP_A11TP_A11
TP_B9TP_B9
C61
0.1uF
CC0402
C61
0.1uF
CC0402
R101
220
CR0603
R101
220
CR0603
D12
GREEN_LED
CR0603
D12
GREEN_LED
CR0603
TP_A8TP_A8
TP_A12TP_A12
TP_8TP_8
TP_11TP_11
TP_E10TP_E10
TP_F12TP_F12
R104
0
R104
0
R109
10K
CR0603
R109
10K
CR0603
TP_18TP_18
C63
0.1uF
CC0402
C63
0.1uF
CC0402
TP_D12TP_D12
TP_B6TP_B6
TP_E7TP_E7
TP_7TP_7
J25
RJ-45
J25
RJ-45
12
3 4
5 6
78
R102
10K
CR0603
R102
10K
CR0603
SW5SW PUSHBUTTON
4.7mmX3.5mm
SW5SW PUSHBUTTON
4.7mmX3.5mm
12
TP_C12TP_C12
C60
10uF
SizeC
C60
10uF
SizeC
R93
220
CR0603
R93
220
CR0603
R100
220
CR0603
R100
220
CR0603
TP_B10TP_B10
D9
GREEN_LED
CR0603
D9
GREEN_LED
CR0603
TP_D6TP_D6
R108
10K
CR0603
R108
10K
CR0603
R94
220
CR0603
R94
220
CR0603
D13
GREEN_LED
CR0603
D13
GREEN_LED
CR0603
TP_D11TP_D11
C55
0.1uF
CC0402
C55
0.1uF
CC0402
TP_C13TP_C13
TP_12TP_12
R95
220
CR0603
R95
220
CR0603
17
LatticeXP Standard Evaluation Board
Lattice Semiconductor User’s Guide
Figure 12. Banks 4 and 5
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
B6
B25
B13
B10
B15
B14
B20
B24
B21
B23
B0
B1
B14
B6
B18
B15
B20
B6
B7
B15
B1
B12
B0
B14
B25
B21
B6
B5
B24
B13
B18
B3
B12
B1
B8
B25
B10
B11
B10
B22
B20
B15
B12
B20
B19
B24
B23
B22
B9
B19
B18
B19
B19
B17
B25
B9
B11
B0
B21
B7
B22
B4
B14
B13
B4
B8
B8
B11
B2
B23
B18
B8
B2
B9
B21
B12
B2
B22
B17
B23
B13
B5
B24
B5
B9
B10
B0
B17
B1
B5
B17
B2
B11
B3 B3
TOE
TOE
B7
B3
B16 B16
B16B16
B4B4
B[25..0]
B7
A10
A11
A22
A12
A16
A24
A24
A4
A5
A11
A20
A8
A8
A14
A19
A19
A6
A25
A12
A4
A5
A10
A1
A21
A13
A7
A7
A23
A14
A11
A17
A13
A2
A3
A16
A19
A20
A24
A24
A0
A6
A9
A25
A14
A12
A5
A20
A25
A21
A13
A2
A18
A5
A6
A1
A17
A13
A22
A2
A8
A8
A15
A7
A2
A10
A1
A18
A16
A0
A[25..0]
A6
A9
A20
A25
A23
A12
A10
A0
A17
A23
A23
A14
A3
A16
A19
A17
A21
A21
A3
A4
A11
A0
A9
A9
A15
A15
A7
A22
A18
A15
A22
A18
A3
A4A1
VCCIO_5
VCCIO_4
VCCIO_5
Title
veRreb
mu
N tn
emu
c
oD
eziS
te
e
h
S
:etaD of
<Doc> A
Banks 4 and 5
B
58
Tuesday, June 17, 2008
Title
v
eR
r
eb
mu
N tn
emucoD
eziS
teeh
S
:etaD of
<Doc> A
Banks 4 and 5
B
58
Tuesday, June 17, 2008
Title
v
eR
r
eb
mu
N tn
emucoD
eziS
teeh
S
:etaD of
<Doc> A
Banks 4 and 5
B
58
Tuesday, June 17, 2008
[7]
Test Points have
0.100 inch spacing.
Optional pull-up, pull-down,
and pad resistors. Do not
load these resistors.
Test Points have
0.100 inch spacing.
Optional pull-up, pull-down,
and pad resistors. Do not
load these resistors.
[7]
R207
DNS
R207
DNS
R216
DNS
R216
DNS
TPT9GTPT9G
R231
0
R231
0
TPT11GTPT11G
R1780R1780
TP_R2TP_R2
R227
DNS
R227
DNS
R174
DNS
R174
DNS
TP_T14TP_T14
R192
0
R192
0
R176
DNS
R176
DNS
TP_R6TP_R6
R202
DNS
R202
DNS
TPM11GTPM11G
R241
DNS
R241
DNS
TP_N12TP_N12
R2180R2180
R242
DNS
R242
DNS
R114
DNS
R114
DNS
R255
DNS
R255
DNS
R228
DNS
R228
DNS
TPR13GTPR13G
TP_P8TP_P8
R166
DNS
R166
DNS
R267
DNS
R267
DNS
TPM10GTPM10G
TP_P5TP_P5
R1570R1570
R254
DNS
R254
DNS
R200
DNS
R200
DNS
TP_T11TP_T11
TPN9GTPN9G
R141
DNS
R141
DNS
TPR6GTPR6G
TPM8GTPM8G
R1450R1450
R262
DNS
R262
DNS
R211
0
R211
0
R256
DNS
R256
DNS
R259
DNS
R259
DNS
R196
DNS
R196
DNS
R148
DNS
R148
DNS
TPT13GTPT13G
TP_R3TP_R3
TP_T9TP_T9
TP_T3TP_T3
R121
DNS
R121
DNS
R128
DNS
R128
DNS
R162
DNS
R162
DNS
TPP8GTPP8G
R152
0
R152
0
TP_N7TP_N7
R220
DNS
R220
DNS
TP_T15TP_T15
TP_T5TP_T5
R2450R2450
R187
DNS
R187
DNS
R115
DNS
R115
DNS
R2100R2100
TP_P7TP_P7
R1970R1970
R223
DNS
R223
DNS
R154
DNS
R154
DNS
TPR12GTPR12G
TPT3GTPT3G
R184
0
R184
0
TPT15GTPT15G
TP_T2TP_T2
R233
DNS
R233
DNS
R133
DNS
R133
DNS
R144
0
R144
0
R182
DNS
R182
DNS
TPM9GTPM9G
R213
DNS
R213
DNS
TPP7GTPP7G
TPT5GTPT5G
R209
DNS
R209
DNS
R1700R1700
R232
0
R232
0
R2370R2370
TPT14GTPT14G
R180
DNS
R180
DNS
TP_P10TP_P10
R212
0
R212
0
R236
DNS
R236
DNS
TP_T8TP_T8
TPM7GTPM7G
R215
DNS
R215
DNS
TP_T4TP_T4
R1900R1900
R249
DNS
R249
DNS
TP_N11TP_N11
TPT8GTPT8G
R265
DNS
R265
DNS
R171
0
R171
0
R167
DNS
R167
DNS
R257
DNS
R257
DNS
R264
DNS
R264
DNS
R124
DNS
R124
DNS
R146
DNS
R146
DNS
R246
DNS
R246
DNS
R156
DNS
R156
DNS
R159
0
R159
0
R201
DNS
R201
DNS
R1370R1370
TP_R8TP_R8
TP_N6TP_N6
R1250R1250
R142
DNS
R142
DNS
R122
DNS
R122
DNS
R136
DNS
R136
DNS
TPR14GTPR14G
TP_TOETP_TOE
R195
DNS
R195
DNS
TP_R1TP_R1
TP_N8TP_N8TPN8 GTPN8G
C66
0.01uF
CC0402
C66
0.01uF
CC0402
R221
DNS
R221
DNS
R2170R2170
R160
DNS
R160
DNS
R238
0
R238
0
R252
0
R252
0
TP_P14TP_P14
R169
DNS
R169
DNS
TPP14GTPP14G
TPN11GTPN11G
TP_N9TP_N9
TP_P6TP_P6
C69
0.01uF
CC0402
C69
0.01uF
CC0402
R131
0
R131
0R134
DNS
R134
DNS
TPR8GTPR8G
TPT4GTPT4G
TPN5GTPN5G
TP_R9TP_R9
R175
DNS
R175
DNS
TP_R12TP_R12
R193
DNS
R193
DNS
TP_T12TP_T12
R234
DNS
R234
DNS
TPR9GTPR9G
R235
DNS
R235
DNS
TPR2GTPR2G
R222
DNS
R222
DNS
TPN6GTPN6G
R117
DNS
R117
DNS
R2250R2250
TP_R5TP_R5
R1380R1380
R248
DNS
R248
DNS
TPP9GTPP9G
R189
DNS
R189
DNS
R199
0
R199
0
TP_N10TP_N10
R258
DNS
R258
DNS
R263
DNS
R263
DNS
R1500R1500
R208
DNS
R208
DNS
R123
DNS
R123
DNS
TPR7GTPR7G
R239
0
R239
0
R247
DNS
R247
DNS
TP_P9TP_P9
TPN12GTPN12G
R1980R1980
R1770R1770
R266
DNS
R266
DNS
R173
DNS
R173
DNS
R214
DNS
R214
DNS
R139
0
R139
0
R244
0
R244
0
C64
10uF
SizeC
C64
10uF
SizeC
R155
DNS
R155
DNS
R120
DNS
R120
DNS
R181
DNS
R181
DNS
TPN10GTPN10G
TP_R11TP_R11
R149
DNS
R149
DNS
TPR11GTPR11G
R2050R2050
R158
0R158
0
C67
10uF
SizeC
C67
10uF
SizeC
R206
DNS
R206
DNS
TPR5GTPR5G
R151
0
R151
0
R147
DNS
R147
DNS
TPR4GTPR4G
TPT6GTPT6G
R126
DNS
R126
DNS
R226
DNS
R226
DNS
TPT12GTPT12G
TP_P13TP_P13
R135
DNS
R135
DNS
R168
DNS
R168
DNS
TP_M7TP_M7
R251
0
R251
0
TPP11GTPP11G
TPP6GTPP6G
R300 0R300 0
R172
0
R172
0
R113
DNS
R113
DNS
TPR15GTPR15G
R161
DNS
R161
DNS
R219
0
R219
0
TPN7GTPN7G
TPP5GTPP5G
TP_M10TP_M10
TP_T13TP_T13
R203
DNS
R203
DNS
TP_M11TP_M11
TP_M9TP_M9
TPT2GTPT2G
TPP10GTPP10G
R229
DNS
R229
DNS
TPT10GTPT10G
TP_R7TP_R7
BANK 4BANK 5
LFXP10E (fpBGA256)
(2 OF 5)
U4B
LFXP10E-5F256C
BANK 4BANK 5
LFXP10E (fpBGA256)
(2 OF 5)
U4B
LFXP10E-5F256C
PB6A
R4
PB6B
N5
PB7A / VREF0_5
P5
PB7B
R1
PB8A
N6
PB9B
M7
PB10A / BDQS10
R2
PB10B
T2
PB11A
R3
PB11B
T3
PB12A
T4
PB12B / VREF1_5
R5
PB13A
N7
PB13B
M8
PB14A
T5
PB14B
P6
PB15A
T6
PB15B
R6
PB16A
P7
PB17B
N8
PB18A / BDQS18
R7
PB18B
T7
PB19A
P8
PB19B
T8
PB20A
R8
PB20B
T9
PB21A R9
PB21B P9
PCLKT4_0 / PB22A T10
PCLKC4_0 / PB22B T11
PB23A R10
PB23B P10
PB24A N9
PB25B M9
BDQS26 / PB26A R12
VREF0_4 / PB26B T12
PB27A P13
PB27B R13
PB28AM11
PB28BN11
PB29A N10
PB29B M10
PB30A T13
PB30B P14
VREF1_4 / PB31A R11
PB31B P12
PB32A T14
PB33B R14
BDQS34 / PB34A P11
PB34B N12
PB35A T15
PB35B R15
VCCIO4_L9 L9
VCCIO4_L10 L10
VCCIO5_L7
L7
VCCIO5_L8
L8
TOE
P4
R194
DNS
R194
DNS
R140
DNS
R140
DNS
R240
DNS
R240
DNS
R243
DNS
R243
DNS
C65
0.1uF
CC0402
C65
0.1uF
CC0402
R130
0R130
0
R2300R2300
R183
DNS
R183
DNS
R118
DNS
R118
DNS
TPP12GTPP12G
R268
DNS
R268
DNS
TP_R10TP_R10
TP_P12TP_P12
R253
DNS
R253
DNS
R260
DNS
R260
DNS
TP_R4TP_R4
C68
0.1uF
CC0402
C68
0.1uF
CC0402
TPR3GTPR3G
R179
0
R179
0
R191
0
R191
0
R261
DNS
R261
DNS
R132
0
R132
0
TP_R14TP_R14
R119
DNS
R119
DNS
TP_R13TP_R13
TPP13GTPP13G
TP_T7TP_T7
R1650R1650
R186
DNS
R186
DNSR188
DNS
R188
DNS
R116
DNS
R116
DNS
TP_N5TP_N5
R164
0
R164
0
TP_T10TP_T10
TP_T6TP_T6
R129
DNS
R129
DNS
R163
DNS
R163
DNS
TP_R15TP_R15
R204
0
R204
0
TPR1GTPR1G
R1850R1850
R127
DNS
R127
DNS
TPR10GTPR10G
R153
DNS
R153
DNS
R2500R2500
R224
0
R224
0
TP_P11TP_P11
R143
DNS
R143
DNS
TPT7GTPT7G
TP_M8TP_M8
18
LatticeXP Standard Evaluation Board
Lattice Semiconductor User’s Guide
Figure 13. Banks 6 and 7
5
5
4
4
3
3
2
2
1
1
D D
C C
BB
A A
VCCIO_7
VCCIO_6
Title
veRrebm
u
N tnemucoDeziS
teehS:et
a
Dof
<Doc> A
Banks 6 and 7
Custom
68
Tuesday, June 17, 2008
Title
veRrebm
u
N tnemucoDeziS
teehS:etaD of
<Doc> A
Banks 6 and 7
Custom
68
Tuesday, June 17, 2008
Title
veRrebm
u
N tnemucoDeziS
teehS:etaD of
<Doc> A
Banks 6 and 7
Custom
68
Tuesday, June 17, 2008
[7]
Diff pair, equal length, 50 ohms
Diff pair, equal length, 50 ohms
Diff pair, equal length, 50 ohms
Diff pair, equal length, 50 ohms
Diff pair, equal length, 50 ohms
sr
i
a
p f
f
id lla
no s
but
s tr
o
h
S
sri
a
p
f
fid l
l
a n
o sbu
ts tro
h
S
Diff pair, equal length, 50 ohms
Diff pair, equal length, 50 ohms
Diff pair, equal length, 50 ohms
50 ohm SMA Connectors 50 ohm SMA Connectors
Check Datasheet for Proper Termination Selection
[7]
J7
SMA Connector
th_sma
J7
SMA Connector
th_sma
GND
2
GND
3
GND
4
GND
5
S1
TP_ L3TP_ L3
R28
DNS
R28
DNS
R33
0
R33
0R32
0
R32
0
TP_ P1TP_P1
TP_ J4TP _J 4
J8
SMA Connector
th_sma
J8
SMA Connector
th_sma
GND2
GND3
GND4
GND5
S
1
TP_ G5TP _G5
TP_ L1TP_ L1
R26
0
R26
0
TP_ F2TP_F 2
TP_ G1TP _G1
J20
SMA Connector
th_sma
J20
SMA Connector
th_sma
GND2
GND3
GND4
GND5
S
1
J14
SMA Connector
th_sma
J14
SMA Connector
th_sma
GND2
GND3
GND4
GND5
S
1
R27
0
R27
0
J16
SMA Connector
th_sma
J16
SMA Connector
th_sma
GND2
GND3
GND4
GND5
S
1
J11
SMA Connector
th_sma
J11
SMA Connector
th_sma
GND
2
GND
3
GND
4
GND
5
S1
6 KNAB7
K
NA
B
LFXP10E (fpBGA256)
(1 OF 5)
U4A
LFXP10E-5F256C
6 KNAB7
K
NA
B
LFXP10E (fpBGA256)
(1 OF 5)
U4A
LFXP10E-5F256C
PL6B / VREF0_7
E2 PL5A / LUM0_PLL_RST
D1
PL3B / LUM0_PLLC_FB_A
D3 PL3A / LUM0_PLLT_FB_A
D2
PL7A / LDQS7
E1
PL7B
F1
PL8A / LUM0_PLLT_OUT_A
E3
PL8B / LUM0_PLLC_OUT_A
F4
PL9A
F3
PL9B
F2
PL11B
G1
PL12A / LUM0_PLLT_IN_A
G3
PL12B / LUM0_PLLC_IN_A
G2
PL13A
H1
PL13B
H2
PL14A / VREF1_7
G4
PL15B
G5
PL16A / LDQS16
J1
PL16B
J2
PL18A
H3
PL18B
J3
PL28AL4
PL26B L3
PL26A K3
LLM0_PLLC_IN_A / PL25B M2
LLM0_PLLT_IN_A / PL25A M1
PL24B L2
LDQS24 / PL24A L1
VREF0_6 / PL23B J5
PL22A J4
PCLKC6_0 / PL20B K2
PCLKT6_0 / PL20A K1
LLM0_PLLT_OUT_A / PL29A K4
LLM0_PLLC_OUT_A / PL29B K5
VREF1_6 / PL31A N1
LLM0_PLL_RST / PL32B N2
LDQS33 / PL33A P1
PL33B P2
LLM0_PLLT_FB_A / PL34A L5
LLM0_PLLC_FB_A / PL34B M6
PL35A M3
PL35B N3
VCCIO6_J6 J6
VCCIO6_K 6 K6
VCCIO7_G6
G6
VCCIO7_H6
H6
C17
10uF
SizeC
C17
10uF
SizeC
R34
DNS
R34
DNS
R16
0
R16
0
TP_ L4TP_ L4
R20
0
R20
0
TP_ P2TP_P2
C22
0.01uF
CC0402
C22
0.01uF
CC0402
R31
DNS
R31
DNS
TP_ H3TP_ H3
TP_ G4TP _G4
TP_ F3TP_F 3
TP_ 3TP _3
R18
0
R18
0
R15
DNS
R15
DNS
R13
0
R13
0
C19
0.01uF
CC0402
C19
0.01uF
CC0402
R35
0
R35
0
TP_ J5TP _J 5
R22
DNS
R22
DNS
J21
SMA Connector
th_sma
J21
SMA Connector
th_sma
GND
2
GND
3
GND
4
GND
5
S1
TP_ L2TP_ L2
C21
0.1uF
CC0402
C21
0.1uF
CC0402
J10
SMA Connector
th_sma
J10
SMA Connector
th_sma
GND2
GND3
GND4
GND5
S
1
TP_ N1TP_N1
TP_ M3TP_ M3
J17
SMA Connector
th_sma
J17
SMA Connector
th_sma
GND
2
GND
3
GND
4
GND
5
S1
J12
SMA Connector
th_sma
J12
SMA Connector
th_sma
GND2
GND3
GND4
GND5
S
1
R30
0
R30
0
TP_ J2TP _J 2
R29
0
R29
0
R12
0
R12
0
J9
SMA Connector
th_sma
J9
SMA Connector
th_sma
GND
2
GND
3
GND
4
GND
5
S1
C20
10uF
SizeC
C20
10uF
SizeC
TP_ H2TP_ H2
C18
0.1uF
CC0402
C18
0.1uF
CC0402
TP_ E2TP _E 2
TP_ 5TP _5
R24
0
R24
0
TP_ J3TP _J 3
TP_ K3TP _K 3
TP_ 4TP _4
R19
DNS
R19
DNS
R23
0
R23
0
TP_ N2TP_N2
J22
SMA Connector
th_sma
J22
SMA Connector
th_sma
GND2
GND3
GND4
GND5
S
1
TP_ N3TP_N3
R21
0
R21
0
J18
SMA Connector
th_sma
J18
SMA Connector
th_sma
GND2
GND3
GND4
GND5
S
1
R25
DNS
R25
DNS
J13
SMA Connector
th_sma
J13
SMA Connector
th_sma
GND
2
GND
3
GND
4
GND
5
S1
TP_ J1TP _J 1
R17
0
R17
0
J19
SMA Connector
th_sma
J19
SMA Connector
th_sma
GND
2
GND
3
GND
4
GND
5
S1
TP_ H1TP_ H1
TP_ D1TP_ D1
J15
SMA Connector
th_sma
J15
SMA Connector
th_sma
GND
2
GND
3
GND
4
GND
5
S1
R14
DNS
R14
DNS
19
LatticeXP Standard Evaluation Board
Lattice Semiconductor User’s Guide
Figure 14. Power
5
5
4
4
3
3
2
2
1
1
DD
CC
B B
A A
VCC_3.3V
VCC_3.3V
VCC_1.2V
VCC_ADJ
VCC_3.3V
VCC_3.3V
VCC_ADJ
VCC_ADJ
VCC_3.3V
VCC_1.2V
VCC_ADJ
VCC_3.3V
VCC_ADJ
VCC_3.3V
VCC_1.2V
VCC_1.2V
VCC_ADJ
VCC_3.3V
VCC_1.2V
VCC_1.2V
VCC_ADJ
VCC_3.3V
VCC_1.2V
VCC_1.2V
VCC_ADJ
VCC_3.3V
VCCIO_0
VCC_3.3V
VCC_ADJ
VCC_1.2V
PWR_AD J
DRAIN_ADV
PWR_1.2V
VCC_IN
DRAIN_1.2
VCC_ADJ
VCC_1.2V
PWR_3.3 V
FCB
INTVCC
PWR_3.3V
PWR_3.3 V
INTVCC FCB
VCC_CORE
VCCIO_0
VCCIO_1
VCCIO_3
VCCIO_4
VCCIO_7
VCCIO_6
VCCM_3.3V
VCCIO_2
VCCIO_5
VCC_3.3V
Title
t
e
e
h
S
:etaD of78Wednesday, September 07, 2005
Title
teeh
S
:etaD of78Wednesday, September 07, 2005
Title
teeh
S
:etaD of78Wednesday, September 07, 2005
Title
ve
R
rebmuN
tnemu
c
oD
eziS
A
>
coD
<
Power
C
Title
A
>
coD
<
Power
C
Title
Power
C
Lattice Semiconductor Corporation
Another P-Channel MOSFET option in SOT23 package
Select only one voltage for each VCCIO
Use 1.2V for LFXPxxE devices
Use 1.8V, 2.5V, or 3.3V for LFXPxxC devices
For 1.8V and 2.5V use VCC_ADJ
Load only one current
sense resistor for VCC_CORE
[2]
[2]
Another P-Channel MOSFET option in SOT23 package
C0603C474K8PACTU
On Off
3.3V On/Off Switch
C2012X5ROJ475M
Banana Jack
Banana Jack
EG1257
[2,3]
Output Voltage Adjust
DO5022P-103
4.5VDC to 28VDC
RAPC712
Place Switch next to
DC input jack
EEVFK1V101P
T520D477M004ASE040
2.5mm Pin, (+)
5.5mm Barrel, (-)
JB1
JBLOCK
JB1
JBLOCK
R11
100K
CR0805
R11
100K
CR0805
JB12
JBLOCK
JB12
JBLOCK
R270
1
CR0805
R270
1
CR0805
JP1
HEADER_3X 2
JP1
HEADER_3X 2
2
4
6
1
3
5
Q4
Si2323DS
SOT23
Q4
Si2323DS
SOT23
G
D S
J3
PWR JAC K
J3
PWR JAC K
3
2
1
R6 10
CR0805
R6 10
CR0805
D3
MBRS340
SMC
D3
MBRS340
SMC
L1
10uH
15.24mmX18.54mm
L1
10uH
15.24mmX18.54mm
12
C16
4.7pF
CC0805
C16
4.7pF
CC0805
R272 0
CR0805
R272 0
CR0805
SW1
SW SPDT
SW1
SW SPDT
2
13
JP4
HEADER1X2
JP4
HEADER1X2
1 2
L3
6.2uH
7mmX7mm
L3
6.2uH
7mmX7mm
1 2
F3
3A
F3
3A
1 2
C14
1uF
SizeA
C14
1uF
SizeA
12
JB13
JBLOCK
JB13
JBLOCK
JB4
JBLOCK
JB4
JBLOCK
J1
CONN_RED
J1
CONN_RED
S
1
U1
LTC1775
U1
LTC1775
SGND
6
Run/SS
3TG 13
SW14
TK 15
EXTVcc
1
Vosence
7
Ith
5
Vprog
8
FCB
4
PGND
9
Boost 12
INTVcc 11
BG 10
Vin 16
JP11
HEADER_3X 2
JP11
HEADER_3X 2
2
4
6
1
3
5
JB8
JBLOCK
JB8
JBLOCK
C2
0.001uF
CC0805
C2
0.001uF
CC0805
JB3
JBLOCK
JB3
JBLOCK
+
C6
4.7uF
+
C6
4.7uF
JP2
HEADER_3X 2
JP2
HEADER_3X 2
2
4
6
1
3
5
R8
10K
CR0805
R8
10K
CR0805
R10
10K
CR0805
R10
10K
CR0805
JP5
HEADER1X2
JP5
HEADER1X2
12
JB14
JBLOCK
JB14
JBLOCK
JB5
JBLOCK
JB5
JBLOCK
C3
.47uF
CC0805
C3
.47uF
CC0805
JB2
JBLOCK
JB2
JBLOCK
C13
100uF
SizeD
C13
100uF
SizeD
12
R5
10K
CR0805
R5
10K
CR0805
J6
CONN_RED
J6
CONN_RED
S
1
R2
10K
CR0805
R2
10K
CR0805
U2
TPS64203DVB
SOT23-6
U2
TPS64203DVB
SOT23-6
/EN
1
GND
2
FB
3ISENSE 4
VIN5
SW6
Q3
Si2323DS
SOT23
Q3
Si2323DS
SOT23
G
D S
D4
B320A
SMA
D4
B320A
SMA
F1
3A
F1
3A
1 2
JB6
JBLOCK
JB6
JBLOCK
Q6
Si5447DC
Q6
Si5447DC
D
1D
2D
3G
4S5
D6
D7
D8
C7
2200pF
CC0805
C7
2200pF
CC0805
+
C4
470uF
+
C4
470uF
D1
MBRS340
SMC
D1
MBRS340
SMC
R271 DNI
CR0805
R271 DNI
CR0805
JP6
HEADER1X2
JP6
HEADER1X2
1 2
JB10
JBLOCK
JB10
JBLOCK
C12
4.7pF
CC0805
C12
4.7pF
CC0805
F2
3A
F2
3A
1 2
JP12
HEADER_3X2
JP12
HEADER_3X2
2
4
6
1
3
5
Q5
Si5447DC
Q5
Si5447DC
D
1D
2D
3G
4S5
D6
D7
D8
Q1
Si4840DY
Q1
Si4840DY
5
4
1
6
23
7
8
TP_ 2TP _2
JP14
HEADER_3X 2
JP14
HEADER_3X 2
2
4
6
1
3
5
JB7
JBLOCK
JB7
JBLOCK
C15
4.7pF
CC0805
C15
4.7pF
CC0805
D2
1N5819
SOD-123
D2
1N5819
SOD-123
R7 10
CR0805
R7 10
CR0805
J4
CONN_BLACK
J4
CONN_BLACK
S1
L2
6.2uH
7mmX7mm
L2
6.2uH
7mmX7mm
1 2
R9
200K POT
5.6mmX3.6mm
R9
200K POT
5.6mmX3.6mm
1 3
2
C70
0.1uF
CC0805
C70
0.1uF
CC0805
12
JP3
HEADER_3X 2
JP3
HEADER_3X 2
2
4
6
1
3
5
R4 10
CR0805
R4 10
CR0805
R3
10K
CR0805
R3
10K
CR0805
JB9
JBLOCK
JB9
JBLOCK
R1 10
CR0805
R1 10
CR0805
C9
10uF
SizeC
C9
10uF
SizeC
12
TP_ 1TP _1
D5
B320A
SMA
D5
B320A
SMA
+
C5
470uF
+
C5
470uF
J2
CONN_RED
J2
CONN_RED
S1
U3
TPS64203DVB
SOT23-6
U3
TPS64203DVB
SOT23-6
/EN
1
GND
2
FB
3ISENSE 4
VIN5
SW6
JP13
HEADER_3X 2
JP13
HEADER_3X 2
2
4
6
1
3
5
JB11
JBLOCK
JB11
JBLOCK
C11
1uF
SizeA
C11
1uF
SizeA
12
C8
10uF
SizeC
C8
10uF
SizeC
12
Q2
Si4840DY
Q2
Si4840DY
5
4
1
6
2
3
78
J5
CONN_RED
J5
CONN_RED
S
1
JP10
HEADER_3X 2
JP10
HEADER_3X 2
2
4
6
1
3
5
C10
100uF
SizeD
C10
100uF
SizeD
12
+
C1
100uF
+
C1
100uF
20
LatticeXP Standard Evaluation Board
Lattice Semiconductor User’s Guide
Figure 15. Mechanical Drawing
5
5
4
4
3
3
2
2
1
1
DD
CC
B B
A A
Title
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N
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Mechanical Drawing
C
88Wednesday, September 07, 2005
Title
veR
r
eb
mu
N
t
n
em
uc
oDez
i
S
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S
:etaD of
A
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C
88Wednesday, September 07, 2005
Title
veR
r
eb
mu
N
t
n
em
uc
oDez
i
S
teeh
S
:etaD of
A
>
c
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C
88Wednesday, September 07, 2005
Lattice Semiconductor Corporation
