Standard Product August 1992 LXP2175 T1/E1 Elastic Store The LXP2175 is one of a family of Level One Primary Rate + - Drop-in replacement for the DS2175 Interface solutions. It is compatible with LXT30x series . transceivers, and LXP2180A/2181A framer/formatters. | * Rate buffer for T1/E1 transmissions The LXP2175 is a low-power CMOS elastic-store memory . . . 4 optimized for use in primary rate telecommunicationstrans- * Synchronizes loop-timed and system-timed T1/E1 data foot : Streams mission equipment. tr * Ideal for 1.544 to 2.048 MHz rate conversion Compatible with North American T1 (1.544 MHz) and European E 1 (2.048 MHz) primary rate networks, the device serves as a synchronous element between asynchronous data streams. The LXP2175 has several flexible operating modes + Easily monitored two-frame buffer depth which eliminate support logic and hardware otherwise re- quired to interconnect parallel or serial TDM backplanes. | * Comprehensive on-chip slip control logic The LXP2175 is a drop-in replacement for the DS2175. * Supports parallel and serial backplanes * Slips occur only on frame boundaries . Digital Trunks Outputs report slip occurrences and direction . Drop and Insert Equipment * Align feature allows buffer to be recentered at any time * Digital Cross-connects (DACS) * Available in 16-pin DIP and SOP . Private Network Equipment * Compatible with Level One LXP2180A and . PABX-to-computer interfaces such as DMI and CPI. LXP2181A framer/formatters RSER SSER PCM SYSCLK BUFFER SYSTEM RCLK SFSYNC RECEIVE sp RMSYNC CONTROLLER SMSYNC RCLKSEL SCHCLK SCLKSEL FSD ALN SLIP @LEVEL (c ONE 2-157LXP2175 T1/E1 Elastic Store OY RCLKSEL 4 1 16 VDD RCLK CJ 2 15 SYSCLK RSER 3 14 SSER RMSYNC [4 13 1 SMSYNC FSD 5 121 SFSYNC SUP []76 1111 SCHCLK AN M7 100 SP vsS 18 9 171 SCLKSEL Pin Descriptions Pin Sym vo Name Description 1 | RCLKSEL} I Receive Clock Tie to VSS for 1.544 MHz applications, to VDD for 2.048 MHz. Select 2 RCLK | I | Receive Clock | Primary 1.544 MHz or 2.048 MHz data clock. 3 RSER I | Receive Serial Sampled on falling edge of RCLK. Data 4 | RMSYNC]| I | Receive Multi- Rising edge establishes receive side frame and multiframe boundaries. frame Sync 5 FSD Oo Frame Slip State indicates direction of last slip; latched on slip occurrence. Direction 6 SLIP 0 Frame Slip Active low, open collector output. Held low for 65 SYSCLK cycles when a slip occurs. 7 ALN I Align Recenters buffer on next system side frame boundary when forced low. 8 VSS - | Signal Ground 0.0 volt ground return. 9 | SCLKSEL| I System Clock Tie to VSS for 1.544 MHz applications, to VDD for 2.048 MHz. Select 10 Ss/P I Serial Parallel Tie to VSS for parallel backplane applications, to VDD for serial. Select 11 | SCHCLK } O | System Channel | Transitions high on channel boundaries; useful for serial to parallel Clock conversion of channel data. 12 | SFSYNC | 1 System Frame Rising edge establishes system side frame boundaries. Sync 13] SMSYNC} O | System Multi- | Slip-compensated multiframe output. Used with RMSYNC to monitor frame Sync depth of store in real time. 14 SSER 0 System Serial Updated on rising edge of SYSCLK. Data 15 | SYSCLK | I System Clock 1.544 or 2.048 MHz data clock. 16 VDD I | Positive Supply | +5 Volt power supply input. (OGL EVEL 2-158 ONE LXP2175 T1/E1 Elastic Store PCM Buffer The LXP2175 utilizes a two-frame buffer to synchronize incoming PCM data to the system backplane clock. Buffer depth is mode dependent: 2.048 MHz to 2.048 MHz appli- cations use 64 bytes of buffer memory; all other modes are supported by 48 bytes. The buffer samples data at RSER on the falling edge of RCLK. Output data appears at SSER and is updated on the rising edge of SYSCLK. The buffer depth is constantly monitored by on-board contention logic. A "slip" occurs when the buffer is completely emptied or filled. Slips automatically recenter the buffer to a one-frame depth and always occur on frame boundaries. Data Format Data is presented to, and output from, the elastic store in a framed format. A rising edge at RMSYNC establishes receive side frame boundaries (see Figures 2 and 3). A rising edge at SFSYNC establishes system side multiframe boundaries (see Figures 4 and 5). North American (T1) frames contain 24 data channels of 8 bits each and an F-bit (193 bits total). European (E1) frames contain 32 data channels (256 bits). The frame rate of both systems is 8 KHz. RMSYNC and SFSYNC do not require a pulse at every frame boundary. If desired, they may be pulsed once to establish frame alignment. Internal counters will then main- tain the frame alignment and may be reinforced by the next rising edge at RMSYNC and/or SFSYNC. Slip Correction Capability The two-frame buffer depth is adequate for T1 and El applications where short-term jitter synchronization, rather than correction of significant frequency differences, is re- quired. The LXP2175 provides a balance between total delay (less than 250 ms at its full depth) and slip correction capability. Buffer Recentering Many applications require that the buffer be recentered during system power-up and/or initialization. Forcing ALN low recenters the buffer on the nextrising edge of SFSYNC, A slip will occur during this recentering if the buffer depth LEVEL (CONE is adjusted. Ifthe depth is presently optimum, no adjustment (slip) occurs. Slip Reporting SLIP is held low for 65 SYSCLK cycles when a slip occurs. SLIP is an active-low, open-collector output. FSD indicates slip direction. When low (buffer empty), a frame of data was repeated at SSER during the previous slip. When high (buffer full), a frame of data was deleted. FSD is updated at every slip occurrence. Buffer Depth Monitoring SMSYNC is a system side output pulse which indicates system side multiframe boundaries. The distance between rising edges at RMSYNC and SMSYNC indicates the cur- rent buffer depth. Slip direction and/or an impending slip condition may be determined by monitoring RMSYNC and SMSYNC real time. SMSYNC is held high for 65 SYSCLK cycles. Clock Select Receive and system side clock frequencies are independ- ently selectable by inputs RCLKSEL and SCLKSEL. 1.544 MHz is selected when RCLKSEL (SCLKSEL)=0; and 2.048 MHz is selected when RCLKSEL (SCLKSEL)= 1. In 1.544 MHz (receive) to 1.544 MHz (system) applications, the F-bit is passed through the receive buffer and presented at SSER immediately after arising edge on SFSYNC. The F- bit is forced to 1 in 2.048 MHz to 1.544 MHz applications. No F-bit position exists in 2.048 MHz system side applica- tions. Parallel Compatibility The LXP2175 is compatible with parallel and serial backplanes. In serial applications (S/P = 1), channel 1 data appears at SSER after a rising edge at SFSYNC. In parallel applications (S/P = 0), the device utilizes a look-ahead cir- cuit. Datais output 8 clocks earlier as shown in Figures 4 and 5, allowing a user to parallel convert data externally, using an HCS95 shift register. 2-159LXP2175 T1/E1 Elastic Store Figure 2: Receive Side Timing (RCLK = 1.544 MHz) rex JU UU UU UU UU UU UU RMSYNC [\ Channel 24 -| [. Channel 4 -| Figure 3: Receive Side Timing (RCLK = 2.048 MHz) reek J LU LU LU UU UU UU UU UU RMSYNC \ |}--canne! 32. channel 1+ * All channel data is passed through the elastic store in 2.048 MHz system side applications (SCLKSEL = 1); Data in channels > 24 is ignored in 1.544 MHz system side applications (SCLKSEL = 0). Figure 4: System Multiframe Boundary Timing (SYSCLK = 1.544 MHz) SFSYNC [\ SMSYNC SCHCLK | SSER (S/P = 1) Note 4 SSER , \ (SP = 0) a Channel 2 >| Note 4 |}channe! 1 | Channel 2 | In 1.544 MHz receive side applications (RCLKSEL = 0), the F-bit position contains F-bit data extracted from the data stream at RSER. The F-bit position is forced to "1" in 2.048 MHz receive side applications (RCLKSEL = 1). (Og LEVEL ONE @ 2-160LXP2175 T1/E1 Elastic Store Figure 5: System Multiframe Boundary Timing (SYSCLK = 2.048 MHz) svsoux | IL UU UU UU UU UU SFSYNC )\ SMSYNC | SCHCLK SSER (S/P = 1) Note 1 SSER Oro. }~<Channel 1 ~| Channel 2 >| All channel data is passed through the elastic store in 2.048 MHz system side applications (SCLKSEL = 1); Data in channels > 24 is ignored in 1.544 MHz system side applications (SCLKSEL = 0). A bsolute Maximum Ratings* Voltage on any pin relative to ground -1.0V to+7V * Exceeding wiese values may case * Operating temperature (2175SC and NC) 0 C (min) to 70 C (max) permanent damage. Functional operation . under these conditions is not implied. (2175SE and NE) -40 C (min) to 85 c (max) Exposure to absolute maximum rating Storage temperature -55 C (min) to 125 C (max) conditions for extended periods may * Soldering temperature 260 C for 10 seconds affect device reliability. Recommended Operating Conditions (votages are with respect to ground (VSS) unless otherwise stated) Parameter Sym Min Typ' Max Units Logic 1 Vin 2.0 - Vopt 3 Vv Logic 0 Viv -0.3 - +0.8 Vv Supply voltage Vo 4.5 5 5.5 v DC Electrical Characteristics - Clocked operation over recommended temperature and power supply ranges Parameter Sym Min | Typ' Max | Units Test Conditions Input capacitance Cw - - 5 pF Output capacitance Cour = - 7 pF Supply current Lp - 6 - mA See Notes 2 and 3 Input leakage I, ~1.0 - +1.0 pA Output high current Loe -1.0 = = mA | Vo,=2-4 V, See Note 4 Output low current fo +4.0 - - mA Vo, = 0.4 V, See Note 5 ' Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. ? SYSCLK = RCLK = 1.544 MHz + Outputs Open + All outputs except SLIP, which is open collector. 5 All outputs. LEVEL ONES 2-161LXP2175 T1/E1 Elastic Store A.C. Electrical Characteristics Parameter Sym Min Max Units RCLK Period tectx 200 - ns RCLK, SYSCLK Rise and Fall ta tp - 20 ns RCLK Pulse Width tewn, Rw 100 - ns SYSCLK Pulse Width towes swe 100 - ns SYSCLK Period teak 200 - ns RMSYNC Setup to RCLK Rising toc hwy 2 thew? ns SFSYNC Setup to SYSCLK Rising tye tewny 9 tHowy 2 ns RMSYNC, SFSYNC, ALN Pulse Width tow 100 ns RSER Setup to RCLK Falling tp 50 ns RSER Hold from RCLK Falling typ 50 ns Propagation Delay SYSCLK to SSER, typ - 75 ns or RCLK to RSER Propagation Delay SYSCLK to SMSYNC High toss - 7 ns Propagation Delay SYSCLK or RCLK to tos - 100 ns SLIP Low, FSD low/high ALN Setup to SFSYNC Rising ten 500 - ns (c LEVEL 2-162 ONE LXP2175 T1/E1 Elastic Store Figure 6: Receive A.C. Timing Diagram tsc tr tr tACLK sal _ La tRWL Na AN RCLK tRWH RMSYNC tPvD tso | tHD >} . RSER x : k I Figure 7: System A.C. Timing Diagram tsc tr tr tSCLkK [-anfomef \|_tswe SYSCLK i tSWH \ _.. (Pw sFsync / tevo +] sen XxX =X _| tPs Sip tes we] FSD tess ~] SMSYNC tsA ALN tew @LEVEL ic ONE @ 2-163