March 2001
Copyright © Alliance Semiconductor. All rights reserved.
®
AS7C1024
AS7C31024
3/23/01; v.1.0 Alliance Semiconductor P. 1 of 9
5V/3.3V 128K×8 CMOS SRAM (Evolutionary Pinout)
Features
• AS7C1024 (5V version)
• AS7C31024 (3.3V version)
• Industrial and commercial temperatures
• Organization: 131,072 words × 8 bits
• High speed
- 12/15/20 ns address access time
- 6,7,8 ns output enable access time
• Low power consumption: ACTIVE
- 825 mW (c) / max @ 12 ns
- 360 mW (AS7C31024) / max @ 12 ns
• Low power consumption: STANDBY
- 55 mW (AS7C1024) / max CMOS
- 36 mW (AS7C31024) / max CMOS
• 2.0V data retention
• Easy memory expansion with CE1, CE2, OE inputs
• TTL/LVTTL-compatible, three-state I/O
• 32-pin JEDEC standard packages
-300 mil SOJ
-400 mil SOJ
- 8 × 20mm TSOP I
- 8 × 13.4 mm sTSOP I
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Logic block diagram
512
×
256
×
8
Array
(1,048,576)
Sense amp
Input buffer
A10
A11
A12
A13
A14
A15
A16
I/O0
I/O7
OE
CE1
WE
Column decoder
Row decoder
Control
circuit
A9
A0
A1
A2
A3
A4
A5
A6
A7
V
CC
GND
A8
CE2
Pin arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
AS7C1024
AS7C31024
32-pin SOJ (300 mil)
VCC
A15
CE2
WE
A13
A8
A9
A11 OE
A10
CE1
I/O7
I/O6
I/O4
NC
A16
A14
A12
A7
A6
A5
A4 A3
A2
A1
A0
I/O0
I/O1
32-pin TSOP I
I/O2
GND
I/O5
I/O3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
32
31
30
29
28
27
26
25
24
23
22
21
AS7C1024
AS7C31024
20
19
15
16
18
17
(8 x 20mm) 32-pin SOJ (400 mil)
Selection guide
Shaded areas contain advance information.
AS7C1024-12
AS7C31024-12
AS7C1024-15
AS7C31024-15
AS7C1024-20
AS7C31024-20 Unit
Maximum address access time 12 15 20 ns
Maximum output enable access time 6 8 10 ns
Maximum operating current AS7C1024 140 125 110 mA
AS7C31024 90 80 75 mA
Maximum CMOS standby current AS7C1024 10 10 15 mA
AS7C31024 10 10 15 mA
®
AS7C1024
AS7C31024
3/23/01; v.1.0 Alliance Semiconductor P. 2 of 9
Functional description
The AS7C1024 and AS7C31024 are high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices
organized as 131,072 words × 8 bits. It is designed for memory applications where fast data access, low power, and simple
interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 12/15/20 ns with output enable access times (tOE) of 6,7,8 ns are ideal
for high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with
multiple-bank systems.
When CE1 is high or CE2 is low the devices enter standby mode. If inputs are still toggling, the device will consume ISB power.
If the bus is static, then full standby power is reached (ISB1 or ISB2). For example, the AS7C31024 is guaranteed not to exceed
0.33mW under nominal full standby conditions. All devices in this family will retain data when VCC is reduced as low as 2.0V.
A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0-
I/O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid
bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write
enable (WE).
A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) high.
The chips drive I/O pins with the data word referenced by the input address. When either chip enable is inactive, output
enable is inactive, or write enable is active, output drivers stay in high-impedance mode.
Absolute maximum ratings
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
Key: X = Don’t Care, L = Low, H = High
Parameter Symbol Min Max Unit
Voltage on VCC relative to GND AS7C1024 Vt1 –0.50 +7.0 V
AS7C31024 Vt1 -0.50 +5.0 V
Voltage on any pin relative to GND Vt2 –0.50 VCC +0.50 V
Power dissipation PD–1.0W
Storage temperature (plastic) Tstg –65 +150 °C
Ambient temperature with VCC applied Tbias –55 +125 °C
DC current into outputs (low) IOUT –20mA
CE1
CE2
WE OE
Data Mode
HXXX High Z Standby (I
SB, ISB1)
XLXX High Z Standby (I
SB, ISB1)
L H H H High Z Output disable (ICC)
LHHL D
OUT Read (ICC)
LHLX D
IN Write (ICC)
®
AS7C1024
AS7C31024
3/23/01; v.1.0 Alliance Semiconductor P. 3 of 9
Recommended operating conditions
† VILmin = –3.0V for pulse width less than tRC/2.
DC operating characteristics (over the operating range)1
Shaded areas contain advance information.
Capacitance (f = 1 MHz, Ta = 25 °C, VCC = NOMINAL)2
Parameter Device Symbol Min Nominal Max Unit
Supply voltage AS7C1024 VCC 4.5 5.0 5.5 V
AS7C31024 VCC 3.0 3.3 3.6 V
Input voltage
AS7C1024 VIH 2.2 – VCC + 0.5 V
AS7C31024 VIH 2.0 – VCC + 0.5 V
VIL†–0.5 – 0.8 V
Ambient operating temperature commercial TA0–70°C
industrial TA–40 – 85 °C
Parameter Sym Test conditions Device
-12 -15 -20 Unit
Min Max Min Max Min Max
Input leakage
current |ILI|V
CC = Max, VIN = GND to VCC –1–1–1µA
Output leakage
current |ILO|VCC = Max, CE1 = VIH or
CE2 = VIL, VOUT = GND to VCC –1–1–1µA
Operating
power supply
current
ICC
VCC = Max, CE1 = VIL,
CE2 = VIH, f = fMax, IOUT = 0
mA
AS7C1024 – 140 – 125 – 110
mA
AS7C31024 – 90 – 80 – 75
Standby power
supply current
ISB
VCC = Max, CE1 ≥ VIH and/or
CE2 ≤ VIL, VIN = VIH or VIL,
f = fMax, IOUT = 0mA
AS7C1024 – 75 – 65 – 60
mA
AS7C31024 – 50 – 40 – 35
ISB1
VCC = Max, CE1 ≥ VCC–0.2V
VIN ≤ GND + 0.2V or
VIN ≥ VCC –0.2V, f = 0
AS7C1024 – 10 – 10 – 15
mA
AS7C31024 – 10 – 10 – 15
Output voltage VOL IOL = 8 mA, VCC = Min –0.4–0.4–0.4V
VOH IOH = –4 mA, VCC = Min 2.4 – 2.4 – 2.4 – V
Parameter Symbol Signals Test conditions Max Unit
Input capacitance CIN A, CE1, CE2, WE, OE VIN = 0V 5 pF
I/O capacitance CI/O I/O VIN = VOUT = 0V 7 pF
®
AS7C1024
AS7C31024
3/23/01; v.1.0 Alliance Semiconductor P. 4 of 9
Read cycle (over the operating range)3,9,12
Key to switching waveforms
Read waveform 1 (address controlled)3,6,7,9,12
Read waveform 2 (CE1, CE2, and OE controlled)3,6,8,9,12
Parameter Symbol
-12 -15 -20
Unit NotesMinMaxMinMaxMinMax
Read cycle time tRC 12 – 15 – 20 – ns
Address access time tAA –12–15–20ns 3
Chip enable (CE1) access time tACE1 –12–15–20ns 3, 12
Chip enable (CE2) access time tACE2 –12–15–20ns 3, 12
Output enable (OE) access time tOE –6–7–8ns
Output hold from address change tOH 3–3–3–ns 5
CE1 Low to output in low Z tCLZ1 3 – 3 – 3 – ns 4, 5, 12
CE2 High to output in low Z tCLZ2 3 – 3 – 3 – ns 4, 5, 12
CE1 Low to output in high Z tCHZ1 – 3 – 4 – 5 ns 4, 5, 12
CE2 Low to output in high Z tCHZ2 – 3 – 4 – 5 ns 4, 5, 12
OE Low to output in low Z tOLZ 0–0–0–ns 4, 5
OE High to output in high Z tOHZ –3–4–5ns 4, 5
Power up time tPU 0 – 0 – 0 – ns 4, 5, 12
Power down time tPD –12–15–20ns4, 5, 12
Undefined / don’t careFalling inputRising input
Address
D
OUT
Data valid
t
OH
t
AA
t
RC
supply
Current
CE2
OE
D
OUT
t
OE
t
OLZ
t
ACE1
,
tACE2
t
CHZ1
, t
CHZ2
t
CLZ1
, t
CLZ2
t
PU
t
PD
I
CC
I
SB
50% 50%
Data valid
t
RC1
CE1
t
OHZ
®
AS7C1024
AS7C31024
3/23/01; v.1.0 Alliance Semiconductor P. 5 of 9
Write cycle (over the operating range)11, 12
Shaded areas contain advance information.
Write waveform 1 ( WE controlled)10,11,12
Write waveform 2 (CE1 and CE2 controlled)10,11,12
Parameter Symbol
-12 -15 -20
Unit NotesMin Max Min Max Min Max
Write cycle time tWC 12 – 15 – 20 – ns
Chip enable (CE1) to write end tCW1 10 – 12 – 12 – ns 12
Chip enable (CE2) to write end tCW2 10 – 12 – 12 – ns 12
Address setup to write end tAW 10 – 12 – 12 – ns
Address setup time tAS 0–0–0–ns 12
Write pulse width tWP 8–9–12–ns
Address hold from end of write tAH 0–0–0–ns
Data valid to write end tDW 6–9–10–ns
Data hold time tDH 0 – 0 – 0 – ns 4, 5
Write enable to output in high Z tWZ – 5 – 5 – 5 ns 4, 5
Output active from write end tOW 3 – 3 – 3 – ns 4, 5
t
AW
t
AH
t
WC
Address
WE
D
OUT
t
DH
t
OW
t
DW
t
WZ
t
WP
t
AS
Data valid
D
IN
t
AW
Address
CE1
WE
D
OUT
t
CW1
, t
CW2
t
WP
t
DW
t
DH
t
AH
t
WZ
t
WC
t
AS
CE2
Data valid
D
IN
®
AS7C1024
AS7C31024
3/23/01; v.1.0 Alliance Semiconductor P. 6 of 9
Data retention characteristics (over the operating range)13
Data retention waveform
AC test conditions
Notes
1During V
CC power-up, a pull-up resistor to VCC on CE1 is required to meet ISB specification.
2 This parameter is sampled and not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A, B, and C.
4t
CLZ and tCHZ are specified with CL = 5pF, as in Figure C. Transition is measured ±500mV from steady-state voltage.
5 This parameter is guaranteed, but not 100% tested.
6WE
is High for read cycle.
7CE1
and OE are Low and CE2 is High for read cycle.
8 Address valid prior to or coincident with CE1 transition Low.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CE1 or WE must be High or CE2 Low during address transitions. Either CE1 or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 CE1 and CE2 have identical timing.
13 2V data retention applies to commercial temperature operating range only.
14 C=30pF, except all high Z and low Z parameters, C=5pF.
Parameter Symbol Test conditions Device Min Max Unit
VCC for data retention VDR
VCC = 2.0V
CE1 ≥ VCC–0.2V or
CE2 ≤ 0.2V
VIN ≥ VCC–0.2V or
VIN ≤ 0.2V
2.0 – V
Data retention current ICCDR AS7C1024 – 5 mA
AS7C31024 – 1 mA
Chip deselect to data retention time tCDR 0 – ns
Operation recovery time tR tRC –ns
Input leakage current | ILI | – 1 µA
V
CC
CE1
t
R
t
CDR
Data retention mode
V
CC
V
CC
V
DR
≥
2.0V
V
IH
V
IH
V
DR
255W
– 5V output load: see Figure B or Figure C.
– Input pulse level: GND to 3.0V. See Figure A.
– Input rise and fall times: 2 ns. See Figure A.
– Input and output timing reference levels: 1.5V.
C(14)
320W
D
OUT
GND
+3.3V
168W
Thevenin equivalent:
D
OUT
+1.728V (5V and 3.3V)
Figure C: 3.3V Output load
255W C(14)
480W
D
OUT
GND
+5V
Figure B: 5V Output load
10%
90%
10%
90%
GND
+3.0V
Figure A: Input pulse
2 ns
®
AS7C1024
AS7C31024
3/23/01; v.1.0 Alliance Semiconductor P. 7 of 9
Typical DC and AC characteristics
Supply voltage (V)
MIN MAX
NOMINAL
0.0
0.2
0.6
0.8
0.4
1.0
1.2
1.4
Normalized I
CC
, I
SB
Normalized supply current I
CC
, I
SB
Ambient temperature (°C)
–55 80 125
35–10
0.0
0.2
0.6
0.8
0.4
1.0
1.2
1.4
Normalized I
CC
, I
SB
Normalized supply current I
CC
, I
SB
vs. ambient temperature T
a
vs. supply voltage V
CC
I
CC
I
SB
I
CC
I
SB
Ambient temperature (°C)
-55 80 125
35-10
0.2
1
0.04
5
25
625
Normalized ISB1 (log scale)
Normalized supply current I
SB1
vs. ambient temperature T
a
VCC = VCC(NOMINAL)
Supply voltage (V)
MIN MAX
NOMINAL
0.8
0.9
1.1
1.2
1.0
1.3
1.4
1.5
Normalized access time
Normalized access time t
AA
Ambient temperature (°C)
–55 80 125
35–10
0.8
0.9
1.1
1.2
1.0
1.3
1.4
1.5
Normalized access time
Normalized access time t
AA
Cycle frequency (MHz)
075
100
5025
0.0
0.2
0.6
0.8
0.4
1.0
1.2
1.4
Normalized ICC
Normalized supply current I
CC
vs. ambient temperature T
a
vs. cycle frequency 1/t
RC
, 1/t
WC
vs. supply voltage V
CC
Ta = 25° C VCC = VCC(NOMINAL)
VCC = VCC(NOMINAL)
Ta = 25° C
Output voltage (V)
V
CC
0
20
60
80
40
100
120
140
Output source current (mA)
Output source current I
OH
Output voltage (V)
V
CC
Output sink current (mA)
Output sink current I
OL
vs. output voltage V
OL
vs. output voltage V
OH
0
20
60
80
40
100
120
140
Capacitance (pF)
0750 1000
500250
0
5
15
20
10
25
30
35
Change in t
AA
(ns)
Typical access time change
∆
t
AA
vs. output capacitive loading
00
VCC = VCC(NOMINAL)
Ta = 25° C
VCC = VCC(NOMINAL)
Ta = 25° C VCC = VCC(NOMINAL)
®
AS7C1024
AS7C31024
3/23/01; v.1.0 Alliance Semiconductor P. 8 of 9
Package dimensions
c
eA
α
Seating
bA1
E1 E
D
e
L
S
Plane
B
A
Pin 1
Seating
Plane
e
b
E
Hd
D
α
c
LA1AA2
pin 1 pin 32
pin 16 pin 17
Pin 1
D
e
E1 E2 A1
B
b
A
A2
E
c
32-pin PDIP
Min Max
A - 0.180
A1 0.015 -
B 0.045 0.055
b 0.015 0.021
c 0.008 0.012
D - 1.571
E 0.300 0.325
E1 0.280 0.295
e0.100 BSC
eA 0.330 0.370
L 0.110 0.142
a 0° 15°
S - 0.043
32-pin SOJ 300 mil 32-pin SOJ 400 mil
Min Max Min Max
A - 0.145 - 0.145
A1 0.025 - 0.025 -
A2 0.086 0.105 0.086 0.115
B 0.026 0.032 0.026 0.032
b 0.014 0.020 0.015 0.020
c 0.006 0.013 0.007 0.013
D 0.820 0.830 0.820 0.830
E 0.250 0.275 0.360 0.380
E1 0.292 0.305 0.395 0.405
E2 0.330 0.340 0.435 0.445
e 0.050 BSC 0.050 BSC
32-pin TSOP 8×20
Min Max
A–1.20
A1 0.05 0.15
A2 0.95 1.05
b 0.17 0.27
c 0.10 0.21
D 18.20 18.60
e 0.50 nominal
E 7.80 8.20
Hd 19.80 20.20
L 0.50 0.70
α0° 5°
®
AS7C1024
AS7C31024
3/23/01; v.1.0 Alliance Semiconductor P. 9 of 9
© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be
the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may
appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the
product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential
customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use
of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose,
merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made
exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other
intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected
to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all
claims arising from such use
Ordering codes
NA: not available
Shaded areas contain advance information.
Part numbering system
Package \ Access time Volt/ Te m p 12 ns 15 ns 20 ns
Plastic SOJ, 300 mL
5V commercial AS7C1024-12TJC AS7C1024-15TJC AS7C1024-20TJC
5V industrial AS7C1024-12TJI AS7C1024-15TJI AS7C1024-20TJI
3.3V commercial AS7C31024-12TJC AS7C31024-15TJC AS7C31024-20TJC
3.3V industrial AS7C31024-12TJI AS7C31024-15TJI AS7C31024-20TJI
Plastic SOJ, 400 mL
5V commercial AS7C1024-12JC AS7C1024-15JC AS7C1024-20JC
5V industrial AS7C1024-12JI AS7C1024-15JI AS7C1024-20JI
3.3V commercial AS7C31024-12JC AS7C31024-15JC AS7C31024-20JC
3.3V industrial AS7C31024-12JI AS7C31024-15JI AS7C31024-20JI
TSOP 8×20
5V commercial AS7C1024-12TC AS7C1024-15TC AS7C1024-20TC
5V industrial AS7C1024-12TI AS7C1024-15TI AS7C1024-20TI
3.3V commercial AS7C31024-12TC AS7C31024-15TC AS7C31024-20TC
3.3V industrial AS7C31024-12TI AS7C31024-15TI AS7C31024-20TI
AS7C X 1024 –XX X X
SRAM
prefix
Blank=5V CMOS
3=3.3V CMOS
Device
number
Access
time
Package: TP=PDIP 300 mil
T=TSOP 8×20
J=SOJ 400 mil
TJ=SOJ 300 mil
Temperature range
C = Commercial, 0°C to 70°C
I = Industrial, -40°C to 85°C
