LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 LM49370 Boomer(R) Audio Power Amplifier Series Audio Sub-System with an Ultra Low EMI, Spread Spectrum, Class D Loudspeaker Amplifier, a Dual-Mode Stereo Headphone Amplifier, and a Dedicated PCM Interface for Bluetooth Transceivers Check for Samples: LM49370 FEATURES 1 * 2 * * * * * * * * * * * * * * * * * * * * * * * * * Spread Spectrum Class D Architecture Reduces EMI Mono Class D 8 Amplifier, 490 mW at 3.3V OCL or AC-Coupled Headphone Operation 33mW Stereo Headphone Amplifier at 3.3V 115 mW Earpiece Amplifier at 3.3V 18-bit Stereo DAC 16-bit Mono ADC 8 kHz to 192 kHz Stereo Audio Playback 8 kHz to 48 kHz Mono Recording Bidirectional I2S Compatible Audio Interface Bidirectional PCM Compatible Audio Interface for Bluetooth Transceivers I2S-PCM Bridge with Sample Rate Conversion Sigma-Delta PLL for Operation from Any Clock at Any Sample Rate Digital 3D Stereo Enhancement FIR Filter Programmability for Simple Tone Control Low Power Clock Network Operation if a 12 MHz or 13 MHz System Clock is Available Read/Write I2C or SPI Compatible Control Interface Automatic Headphone & Microphone Detection Support for Internal and External Microphones Automatic Gain Control for Microphone Input Differential Audio I/O for External Cellphone Module Mono Differential Auxiliary Output Stereo Auxiliary Inputs Differential Microphone Input for Internal Microphone Flexible Audio Routing from Input to Output 32 Step Volume Control for Mixers in 1.5 dB Steps * * * * * * * 16 Step Volume Control for Microphone in 2 dB Steps Programmable Sidetone Attenuation in 3 dB Steps Two Configurable GPIO Ports Multi-Function IRQ Output Micro-Power Shutdown Mode Available in the 4 x 4 mm 49 Bump DSBGA Package Key Specifications - PHP (AC-COUP) (A_VDD = 3.3V, 32, 1% THD) 33 mW - PHP (OCL) (A_VDD = 3.3V, 32, 1% THD) 31 mW - PLS ( LS_VDD = 5V, 8, 1% THD) 1.2 W - PLS (LS_VDD = 4.2V, 8, 1% THD) 900 mW - PLS (LS_VDD = 3.3V, 8, 1% THD) 490 mW - Shutdown Current 0.8 A - PSRRLS (217 Hz, LS_VDD = 3.3V) 70 dB - SNRLS (AUX IN to Loudspeaker) 90 dB (typ) - SNRDAC (Stereo DAC to AUXOUT) 85 dB (typ) - SNRADC (Mono ADC from Cell Phone In) 90 dB (typ) - SNRHP (Aux In to Headphones) 98 dB (typ) APPLICATIONS * * * * * Smart Phones Mobile Phones and Multimedia Terminals PDAs, Internet Appliances and Portable Gaming Portable DVD/CD/AAC/MP3 Players Digital Cameras/Camcorders 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2007-2012, Texas Instruments Incorporated LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com DESCRIPTION The LM49370 is an integrated audio subsystem that supports both analog and digital audio functions. The LM49370 includes a high quality stereo DAC, a mono ADC, a stereo headphone amplifier, which supports output cap-less (OCL) or AC-coupled (SE) modes of operation, a mono earpiece amplifier, and an ultra-low EMI spread spectrum Class D loudspeaker amplifier. It is designed for demanding applications in mobile phones and other portable devices. The LM49370 features a bi-directional I2S interface and a bi-directional PCM interface for full range audio on either interface. The LM49370 utilizes an I2C or SPI compatible interface for control. The stereo DAC path features an SNR of 85 dB with an 18-bit 48 kHz input. In SE mode the headphone amplifier delivers at least 33 mWRMS to a 32 single-ended stereo load with less than 1% distortion (THD+N) when A_VDD = 3.3V. The mono earpiece amplifier delivers at least 115mWRMS to a 32 bridged-tied load with less than 1% distortion (THD+N) when A_VDD = 3.3V. The mono speaker amplifier delivers up to 490mW into an 8 load with less than 1% distortion when LS_VDD = 3.3V and up to 1.2W when LS_VDD = 5.0V. The LM49370 employs advanced techniques to reduce power consumption, to reduce controller overhead, to speed development time, and to eliminate click and pop. Boomer audio power amplifiers were designed specifically to provide high quality output power with a minimal amount of external components. It is therefore ideally suited for mobile phone and other low voltage applications where minimal power consumption, PCB area and cost are primary requirements. LM49370 Overview SCL/SCK SDA/SDI TEST_MODE/CS A_VSS LS_VDD LS_VSS 2 I C/SPI SLAVE AB AUX_OUT AB EP_OUT D LS_OUT CPI POWER MANAGEMENT and CONTROL CLOCKS and 6'_PLL MCLK A_VDD RIGHT PLL_FLT D_VSS LEFT PLL_VDD BB_VDD D_VDD REGISTERS SPI_MODE PCM_CLK PCM_SYNC PCM_SDI PCM_SDO GPIO1 GPIO2 G7.11 HP_VMIDFB HP_VMID AB HPL_OUT AB HPR_OUT L 6' STEREO R DAC FIR FILTER and DIGITAL 3D ALGORITHM -46.5 dB to 12 dB SIDETONE I2S_SDO 6' MONO ADC 2 I2S_SDI DIGITAL AUDIO INTERFACE with PCM - I S BRIDGE I2S_WS LEVEL SHIFTERS I2S_CLK BYPASS AMP BIAS and DET BG 0 dB to -30 dB VREF_FLT MIC BIAS and DET INT_BIAS EXT_BIAS MIC_DET EXT_MIC 6 dB to MIC 36 dB INT_MIC IRQ AUX_R AUX_L AB AUTOMATIC GAIN CONTROL -34.5 dB to 12 dB CP_OUT CP_IN Figure 1. Conceptual Schematic 2 Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 Typical Application Synthesized FM Radio/ Analog Inputs LM4675 Can Be Used for Stereo Loudspeakers AUX_L AUX_R BYPASS VREF_FLT PLL_FILT AUX_OUT LM4675 GPIO1 0.5-30 MHz LS MCLK BB_VDD EP 2 I C INT_BIAS INT_MIC IRQ Baseband Controller GPIO2 HP_VMIDFB MIC_DET EXT_BIAS EXT_MIC HP_VMID HP_R HP_L 2 I S (Stereo) A2DP Bluetooth Transceiver PCM (Mono) CP_OUT CP_IN LM49370 Radio Module Figure 2. Example Application in Multimedia Mobile Phone Connection Diagrams 7 6 5 4 3 2 1 A B C D E F G Figure 3. 49 Bump DSBGA Top View (Bump Side Down) See Package Number YPG0049UUA Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 3 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com Pin Descriptions 4 Pin Pin Name Type Direction Description A1 EP_NEG Analog Output A2 A_VDD Supply Input Headphone and mixer VDD A3 INT_MIC_POS Analog Input Internal microphone positive input A4 PCM_SDO Digital Output A5 PCM_CLK Digital Inout PCM clock signal A6 PCM_SYNC Digital Inout PCM sync signal A7 PCM_SDI Digital Input PCM Serial Data Input B1 A_VSS Supply Input Headphone and mixer ground B2 EP_POS Analog Output B3 INT_MIC_NEG Analog Input Internal microphone negative input B4 BYPASS Analog Input A_VDD/2 filter point B5 TEST_MODE/CS Digital Input If SPI_MODE = 1, then this pin becomes CS. B6 PLL_FILT Analog Input Filter point for PLL VCO input PLL VDD Earpiece negative output PCM Serial Data Output Earpiece positive output B7 PLL_VDD Supply Input C1 HP_R Analog Output Headphone Right Output C2 EXT_BIAS Analog Output External microphone supply (2.0/2.5/2.8/3.3V) C3 INT_BIAS Analog Output Internal microphone supply (2.0/2.5/2.8/3.3V) C4 AUX_R Analog Input Right Analog Input C5 GPIO_2 Digital Inout General Purpose I/O 2 C6 SDA Digital Inout Control Data, I2C_SDA or SPI_SDA C7 SCL Digital Input Control Clock, I2C_SCL or SPI_SCL D1 HP_L Analog Output D2 VREF_FLT Analog Inout Filter point for the microphone power supply D3 EXT_MIC Analog Input External microphone input D4 SPI_MODE Digital Input Control mode select 1 = SPI, 0 = I2C Headphone Left Output D5 GPIO_1 Digital Inout General Purpose I/O 1 D6 BB_VDD Supply Input Baseband VDD for the digital I/Os D7 D_VDD Supply Input Digital VDD E1 HP_VMID Analog Inout Virtual Ground for Headphones in OCL mode, otherwise 1st headset detection input E2 MIC_DET Analog Input Headset insertion/removal and microphone presence detection input. E3 AUX_L Analog Input Left Analog Input E4 CPI_NEG Analog Input Cell Phone analog input negative E5 IRQ Digital Output Interrupt request signal (NOT open drain) E6 I2S_SDO Digital Output I2S Serial Data Out Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 Pin Descriptions (continued) Pin Pin Name Type Direction E7 I2S_SDI Digital Input I2S Serial Data Input Description F1 HP_VMID_FB Analog Input VMID Feedback in OCL mode, otherwise a 2nd headset detection input F2 LS_VDD Supply Input Loudspeaker VDD F3 CPI_POS Analog Input Cell Phone analog input positive F4 CPO_NEG Analog Output Cell Phone analog output negative F5 AUX_OUT_NEG Analog Output Auxiliary analog output negative F6 I2S_WS Digital Inout I2S Word Select Signal (can be master or slave) F7 I2S_CLK Digital Inout I2S Clock Signal (can be master or slave) G1 LS_NEG Analog Output Loudspeaker negative output G2 LS_VSS Supply Input Loudspeaker ground G3 LS_POS Analog Output Loudspeaker positive output G4 CPO_POS Analog Output Cell Phone analog output positive G5 AUX_OUT_POS Analog Output Auxiliary analog output positive G6 D_VSS Supply Input Digital ground G7 MCLK Digital Input Input clock from 0.5 MHz to 30 MHz PIN TYPE DEFINITIONS Analog Input-- A pin that is used by the analog and is never driven by the device. Supplies are part of this classification. Analog Output-- A pin that is driven by the device and should not be driven by external sources. Analog Inout-- A pin that is typically used for filtering a DC signal within the device, Passive components can be connected to these pins. Digital Input-- A pin that is used by the digital but is never driven. Digital Output-- A pin that is driven by the device and should not be driven by another device to avoid contention. Digital Inout-- A pin that is either open drain (I2C_SDA) or a bidirectional CMOS in/out. In the later case the direction is selected by a control register within the LM49370. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 5 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 Absolute Maximum Ratings www.ti.com (1) (2) Analog Supply Voltage (A_VDD & LS_VDD) 6.0V Digital Supply Voltage (BB_VDD & D_VDD & PLL_VDD) 6.0V -65C to +150C Storage Temperature Power Dissipation (3) Internally Limited ESD Susceptibility Human Body Model Machine Model (4) 2500V (5) 200V Junction Temperature 150C Thermal Resistance JA - YPG49 (soldered down to PCB with 2in2 1oz. copper plane) 60C/W Soldering Information (1) (2) (3) (4) (5) All voltages are measured with respect to the relevant VSS pin unless otherwise specified. All grounds should be coupled as close as possible to the device. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not ensure specific performance limits. Characteristics state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance. The maximum power dissipation must be de-rated at elevated temperatures and is dictated by TJMAX, JA, and the ambient temperature, TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / JA or the number given in Absolute Maximum Ratings, whichever is lower. Human body model: 100pF discharged through a 1.5k resistor. Machine model: 220pF - 240pF discharged through all pins. Operating Ratings -40C to +85C Temperature Range Supply Voltage D_VDD/PLL_VDD 2.5V to 4.5V BB_VDD 1.8V to 4.5V LS_VDD = A_VDD (1) (1) 2.5V to 5.5V LS_VDD must be equal to A_VDD due to intend ESD diode structure. For proper operation, LS_VDD and A_VDD need to be the highest voltage than BB_VDD, D_VDD, and PLL_VDD and must be applied first. Electrical Characteristics (1) (2) Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V. The following specifications apply for the circuit shown in Figure 2 unless otherwise stated. Limits apply for 25C. LM49370 Symbol Parameter Conditions Typical (3) Limit (4) Units (5) POWER DISD Digital Shutdown Current (6) Chip Mode '00', fMCLK = 13MHz 0.7 2.2 A (max) DIST Digital Standby Current Chip Mode '01', fMCLK = 13MHz 0.9 1.8 mA(max) AISD Analog Shutdown Current Chip Mode '00' 0.1 1.2 A(max) AIST Analog Standby Current Chip Mode '01' 0.1 1.2 A (max) (1) (2) (3) (4) (5) (6) 6 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not ensure specific performance limits. Characteristics state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance. All voltages are measured with respect to the relevant VSS pin unless otherwise specified. All grounds should be coupled as close as possible to the device. Typical values are measured at 25C and represent the parametric norm. Limits are specified to TI's AOQL (Average Outgoing Quality Level). Datasheet min/max specification limits are specified by design, test, or statistical analysis. Digital shutdown current is measured with system clock set for PLL output while the PLL is disabled. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 Electrical Characteristics (1)(2) (continued) Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V. The following specifications apply for the circuit shown in Figure 2 unless otherwise stated. Limits apply for 25C. LM49370 Symbol Parameter Conditions Typical (3) Limit (4) Units (5) Chip Mode '10', fMCLK = 12MHz, fS = 48kHz, DAC on; PLL off 7.9 Chip Mode '10', fMCLK = 13MHz, fPLLOUT = 12MHz, fS = 48kHz; DAC + PLL on 12.5 14.5 mA(max) Chip Mode '10', HP On, SE mode, DAC inputs selected 9.0 13.5 mA(max) Chip Mode '10', HP On, OCL mode, DAC inputs selected 9.4 13.5 mA(max) Chip Mode '10', LS On, DAC inputs selected 11.5 15.5 mA(max) Chip Mode '10', fMCLK = 13MHz, DAC +ADC + PLL off 0.9 1.8 mA(max) Chip Mode '10', HP On, SE mode, AUX inputs selected 5.9 9.5 mA(max) Chip Mode '10', HP On, OCL mode, AUX inputs selected 6.3 9.7 mA(max) Chip Mode '10', LS On, AUX inputs selected 8.4 12 mA(max) Chip Mode '10', fMCLK = 13MHz, fS = 8kHz, DAC +ADC on; PLL Off 2.7 3.5 mA(max) CODEC Mode Analog Active Current Chip Mode '10', EP On, DAC inputs selected 11.2 15.5 mA(max) Voice Module Mode Digital Active Current Chip Mode '10', fMCLK = 13MHz, DAC +ADC + PLL off 0.9 1.8 mA(max) Voice Module Mode Analog Active Current Chip Mode '10', EP + CPOUT on, CPIN input selected 7.4 11 mA(max) 8 load, LS_VDD = 5V 1.2 8 load, LS_VDD = 4.2V 0.9 8 load, LS_VDD = 3.3V 0.5 0.04 % Digital Playback Mode Digital Active Current Digital Playback Mode Analog Active Current Analog Playback Mode Digital Active Current Analog Playback Mode Analog Active Current CODEC Mode Digital Active Current mA LOUDSPEAKER AMPLIFIER PLS Max Loudspeaker Power W W 0.43 W (min) LSTHD+N Loudspeaker Harmonic Distortion 8 load, LS_VDD = 3.3V, PO = 400mW LSEFF Efficiency 0 dB Input MCLK = 12.000 MHz 84 % PSRRLS Power Supply Rejection Ration (Loudspeaker) AUX inputs terminated CBYPASS = 1.0 F VRIPPLE = 200 mVP-P fRIPPLE = 217 Hz 70 dB SNRLS Signal to Noise Ratio From 0 dB Analog AUX input, A-weighted 90 eN Output Noise (7) A-weighted 62 V VOS Loudspeaker Offset Voltage 12 mV (7) 80 dB(min) Disabling or bypassing the PLL will usually result in an improvement in noise measurements. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 7 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com Electrical Characteristics (1)(2) (continued) Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V. The following specifications apply for the circuit shown in Figure 2 unless otherwise stated. Limits apply for 25C. LM49370 Symbol Parameter Conditions Typical (3) Limit (4) Units 25 mW (min) (5) HEADPHONE AMPLIFIER PHP Headphone Power 32 load, 3.3V, SE 33 16 load, 3.3V, SE 52 mW 32 load, 3.3V, OCL, VCM = 1.5V 31 mW 32 load, 3.3V, OCL, VCM = 1.2V 20 mW 16 load, 3.3V, OCL, VCM = 1.5V 50 mW 16 load, 3.3V, OCL, VCM = 1.2V 32 mW SE Mode 60 dB OCL Mode VCM = 1.2V 68 OCL Mode VCM = 1.5V 65 dB SE Mode 98 dB OCL Mode VCM = 1.2V 97 dB OCL Mode VCM = 1.5V 96 dB AUX inputs terminated CBYPASS = 1.0 F VRIPPLE = 200 mVP-P fRIPPLE = 217 Hz PSRRHP Power Supply Rejection Ratio (Headphones) 55 dB(min) From 0dB Analog AUX input A-weighted SNRHP Signal to Noise Ratio HPTHD+N Headphone Harmonic Distortion 32 load, 3.3V, PO = 7.5mW eN Output Noise A-weighted 0.05 % 12 V ACH-CH Stereo Channel-to-Channel Gain Mismatch 0.3 dB XTALK Stereo Crosstalk SE Mode 61 dB OCL Mode 71 VOS Offset Voltage dB 8 mV EARPIECE AMPLIFIER PEP Earpiece Power 115 16 load, 3.3V 150 mW 76 dB 93 dB PSRREP Power Supply Rejection Ratio (Earpiece) CP_IN terminated CBYPASS = 1.0 F VRIPPLE = 200 mVP-P FRIPPLE = 217 Hz SNREP Signal to Noise Ratio From 0dB Analog AUX input, A-weighted EPTHD+N Earpiece Harmonic Distortion 32 load, 3.3V, PO = 50mW eN Output Noise A-weighted VOS Offset Voltage 100 mW (min) 32 load, 3.3V 0.04 % 41 V 8 mV 0.02 % 86 dB AUXOUT AMPLIFIER THD+N Total Harmonic Distortion + Noise VO = 1VRMS, 5k load PSRR Power Supply Rejection Ratio CP_IN terminated CBYPASS = 1.0F VRIPPLE = 200mVPP fRIPPLE = 217Hz 8 Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 Electrical Characteristics (1)(2) (continued) Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V. The following specifications apply for the circuit shown in Figure 2 unless otherwise stated. Limits apply for 25C. LM49370 Symbol Parameter Conditions Typical (3) Limit (4) Units (5) CP_OUT AMPLIFIER THD+N PSRR Total Harmonic Distortion + Noise VO = 1VRMS, 5k load Power Supply Rejection Ratio CBYPASS = 1.0F VRIPPLE = 200mVPP fRIPPLE = 217Hz 0.02 % 86 dB MONO ADC RADC PBADC ADC Ripple ADC Passband SBAADC ADC Stopband Attenuation SNRADC ADC Signal to Noise Ratio ADCLEVEL ADC Full Scale Input Level 0.25 dB Lower (HPF Mode 1), fS = 8 kHz 300 Hz Upper 3470 Hz Above Passband 60 dB HPF Notch, 50 Hz/60 Hz (worst case) 58 dB From CPI, A-weighted 90 dB 1 VRMS STEREO DAC RDAC DAC Ripple 0.1 dB PBDAC DAC Passband 20 kHz SBADAC DAC Stopband Attenuation 70 dB SNRDAC DAC Signal to Noise Ratio 85 dB DRDAC DAC Dynamic Range 96 dB DACLEVEL DAC Full Scale Output Level 1 VRMS A-weighted, AUXOUT PLL (8) FIN Input Frequency Range Min 0.5 MHz Max 30 MHz I2S/PCM fI2SCLK fPCMCLK I2S CLK Frequency PCM CLK Frequency DCI2S_CLK I2S_CLK Duty Cycle DCI2S_WS I2S_WS Duty Cycle fS = 48kHz; 16 bit mode 1.536 MHz fS = 48kHz; 25 bit mode 2.4 MHz fS = 8kHz; 16 bit mode 0.256 MHz fS = 8kHz; 25 bit mode 0.4 MHz fS = 48kHz; 16 bit mode 0.768 MHz fS = 48kHz; 25 bit mode 1.2 MHz fS = 8kHz; 16 bit mode 0.128 MHz fS = 8kHz; 25 bit mode 0.2 Min Max MHz 40 % (min) 60 % (max) 50 % I2C TI2CSET I2C Data Setup Time Refer to TRANSFERRING DATA for more details 100 ns (min) TI2CHOLD I2C Data Hold Time Refer to TRANSFERRING DATA for more details 300 ns (min) SPI TSPISETENB Enable Setup Time 100 ns (min) TSPIHOLD-ENB Enable Hold Time 100 ns (min) TSPISETD Data Setup Time 100 ns (min) (8) Disabling or bypassing the PLL will usually result in an improvement in noise measurements. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 9 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com Electrical Characteristics (1)(2) (continued) Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V. The following specifications apply for the circuit shown in Figure 2 unless otherwise stated. Limits apply for 25C. LM49370 Symbol Parameter Conditions Typical (3) Limit (4) Units (5) TSPIHOLDD Data Hold Time 100 ns (min) TSPICL Clock Low Time 500 ns (min) TSPICH Clock High Time 500 ns (min) VOLUME CONTROL VCRAUX VCRDAC VCRCPIN AUX Volume Control Range DAC Volume Control Range CPIN Volume Control Range Minimum Gain w/ AUX_BOOST OFF -46.5 dB Maximum Gain w/ AUX_BOOST OFF 0 dB Minimum Gain w/ AUX_BOOST ON -34.5 dB Maximum Gain w/ AUX_BOOST ON 12 dB Minimum Gain w/ DAC_BOOST OFF -46.5 dB Maximum Gain w/ DAC_BOOST OFF 0 dB Minimum Gain w/ DAC_BOOST ON -34.5 dB Maximum Gain w/ DAC_BOOST ON 12 dB Minimum Gain -34.5 dB Maximum Gain 12 dB Minimum Gain 6 dB Maximum Gain 36 dB Minimum Gain -30 dB Maximum Gain 0 dB VCRMIC MIC Volume Control Range VCRSIDE SIDETONE Volume Control Range SSAUX AUX VCR Stepsize 1.5 dB SSDAC DAC VCR Stepsize 1.5 dB SSCPIN CPIN VCR Stepsize 1.5 dB SSMIC MIC VCR Stepsize 2 dB SSSIDE SIDETONE VCR Stepsize 3 dB AUDIO PATH GAIN W/ STEREO (bit 6 of 0x00h) ENABLED (AUX_L & AUX_R signals identical and selected onto mixer) Loudspeaker Audio Path Gain Headphone Audio Path Gain 10 Minimum Gain from AUX input, BOOST OFF -34.5 dB Maximum Gain from AUX input, BOOST OFF 12 dB Minimum Gain from CPI input -22.5 dB Maximum Gain from CPI input 24 dB Minimum Gain from AUX input, BOOST OFF -52.5 dB Maximum Gain from AUX input, BOOST OFF -6 dB Minimum Gain from CPI input -40.5 dB Maximum Gain from CPI input 6 dB Minimum Gain from MIC input using SIDETONE path w/ VCRMIC gain = 6dB -30 dB Maximum Gain from MIC input using SIDETONE path w/ VCRMIC gain = 6dB 0 dB Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 Electrical Characteristics (1)(2) (continued) Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V. The following specifications apply for the circuit shown in Figure 2 unless otherwise stated. Limits apply for 25C. LM49370 Symbol Parameter Conditions Earpiece Audio Path Gain AUXOUT Audio Path Gain CPOUT Audio Path Gain Typical (3) Limit (4) Units (5) Minimum Gain from AUX input, BOOST OFF -40.5 dB Maximum Gain from AUX input, BOOST OFF 6 dB Minimum Gain from CPI input -28.5 dB Maximum Gain from CPI input 18 dB Minimum Gain from MIC input using SIDETONE path w/ VCRMIC gain = 6dB -18 dB Maximum Gain from MIC input using SIDETONE path w/ VCRMIC gain = 6dB 12 dB Minimum Gain from AUX input, BOOST OFF -46.5 dB Maximum Gain from AUX input, BOOST OFF 0 dB Minimum Gain from CPI input -34.5 dB Maximum Gain from CPI input 12 dB Minimum Gain from AUX input, BOOST OFF -46.5 dB Maximum Gain from AUX input, BOOST OFF 0 dB Minimum Gain from MIC input 6 dB Maximum Gain from MIC input 36 dB fMCLK = 12MHz, PLL OFF 56 mW fMCLK = 13MHz, PLL ON fPLLOUT = 12MHz 71 mW 22 mW 46 mW 27 mW Total DC Power Dissipation DAC (fS = 48kHz) and HP ON Digital Playback Mode Power Dissipation AUX Inputs selected and HP ON Analog Playback Mode Power Dissipation fMCLK = 13MHz, PLL OFF PCM DAC (fS = 8kHz) + ADC (fS = 8kHz) VOICE CODEC Mode Power Dissipation and EP ON fMCLK = 13MHz, PLL OFF VOICE Module Mode Power Dissipation CP IN selected. EP and CPOUT ON fMCLK = 13MHz, PLL OFF Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 11 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com System Control Method 1. I2C Compatible Interface I2C SIGNALS In I2C mode the LM49370 pin SCL is used for the I2C clock SCL and the pin SDA is used for the I2C data signal SDA. Both these signals need a pull-up resistor according to I2C specification. The I2C slave address for LM49370 is 00110102. I2C DATA VALIDITY The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can only be changed when SCL is LOW. SCL SDA data change allowed data valid data change allowed data change allowed data valid Figure 4. I2C Signals: Data Validity I2C START AND STOP CONDITIONS START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP bits. The I2C bus is considered to be busy after START condition and free after STOP condition. During data transmission, I2C master can generate repeated START conditions. First START and repeated START conditions are equivalent, function-wise. SDA SCL S P START condition STOP condition TRANSFERRING DATA Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the 9th clock pulse, signifying an acknowledge. A receiver which has been addressed must generate an acknowledge after each byte has been received. After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an eight bit which is a data direction bit (R/W). The LM49370 address is 00110102. For the eighth bit, a "0" indicates a WRITE and a "1" indicates a READ. The second byte selects the register to which the data will be written. The third byte contains data to write to the selected register. MSB ADR6 Bit7 LSB ADR5 bit6 ADR4 bit5 ADR3 bit4 ADR2 bit3 ADR1 bit2 ADR0 bit1 R/W bit0 2 I C SLAVE address (chip address) Figure 5. I2C Chip Address 12 Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 Register changes take an effect at the SCL rising edge during the last ACK from slave. ack from slave ack from slave start MSB Chip Address LSB w ack MSB Register 0x02h LSB ack start slave address = 00110102 w ack MSB ack from slave Data LSB ack stop ack stop SCL SDA register address = 0x02h ack register 0x02h data w = write (SDA = "0") r = read (SDA = "1") ack = acknowledge (SDA pulled down by slave) rs = repeated start Figure 6. Example I2C Write Cycle When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the Read Cycle waveform. ack from slave ack from slave repeated start start MSB Chip Address LSB w ack MSB Register 0x00h LSB ack rs ack from slave data from slave ack from master MSB Chip Address LSB r ack MSB Data LSB ack stop SCL SDA start slave address = 00110102 w ack register address = 0x00h ack rs slave address = 00110102 r ack register 0x00h data ack stop Figure 7. Example I2C Read Cycle SDA 10 8 7 6 1 8 2 7 SCL 1 5 4 3 9 Figure 8. I2C Timing Diagram I2C TIMING PARAMETERS Parameter (1) Symbol Limit Min (1) 1 Hold Time (repeated) START Condition 2 3 4 Units Max 0.6 s Clock Low Time 1.3 s Clock High Time 600 ns Setup Time for a Repeated START Condition 600 ns Data specified by design Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 13 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com 5 Data Hold Time (Output direction, delay generated by LM49370) 300 900 ns 5 Data Hold Time (Input direction, delay generated by the Master) 0 900 ns 6 Data Setup Time 7 Rise Time of SDA and SCL 20+0.1Cb 300 ns 8 Fall Time of SDA and SCL 15+0.1Cb 300 ns 9 Set-up Time for STOP condition 600 ns 10 Bus Free Time between a STOP and a START Condition 1.3 s Cb Capacitive Load for Each Bus Line 10 100 ns 200 pF Method 2. SPI/Microwire Control/3-wire Control The LM49370 can be controlled via a three wire interface consisting of a clock, data and an active low chip_select. To use this control method connect SPI_MODE to BB_VDD and use TEST_MODE/CS as the chip_select as follows: TEST_MODE/CS CLK SDI 15 14 8 7 Register Address 1 0 Write Data Figure 9. SPI Write Transaction If the application requires read access to the register set; for example to determine the cause of an interrupt request, the GPIO2 pin can be configured as an SPI format serial data output by setting the GPIO_SEL in the GPIO configuration register (0x1Ah) to SPI_SDO. To perform a read rather than a write to a particular address the MSB of the register address field is set to a 1, this effectively mirrors the contents of the register field to readonly locations above 0x80h: TEST_MODE/CS CLK SDI 15 14 8 GPIO2 Ignored 11 Register Address 1 4 Register Data Figure 10. SPI Read Transaction Figure 11. Three Wire Mode Write Bus Timing TSPISETENB TSPIHOLDENB TEST_MODE/CS TSPICL TSPIT CLK TSPICH SDI TSPISETD TSPIHOLDD Figure 12. SPI Timing 14 Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 Status & Control Registers Table 1. Register Map (1) Address Register 0x00h Table 2 BASIC 0x01h Table 3 CLOCKS 0x02h (1) 7 6 5 DAC_ MODE 4 CAP_SIZE 3 2 OSC_ENB PLL_ENB DAC_CLK_SEL FORCERQ PLL_N 0x04h PLL_P VCOFATS 0x05h PLL_MOD PLLTEST 0x06h ADC_1 ADC_2 0x08h AGC_1 0x09h AGC_2 0x0Ah AGC_3 0x0Bh MIC_1 0 CHP_MODE R_DIV 0x03h 0x07h 1 PLL_M PLL_N Q_DIV PLL_P PLL_CLK_SEL HPF_MODE NGZXDD PLL_N_MOD SAMPLE_RATE ADC_CLK_SEL NG_ENB AGC_DECAY INT_EXT 0x0Dh SIDETONE 0x0Eh CP_INPUT 0x0Fh AUX_LEFT AUX_DAC 0x10h AUX_RIGHT 0x11h DAC 0x12h CP_OUTPUT 0x13h 0x14h 0x15h HP_OUTPUT 0x16h EP_OUTPUT 0x17h DETECT 0x18h STATUS MIC ADC _MODE AGC_ENB AGC_MAX_GAIN AGC_HOLD_TIME SE_DIFF MUTE BTN_DEBOUNCE_TIM E MIC_2 CPI ADC MUTE AGC_TARGET AGC_ATTACK 0x0Ch LEFT PEAKTIME NOISE_GATE_THRESHOLD AGC _TIGHT RIGHT PREAMP_GAIN BTNTYPE MIC_BIAS_VOLTAGE VCMVOLT SIDETONE_ATTEN MUTE CPI_LEVEL MUTE BOOST AUX_LEFT_LEVEL AUX_DAC MUTE BOOST AUX_RIGHT_LEVEL USAXLVL DACMUTE BOOST DAC_LEVEL MICGATE MUTE LEFT RIGHT MIC AUX OUTPUT MUTE LEFT RIGHT CPI LS_OUTPUT MUTE LEFT RIGHT CPI MUTE LEFT RIGHT CPI SIDE MUTE LEFT OCL STEREO HS_DBNC_TIME GPIN1 0x19h 3D CUST _COMP 0x1Ah I2SMODE WORD_ ORDER 0x1Bh I2SCLOCK GPIN2 ATTENUATE I2S_WS_GEN_MODE COMPAND WS_MS STEREO REVERSE 0x1Dh PCMCLOCK SYNC_MS CLKSRCE 0x1Eh BRIDGE 0x1Fh GPIO 0x20h CMP_0_LSB CMP_0_LSB 0x21h CMP_0_0SB CMP_0_MSB 0x22h CMP_1_LSB CMP_1_LSB 0x23h CMP_1_MSB CMP_1_MSB 0x24h CMP_2_LSB CMP_2_LSB 0x25h CMP_2_MSB CMP_2_MSB PCM_SYNC_GEN_MODE ADC_SRC_ MODE MIC STEREO HEADSET MODE 3DENB INENB OUTENB CLKSCE CLK_MS INENB OUTENB I2S_MOD E I2S_CLOCK_GEN_MODE SDO_ LSB_HZ PCMMODE DAC_SRC_ MODE SIDE DET_INT LEVEL 0x1Ch MONO_SUM_MODE CPI BTN_INT BTN FREQ PCM_SYNC__WIDTH ALAW/LA W TEMP RIGHT TEMP_INT MONO_ SUM_SEL CLK_MS PCM_CLOCKGEN MODE DAC_TX_SEL GPIO_2_SEL I2S_TX_SEL PCM_ TX_SEL GPIO_1_SEL The default value of all I2C registers is 0x00h. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 15 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com BASIC CONFIGURATION REGISTER This register is used to control the basic function of the chip. Table 2. BASIC (0x00h) Bits Field Description 1:0 CHIP_MODE The LM49370 can be placed in one of four modes which dictate its basic operation. When a new mode is selected the LM49370 will change operation silently and will re-configure the power management profile automatically. The modes are described as follows: CHIP MODE Audio System 002 Off Typical Application Power-down Mode 012 Off Stand-by mode with headset event detection 102 On Active without headset event detection 112 On Active with headset event detection 2 PLL_ENABLE 3 USE_OSC If set the power management and control circuits will assume that no external clock is available and will resort to using an on-chip oscillator for headset detection and analog power management functions such as click and pop. The PLL, ADC, and DAC are not wired to use this low quality clock. This bit must be cleared for the part to be fully turned off power-down mode. 5:4 CAP_SIZE This programs the extra delays required to stabilize once charge/discharge is complete, based on the size of the bypass capacitor. 7:6 DAC_MODE This enables the PLL. CAP_SIZE Bypass Capacitor Size 002 0.1 F 45 ms/75 ms 012 1 F 45 ms/140 ms 102 2.2 F 45 ms/260 ms 112 4.7 F 45 ms/500 ms Turn-off/on time The DAC can operate in one of four modes. If an "fs*2N" audio clock is available, then the DAC can be run in a slightly lower power mode. If such a clock is not available, the PLL can be used to generate a suitable clock. DAC MODE DAC OSR Typical Application 002 125 48kHz Playback from 12.000MHz 012 128 48kHz Playback from 12.288MHz 102 64 96kHz Playback from 12.288MHz 112 32 192kHz Playback from 24.576MHz For reliable headset / push button detection the following bits should be defined before enabling the headset detection system by setting bit 0 of CHIP_MODE: The OCL-bit (Cap / Capless headphone interface; bit 6 of HP_OUTPUT (0x15h)) The headset insert/removal debounce settings (bits 6:3 of DETECT (0x17h)) The BTN_TYPE-bit (Parallel / Series push button type; bit 3 MIC_2 register (0x0Ch)) The parallel push button debounce settings (bits 5:4 of MIC_2 register (0x0Ch)) All register fields controlling the audio system should be defined before setting bit 1 of CHIP_MODE and should not be altered while the audio sub-system is active. If the analog or digital levels are below -12dB then it is not necessary to set the stereo bit allowing greater output levels to be obtained for such signals. CLOCKS CONFIGURATION REGISTER This register is used to control the clocks throughout the chip. 16 Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 Table 3. CLOCKS (0x01h) Bits Field 1:0 DAC_CLK Description This selects the clock to be used by the audio DAC system. DAC_CLK 7:2 R_DIV DAC Input Source 002 MCLK 012 PLL_OUTPUT 102 I2S_CLK_IN 112 PCM_CLK_IN This programs the R divider. R_DIV Divide Value 0 Bypass 1 Bypass 2 1.5 3 2 4 2.5 5 3 6 3.5 7 4 8 4.5 9 5 10 5.5 11 6 12 6.5 13 to 61 7 to 31 62 31.5 63 32 LM49370 CLOCK NETWORK The audio ADC operates at 125*fs ( or 128*fs), so it requires a 1.000 MHz (or 1.024MHz) clock to sample at 8 kHz (at point C as marked on the following diagram). If the stereo DAC is running at 125*fs (or128*fs), it requires a 12.000MHz (or 12.288MHz) clock (at point B) for 48 kHz data. It is expected that the PLL is used to drive the audio system operating at 125*fs unless a 12.000 MHz master clock is supplied or the sample rate is always a multiple of 8 kHz. In this case the PLL can be bypassed to reduce power, with clock division being performed by the Q and R dividers instead. The PLL can also be bypassed if the system is running at 128*fs and a 12.288MHz master clock is supplied and the sample rate is a multiple of 8kHz. The PLL can also use the I2S clock input as a source. In this case, the audio DAC uses the clock from the output of the PLL and the audio ADC either uses the PLL output divided by 2*FS(DAC)/FS(ADC) or a system clock divided by Q, this allows n*8 kHz recording and 44.1 kHz playback. MCLK must be less than or equal to 30 MHz. I2S_CLK and PCM_CLK should be below 6.144MHz. When operating at 125*fs, the LM49370 is designed to work from a 12.000 MHz or 11.025 MHz clock at point A. When operating at 128*fs, the LM49370 is designed to work from a 12.288MHz or 11.2896 MHz clock at point A. This is used to drive the power management and control logic. Performance may not meet the electrical specifications if the frequency at this point deviates significantly beyond this range. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 17 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com USE_ONCHIP_OSC From on chip 12 MHz oscillator %R PLL A (to DET, PMC) B %Q MCLK C I2S Interface Stereo DAC PCM Interface Mono ADC I2S_CLK PCM_CLK Figure 13. LM49370 Clock Network COMMON CLOCK SETTINGS FOR THE DAC & ADC When DAC_MODE = '00' (bits 7:6 of (0x00h)), the DAC has an over sampling ratio of 125 but requires a 250*fs clock at point B. This allows a simple clocking solution as it will work from 12.000 MHz (common in most systems with Bluetooth or USB) at 48 kHz exactly, the following table describes the clock required at point B for various clock sample rates in the different DAC modes: Table 4. Common DAC Clock Frequencies DAC Sample Rate (kHz) Clock Required at B (OSR = 125) Clock Required at B (OSR = 128) 8 2 MHz 2.048 MHz 11.025 2.75625 MHz 2.8224 MHz 12 3 MHz 3.072 MHz 16 4 MHz 4.096 MHz 22.05 5.5125 MHz 5.6448 MHz 24 6 MHz 6.144 MHz 32 8 MHz 8.192 MHz 44.1 11.025 MHz 11.2896 MHz 48 12 MHz 12.288 MHz NOTE When DAC_MODE = '01' with the I2S or PCM interface operating as master, the stereo DAC operates at half the frequency of the clock at point B. This divided by two DAC clock is used as the source clock for the audio port. The over sampling ratio of the ADC is set by ADC MODE (bit 0 of 0x07h)). The table below shows the required clock frequency at point C for the different ADC modes. Table 5. Common ADC Clock Frequencies 18 ADC Sample Rate (kHz) Clock Required at C (OSR = 125) 8 1 MHz 1.024 MHz 11.025 1.378125 MHz 1.4112 MHz 12 1.5 MHz 1.536 MHz 16 2 MHz 2.048 MHz 22.05 2.75625 MHz 2.8224 MHz 24 3 MHz 3.072 MHz Submit Documentation Feedback Clock Required at C (OSR = 128) Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 Methods for producing these clock frequencies are described in the PLL Section. PLL M DIVIDER CONFIGURATION REGISTER This register is used to control the input section of the PLL. Table 6. PLL_M (0x02h) (1) Bits Field 0 RSVD 6:0 PLL_M 7 (1) FORCERQ Description RESERVED PLL_M Input Divider Value 0 No Divided Clock 1 1 2 1.5 3 2 4 2.5 ... 3 to 63 126 63.5 127 64 If set, the R and Q divider are enabled and the DAC and ADC clocks are propagated. This allows operation of the I2S and PCM interfaces without the ADC or DAC being enabled, for example to act as a bridge or a clock master. See Further Notes on PLL Programming for more detail. The M divider should be set such that the output of the divider is between 0.5 MHz and 5 MHz. The division of the M divider is derived from PLL_M such that: M = (PLL_M + 1) / 2 PLL N DIVIDER CONFIGURATION REGISTER This register is used to control the feedback divider of the PLL. Table 7. PLL_N (0x03h) (1) Bits Field 7:0 PLL_N (1) Description This programs the PLL feedback divider as follows: PLL_N Feedback Divider Value 0 to 10 10 11 11 12 12 13 13 14 14 ... ... 249 249 250 to 255 250 See Further Notes on PLL Programming for further details. The N divider should be set such that the output of the divider is between 0.5 MHz and 5 MHz. (Fin/M)*N will be the target resting VCO frequency, FVCO. The N divider should be set such that 40 MHz < (Fin/M)*N < 60 MHz. Fin/M is often referred to as Fcomp (comparison frequency) or Fref (reference frequency), in this document Fcomp is used. The integer division of the N divider is derived from PLL_N such that: For 9 < PLL_N < 251: N = PLL_N PLL P DIVIDER CONFIGURATION REGISTER This register is used to control the output divider of the PLL. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 19 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com Table 8. PLL_P (0x04h) (1) Bits Field 3:0 PLL_P 6:4 7 (1) Q_DIV FAST_VCO Description This programs the PLL output divider as follows: PLL_P Output Divider Value 0 No Divided Clock 1 1 2 1.5 3 2 4 2.5 ... 3 to 7 14 7.5 15 8 This programs the Q Divider Q_DIV Divide Value 0002 2 0012 3 0102 4 0112 6 1002 8 1012 10 1102 12 1112 13 This programs the PLL VCO range: FAST_VCO PLL VCO Range 0 40 to 60MHz 1 60 to 80MHz See Further Notes on PLL Programming for more details. The division of the P divider is derived from PLL_P such that: P = (PLL_P + 1) / 2 PLL N MODULUS CONFIGURATION REGISTER This register is used to control the modulation applied to the feedback divider of the PLL. Table 9. PLL_N_MOD (0x05h) (1) Bits Field 4:0 PLL_N_MOD 6:5 PLL_CLK_SEL Description This programs the PLL N divider's fractional component: PLL_N_MOD Fractional Addition 0 0/32 1 1/32 2 to 30 2/32 to 30/32 31 31/32 This selects the clock to be used as input for the audio PLL. PLL_INPUT_CLK 7 (1) 20 RSVD 002 MCLK 012 I2S_CLK_IN 102 PCM_CLK_IN 112 -- Reserved. See Further Notes on PLL Programming for more details. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 The complete N divider is a fractional divider as such: N = PLL_N + PLL_N_MOD/32 If the modulus input is zero then the N divider is simply an integer N divider. The output from the PLL is determined by the following formula: Fout = (Fin*N)/(M*P) FURTHER NOTES ON PLL PROGRAMMING The sigma-delta PLL Is designed to drive audio circuits requiring accurate clock frequencies of up to 30MHz with frequency errors noise-shaped away from the audio band. The 5 bits of modulus control provide exact synchronization of 48kHz and 44.1kHz sample rates from any common system clock. In systems where an isochronous I2S data stream is the source of data to the DAC a clock synchronous to the sample rate should be used as input to the PLL (typically the I2S clock). If no isochronous source is available, then the PLL can be used to obtain a clock that is accurate to within 1Hz of the correct sample rate although this is highly unlikely to be a problem. PLL_P 4 Phase Comparator P = 0,1 + 0/2 - >64 and Charge Pump 0.5-30 MHz %M 40 to 60 MHz External Loop Filter 0 250 x FS VCO %P 0.5 < 5 MHz P = 1..8 7 %N N = 10..250 31/32 PLL_M 6'M 8 8 5 PLL_N PLL_N_MOD Figure 14. PLL Overview Table 10. Example PLL Settings for 48 kHz and 44.1 kHz Sample Rates in DAC MODE 00 Fin (MHz) Fs (kHz) M N P PLL_M PLL_N PLL_N_MO D PLL_P Fout (MHz) 11 48 11 60 5 21 60 0 9 12 12.288 48 4 19.53125 5 7 19 17 9 12 13 48 13 60 5 25 60 0 9 12 14.4 48 9 37.5 5 17 37 16 9 12 16.2 48 27 100 5 53 100 0 9 12 16.8 48 14 50 5 27 50 0 9 12 19.2 48 13 40.625 5 25 40 20 9 12 19.44 48 27 100 6 53 100 0 11 12 19.68 48 20.5 62.5 5 40 62 16 9 12 19.8 48 16.5 50 5 32 50 0 9 12 11 44.1 11 55.125 5 21 55 4 9 11.025 11.2896 44.1 8 39.0625 5 15 39 2 9 11.025 12 44.1 5 22.96875 5 9 22 31 9 11.025 13 44.1 13 55.125 5 25 55 4 9 11.025 14.4 44.1 12 45.9375 5 23 45 30 9 11.025 16.2 44.1 9 30.625 5 17 9 20 9 11.025 16.8 44.1 17 55.78125 5 33 30 25 9 11.025 19.2 44.1 16 45.9375 5 31 45 30 9 11.025 19.44 44.1 13.5 38.28125 5 26 38 9 9 11.025 19.68 44.1 20.5 45.9375 4 40 45 30 7 11.025 19.8 44.1 11 30.625 5 21 30 20 9 11.025 Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 21 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com Table 11. Example PLL Settings for 48 kHz and 44.1 kHz Sample Rates in DAC MODE 01 Fin (MHz) Fs (kHz) M N P PLL_M PLL_N PLL_N_MO D PLL_P Fout (MHz) 12 48 12.5 64 5 24 64 0 9 12.288 13 48 26.5 112.71875 4.5 52 112 23 8 12.288 14.4 48 37.5 128 4 74 128 0 7 12.288 16.2 48 37.5 128 4.5 74 128 0 8 12.288 16.8 48 12.53 32 3.5 24 32 0 6 12.288 19.2 48 12.5 32 4 24 32 0 7 12.288 19.44 48 40.5 128 58 80 128 0 9 12.288 19.68 48 20.5 64 5 40 64 0 9 12.288 19.8 48 37.5 128 5.5 74 128 0 10 12.288 12 44.1 35.5 133.59375 4 70 133 19 7 11.2896 13 44.1 37 144.59375 4.5 73 144 19 8 11.2896 14.4 44.1 37.5 147 5 74 147 0 9 11.2896 16.2 44.1 47.5 182.0625 5.5 94 182 2 10 11.2896 16.8 44.1 12.5 42 5 24 42 0 9 11.2896 19.2 44.1 12.5 36.75 5 24 36 24 9 11.2896 19.44 44.1 37.5 98 4.5 74 98 0 9 11.2896 19.68 44.1 44.5 114.875 4.5 88 114 28 8 11.2896 19.8 44.1 48 136.84375 5 95 136 27 9 11.2896 These tables cover the most common applications, obtaining clocks for derivative sample rates such as 22.05 kHz should be done by increasing the P divider value or using the R/Q dividers. An example of obtaining 12.000 MHz from 1.536 MHz is shown below (this is typical for deriving DAC clocks from I2S datastreams). Choose a small range of P so that the VCO frequency is swept between 40 MHz and 60 MHz (or 60-80 MHz if VCOFAST is used). Remembering that the P divider can divide by half integers, for a 12 MHz output, this gives possible P values of 3, 3.5, 4, 4.5, or 5. The M divider should be set such that the comparison frequency (Fcomp) is between 0.5 and 5 MHz. This gives possible M values of 1, 1.5, 2, 2.5, or 3. The most accurate N and N_MOD can be calculated by sweeping the P and M inputs of the following formulas: N = FLOOR{[(Fout/Fin)*(P*M)],1} N_MOD = ROUND{32*[((Fout)/Fin)*(P*M)-N],0} This shows that setting M = 1, N = 39+1/16, P = 5 (i.e. PLL_M = 0, PLL_N = 39, PLL_N_MOD = 2, & PLL_P = 4) gives a comparison frequency of 1.536MHz, a VCO frequency of 60 MHz and an output frequency of 12.000 MHz. The same settings can be used to get 11.025 from 1.4112 MHz for 44.1 kHz sample rates. Care must be taken when synchronization of isochronous data is not possible, i.e. when the PLL has to be used but an exact frequency match cannot be found. The I2S should be master on the LM49370 so that the data source can support appropriate SRC as required. This method should only be used with data being read on demand to eliminate sample rate mismatch problems. Where a system clock exists at an integer multiple of the required ADC or DAC clock rate it is preferable to use this rather than the PLL. The LM49370 is designed to work in 8, 12, 16, 24, 48 kHz modes from a 12 MHz clock and 8 kHz modes from a 13 MHz clock without the use of the PLL. This saves power and reduces clock jitter which can affect SNR. PLL Loop Filter LM49370 requires a second or third order loop filter on PLL_FILT pin. LM49370 demoboard schematic has the recommended values to use for the second order filter. Please refer to the LM49370 demoboard schematic. 22 Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 ADC_1 CONFIGURATION REGISTER This register is used to control the LM49370's audio ADC. Table 12. ADC_1 (0x06h) Bits Field 0 MIC_SELECT If set the microphone preamp output is added to the ADC input signal. 1 CPI_SELECT If set the cell phone input is added to the ADC input signal. 2 LEFT_SELECT 3 RIGHT_SELECT 5:4 ADC_SAMPLE _RATE Description If set the left stereo bus is added to the ADC input signal. If set the right stereo bus is added to the ADC input signal. This programs the closest expected sample rate of the mono ADC, which is a variable required by the AGC algorithm whenever the AGC is in use. This does not set the sample rate of the mono ADC. ADC_SAMPLE_RATE 7:6 HPF_MODE Sample Rate 002 8 kHz 012 12 kHz 102 16 kHz 112 24 kHz This sets the HPF of the ADC HPF-MODE HPF Response 002 No HPF 012 FS = 8 kHz, -0.5 dB @ 300 Hz, Notch @ 55 Hz FS = 12 kHz, -0.5 dB @ 450 Hz, Notch @ 82 Hz FS = 16 kHz, -0.5 dB @ 600 Hz, Notch @ 110 Hz 102 FS = 8 kHz, -0.5 dB @ 150 Hz, Notch @ 27 Hz FS = 12 kHz, -0.5 dB @ 225 Hz, Notch @ 41 Hz FS = 16 kHz, -0.5 dB @ 300 Hz, Notch @ 55 Hz 112 No HPF ADC_2 CONFIGURATION REGISTER This register is used to control the LM49370's audio ADC. Table 13. ADC_2 (0x07h) Bit s Field 0 ADC_MODE 1 ADC_MUTE Description This sets the oversampling ratio of the ADC MODE ADC OSR 0 125fs 1 128fs If set, the analog inputs to the ADC are muted. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 23 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com Table 13. ADC_2 (0x07h) (continued) Bit s Field 4:2 AGC_FRAME_TIME 6:5 7 (1) ADC_CLK NGZXDD Description This sets the frame time to be used by the AGC algorithm. In a given frame, the AGC's peak detector determines the peak value of the incoming microphone audio signal and compares this value to the target value of the AGC defined by AGC_TARGET (bits [3:1] of register (0x08h)) in order to adjust the microphone preamplifier's gain accordingly. AGC_FRAME_TIME basically sets the sample rate of the AGC to adjust for a wide variety of speech patterns. (1) AGC_FRAME_TIME Time (ms) 0002 96 0012 128 0102 192 0112 256 1002 384 1012 512 1102 768 1112 1000 This selects the clock to be used by the audio ADC system. ADC_CLK Source 002 MCLK 012 PLL_OUTPUT 102 I2S_CLK_IN 112 PCM_CLK_IN If set, the noise gate will not wait for a zero crossing before mute/unmuting. This bit should be set if the ADC's HPF is disabled and if there is a large DC or low frequency component at the ADC input. NGZXDD Result 0 Noise Gate operates on ZXD events 1 Noise Gate operates on frame boundaries Refer to the AGC Overview for further detail. AGC_1 CONFIGURATION REGISTER This register is used to control the LM49370's Automatic Gain Control. (2) Table 14. AGC_1 (0x08h) Bit s Field 0 AGC_ENABLE 3:1 AGC_TARGET 4 (2) 24 NOISE_GATE_ON Description If set, the AGC controls the analog microphone preamplifier gain into the system. This feature is useful for microphone signals that are routed to the ADC. This programs the target level of the AGC. This will depend on the expected transients and desired headroom. Refer to AGC_TIGHT (bit 7 of 0x09h) for more detail. AGC_TARGET Target Level 0002 -6 dB 0012 -8 dB 0102 -10 dB 0112 -12 dB 1002 -14 dB 1012 -16 dB 1102 -18 dB 1112 -20 dB If set, signals below the noise gate threshold are muted. The noise gate is only activated after a set period of signal absence. See the AGC Overview. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 Table 14. AGC_1 (0x08h) (continued) Bit s Field 7:5 NOISE_ GATE_ THRES Description This field sets the expected background noise level relative to the peak signal level. The sole presence of signals below this level will not result in an AGC gain change of the input and will be gated from the ADC output if the NOISE_GATE_ON is set. This level must be set even if the noise gate is not in use as it is required by the AGC algorithm. NOISE_GATE_THRES Level 0002 -72 dB 0012 -66 dB 0102 -60 dB 0112 -54 dB 1002 -48 dB 1012 -42 dB 1102 -36 dB 1112 -30 dB AGC_2 CONFIGURATION REGISTER This register is used to control the LM49370's Automatic Gain Control. Table 15. AGC_2 (0x09h) Bits Field 3:0 AGC_MAX_GAIN 6:4 AGC_DECAY Description This programs the maximum gain that the AGC algorithm can apply to the microphone preamplifier. AGC_MAX_GAIN Max Preamplifier Gain 00002 6 dB 00012 8 dB 00102 10 dB 00112 12 dB 01002 to 11002 14 dB to 30 dB 11012 32 dB 11102 34 dB 11112 36 dB This programs the speed at which the AGC will increase gains if it detects the input level is a quiet signal. AGC_DECAY Step Time (ms) 0002 32 0012 64 0102 128 0112 256 1002 512 1012 1024 1102 2048 1112 4096 Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 25 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com Table 15. AGC_2 (0x09h) (continued) Bits Field 7 AGC_TIGHT AGC_TIGHT = 0 Description If set, the AGC algorithm controls the microphone preamplifier more exactly. AGC_TARGET Min Level Max Level 0002 -6 dB -3 dB 0012 -8 dB -4 dB 0102 -10 dB -5 dB 0112 -12 dB -6 dB 1002 -14 dB -7 dB 1012 -16 dB -8 dB 1102 -18 dB -9 dB 1112 -20 dB -10 dB 0002 -6 dB -3 dB 0012 -8 dB -5 dB 0102 -10 dB -7 dB 0112 -12 dB -9 dB 1002 -14 dB -11 dB 1012 -16 dB -13 dB 1102 -18 dB -15 dB 1112 -20 dB -17 dB AGC_TIGHT = 1 (1) (1) The AGC can be used to control the analog path of the microphone to the output stages or to optimize the microphone path for recording on the ADC. When the analog path is used this bit should be set to ensure the target is tightly adhered to. If the ADC is the only destination of the microphone or the desired analog mixer level is line level then AGC_TIGHT should be cleared, allowing greater dynamic rage of the recorded signal. For further details see the AGC Overview. AGC_3 CONFIGURATION REGISTER This register is used to control the LM49370's Automatic Gain Control. (2) Table 16. AGC_3 (0x0Ah) Bits Field 4:0 AGC_HOLDTIME (2) 26 Description This programs the amount of delay before the AGC algorithm begins to adjust the gain of the microphone preamplifier. AGC_HOLDTIME No. of speech segments 000002 0 000012 1 000102 2 000112 3 001002 to 111002 4 to 28 111012 29 111102 30 111112 31 See the AGC Overview. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 Table 16. AGC_3 (0x0Ah) (continued) Bits Field 7:5 AGC_ATTACK Description This programs the speed at which the AGC will reduce gains if it detects the input level is too large. AGC_ATTACK Step Time (ms) 0002 32 0012 64 0102 128 0112 256 1002 512 1012 1024 1102 2048 1112 4096 AGC OVERVIEW The Automatic Gain Control (AGC) system can be used to optimize the dynamic range of the ADC for voice data when the level of the source is unknown. A target level for the output is set so that any transients on the input won't clip during normal operation. The AGC circuit then compares the output of the ADC to this level and increases or decreases the gain of the microphone preamplifier to compensate. If the audio from the microphone is to be output digitally through the ADC then the full dynamic range of the ADC can be used automatically. If the output is through the analog mixer then the ADC is used to monitor the microphone level. In this case, the analog dynamic range is less important than the absolute level, so AGC_TIGHT should be set to tie transients closely to the target level. To ensure that the system doesn't reduce the quality of the speech by constantly modulating the microphone preamplifier gain, the ADC output is passed through an envelope detector. This frames the output of the ADC into time segments roughly equal to the phonemes found in speech (AGC_FRAME_TIME). To calculate this, the circuit must also know the sample rate of the data from the ADC (ADC_SAMPLERATE). If after a programmable number of these segments (AGC_HOLDTIME), the level is consistently below target, the gain will be increased at a programmable rate (AGC_DECAY). If the signal ever exceeds the target level (AGC_TARGET) then the gain of the microphone is reduced immediately at a programmable rate (AGC_ATTACK). This is demonstrated below: (1) Decay hold time, (2) Slow Decay, (3) Quick Attack (2) (3) (1) target level peak detection and ADC output attack decay microphone gain 12 dB 12 dB 14 dB signal below target 10 dB signal above target Figure 15. AGC Operation Example The signal in the above example starts with a small analog input which, after the hold time has timed out, triggers a rise in the gain [(1) (2)]. After some time the real analog input increases and it reaches the threshold for a gain reduction which decreases the gain at a faster rate [(2) (3)] to allow the elimination of typical popping noises. Only ADC outputs that are considered signal (rather than noise) are used to adjust the microphone preamplifier gain. The signal to noise ratio of the expected input signal is set by NOISE_GATE_THRESHOLD. In some situations it is preferable to remove audio considered to be consisting solely of background noise from the audio output; for example conference calls. This can be done by setting NOISE_GATE_ON. This does not affect the performance of the AGC algorithm. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 27 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com The AGC algorithm should not be used where very large background noise is present. If the type of input data, application and microphone is known then the AGC will typically not be required for good performance, it is intended for use with inputs with a large dynamic range or unknown nominal level. When setting NOISE_GATE_THRESHOLD be aware that in some mobile phone scenarios the ADC SNR will be dictated by the microphone performance rather than the ADC or the signal. Gain changes to the microphone are performed on zero crossings. To eliminate DC offsets, wind noise, and pop sounds from the output of the ADC, the ADC's HPF should always be enabled. MIC_1 CONFIGURATION REGISTER This register is used to control the microphone configuration. Table 17. MIC_1 (0x0Bh) Bits Field 3:0 PREAMP_GAIN Description This programs the gain applied to the microphone preamplifier if the AGC is not in use. PREAMP_GAIN Gain 00002 6 dB 00012 8 dB 00102 10 dB 00112 12 dB 01002 to 11002 14 dB to 30 dB 11012 32 dB 11102 34 dB 11112 36 dB 4 MIC_MUTE 5 INT_SE_DIFF If set, the internal microphone is assumed to be single ended and the negative connection is connected to the ADC common mode point internally. This allows a single-ended internal microphone to be used. 6 INT_EXT If set, the single ended external microphone is used and the negative microphone input is grounded internally, otherwise internal microphone operation is assumed. (1) (1) If set, the microphone preamplifier is muted. On changing INT_EXT from internal to external note that the dc blocking cap will not be charged so some time should be taken (300ms for a 1F cap) between the detection of an external headset and the switching of the output stages and ADC to that input to allow the DC points on either side of this cap to stabilize. This can be accomplished by deselecting the microphone input from the audio outputs and ADC until the DC points stabilize. An active MIC path to CPOUT or the ADC may result in the microphone DC blocking caps causing audio pops under the following situations:1) Switching between internal and external microphone operation while in chip modes '10' or '11'.2) Toggling in and out of powerdown/standby modes.3) Toggling between chip modes '10' and '11' whenever external microphone operation is selected.4) The insertion/removal of a headset while in chip modes '10' or '11' whenever external microphone operation is selected. To avoid these potential pop issues, it is recommended to deselect the microphone input from CPOUT and ADC until the DC points stabilize. MIC_2 CONFIGURATION REGISTER This register is used to control the microphone configuration. Table 18. MIC_2 (0x0Ch) Bits Field 0 OCL_ VCM_ VOLTAGE 28 Description This selects the voltage used as virtual ground (HP_VMID pin) in OCL mode. This will depend on the available supply and the power output requirements of the headphone amplifiers. OCL_VCM_VOLTAGE Voltage 0 1.2V 1 1.5V Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 Table 18. MIC_2 (0x0Ch) (continued) Bits Field Description 2:1 MIC_ BIAS_ VOLTAGE This selects the voltage as a reference to the internal and external microphones. Only one bias pin is driven at once depending on the INT_EXT bit setting found in the MIC_1 (0x0Bh) register. MIC_BIAS_VOLTAGE should be set to '11' only if A_VDD > 3.4V. In OCL mode, MIC_BIAS_VOLTAGE = '00' (EXT_BIAS = 2.0V) should not be used to generate the EXT_BIAS supply for a cellular headset external microphone. Please refer to Table 19 for more detail. 3 BUTTON_TYPE 5:4 BUTTON_ DEBOUNCE_ TIME MIC_BIAS_VOLTAGE EXT_BIAS/INT_BIAS 002 2.0V 012 2.5V 102 2.8V 112 3.3V If set, the LM49370 assumes that the button (if used) in the headset is in series (series push button) with the microphone, opening the circuit when pressed. The default is for the button to be in parallel (parallel push button), shorting out the microphone when pressed. This sets the time used for debouncing the pushing of the button on a headset with a parallel push button. BUTTON_DEBOUNCE_TIME Time (ms) 002 0 012 8 102 16 112 32 In OCL mode there is a trade-off between the external microphone supply voltage (EXT_MIC_BIAS OCL_VCM_ VOLTAGE) and the maximum output power possible from the headphones. A lower OCL_VCM_VOLTAGE gives a higher microphone supply voltage but a lower maximum output power from the headphone amplifiers due to the lower OCL_VCM_VOLTAGE - A_VSS. Table 19. External MIC Supply Voltages in OCL Mode Available A_VDD Recommended EXT_MIC_BIAS Supply to Microphone OCL_VCM_VOLT = 1.5V OCL_VCM_VOLT = 1.2V > 3.4V 3.3V 1.8V 2.1V 2.9V to 3.4V 2.8V 1.3V 1.6V 2.8V to 2.9V 2.5V 1.0V 1.3V 2.7V to 2.8V 2.5V - 1.3V Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 29 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com SIDETONE ATTENUATION REGISTER This register is used to control the analog sidetone attenuation. (1) Table 20. SIDETONE (0x0Dh) Bits Field 3:0 SIDETONE_ ATTEN (1) Description This programs the attenuation applied to the microphone preamp output to produce a sidetone signal. SIDETONE_ATTEN Attenuation 00002 -Inf 00012 -30 dB 00102 -27 dB 00112 -24 dB 01002 -21 dB 01012 to 10102 -18 dB to -3 dB 10112 to 11112 0 dB An active SIDETONE path to an audio output may result in the microphone DC blocking caps causing audio pops under the following situations:1) Switching between internal and external microphone operation while in chip modes '10' or '11'.2) Toggling in and out of powerdown/standby modes.3) Toggling between chip modes '10' and '11' whenever external microphone operation is selected.4) The insertion/removal of a headset while in chip modes '10' or '11' whenever external microphone operation is selected.To avoid potential pop noises, it is recommended to set SIDETONE_ATTEN to '0000' until DC points have stabilized whenever the SIDETONE path is used. CP_INPUT CONFIGURATION REGISTER This register is used to control the differential cell phone input. Table 21. CP_INPUT (0x0Eh) Bits Field 4:0 CPI_LEVEL 5 30 CPI_MUTE Description This programs the gain/attenuation applied to the cell phone input. CPI_LEVEL Level 000002 -34.5 dB 000012 -33 dB 000102 -31.5 dB 000112 -30 dB 00100 to 111002 -28.5 dB to +7.5 dB 111012 +9 dB 111102 +10.5 dB 111112 +12 dB If set, the CPI input is muted at source. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 AUX_LEFT CONFIGURATION REGISTER This register is used to control the left aux analog input. Table 22. AUX_LEFT (0x0Fh) Bits Field 4:0 AUX_ LEFT_ LEVEL 5 AUX_ LEFT_ BOOST 6 AUX_L_MUTE 7 AUX_OR_DAC_L (1) Description This programs the gain/attenuation applied to the AUX LEFT analog input to the mixer. (1) AUX_LEFT_LEVEL Level (With Boost) Level (Without Boost) 000002 -34.5 dB -46.5 dB 000012 -33 dB -45 dB 000102 -31.5 dB -43.5 dB 000112 -30 dB -42 dB 00100 to 111002 -28.5 dB to +7.5 dB -40.5 dB to -4.5 dB 111012 +9 dB -3 dB 111102 +10.5 dB -1.5 dB 111112 +12 dB 0 dB If set, the gain of the AUX_LEFT input to the mixer is increased by 12 dB (see above). If set, the AUX LEFT input is muted. If set, the AUX LEFT input is passed to the mixer, the default is for the DAC LEFT output to be passed to the mixer. The recommended mixer level is 1V RMS. The auxiliary analog inputs can be boosted by 12 dB if enough headroom is available. Clipping may occur if the analog power supply is insufficient to cater for the required gain. AUX_RIGHT CONFIGURATION REGISTER This register is used to control the right aux analog input. Table 23. AUX_RIGHT (0x10h) Bits Field 4:0 AUX_ RIGHT_ LEVEL 5 (1) Description This programs the gain/attenuation applied to the AUX RIGHT analog input to the mixer. (1) AUX_RIGHT_LEVEL Level (With Boost) Level (Without Boost) 000002 -34.5 dB -46.5 dB 000012 -33 dB -45 dB 000102 -31.5 dB -43.5 dB 000112 -30 dB -42 dB 00100 to 111002 -28.5 dB to +7.5 dB -40.5 dB to -4.5 dB 111012 +9 dB -3 dB 111102 +10.5 dB -1.5 dB 111112 +12 dB 0 dB AUX_ RIGHT_BOOST If set, the gain of the AUX_RIGHT input to the mixer is increased by 12 dB (see above). 6 AUX_R_MUTE If set, the AUX RIGHT input is muted. 7 AUX_OR_DAC_R If set, the AUX RIGHT input is passed to the mixer, the default is for the DAC RIGHT output to be passed to the mixer. The recommended mixer level is 1V RMS. The auxiliary analog inputs can be boosted by 12 dB if enough headroom is available. Clipping may occur if the analog power supply is insufficient to cater for the required gain. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 31 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com DAC CONFIGURATION REGISTER This register is used to control the DAC levels to the mixer. Table 24. DAC (0x11h) Bits Field 4:0 DAC_LEVEL Description This programs the gain/attenuation applied to the DAC input to the mixer. (1) DAC_LEVEL Level (With Boost) Level (Without Boost) 000002 -34.5 dB -46.5 dB 000012 -33 dB -45 dB 000102 -31.5 dB -43.5 dB 000112 -30 dB -42 dB 00100 to 111002 -28.5 dB to +7.5 dB -40.5 dB to -4.5 dB 111012 +9 dB -3 dB 111102 +10.5 dB -1.5 dB 111112 +12 dB 0 dB 5 DAC_BOOST 6 DAC_MUTE If set, the stereo DAC input is muted on the next zero crossing. 7 USE_AUX_ LEVELS If set, the gain of the DAC inputs is controlled by the AUX_LEFT and AUX_RIGHT registers, allowing a stereo balance to be applied. (1) If set, the gain of the DAC inputs to the mixer is increased by 12dB (see above). The output from the DAC is 1V RMS for a full scale digital input. This can be boosted by 12 dB if enough headroom is available. Clipping may occur if the analog power supply is insufficient to cater for the required gain. CP_OUTPUT CONFIGURATION REGISTER This register is used to control the differential cell phone output. (2) Table 25. CP_OUTPUT (0x12h) Bit s Field 0 MIC_SELECT 1 RIGHT_SELECT 2 LEFT_SELECT 3 CPO_MUTE 4 MIC_NOISE_GAT E (2) Description If set, the microphone channel of the mixer is added to the CP_OUT output signal. If set, the right channel of the mixer is added to the CP_OUT output signal. If set, the left channel of the mixer is added to the CP_OUT output signal. If set, the CPOUT output is muted. If this is set and NOISE_GATE_ON (register 0x08h) is enabled, the MIC to CPO path will be gated if the signal is determined to be noise by the AGC (that is, if the signal is below the set noise threshold). The gain of cell phone output amplifier is 0 dB. AUX_OUTPUT CONFIGURATION REGISTER This register is used to control the differential auxiliary output. (1) Table 26. AUX_OUTPUT (0x13h) Bits Field 0 CPI_SELECT 1 RIGHT_SELECT 2 LEFT_SELECT 3 AUX_MUTE (1) 32 Description If set, the cell phone input channel of the mixer is added to the AUX_OUT output signal. If set, the right channel of the mixer is added to the AUX_OUT output signal. If set, the left channel of the mixer is added to the AUX_OUT output signal. If set, the AUX_OUT output is muted. The gain of the auxiliary output amplifier is 0 dB. If a second (external) loudspeaker amplifier is to be used its gain should be set to 12 dB to match the onboard loudspeaker amplifier gain. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 LS_OUTPUT CONFIGURATION REGISTER This register is used to control the loudspeaker output. (1) Table 27. LS_OUTPUT (0x14h) Bits Field 0 CPI_SELECT 1 RIGHT_SELECT 2 LEFT_SELECT 3 LS_MUTE 4 RSVD (1) Description If set, the cell phone input channel of the mixer is added to the loudspeaker output signal. If set, the right channel of the mixer is added to the loudspeaker output signal. If set, the left channel of the mixer is added to the loudspeaker output signal. If set, the loudspeaker output is muted. Reserved. The gain of the loudspeaker output amplifier is 12 dB. HP_OUTPUT CONFIGURATION REGISTER This register is used to control the stereo headphone output. (1) Table 28. HP_OUTPUT (0x15h) Bits Field 0 SIDETONE_SELECT 1 CPI_SELECT 2 RIGHT_SELECT If set, the right channel of the mixer is added to the headphone output. If the STEREO bit (0x00h) is set, the right channel is added to the right headphone output signal only. If the STEREO bit (0x00h) is cleared, it is added to both the right and left headphone output signals. 3 LEFT_SELECT If set, the left channel of the mixer is added to the headphone output. If the STEREO bit (0x00h) is set, the left channel is added to the left headphone output signal only. If the STEREO bit (0x00h) is cleared, it is added to both the right and left headphone output signals. 4 HP_MUTE 5 STEREO 6 OCL (1) Description If set, the sidetone channel of the mixer is added to both of the headphone output signals. If set, the cell phone input channel of the mixer is added to both of the headphone output signals. If set, the headphone output is muted. If set, the mixers assume that the signals on the left and right internal busses are highly correlated and when these signals are combined their levels are reduced by 6dB to allow enough headroom for them to be summed. If set, the part is placed in OCL (Output Capacitor Less) mode. The gain of the headphone output amplifier is -6 dB for the cell phone input channel and sidetone channel of the mixer. When the STEREO bit (0x00h) is set, headphone output amplifier gain is -6 dB for the left and right channel. When the STEREO bit (0x00h) is cleared, the headphone output amplifier gain is -12 dB for the left and right channel (to allow enough headroom for adding them and routing them to both headphone amplifiers). EP_OUTPUT CONFIGURATION REGISTER This register is used to control the mono earpiece output. (1) Table 29. EP_OUTPUT (0x16h) Bits Field 0 SIDETONE_SELECT (1) 1 CPI_SELECT 2 RIGHT_SELECT 3 LEFT_SELECT 4 EP_MUTE Description If set, the sidetone channel of the mixer is added to the earpiece output signal. If set, the cell phone input channel of the mixer is added to the earpiece output signal. If set, the right channel of the mixer is added to the earpiece output signal. If set, the left channel of the mixer is added to the earpiece output signal. If set, the earpiece output is muted. The gain of the earpiece output amplifier is 6 dB. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 33 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com DETECT CONFIGURATION REGISTER This register is used to control the headset detection system. Table 30. DETECT (0x17h) Bits Field 0 DET_INT If set, an IRQ is raised when a change is detected in the headset status. Clearing this bit will clear an IRQ that has been triggered by the headset detect. Description 1 BTN_INT If set, an IRQ is raised when the headset button is pressed. Clearing this bit will clear an IRQ that has been triggered by a button event. 2 TEMP_INT If set, an IRQ is raised during a temperature event. The LM49370 will still automatically cycle the class AB power amplifiers off if the internal temperature is too high. This bit should not be set whenever the class D amplifier is turned on. Clearing this bit will clear an IRQ that has been triggered by a temperature event. 6:3 HS_ DBNC_TIME This sets the time used for debouncing the analog signals from the detection inputs used to sense the insertion/removal of a headset. HS_DBNC_TIME Time (ms) 00002 0 00012 8 00102 16 00112 32 01002 48 01012 64 01102 96 01112 128 10002 192 10012 256 10102 384 10112 512 11002 768 11012 1024 11102 1536 11112 2048 HEADSET DETECT OVERVIEW The LM49370 has built in monitors to automatically detect headset insertion or removal. The detection scheme can differentiate between mono, stereo, mono-cellular and stereo-cellular headsets. Upon detection of headset insertion or removal, the LM49370 updates read-only bit 0 - headset absence/presence, bit 1- mono/stereo headset and bit 2 - headset without mic / with mic, of the STATUS register (0x18h). Headset insertion/removal and headset type can also be detected in standby mode; this consumes no analog supply current when the headset is absent. The LM49370 can be programmed to raise an interrupt (set the IRQ pin high) when headset insert/removal is sensed by setting bit 0 of DETECT (0x17h). When headset detection is enabled in active mode and a headset is not detected, the HPL_OUT and HPR_OUT amplifiers will be disabled (switched off for capless mode and muted for AC-coupled mode) and the EXT_BIAS pin will be disconnected from the MIC_BIAS amplifier, irrespective of control register settings. 34 Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 The LM49370 also has the capability to detect button press, when a button is present on the headset microphone. Both parallel button-type (in parallel with the headset microphone, default value) and series buttontype (in series with the headset microphone) can be detected; the button type used needs to be defined in bit 3 of MIC_2 (0x0Ch). Button press can also be detected in stand-by mode; this consumes 10 A of analog supply current for a series type push button and 100 A for a parallel type push button. Upon button press, the LM49370 updates bit 3 of STATUS (0x18h). In active OCL mode, with internal microphone selected (INT_EXT = 0; (reg 0x0Bh)), if a parallel pushbutton headset is inserted into the system, INT_EXT must be set high before BTN (bit 3 of STATUS (0x18h)) can be read. The LM49370 can also be programmed to raise an interrupt on the IRQ pin when button press is sensed by setting bit 1 of DETECT (0x17h). The LM49370 provides debounce programmability for headset and button detect. Debounce programmability can be used to reject glitches generated, and hence avoid false detection, while inserting/removing a headset or pressing a button. Headset insert/removal debounce time is defined by HS_DBNC_TIME; bits 6:3 of DETECT (0x17h). Parallel button press debounce time is defined by BTN_DBNC_TIME; bits 5:4 of MIC_2 (0x0Ch). Note that since the first effect of a series button press (microphone disconnected) is indistinguishable from headset removal, the debounce time for series button press in defined by HS_DBNC_TIME. Headset and push button detection can be enabled by setting CHIP_MODE 0; bit 0 of BASIC (0x00h). For reliable headset / push button detection all following bits should be defined before enabling the headset detection system: 1. 2. 3. 4. the the the the OCL-bit (AC-Coupled / Capless headphone interface (bit 6 of HP_OUTPUT (0x15h)) headset insert/removal debounce settings (bit 6:3 of DETECT (0x17h)) BTN_TYPE-bit (Parallel / Series push button type (bit 3 of MIC_2 (0x0Ch)) parallel push button debounce settings (bit 5:4 of MIC_2 (0x0Ch)) Figure 16 shows terminal connections and jack configuration for various headsets. Care should be taken to avoid any DC path from the MIC_DET pin to ground when a headset is not inserted. s s s g g g 47: s 47: s m m Stereo + Cellular g m s s Cellular g m s s s g g Stereo g s s s m m Stereo + Cellular g m s s Cellular g m s Figure 16. Headset Configurations Supported by the LM49370 Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 35 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com The wiring of the headset jack to the LM49370 will depend on the intended mode of the headphone amplifier: EXT_MIC_BIAS 3.3/2.8/2.5V MIC_DET 2.2 k: EXT_MIC s s 1 PF LM49370 g Stereo HP_L Cellular g m Stereo + Cellular g m s HP_R s s HP_VMID_FB m = mic s = speaker g = virtual ground HP_VMID 1.2/1.5V Connection for OCL Mode (DC-Coupled) Headset Detection EXT_MIC_BIAS 2.0/2.5V MIC_DET 2.2 k: s s 1 PF s 47 PF s 47 PF LM49370 EXT_MIC g Stereo HP_L Cellular g m Stereo + Cellular g m HP_R s HP_VMID_FB m = mic s = speaker 1 k: g = ground (A_VSS) HP_VMID A_VDD/2 1 k: Connection for Non-OCL Mode (AC-Coupled) Headset Detection Figure 17. Connection of Headset Jack to LM49370 Depends on the Mode of the Headphone Amplifier. In non-OCL mode, two 1k resistors are optional and not needed if chip is active without headset event detection in Basic Register (0x00h) bits 1:0. If chip is active with headset event detection, these two resistors set an internal threshold voltage for a comparator that produces the headphone detect pulse. The value of these should be 1k with tolerance of 10% or better. STATUS REGISTER This register is used to report the status of the device. Table 31. STATUS (0x18h) (1) (2) Bits Field 0 HEADSET This field is high when headset presence is detected (only valid if the detection system is enabled). (1) 1 STEREO_ HEADSET This field is high when a headset with stereo speakers is detected (only valid if the detection system is enabled). (1) 2 MIC (1) (2) 36 Description This field is high when a headset with a microphone is detected (only valid if the detection system is enabled). (1) The detection IRQ is cleared when this register has been written to. This field is cleared whenever the STATUS (0x18h) register has been written to. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 Table 31. STATUS (0x18h)(1)(2) (continued) Bits Field 3 BTN This field is high when the button on the headset is pressed (only valid if the detection system is enabled). IRQ is cleared when the button has been released and this register has been written to. (2) Description 4 TEMP If this field is high then a temperature event has occurred (write to this register to clear IRQ). This field will stay high even when the IRQ is cleared so long as the event occurs. This bit is only valid whenever the loudspeaker amplifier is turned off. (2) 5 GPIN1 When GPIO_SEL is set to a readable configuration a digital input on GPIO1 can be read back here. 6 GPIN2 When GPIO_SEL is set to a readable configuration, a digital input on the relevant GPIO can be read back here. 3D CONFIGURATION REGISTER This register is used to control the configuration of the 3D circuit. Table 32. 3D (0x19h) Bits Field Description 0 3D_ENB Setting this bit enables the 3D effect. When cleared to zero, the 3D effect is disabled and the 3D module then passes the I2S left and right channel inputs to the DAC unchanged. The stereo AUX inputs are unaffected by the 3D module. 1 3D_TYPE This bit selects between type 1 and type 2 3D sound effect. Clearing this bit to zero selects type 1 effect and setting it to one selects type 2. Type1: Rout = Ri-G*Lout3d, Lout = Li-G*Rout3d Type2: Rout = -Ri-G*Lout3d, Lout = Li+G*Rout3d where, Ri = Right I2S channel input Li = Left I2S channel input G = 3D gain level (Mix ratio) Rout3d = Ri filtered through a high-pass filter with a corner frequency controlled by FREQ Lout3d = Li filtered through a high-pass filter with a corner frequency controlled by FREQ 3:2 LEVEL This programs the level of 3D effect that is applied. LEVEL 5:4 FREQ 002 25% 012 37.5% 102 50% 112 75% This programs the HPF rolloff (-3dB) frequency of the 3D effect. FREQ 002 0Hz 012 300Hz 102 600Hz 112 900Hz 6 ATTENUATE Clearing this bit to zero maintains the level of the left and right input channels at the output. Setting this bit to one attenuates the output level by 50%. This may be appropriate for high level audio inputs when type 2 3D effect is used. Type 2 effect involves adding the same polarity of left and right inputs to give the final outputs. Type 2 effect has the potential for creating a clipping condition, however this bit offers an alternative to clipping. 7 CUST_COMP If set, the DAC compensation filter may be programmed by the user through registers (0x20h) to( 0x25h). Otherwise, the defaults are used. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 37 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com I2S PORT MODE CONFIGURATION REGISTER This register is used to control the audio data interfaces. Table 33. I2S Mode (0x1Ah) Bit s Field 0 I2S_OUT_ENB 1 I2S_IN_ENB 2 I2S_MODE Description If set, the I2S output bus is enabled. If cleared, the I2S output will be tristate and all RX clocks will be gated. If set, the I2S input is enabled. If this bit cleared, the I2S input is ignored and all TX clocks gated. This programs the format of the I2S interface. Definition 3 I2S_STEREO_REVERSE 0 Normal 1 Left Justified If set, the left and right channels are reversed. Operation 4 I2S_WS_MS 6:5 I2S_WS_GEN_MODE 0 Normal 1 Reversed If set, I2S_WS generation is enabled and is Master. If cleared, I2S_WS acts as slave. This programs the I2S word length. Bits/Word 7 I2S_WORD_ORDER 002 16 012 25 102 32 112 -- This bit alters the RX phasing of left and right channels. If this bit is cleared: right then left. If this bit is set: left then right. ADC_CLOCK I2S CLKGEN DAC_CLOCK I2S_CLK_OUT I2S_CLK_IN I2S_CLK I2S WSGEN I2S_WS_OUT I2S_WS I2S_WS_IN Figure 18. I2S Audio Port CLOCK/SYNC Options I2S PORT CLOCK CONFIGURATION REGISTER This register is used to control the audio data interfaces. Table 34. I2S Clock (0x1Bh) Bit s Field Description 0 I2S_CLOCK_MS If set, then I2S clock generation is enabled and is Master. If this bit is cleared, then the I2S clock is driven by the device slave. 1 I2S_CLOCK_SOURCE 38 This selects the source of the clock to be used by the I2S clock generator. I2S_CLOCK_SOURCE Clock is source from 0 DAC (from R divider) 1 ADC (from Q divider) Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 Table 34. I2S Clock (0x1Bh) (continued) Bit s Field 5:2 I2S_CLOCK_GEN_MODE 7:6 Description This programs a clock divider that divides the clock defined by I2S_CLOCK_SOURCE. This divided clock is used to generate I2S_CLK in Master mode. (1) PCM_SYNC_WIDTH Value Divide By 00002 1 00012 2 00102 4 00112 6 01002 8 01012 10 01102 16 Ratio 01112 20 -- 10002 2.5 2/5 10012 3 1/3 10102 3.90625 32/125 10112 5 25/125 11002 7.8125 16/125 11012 -- -- 11102 -- -- 11112 -- -- This programs the width of the PCM sync signal. Generated SYNC Looks like: (1) 002 1 bit (Used for Short PCM Modes) 012 4 bits (Used for Long PCM Modes) 102 8 bits (Used for Long PCM Modes) 112 15 bits (Used for Long PCM Modes) Should not be set if the bits/word is less than 16. For DAC_MODE = '00', '10', '11', DAC_CLOCK is the clock at the output of the R divider. For DAC_MODE = '01', DAC_CLOCK is a divided by two version of the clock at the output of the R divider. DIGITAL AUDIO DATA FORMATS I2S master mode can only be used when the DAC is enabled unless the FORCE_RQ bit is set. PCM Master mode can only be used when the ADC is enabled, unless the FORCE_RQ bit is set. If the PCM receiver interface is operated in slave mode the clock and sync should be enabled at the same time because the PCM receiver uses the first PCM frame to calculate the PCM interface format. This format can not be changed unless a soft reset is issued. Operating the LM49370 in master mode eliminates the risk of sample rate mismatch between the data converters and the audio interfaces. In slave mode, the PCM and I2S receivers only record the 1st 16 and 18 bits of the serial words respectively. The I2S and PCM formats are as followed: I2S_CLK I2S_WS I2S_SDO/ I2S_SDI 0 24 23 22 21 3 2 1 0 24 23 22 Left Word 21 3 2 1 0 24 Right Word Figure 19. I2S Serial Data Format (Default Mode) Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 39 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com I2S_CLK I2S_WS I2S_SDO/ I2S_SDI 0 24 23 22 21 3 2 1 0 24 23 22 21 Left Word 3 2 1 0 24 12 11 10 9 Right Word 2 Figure 20. I S Serial Data Format (Left Justified) PCM_CLK PCM_SYNC PCM_SDO/ PCM_SDI 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 Short frame sync mode (PCM_SYNC_WIDTH = '00') Long frame sync mode (PCM_SYNC_WIDTH = '11') Figure 21. PCM Serial Data Format (16 bit Slave Example) PCM PORT MODE CONFIGURATION REGISTER This register is used to control the audio data interfaces. Table 35. PCM MODE (0x1Ch) Bits Field 0 PCM_OUT_ENB 1 PCM_IN_ENB 3 PCM_CLOCK_SOURCE 4 PCM_SYNC_MS 5 PCM_SDO_LSB_HZ 6 PCM_COMPAND 7 (1) 40 PCM_ALAW_LAW Description If set, the PCM output bus is enabled. If this bit is cleared, thr PCM output will be tristate and all RX clocks will be gated. If set, the PCM input is enabled. If this bit is cleared, the PCM input is ignored and TX clocks are generated. DAC or ADC Clock 0 = DAC, 1 = ADC (1) If set, PCM_SYNC generation is enabled and is driven by the device (Master). If set, when the PCM port has run out of bits to transmit, it will tristate the SDO output. If set, the data sent to the PCM port is companded and the PCM data received by the PCM receiver is treated as companded data. If PCM_ COMPAND is set, then the data across the PCM interface to the DAC and from the ADC is companded as follows: PCM_ALAW_LAW Commanding Type 0 -LAW 1 A-Law For DAC_MODE = '00', '10', '11', DAC_CLOCK is the clock at the output of the R divider. For DAC_MODE = '01', DAC_CLOCK is a divided by two version of the clock at the output of the R divider. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 ADC_CLOCK DAC_CLOCK PCM CLKGEN PCM_CLK_OUT PCM_CLK_IN PCM_CLOCK PCM SYNCGEN PCM_SYNC_OUT PCM_SYNC PCM_SYNC_IN Figure 22. PCM Audio Port CLOCK/SYNC Options PCM PORT CLOCK CONFIGURATION REGISTER This register is used to control the configuration of audio data interfaces. Table 36. PCM Clock (0x1Dh) Bits Field Description 3:0 PCM_CLOCK_ GEN_MODE This programs a clock divider that divides the clock defined by PCM_CLOCK_SOURCE reg(0x1Ch). The divided clock is used to generate PCM_CLK in Master mode. (1) 6:4 PCM_SYNC_MODE Value Divide By 00002 1 00012 2 00102 4 00112 6 01002 8 01012 10 01102 16 01112 20 -- 10002 2.5 2/5 10012 3 1/3 10102 3.90625 32/125 10112 5 25/125 11002 7.8125 16/125 11012 -- -- 11102 -- -- 11112 -- -- This programs a clock divider that divides PCM_CLK. The divided clock is used to generate PCM_SYNC. Valve (1) Ratio Divide By 0002 8 0012 16 0102 25 0112 32 1002 64 1012 128 1102 -- 1112 -- For DAC_MODE = '00', '10', '11', DAC_CLOCK is the clock at the output of the R divider. For DAC_MODE = '01', DAC_CLOCK is a divided by two version of the clock at the output of the R divider. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 41 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com SRC CONFIGURATION REGISTER (2) This register is used to control the configuration of the Digital Routing interfaces. Table 37. Bridges (0x1Eh) Bits Field 0 PCM_TX_SEL Description This controls the data sent to the PCM transmitter. PCM_TX_SEL 2:1 I2S_TX_SEL Source 0 ADC 1 MONO SUM Circuit This controls the data sent to the I2S transmitter. I2S_TX_SEL 4:3 DAC_INPUT_SEL Source 002 ADC 012 PCM Receiver 102 DAC Interpolator (oversampled) 112 Disabled This controls the data sent to the DAC. DAC_INPUT_SEL 5 7:6 (2) 42 MONO_SUM_SEL MONO_SUM_MODE Source 002 I2S Receiver (In stereo) 012 PCM Receiver (Dual Mono) 102 ADC 112 Disabled This controls the data sent to the Stereo to Mono Converter MONO_SUM_SEL Source 0 DAC Interpolated Output 1 I2S Receiver Output This controls the operation of the Stereo to Mono Converter. MONO_SUM_ MODE Operation 002 (Left + Right)/2 012 Left 102 Right 112 (Left + Right)/2 Please refer to the Application Note AN-1591 (SNAA039) for the detailed discussion on how to use the I2S to PCM Bridge. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 ADC_SRC_MODE PCM_TX_SEL IIR Dec PCM_SDI CIC PCM PCM_SDO Mono ADC Sample & Hold STEREO/ MONO 2 I S_TX_SEL MONO_SUM_MODE MONO_SUM_SEL 2 @FSI DAC_TX_SEL Automatic Handshaking DSDM 2 2 I S_SDI I S I S_SDO FIR Interp Stereo DAC DAC_SRC_MODE Figure 23. I2S to PCM Bridge GPIO CONFIGURATION REGISTER This register is used to control the GPIOs and to control the digital signal routing when using the ADC and DAC to perform sample rate conversion. Table 38. GPIO Control (0x1Fh) Bits Field 2:0 GPIO_1_SEL 5:3 GPIO_2_SEL Description This configures the GPIO_1 pin. GPIO_1_SEL Does What? 0002 Disable Direction HiZ 0012 SPI_SDO Output 0102 Output 0 Output 0112 Output 1 Output 1002 Read Input 1012 Class D Enable Output 1102 AUX Enable Output 1112 Dig_Mic_Data Input GPIO_2_SEL Does What? Direction 0002 Disable HiZ 0012 SPI_SDO Output 0102 Output 0 Output 0112 Output 1 Output 1002 Read Input 1012 Class D Enable Output 1102 Dig_Mic L Clock Output 1112 Dig_Mic R Clock Output This configures the GPIO_2 pin. 6 ADC_SRC_MODE If set, the ADC analog is disabled and the digital is enabled, using the resampler input. 7 DAC_SRC_MODE This does not have to be set to use DAC in SRC mode, but should be set if the user wishes to disable the DAC analog to save power. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 43 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com DAC PATH COMPENSATION FIR CONFIGURATION REGISTERS To allow for compensation of roll off in the DAC and analog filter sections an FIR compensation filter is applied to the DAC input data at the original sample rate. Since the DAC can operate at different over sampling ratios the FIR compensation filter is programmable. By default the filter applies approx 2dB of compensation at 20kHz. 5 taps is sufficient to allow passband equalization and ripple cancellation to around +/0.01dB. The filter can also be used for precise digital gain and simple tone controls although a DSP or CPU should be used for more powerful tone control if required. As the FIR filter must always be phase linear, the coefficients are symmetrical. Coefficients C0, C1, and C2 are programmable, C3 is equal to C1 and C4 is equal to C0. The maximum power of this filter must not exceed that of the examples given below: -1 -1 Z C0 -1 Z C1 -1 Z C2 Z C3 C4 Figure 24. FIR Consumption Filter Taps Sample Rate DAC_MODE C0 C1 C2 C3 C4 48kHz 00 334 -2291 26984 -2291 343 48kHz 01 61 -371 25699 -371 61 For DAC_MODE = '00 and '01', the defaults should be sufficient; but for DAC_MODE = '10' and '11', care should be taken to ensure the widest bandwidth is available without requiring such a large attenuation at DC that inband noise becomes audible. Table 39. Compensation Filter C0 LSBs (0x20h) Bits Field 7:0 C0_LSB Description Bits 7:0 of C0[15:0] Table 40. Compensation Filter C0 MSBs (0x21h) Bits Field 7:0 C0_MSB Description Bits 15:8 of C0[15:0] Table 41. Compensation Filter C1 LSBs (0x22h) Bits Field 7:0 C1_LSB Bits Field 7:0 C1_MSB Description Bits 7:0 of C1[15:0] Table 42. Compensation Filter C1 MSBs (0x23h) Description Bits 15:8 of C1[15:0] Table 43. Compensation Filter C2 LSBs (0x24h) Bits Field 7:0 C2_LSB 44 Description Bits 7:0 of C2[15:0] Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 Table 44. Compensation Filter C2 MSBs (0x25h) Bits Field 7:0 C2_MSB Description Bits 15:8 of C2[15:0] Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 45 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com Typical Performance Characteristics (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. +3 Stereo DAC Frequency Response fS = 8kHz Stereo DAC Frequency Response Zoom fS = 8kHz +0.5 +0.4 +0.3 MAGNITUDE (dB) MAGNITUDE (dB) +2 +1 +0 -1 +0.2 +0.1 +0 -0.1 -0.2 -0.3 -2 -0.4 -3 20 50 100 200 500 1k 2k -0.5 20 5k 10k 20k FREQUENCY (Hz) 5k 10k 20k FREQUENCY (Hz) Figure 25. +3 50 100 200 500 1k 2k Figure 26. Stereo DAC Frequency Response fS = 16kHz Stereo DAC Frequency Response Zoom fS = 16kHz +0.5 +0.4 +0.3 MAGNITUDE (dB) MAGNITUDE (dB) +2 +1 +0 -1 +0.2 +0.1 +0 -0.1 -0.2 -0.3 -2 -0.4 -3 20 50 100 200 500 1k 2k -0.5 20 5k 10k 20k FREQUENCY (Hz) 5k 10k 20k FREQUENCY (Hz) Figure 27. +3 50 100 200 500 1k 2k Figure 28. Stereo DAC Frequency Response fS = 24kHz Stereo DAC Frequency Response Zoom fS = 24kHz +0.5 +0.4 +0.3 MAGNITUDE (dB) MAGNITUDE (dB) +2 +1 +0 -1 +0.2 +0.1 +0 -0.1 -0.2 -0.3 -2 -0.4 -3 20 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) Figure 29. 46 -0.5 20 Figure 30. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. +3 Stereo DAC Frequency Response fS = 32kHz Stereo DAC Frequency Response Zoom fS = 32kHz +0.5 +0.4 +0.3 MAGNITUDE (dB) MAGNITUDE (dB) +2 +1 +0 -1 +0.2 +0.1 +0 -0.1 -0.2 -0.3 -2 -0.4 -3 20 50 100 200 500 1k 2k -0.5 20 5k 10k 20k FREQUENCY (Hz) 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) Figure 31. Figure 32. Stereo DAC Frequency Response fS = 48kHz Stereo DAC Frequency Response Zoom fS = 48kHz +0.5 +3 +0.4 +0.3 MAGNITUDE (dB) MAGNITUDE (dB) +2 +1 +0 -1 +0.2 +0.1 +0 -0.1 -0.2 -0.3 -2 -0.4 -3 20 50 100 200 500 1k 2k 5k 10k 20k 30k -0.5 20 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) FREQUENCY (Hz) Figure 33. Figure 34. THD+N vs Stereo DAC Input Voltage (0dB DAC, AUXOUT) Stereo DAC Crosstalk (0dB, DAC, HP SE, 32) 10 5 2 THD+N (%) 1 0.5 0.2 0.1 0.05 0.02 0.01 1m 2m 5m 10m 20m 50m 100m200m 500m 1 2 I S INPUT VOLTAGE (FFS) Figure 35. Figure 36. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 47 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. MONO ADC Frequency Response Zoom fS = 8kHz, 6dB MIC +0.5 +0 +0.4 -10 +0.3 -20 MAGNITUDE (dB) MAGNITUDE (dB) +10 MONO ADC Frequency Response fS = 8kHz, 6dB MIC -30 -40 -50 -60 -70 +0.2 +0.1 +0 -0.1 -0.2 -80 -0.3 -90 -0.4 -100 20 50 100 200 500 1k 2k -0.5 20 5k 10k 20k FREQUENCY (Hz) Figure 37. Figure 38. MONO ADC Frequency Response fS = 8kHz, 36dB MIC MONO ADC Frequency Response Zoom fS = 8kHz, 36dB MIC +0.5 +0 +0.4 -10 +0.3 -20 -30 -40 -50 -60 -70 +0.2 +0.1 +0 -0.1 -0.2 -80 -0.3 -90 -0.4 -100 20 50 100 200 500 1k 2k -0.5 20 5k 10k 20k FREQUENCY (Hz) 5k 10k 20k Figure 39. Figure 40. MONO ADC Frequency Response fS = 16kHz, 6dB MIC MONO ADC Frequency Response Zoom fS = 16kHz, 6dB MIC +0.5 +0 +0.4 -10 +0.3 -20 -30 -40 -50 -60 -70 +0.2 +0.1 +0 -0.1 -0.2 -80 -0.3 -90 -0.4 -100 20 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) -0.5 20 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) Figure 41. 48 50 100 200 500 1k 2k FREQUENCY (Hz) MAGNITUDE (dB) MAGNITUDE (dB) +10 5k 10k 20k FREQUENCY (Hz) MAGNITUDE (dB) MAGNITUDE (dB) +10 50 100 200 500 1k 2k Figure 42. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. MONO ADC Frequency Response Zoom fS = 16kHz, 36dB MIC +0.5 +0 +0.4 -10 +0.3 -20 MAGNITUDE (dB) MAGNITUDE (dB) +10 MONO ADC Frequency Response fS = 16kHz, 36dB MIC -30 -40 -50 -60 -70 +0.2 +0.1 +0 -0.1 -0.2 -80 -0.3 -90 -0.4 -100 20 50 100 200 500 1k 2k -0.5 20 5k 10k 20k FREQUENCY (Hz) Figure 43. Figure 44. MONO ADC Frequency Response fS = 24kHz, 6dB MIC MONO ADC Frequency Response Zoom fS = 24kHz, 6dB MIC +0.5 +0 +0.4 -10 +0.3 -20 -30 -40 -50 -60 -70 +0.2 +0.1 +0 -0.1 -0.2 -80 -0.3 -90 -0.4 -100 20 50 100 200 500 1k 2k -0.5 20 5k 10k 20k FREQUENCY (Hz) 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) Figure 45. Figure 46. MONO ADC Frequency Response fS = 24kHz, 36dB MIC MONO ADC Frequency Response Zoom fS = 24kHz, 36dB MIC +0.5 +0 +0.4 -10 +0.3 -20 MAGNITUDE (dB) MAGNITUDE (dB) +10 5k 10k 20k FREQUENCY (Hz) MAGNITUDE (dB) MAGNITUDE (dB) +10 50 100 200 500 1k 2k -30 -40 -50 -60 -70 +0.2 +0.1 +0 -0.1 -0.2 -80 -0.3 -90 -0.4 -100 20 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) -0.5 20 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) Figure 47. Figure 48. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 49 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. MONO ADC Frequency Response Zoom fS = 32kHz, 6dB MIC +0.5 +0 +0.4 -10 +0.3 -20 +0.2 MAGNITUDE (dB) MAGNITUDE (dB) +10 MONO ADC Frequency Response fS = 32kHz, 6dB MIC -30 -40 -50 -60 -70 +0.1 +0 -0.1 -0.2 -80 -0.3 -90 -0.4 -100 20 50 100 200 500 1k 2k -0.5 20 5k 10k 20k 50 100 200 500 1k 2k FREQUENCY (Hz) Figure 49. Figure 50. MONO ADC Frequency Response fS = 32kHz, 36dB MIC MONO ADC Frequency Response Zoom fS = 32kHz, 36dB MIC +0.5 +0 +0.4 -10 +0.3 -20 +0.2 MAGNITUDE (dB) MAGNITUDE (dB) +10 -30 -40 -50 -60 -70 +0.1 +0 -0.1 -0.2 -80 -0.3 -90 -0.4 -100 20 50 100 200 500 1k 2k -0.5 20 5k 10k 20k 50 100 200 500 1k 2k FREQUENCY (Hz) Figure 51. Figure 52. MONO ADC HPF Frequency Response fS = 8kHz, 36dB MIC (from left to right: HPF_MODE '00', '10', '01') MONO ADC HPF Frequency Response fS = 16kHz, 36dB MIC (from left to right: HPF_MODE '00', '10', '01') +10 +0 +0 -10 -10 -20 -20 MAGNITUDE (dB) MAGNITUDE (dB) 5k 10k 20k FREQUENCY (Hz) +10 -30 -40 -50 -60 -70 -80 -30 -40 -50 -60 -70 -80 -90 -90 -100 20 -100 20 50 100 200 500 1k 2k FREQUENCY (Hz) 50 100 200 500 1k 2k FREQUENCY (Hz) Figure 53. 50 5k 10k 20k FREQUENCY (Hz) Figure 54. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. MONO ADC HPF Frequency Response fS = 24kHz, 36dB MIC (from left to right: HPF_MODE '00', '10', '01') MONO ADC HPF Frequency Response fS = 32kHz, 36dB MIC (from left to right: HPF_MODE '00', '10', '01') +10 +0 +0 -10 -10 -20 -20 MAGNITUDE (dB) MAGNITUDE (dB) +10 -30 -40 -50 -60 -70 -80 -30 -40 -50 -60 -70 -80 -90 -90 -100 20 -100 20 50 100 200 500 1k 2k FREQUENCY (Hz) 10 5 200 500 1k Figure 55. Figure 56. MONO ADC THD+N vs MIC Input Voltage (fS = 8kHz, 6dB MIC) MONO ADC THD+N vs MIC Input Voltage (fS = 8kHz, 36dB MIC) 10 5 2k 2 1 0.5 THD+N (%) 0.5 THD+N (%) 100 FREQUENCY (Hz) 2 1 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 200m 500m 1 0.002 0.001 100P 200P 500P 1m 2m 5m 10m 20m 40m MIC INPUT VOLTAGE (Vrms) MIC INPUT VOLTAGE (Vrms) 0 Figure 57. Figure 58. MONO ADC PSRR vs Frequency AVDD = 3.3V, 6dB MIC MONO ADC PSRR vs Frequency AVDD = 5V, 6dB MIC 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) 50 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) 20 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) Figure 59. Figure 60. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 51 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. MONO ADC PSRR vs Frequency AVDD = 3.3V, 36dB MIC 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) 0 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k MONO ADC PSRR vs Frequency AVDD = 5V, 36dB MIC 5k 10k 20k 20 FREQUENCY (Hz) AUXOUT PSRR vs Frequency AVDD = 3.3V, 0dB AUX (AUX inputs terminated) AUXOUT PSRR vs Frequency AVDD = 5V, 0dB AUX (AUX inputs terminated) 0 0 -10 -10 -20 -20 -30 -30 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 63. Figure 64. AUXOUT PSRR vs Frequency AVDD = 3.3V, 0dB CPI (CPI inputs terminated) AUXOUT PSRR vs Frequency AVDD = 5V, 0dB CPI (CPI inputs terminated) 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) 5k 10k 20k Figure 62. 20 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 52 500 1k 2k Figure 61. PSRR (dB) PSRR (dB) FREQUENCY (Hz) 50 100 200 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 65. Figure 66. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. 0 0 -10 -10 -20 -20 -30 -30 -40 -50 -60 -50 -60 -70 -80 -80 -90 -90 -100 -100 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 67. Figure 68. CPOUT PSRR vs Frequency AVDD = 3.3V, 0dB AUX (AUX inputs terminated) CPOUT PSRR vs Frequency AVDD = 5V, 0dB AUX (AUX inputs terminated) 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) -40 -70 20 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 69. Figure 70. CPOUT PSRR vs Frequency AVDD = 3.3V, 0dB DAC (DAC inputs selected) CPOUT PSRR vs Frequency AVDD = 5V, 0dB DAC (DAC inputs selected) 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) AUXOUT PSRR vs Frequency AVDD = 5V, 0dB DAC (DAC inputs selected) PSRR (dB) PSRR (dB) AUXOUT PSRR vs Frequency AVDD = 3.3V, 0dB DAC (DAC inputs selected) -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 71. Figure 72. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 53 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. 0 0 -10 -10 -20 -20 -30 -30 -40 -50 -60 -60 -70 -80 -90 -90 -100 -100 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 73. Figure 74. Earpiece PSRR vs Frequency AVDD = 3.3V, 0dB CPI (CPI input terminated) Earpiece PSRR vs Frequency AVDD = 5V, 0dB CPI (CPI input terminated) 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) -50 -80 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 75. Figure 76. Earpiece PSRR vs Frequency AVDD = 3.3V, 0dB DAC (DAC input selected) Earpiece PSRR vs Frequency AVDD = 5V, 0dB DAC (DAC input selected) 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) -40 -70 20 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 54 Earpiece PSRR vs Frequency AVDD = 5V, 0dB AUX (AUX inputs terminated) PSRR (dB) PSRR (dB) Earpiece PSRR vs Frequency AVDD = 3.3V, 0dB AUX (AUX inputs terminated) 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 77. Figure 78. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. Headphone PSRR vs Frequency AVDD = 5V, 0dB AUX, OCL 1.2V (AUX inputs terminated) 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) Headphone PSRR vs Frequency AVDD = 3.3V, 0dB AUX, OCL 1.2V (AUX inputs terminated) -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) Figure 79. Figure 80. Headphone PSRR vs Frequency AVDD = 3.3V, 0dB CPI, OCL 1.2V (CPI input terminated) Headphone PSRR vs Frequency AVDD = 5V, 0dB CPI, OCL 1.2V (CPI input terminated) 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) FREQUENCY (Hz) -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) Figure 81. Figure 82. Headphone PSRR vs Frequency AVDD = 3.3V, 0dB ADC, OCL 1.2V (DAC input selected) Headphone PSRR vs Frequency AVDD = 5V, 0dB ADC, OCL 1.2V (DAC input selected) 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) FREQUENCY (Hz) -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 83. Figure 84. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 55 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. 0 0 -10 -10 -20 -20 -30 -30 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) Figure 85. Figure 86. Headphone PSRR vs Frequency AVDD = 3.3V, 0dB CPI, OCL 1.5V (CPI input terminated) Headphone PSRR vs Frequency AVDD = 5V, 0dB CPI, OCL 1.5V (CPI input terminated) 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) FREQUENCY (Hz) -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) Figure 87. Figure 88. Headphone PSRR vs Frequency AVDD = 3.3V, 0dB DAC, OCL 1.5V (DAC input selected) Headphone PSRR vs Frequency AVDD = 5V, 0dB DAC, OCL 1.5V (DAC input selected) 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) FREQUENCY (Hz) -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 56 Headphone PSRR vs Frequency AVDD = 5V, 0dB AUX, OCL 1.5V (AUX inputs terminated) PSRR (dB) PSRR (dB) Headphone PSRR vs Frequency AVDD = 3.3V, 0dB AUX, OCL 1.5V (AUX inputs terminated) 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 89. Figure 90. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. 0 0 -10 -10 -20 -20 -30 -30 -40 -50 -60 -50 -60 -70 -80 -80 -90 -90 -100 -100 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 91. Figure 92. Headphone PSRR vs Frequency AVDD = 3.3V, 0dB CPI, SE (CPI input terminated) Headphone PSRR vs Frequency AVDD = 5V, 0dB CPI, SE (CPI input terminated) 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) -40 -70 20 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 93. Figure 94. Headphone PSRR vs Frequency AVDD = 3.3V, 0dB DAC, SE (DAC input selected) Headphone PSRR vs Frequency AVDD = 5V, 0dB DAC, SE (DAC input selected) 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) Headphone PSRR vs Frequency AVDD = 5V, 0dB AUX, SE (AUX inputs terminated) PSRR (dB) PSRR (dB) Headphone PSRR vs Frequency AVDD = 3.3V, 0dB AUX, SE (AUX inputs terminated) -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 95. Figure 96. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 57 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. +0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 20 Loudspeaker PSRR vs Frequency AVDD = 5V, 0dB AUX (AUX inputs terminated) PSRR (dB) PSRR (dB) Loudspeaker PSRR vs Frequency AVDD = 3.3V, 0dB AUX (AUX inputs terminated) 50 100 200 500 1k 2k 5k 10k 20k +0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 20 Figure 98. Loudspeaker PSRR vs Frequency AVDD = 3.3V, 0dB CPI (CPI input terminated) Loudspeaker PSRR vs Frequency AVDD = 5V, 0dB CPI (CPI input terminated) +0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 50 100 200 500 1k 2k 5k 10k 20k +0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 20 FREQUENCY (Hz) 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) Figure 99. Figure 100. Loudspeaker PSRR vs Frequency AVDD = 3.3V, 0dB DAC (DAC input selected) Loudspeaker PSRR vs Frequency AVDD = 5V, 0dB DAC (DAC input selected) +0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 20 PSRR (dB) PSRR (dB) 5k 10k 20k Figure 97. 20 58 50 100 200 500 1k 2k FREQUENCY (Hz) PSRR (dB) PSRR (dB) FREQUENCY (Hz) 50 100 200 500 1k 2k 5k 10k 20k +0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 20 50 100 200 500 1k 2k FREQUENCY (Hz) FREQUENCY (Hz) Figure 101. Figure 102. Submit Documentation Feedback 5k 10k 20k Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. INT/EXT MICBIAS PSRR vs Frequency AVDD = 3.3V, MICBIAS = 2.0V -10 -20 -20 -30 -30 -40 -50 -60 -50 -60 -70 -80 -80 -90 -90 -100 -100 0 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 FREQUENCY (Hz) Figure 104. INT/EXT MICBIAS PSRR vs Frequency AVDD = 3.3V, MICBIAS = 2.5V INT/EXT MICBIAS PSRR vs Frequency AVDD = 5V, MICBIAS = 2.5V 0 -10 -20 -20 -30 -30 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 0 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 105. Figure 106. INT/EXT MICBIAS PSRR vs Frequency AVDD = 3.3V, MICBIAS = 2.8V INT/EXT MICBIAS PSRR vs Frequency AVDD = 5V, MICBIAS = 2.8V 0 -10 -20 -20 -30 -30 PSRR (dB) -10 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 20 5k 10k 20k 50k 100k Figure 103. -10 20 50 100 200 500 1k 2k FREQUENCY (Hz) PSRR (dB) PSRR (dB) -40 -70 20 PSRR (dB) 0 -10 PSRR (dB) PSRR (dB) 0 INT/EXT MICBIAS PSRR vs Frequency AVDD = 5V, MICBIAS = 2.0V 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 107. Figure 108. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 59 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. INT/EXT MICBIAS PSRR vs Frequency AVDD = 5V, MICBIAS = 3.3V 0 AUXOUT THD+N vs Frequency AVDD = 3.3V, 0dB, VOUT = 1VRMS, 5k 10 5 -10 2 1 -20 0.5 THD+N (%) PSRR (dB) -30 -40 -50 -60 0.2 0.1 0.05 0.02 0.01 0.005 -70 -80 -90 0.002 0.001 20 -100 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k Figure 110. AUXOUT THD+N vs Frequency AVDD = 5V, 0dB, VOUT = 1VRMS, 5k CPOUT THD+N vs Frequency AVDD = 3.3V, 0dB, VOUT = 1VRMS, 5k 10 5 10 5 2 1 2 1 0.5 0.5 THD+N (%) THD+N (%) Figure 109. 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 20 0.2 0.1 0.05 0.02 0.01 0.005 50 100 200 500 1k 2k 0.002 0.001 20 5k 10k 20k FREQUENCY (Hz) 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) Figure 111. Figure 112. CPOUT THD+N vs Frequency AVDD = 5V, 0dB, VOUT = 1VRMS, 5k Earpiece THD+N vs Frequency AVDD = 3.3V, 0dB, POUT = 500mW, 32 10 10 5 5 2 1 2 0.5 1 THD+N (%) THD+N (%) 5k 10k 20k FREQUENCY (Hz) FREQUENCY (Hz) 0.2 0.1 0.05 0.002 0.001 20 0.5 0.2 0.1 0.02 0.01 0.005 0.05 0.02 50 100 200 500 1k 2k 5k 10k 20k 0.01 20 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) FREQUENCY (Hz) Figure 113. 60 50 100 200 500 1k 2k Figure 114. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. Earpiece THD+N vs Frequency AVDD = 5V, 0dB, POUT = 50mW, 32 Headphone THD+N vs Frequency AVDD = 3.3V, OCL 1.5V, 0dB POUT = 7.5mW, 32 10 10 5 2 2 1 1 THD+N (%) THD+N (%) 5 0.5 0.2 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 20 0.01 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k FREQUENCY (Hz) Figure 115. Figure 116. Headphone THD+N vs Frequency AVDD = 5V, OCL 1.5V, 0dB POUT = 10mW, 32 Headphone THD+N vs Frequency AVDD = 3.3V, OCL 1.2V, 0dB POUT = 7.5mW, 32 10 5 5 2 2 THD + N (%) 1 0.5 0.2 0.1 1 0.5 0.2 0.1 0.05 0.05 0.02 0.02 0.01 20 50 100 200 500 1k 2k 0.01 20 5k 10k 20k FREQUENCY (Hz) 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) Figure 117. Figure 118. Headphone THD+N vs Frequency AVDD = 5V, OCL 1.2V, 0dB POUT = 10mW, 32 Headphone THD+N vs Frequency AVDD = 3.3V, SE, 0dB POUT = 7.5mW, 32 10 10 5 5 2 2 1 1 THD+N (%) THD+N (%) 50 100 200 500 1k 2k FREQUENCY (Hz) 10 THD+N (%) 0.5 0.5 0.2 0.5 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 20 0.01 20 50 100 200 500 1k 2k 5k 10k 20k 50 100 200 500 1k 2k FREQUENCY (Hz) FREQUENCY (Hz) Figure 119. Figure 120. 5k 10k 20k Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 61 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. 10 Headphone THD+N vs Frequency AVDD = 5V, SE, 0dB POUT = 10mW, 32 Loudspeaker THD+N vs Frequency AVDD = 3.3V, POUT = 400mW 15H+8+15H 10 5 2 2 1 1 0.5 THD+N (%) THD+N (%) 5 0.5 0.2 0.1 0.02 0.01 0.005 0.05 0.02 0.01 20 0.2 0.1 0.05 50 100 200 500 1k 2k 0.002 0.001 20 5k 10k 20k Figure 122. Loudspeaker THD+N vs Frequency AVDD = 5V, POUT = 400mW 15H+8+15H Earpiece THD+N vs Output Power AVDD = 3.3V, 0dB AUX fOUT = 1kHz, 16 10 5 10 5 2 1 2 1 0.5 THD+N (%) THD+N (%) 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 20 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 200m 500m 1 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) OUTPUT POWER (W) Figure 123. Figure 124. Earpiece THD+N vs Output Power AVDD = 5V, 0dB AUX fOUT = 1kHz, 16 Earpiece THD+N vs Output Power AVDD = 3.3V, 0dB AUX fOUT = 1kHz, 32 10 5 10 5 2 1 2 1 0.5 THD+N (%) 0.5 THD+N (%) 5k 10k 20k Figure 121. 0.5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 200m 500m 1 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 200m 500m 1 OUTPUT POWER (W) OUTPUT POWER (W) Figure 125. 62 50 100 200 500 1k 2k FREQUENCY (Hz) FREQUENCY (Hz) Figure 126. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. Earpiece THD+N vs Output Power AVDD = 5V, 0dB AUX fOUT = 1kHz, 32 Earpiece THD+N vs Output Power AVDD = 3.3V, 0dB CPI fOUT = 1kHz, 16 10 5 10 5 2 1 2 1 0.5 THD+N (%) THD+N (%) 0.5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 200m 500m 1 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 200m 500m 1 OUTPUT POWER (W) OUTPUT POWER (W) Figure 127. Figure 128. Earpiece THD+N vs Output Power AVDD = 5V, 0dB CPI fOUT = 1kHz, 16 Earpiece THD+N vs Output Power AVDD = 3.3V, 0dB CPI fOUT = 1kHz, 32 10 5 10 5 2 1 2 1 0.5 THD+N (%) THD+N (%) 0.5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 200m 500m 1 0.002 0.001 1m 2m OUTPUT POWER (W) Figure 129. Figure 130. Earpiece THD+N vs Output Power AVDD = 5V, 0dB CPI fOUT = 1kHz, 32 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 0dB DAC fOUT = 1kHz, 16 10 5 10 5 2 1 2 1 0.5 THD+N (%) 0.5 THD+N (%) 5m 10m 20m 50m 100m 200m OUTPUT POWER (W) 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 200m 500m 1 0.002 0.001 1m OUTPUT POWER (W) 2m 5m 10m 20m 50m 100m OUTPUT POWER (W) Figure 131. Figure 132. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 63 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 0dB DAC fOUT = 1kHz, 16 10 5 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 0dB DAC fOUT = 1kHz, 32 10 5 2 1 0.5 THD+N (%) THD+N (%) 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 2m 5m 10m 20m 50m 100m OUTPUT POWER (W) OUTPUT POWER (W) Figure 133. Figure 134. Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 0dB DAC fOUT = 1kHz, 32 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 12dB DAC fOUT = 1kHz, 16 10 5 10 5 2 1 0.5 THD+N (%) THD+N (%) 2 1 0.5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 2m 5m 10m 20m 50m 100m OUTPUT POWER (W) OUTPUT POWER (W) Figure 135. Figure 136. Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 12dB DAC fOUT = 1kHz, 16 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 12dB DAC fOUT = 1kHz, 32 10 5 10 5 2 1 0.5 THD+N (%) THD+N (%) 2 1 0.5 64 0.2 0.1 0.05 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 2m 5m 10m 20m OUTPUT POWER (W) OUTPUT POWER (W) Figure 137. Figure 138. Submit Documentation Feedback 50m 100m Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 12dB DAC fOUT = 1kHz, 32 10 5 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 0dB DAC fOUT = 1kHz, 16 10 5 2 1 0.5 THD+N (%) THD+N (%) 2 1 0.5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 2m 5m 10m 20m 50m 100m OUTPUT POWER (W) OUTPUT POWER (W) Figure 139. Figure 140. Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 0dB DAC fOUT = 1kHz, 16 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 0dB DAC fOUT = 1kHz, 32 10 5 10 5 2 1 0.5 THD+N (%) THD+N (%) 2 1 0.5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 2m 5m 10m 20m 50m 100m OUTPUT POWER (W) OUTPUT POWER (W) Figure 141. Figure 142. Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 0dB DAC fOUT = 1kHz, 32 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 12dB DAC fOUT = 1kHz, 16 10 5 10 5 2 1 0.5 THD+N (%) THD+N (%) 2 1 0.5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 2m 5m 10m 20m OUTPUT POWER (W) OUTPUT POWER (W) Figure 143. Figure 144. 50m 100m Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 65 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 12dB DAC fOUT = 1kHz, 16 10 5 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 12dB DAC fOUT = 1kHz, 32 10 5 2 1 0.5 THD+N (%) THD+N (%) 2 1 0.5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 5m 10m 20m 50m 100m OUTPUT POWER (W) Figure 145. Figure 146. Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 12dB DAC fOUT = 1kHz, 32 Headphone THD+N vs Output Power AVDD = 3.3V, SE, 0dB DAC fOUT = 1kHz, 16 10 5 10 5 2 1 0.5 THD+N (%) THD+N (%) 2 1 0.5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 2m 5m 10m 20m 50m 100m OUTPUT POWER (W) Figure 147. Figure 148. Headphone THD+N vs Output Power AVDD = 5V, SE, 0dB DAC fOUT = 1kHz, 16 Headphone THD+N vs Output Power AVDD = 3.3V, SE, 0dB DAC fOUT = 1kHz, 32 10 5 2 1 0.5 2 1 THD+N (%) 0.5 THD+N (%) 5m 10m 20m 50m 100m 200m OUTPUT POWER (W) 10 5 66 2m OUTPUT POWER (W) 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 2m 0.002 0.001 1m 5m 10m 20m 50m 100m 200m 2m 5m 10m 20m OUTPUT POWER (W) OUTPUT POWER (W) Figure 149. Figure 150. Submit Documentation Feedback 50m 100m Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. Headphone THD+N vs Output Power AVDD = 5V, SE, 0dB DAC fOUT = 1kHz, 32 Headphone THD+N vs Output Power AVDD = 3.3V, SE, 12dB DAC fOUT = 1kHz, 16 10 5 10 5 2 1 0.5 THD+N (%) THD+N (%) 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 2m 5m 10m 20m 50m 100m 5m 10m 20m 50m 100m 200m OUTPUT POWER (W) OUTPUT POWER (W) Figure 151. Figure 152. Headphone THD+N vs Output Power AVDD = 5V, SE, 12dB DAC fOUT = 1kHz, 16 Headphone THD+N vs Output Power AVDD = 3.3V, SE, 12dB DAC fOUT = 1kHz, 32 10 5 10 5 2 1 0.5 2 1 THD+N (%) THD+N (%) 0.5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 2m 0.002 0.001 1m 5m 10m 20m 50m 100m 200m 2m 5m 10m 20m 50m 100m OUTPUT POWER (W) OUTPUT POWER (W) Figure 153. Figure 154. Headphone THD+N vs Output Power AVDD = 5V, SE, 12dB DAC fOUT = 1kHz, 32 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 0dB AUX fOUT = 1kHz, 16 10 5 10 5 2 1 0.5 THD+N (%) 2 1 0.5 THD+N (%) 0.2 0.1 0.05 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 2m 5m 10m 20m OUTPUT POWER (W) OUTPUT POWER (W) Figure 155. Figure 156. 50m 100m Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 67 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 12dB AUX fOUT = 1kHz, 16 10 5 Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 0dB AUX fOUT = 1kHz, 16 10 5 2 1 0.5 THD+N (%) THD+N (%) 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 2m 5m 10m 20m 50m 100m OUTPUT POWER (W) OUTPUT POWER (W) Figure 157. Figure 158. Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 12dB AUX fOUT = 1kHz, 16 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 0dB AUX fOUT = 1kHz, 32 10 5 10 5 2 1 0.5 THD+N (%) THD+N (%) 2 1 0.5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 2m 5m 10m 20m 50m 100m OUTPUT POWER (W) OUTPUT POWER (W) Figure 159. Figure 160. Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 12dB AUX fOUT = 1kHz, 32 Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 0dB AUX fOUT = 1kHz, 32 10 5 10 5 2 1 0.5 THD+N (%) THD+N (%) 2 1 0.5 68 0.2 0.1 0.05 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 2m 5m 10m 20m OUTPUT POWER (W) OUTPUT POWER (W) Figure 161. Figure 162. Submit Documentation Feedback 50m 100m Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 12dB AUX fOUT = 1kHz, 32 10 5 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 0dB CPI fOUT = 1kHz, 16 10 5 2 1 0.5 THD+N (%) THD+N (%) 2 1 0.5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 2m 5m 10m 20m 50m 100m OUTPUT POWER (W) OUTPUT POWER (W) Figure 163. Figure 164. Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 0dB CPI fOUT = 1kHz, 16 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 0dB CPI fOUT = 1kHz, 32 10 5 10 5 2 1 0.5 THD+N (%) THD+N (%) 2 1 0.5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 2m 5m 10m 20m 50m 100m OUTPUT POWER (W) OUTPUT POWER (W) Figure 165. Figure 166. Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 0dB CPI fOUT = 1kHz, 32 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 0dB AUX fOUT = 1kHz, 16 10 5 10 5 2 1 0.5 THD+N (%) THD+N (%) 2 1 0.5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 2m 5m 10m 20m OUTPUT POWER (W) OUTPUT POWER (W) Figure 167. Figure 168. 50m 100m Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 69 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 12dB AUX fOUT = 1kHz, 16 10 5 Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 0dB AUX fOUT = 1kHz, 16 10 5 2 1 0.5 THD+N (%) THD+N (%) 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 2m 5m 10m 20m 50m 100m OUTPUT POWER (W) OUTPUT POWER (W) Figure 169. Figure 170. Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 12dB AUX fOUT = 1kHz, 16 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 0dB AUX fOUT = 1kHz, 32 10 5 10 5 2 1 0.5 THD+N (%) THD+N (%) 2 1 0.5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 2m 5m 10m 20m 50m 100m OUTPUT POWER (W) OUTPUT POWER (W) Figure 171. Figure 172. Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 12dB AUX fOUT = 1kHz, 32 Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 0dB AUX fOUT = 1kHz, 32 10 5 10 5 2 1 0.5 THD+N (%) THD+N (%) 2 1 0.5 70 0.2 0.1 0.05 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 2m 5m 10m 20m OUTPUT POWER (W) OUTPUT POWER (W) Figure 173. Figure 174. Submit Documentation Feedback 50m 100m Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 12dB AUX fOUT = 1kHz, 32 10 5 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 0dB CPI fOUT = 1kHz, 16 10 5 2 1 0.5 THD+N (%) THD+N (%) 2 1 0.5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 2m 5m 10m 20m 50m 100m OUTPUT POWER (W) OUTPUT POWER (W) Figure 175. Figure 176. Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 0dB CPI fOUT = 1kHz, 16 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 0dB CPI fOUT = 1kHz, 32 10 5 THD + N (%) THD+N (%) 2 1 0.5 10 5 0.2 0.1 0.05 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 2m OUTPUT POWER (W) 5m 10m 20m 50m 100m OUTPUT POWER (W) Figure 177. Figure 178. Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 0dB CPI fOUT = 1kHz, 32 Headphone THD+N vs Output Power AVDD = 3.3V, SE, 0dB AUX fOUT = 1kHz, 16 2 1 0.5 10 5 THD + N (%) THD + N (%) 10 5 0.2 0.1 0.05 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 2m 5m 10m 20m OUTPUT POWER (W) OUTPUT POWER (W) Figure 179. Figure 180. 50m 100m Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 71 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. Headphone THD+N vs Output Power AVDD = 5V, SE, 0dB AUX fOUT = 1kHz, 16 Headphone THD+N vs Output Power AVDD = 3.3V, SE, 0dB AUX fOUT = 1kHz, 32 10 5 10 5 2 1 0.5 THD+N (%) THD + N (%) 2 1 0.5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 2m OUTPUT POWER (W) Headphone THD+N vs Output Power AVDD = 5V, SE, 0dB AUX fOUT = 1kHz, 32 Headphone THD+N vs Output Power AVDD = 3.3V, SE, 0dB CPI fOUT = 1kHz, 16 10 5 2 1 0.5 THD+N (%) THD+N (%) 50m 100m Figure 182. 2 1 0.5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 2m 5m 10m 20m 50m 100m OUTPUT POWER (W) OUTPUT POWER (W) Figure 183. Figure 184. Headphone THD+N vs Output Power AVDD = 5V, SE, 0dB CPI fOUT = 1kHz, 16 Headphone THD+N vs Output Power AVDD = 3.3V, SE, 0dB CPI fOUT = 1kHz, 32 10 5 10 5 2 1 2 1 0.5 THD+N (%) 0.5 THD+N (%) 10m 20m Figure 181. 10 5 72 5m OUTPUT POWER (W) 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 2m 0.002 0.001 1m 2m 5m 10m 20m 50m 100m 200m 5m 10m 20m 50m 100m 200m OUTPUT POWER (W) OUTPUT POWER (W) Figure 185. Figure 186. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. Headphone THD+N vs Output Power AVDD = 5V, SE, 0dB CPI fOUT = 1kHz, 32 Loudspeaker THD+N vs Output Power AVDD = 3.3V, 0dB AUX fOUT = 1kHz, 15H+8+15H 10 5 2 1 2 1 0.5 0.5 THD+N (%) THD+N (%) 10 5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 2m 0.002 0.001 10m 20m 5m 10m 20m 50m 100m 200m 2 Figure 188. Loudspeaker THD+N vs Output Power AVDD = 4.2V, 0dB AUX fOUT = 1kHz, 15H+8+15H Loudspeaker THD+N vs Output Power AVDD = 5V, 0dB AUX fOUT = 1kHz, 15H+8+15H 10 5 2 1 2 1 0.5 0.5 THD+N (%) THD+N (%) 1 Figure 187. 10 5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 10m 20m 0.002 0.001 10m 20m 50m 100m 200m 500m 1 2 OUTPUT POWER (W) 50m 100m 200m 500m 1 2 OUTPUT POWER (W) Figure 189. Figure 190. Loudspeaker THD+N vs Output Power AVDD = 3.3V, 0dB CPI fOUT = 1kHz, 15H+8+15H Loudspeaker THD+N vs Output Power AVDD = 4.2V, 0dB CPI fOUT = 1kHz, 15H+8+15H 10 5 10 5 2 1 2 1 0.5 0.5 THD+N (%) THD+N (%) 50m 100m 200m 500m OUTPUT POWER (W) OUTPUT POWER (W) 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 10m 20m 0.2 0.1 0.05 0.02 0.01 0.005 50m 100m 200m 500m 1 2 OUTPUT POWER (W) 0.002 0.001 10m 20m 50m 100m 200m 500m 1 2 OUTPUT POWER (W) Figure 191. Figure 192. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 73 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. Loudspeaker THD+N vs Output Power AVDD = 5V, 0dB CPI fOUT = 1kHz, 15H+8+15H Loudspeaker THD+N vs Output Power AVDD = 3.3V, 0dB DAC fOUT = 1kHz, 15H+8+15H 10 5 2 1 2 1 0.5 0.5 THD+N (%) THD+N (%) 10 5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 10m 20m 0.002 0.001 10m 20m 50m 100m 200m 500m 1 2 OUTPUT POWER (W) Loudspeaker THD+N vs Output Power AVDD = 4.2V, 0dB DAC fOUT = 1kHz, 15H+8+15H Loudspeaker THD+N vs Output Power AVDD = 5V, 0dB DAC fOUT = 1kHz, 15H+8+15H 10 5 2 1 2 1 0.5 0.5 THD+N (%) THD+N (%) 2 Figure 194. 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 10m 20m 0.002 0.001 10m 20m 50m 100m 200m 500m 1 2 OUTPUT POWER (W) 50m 100m 200m 500m 1 2 OUTPUT POWER (W) Figure 195. Figure 196. AUXOUT THD+N vs Output Voltage AVDD = 3.3V, 0dB AUX fOUT = 1kHz, 5k AUXOUT THD+N vs Output Voltage AVDD = 5V, 0dB AUX fOUT = 1kHz, 5k 5 10 5 2 1 0.5 2 1 0.5 THD + N (%) 10 THD + N (%) 1 Figure 193. 10 5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 2m 5m10m 20m 50m 200m 1 100m 500m 0.002 0.001 1m 2m 5m10m 20m 50m 200m 1 100m 500m 2 3 OUTPUT VOLTAGE (VRMS) 2 3 OUTPUT VOLTAGE (VRMS) Figure 197. 74 50m 100m 200m 500m OUTPUT POWER (W) Figure 198. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. AUXOUT THD+N vs Output Voltage AVDD = 3.3V, 0dB CPI fOUT = 1kHz, 5k AUXOUT THD+N vs Output Voltage AVDD = 5V, 0dB CPI fOUT = 1kHz, 5k 5 10 5 2 1 0.5 2 1 0.5 THD + N (%) THD + N (%) 10 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 1m 2m 5m10m 20m 50m 200m 1 100m 500m 0.002 0.001 1m 2m 5m10m 20m 50m 200m 1 2 100m 500m 2 3 OUTPUT VOLTAGE (VRMS) OUTPUT VOLTAGE (VRMS) Figure 199. Figure 200. AUXOUT THD+N vs Output Voltage AVDD = 3.3V, 0dB DAC fOUT = 1kHz, 5k AUXOUT THD+N vs Output Voltage AVDD = 5V, 0dB DAC fOUT = 1kHz, 5k 10 5 10 5 2 1 0.5 THD + N (%) THD + N (%) 2 1 0.5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 0.002 0.001 500m 1 6m 10m 20m 50m 100m 200m 500m 1 6m10m 20m 50m100m 200m 2 3 OUTPUT VOLTAGE (VRMS) 2 4 OUTPUT VOLTAGE (VRMS) Figure 201. Figure 202. AUXOUT THD+N vs Output Voltage AVDD = 3.3V, 12dB DAC fOUT = 1kHz, 5k AUXOUT THD+N vs Output Voltage AVDD = 5V, 12dB DAC fOUT = 1kHz, 5k 10 5 10 5 2 1 0.5 2 1 0.5 THD + N (%) THD + N (%) 4 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 20m 0.2 0.1 0.05 0.02 0.01 0.005 50m 100m 200m 500m 1 2 3 OUTPUT VOLTAGE (VRMS) 0.002 0.001 20m 50m 100m 200m 500m 1 2 4 OUTPUT VOLTAGE (VRMS) Figure 203. Figure 204. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 75 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. CPOUT THD+N vs Output Voltage AVDD = 3.3V, 0dB AUX fOUT = 1kHz, 5k CPOUT THD+N vs Output Voltage AVDD = 5V, 0dB AUX fOUT = 1kHz, 5k 10 5 2 1 2 1 0.5 0.5 THD + N (%) THD + N (%) 10 5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.02 0.01 0.005 0.005 0.002 0.001 1m 2m 5m10m 20m 50m 200m 1 100m 500m 0.002 0.001 1m 2m 5m10m 20m 50m 200m 1 100m 500m 2 3 OUTPUT VOLTAGE (VRMS) OUTPUT VOLTAGE (VRMS) Figure 205. Figure 206. CPOUT THD+N vs Output Voltage AVDD = 3.3V, 0dB DAC fOUT = 1kHz, 5k CPOUT THD+N vs Output Voltage AVDD = 5V, 0dB DAC fOUT = 1kHz, 5k 10 5 10 5 2 1 0.5 2 1 0.5 THD+N (%) THD + N (%) 2 3 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 20m 0.002 0.001 50m 100m 200m 500m 1 6m 10m 20m 2 3 50m 100m 200m 500m 1 OUTPUT VOLTAGE (VRMS) OUTPUT VOLTAGE (VRMS) Figure 207. Figure 208. CPOUT THD+N vs Output Voltage AVDD = 3.3V, 6dB MIC fOUT = 1kHz, 5k CPOUT THD+N vs Output Voltage AVDD = 5V, 6dB MIC fOUT = 1kHz, 5k 10 5 2 2 1 0.5 1 0.5 THD+N (%) THD+N (%) 10 5 0.2 0.1 0.05 0.02 0.02 0.01 0.005 0.01 0.005 0.002 0.002 0.001 1m 5m 2m 20m 100m 500m 10m 1 50m 200m 0.001 1m 2 4 OUTPUT VOLTAGE (VRMS) 5m 2m 10m 20m 100m 500m 1 50m 200m 2 4 OUTPUT VOLTAGE (VRMS) Figure 209. 76 0.2 0.1 0.05 Figure 210. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. CPOUT THD+N vs Output Voltage AVDD = 3.3V, 12dB DAC fOUT = 1kHz, 5k CPOUT THD+N vs Output Voltage AVDD = 5V, 12dB DAC fOUT = 1kHz, 5k 10 5 10 5 2 1 2 1 0.5 THD+N (%) THD+N (%) 0.5 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 20m 0.002 0.001 20m 50m 100m 200m 500m 1 2 3 OUTPUT VOLTAGE (VRMS) 2 4 OUTPUT VOLTAGE (VRMS) Figure 211. Figure 212. CPOUT THD+N vs Output Voltage AVDD = 3.3V, 36dB MIC fOUT = 1kHz, 5k CPOUT THD+N vs Output Voltage AVDD = 5V, 36dB MIC fOUT = 1kHz, 5k 10 5 10 5 2 1 2 1 0.5 THD+N (%) THD+N (%) 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 10m 20m 50m100m 200m 500m 1 2 0.002 0.001 10m 20m 50m100m 200m 500m 1 4 OUTPUT VOLTAGE (VRMS) +0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 20 2 Figure 213. Figure 214. Headphone Crosstalk vs Frequency OCL 1.2V, 0dB AUX, 32 Headphone Crosstalk vs Frequency OCL 1.5V, 0dB AUX, 32 50 100 200 500 1k 2k 4 OUTPUT VOLTAGE (VRMS) CROSSTALK (dB) CROSSTALK (dB) 50m 100m 200m 500m 1 5k 10k 20k +0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 20 50 100 200 500 1k 2k FREQUENCY (Hz) FREQUENCY (Hz) Figure 215. Figure 216. 5k 10k 20k Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 77 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com Typical Performance Characteristics (continued) CROSSTALK (dB) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. +0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 20 Headphone Crosstalk vs Frequency SE, 0dB AUX, 32 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) Figure 217. 78 Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 APPLICATION NOTE MICROPHONE BIAS CONFIGURATIONS Schematic Considerations for MEMs Microphones The internal microphone bias of the LM49370 is provided through a two stage amplifier. Adding a capacitor larger than 100pF directly to this pin can cause instability. In many cases, when using MEMs microphones, a larger bypass capacitor is required on the INT_MIC_BIAS pin. To avoid oscillations and to keep the device stable, it is recommended to add a resistor (RB) greater than 10 in series with the capacitor (CB). Another option is to bias the MEMs microphone from the 1.8V supply used for D_VDD/IO_VDD. VDD A_VDD LS_VDD EXT_MIC_BIAS MIC_DET EXT_MIC RB INT_MIC_BIAS CB INT_MIC_POS INT_MIC_NEG Figure 218. Schematic for MEMs Microphones Schematic Considerations for ECM Microphones When using ECM microphones, refer to the configurations shown in Figure 219 to bias the microphones. VDD A_VDD LS_VDD EXT_MIC_BIAS MIC_DET EXT_MIC INT_MIC_BIAS INT_MIC_POS INT_MIC_NEG Figure 219. Schematic Option for ECM Microphones PCB LAYOUT CONSIDERATIONS A_VDD and LS_VDD Due to internal ESD diodes structure, for best performance, in the PCB board A_VDD and LS_VDD need to be tied to the same plane, but requires separate bypassing capacitors for each supply rail. Microphone Inputs When routing the differential microphone inputs the electrical length of the two traces should be well matched. The differential input pair can be routed in parallel on the same plane or the traces can overlap on two adjacent planes. It is important to surround these traces with a ground plane or trace to isolate the microphone inputs from the noise coupling from the class D amplifier. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 79 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com Class D Loudspeaker To minimize trace resistance and therefore maintain the highest possible output power, the power (LS_VDD) and class D output (LS-, LS+) traces should be as wide as possible. It is also essential to keep these same traces as short and well shielded as possible to decrease the amount of EMI radiation. Capacitors All supply bypass capacitors (for A_VDD, D_VDD. I/O VDD, and LS_VDD), and charge pump capacitors should be as close to the device as possible. Careful consideration should be taken with the ground connection of the analog supply (A_VDD) bypass cap, for proper performance it should be referenced to a low noise ground plane. The charge pump capacitors and traces connecting the capacitor to the device should be kept away from the input and output traces to avoid noise coupling issues. LM49370 Demonstration Board Schematic Diagram 80 Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 Demoboard PCB Layout Figure 220. Top Silkscreen Figure 221. Top Layer Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 81 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com Figure 222. Mid Layer 1 Figure 223. Mid Layer 2 82 Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 LM49370 www.ti.com SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 Figure 224. Bottom Layer Figure 225. Bottom Silkscreen Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 83 LM49370 SNAS356D - FEBRUARY 2007 - REVISED MARCH 2012 www.ti.com REVISION HISTORY 84 Rev Date 1.0 02/14/07 Initial release. Description 1.01 01/08/08 Fixed a typo on X3 value (Physical Dimension section) in the last page. 1.02 02/11/08 Text edits. 1.03 03/31/11 Input edits and added the section "PLL LOOP FILTER". 1.04 05/26/11 Added the Application Note section. 1.05 06/02/11 Edited (tweak) Figures 16 and 17 (schematics for MEM and ECM microphones) respectively. Also added the paragraph "In non-OCL mode, two 1kohm resistors are optional....... (under Figure 9, Connection of Headset.... ) 1.06 03/09/12 Replaced curve 20191721 (stereo DAC crosstalk, 32) with 201917k5 Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Links: LM49370 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Top-Side Markings (3) (4) LM49370RL/NOPB ACTIVE DSBGA YPG 49 250 Green (RoHS & no Sb/Br) SNAG Level-1-260C-UNLIM -40 to 85 GI3 LM49370RLX/NOPB ACTIVE DSBGA YPG 49 1000 Green (RoHS & no Sb/Br) SNAG Level-1-260C-UNLIM -40 to 85 GI3 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LM49370RL/NOPB DSBGA YPG 49 250 178.0 12.4 LM49370RLX/NOPB DSBGA YPG 49 1000 178.0 12.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 4.19 4.19 0.76 8.0 12.0 Q1 4.19 4.19 0.76 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM49370RL/NOPB DSBGA YPG LM49370RLX/NOPB DSBGA YPG 49 250 210.0 185.0 35.0 49 1000 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA YPG0049xxx D 0.6500.075 E RLA49XXX (Rev B) D: Max = 3.94 mm, Min = 3.88 mm E: Max = 3.94 mm, Min = 3.88 mm 4214898/A NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. 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