2008-2013 Microchip Technology Inc. DS22107B-page 1
MCP454X/456X/464X/466X
Features
• Single or Dual Resistor Network Options
• Potentiometer or Rheostat Configuration Options
• Resistor Network Resolution
- 7-bit: 128 Resistors (129 Steps)
- 8-bit: 256 Resistors (257 Steps)
•R
AB Resistances O ptions of:
-5k
-10k
-50k
-100k
• Zero-Scale to Full-Scale Wiper Operation
• Low Wiper Resist anc e: 75 (typical)
•Low Tempco:
- Absolute (Rheostat): 50 ppm typical
(0°C to 70°C)
- Ratiometric (Potentiometer): 15 ppm typical
• Nonvolatile Memory
- Automatic Recall of Saved Wiper Setting
- WiperLock™ Technology
- 10 General Purpose Memory Locations
•I
2C Serial Interface
- 100 kHz, 400 kHz and 3.4 MHz Support
• Serial Protocol Allows:
- High-Speed Read/Write to Wiper
- Read/Write to EEPROM
- Write Protect to be Enabled/Disabled
- WiperLock to be Enabled/Disabled
• Resistor Network Terminal Disconnect Feature
via the Terminal Control (TCON) Register
• Write Protect Feature:
- Hardware Write Protect (WP) Control Pin
- Software W rite Protect (WP) Configuration Bit
• Brown-out Reset Protection (1.5V typical)
• Serial Interface Inactive Current (2.5 uA typical)
• High-Voltage Tolerant Digital Inputs: Up to 12.5V
• Wide Operating Voltage:
- 2.7V to 5.5V - Device Characteristics Specified
- 1.8V to 5.5V - Device Operation
• Wide Bandwidth (-3dB) Operation:
- 2 MHz (typ .) for 5.0 k Device
• Extended Temperature Range (-40°C to +125°C)
Description
The MCP45XX and MCP46XX devices offer a wide
range of product offerings using an I2C int erface . This
family of devices support 7-bit and 8-bit resistor
networks, nonvolatile memory configurations, and
Potentiometer and Rheostat pinouts.
WiperLock Technology allows application-specific
calibration settings to be secured in the EEPROM.
Package Types (top view)
1
2
3
45
6
7
8
P0W
P0B
P0A
VSS
VDD
MCP45X1
Single Potentiometer
MSOP
HVC / A0
SDA
SCL 1
2
3
45
6
7
8
P0B
A1
P0W
VDD
MSOP
1
2
3
411
12
13
14
A2
A1
WP
VDD
MCP46X1 Dual Potentiometers
TSSOP
5
6
78
9
10 P0W
P0B
P0A
P1A
P1W
P1B
VSS
HVC / A0
SDA
SCL
VSS
HVC/A0
SDA
SCL
QFN-16 4x4 (ML) *
1
2
3
47
8
9
10 A1
VDD
MCP46X2 Dual Rheostat
MSOP
56
P0B
P0W
P1W
P1B
VSS
HVC/A0
SDA
SCL
MCP45X2
Single Rheosta t
DFN 3x3 (MF) *
DFN 3x3 (MF) *
SDA
SCL
VSS
A1
P0B
1
2
3
4
8
7
6
5P0W
VDD
HVC / A0
* Includes Exposed Thermal Pad (EP); see Table 3-1.
EP
9
DFN 3x3 (MF) *
SDA
SCL
VSS
P0B
P0W
1
2
3
4
8
7
6
5P0A
VDD
HVC / A0
EP
9
2
VSS
VSS
SCL WP
NC
P1B
P0B
P1W
P1A
P0A
P0W
HVC/A0
VDD
A1
A2
SDA EP
16
1151413
3
4
12
11
10
9
5678
17
SDA
SCL
VSS
A1
P0B
1
2
3
4
10
9
8
7P0W
VDD
HVC / A0
EP
11
P1B 56P1W
7/8-Bit Single/Dual I2C Digital POT with
Nonvolatile Memory
MCP454X/456X/464X/466X
DS22107B-page 2 2008-2013 Microchip Technology Inc.
Device Block Diagram
Device Features
Device
# of POTs
Wiper
Configuration
Control
Interface
Memory
Type
WiperLock
Technology
POR Wiper
Setting
Resistance (typical)
# of Steps
VDD
Operating
Range (2)
RAB Options (k)Wiper
- RW
()
MCP4531 (3) 1 Potentiometer (1) I2CRAM No Mid-Scale 5.0, 10.0, 5 0.0, 10 0.0 75 129 1.8V to 5.5V
MCP4532 (3) 1 Rheostat I2CRAM No Mid-Scale 5.0, 10 .0, 5 0.0, 10 0.0 75 129 1.8V to 5.5V
MCP4541 1 Potentiometer (1) I
2C EE Yes NV Wiper 5.0, 10 .0, 50.0 , 100.0 75 12 9 2.7V to 5.5V
MCP4542 1 Rheostat I2C EE Yes NV Wiper 5.0, 10 .0, 50.0, 10 0.0 75 129 2.7V to 5.5V
MCP4551 (3) 1 Potentiometer (1) I2CRAM No Mid-Scale 5.0, 10.0, 5 0.0, 10 0.0 75 257 1.8V to 5.5V
MCP4552 (3) 1 Rheostat I2CRAM No Mid-Scale 5.0, 10 .0, 5 0.0, 10 0.0 75 257 1.8V to 5.5V
MCP4561 1 Potentiometer (1) I
2C EE Yes NV Wiper 5.0, 10 .0, 50.0 , 100.0 75 25 7 2.7V to 5.5V
MCP4562 1 Rheostat I2C EE Yes NV Wiper 5.0, 10 .0, 50.0, 10 0.0 75 257 2.7V to 5.5V
MCP4631 (3) 2 Potentiometer (1) I2CRAM No Mid-Scale 5.0, 10.0, 5 0.0, 10 0.0 75 129 1.8V to 5.5V
MCP4632 (3) 2 Rheostat I2CRAM No Mid-Scale 5.0, 10 .0, 5 0.0, 10 0.0 75 129 1.8V to 5.5V
MCP4641 2 Potentiometer (1) I
2C EE Yes NV Wiper 5.0, 10 .0, 50.0 , 100.0 75 12 9 2.7V to 5.5V
MCP4642 2 Rheostat I2C EE Yes NV Wiper 5.0, 10 .0, 50.0, 10 0.0 75 129 2.7V to 5.5V
MCP4651 (3) 2 Potentiometer (1) I2CRAM No Mid-Scale 5.0, 10.0, 5 0.0, 10 0.0 75 257 1.8V to 5.5V
MCP4652 (3) 2 Rheostat I2CRAM No Mid-Scale 5.0, 10 .0, 5 0.0, 10 0.0 75 257 1.8V to 5.5V
MCP4661 2 Potentiometer (1) I
2C EE Yes NV Wiper 5.0, 10 .0, 50.0 , 100.0 75 25 7 2.7V to 5.5V
MCP4662 2 Rheostat I2C EE Yes NV Wiper 5.0, 10 .0, 50.0, 10 0.0 75 257 2.7V to 5.5V
Note 1: Floating either terminal (A or B) allows the device to be used as a Rheostat (variable resistor).
2: Analog characteristics only tested from 2.7V to 5.5V unless otherwise noted.
3: Please check Microchip web site for device release and availability
Power-up/
Brown-out
Control
VDD
VSS
I2C Serial
Interface
Module &
Control
Logic
(WiperLock™
Technology)
Resistor
Network 0
(Pot 0)
Wiper 0
& TCON
Register
Resistor
Network 1
(Pot 1)
Wiper 1
& TCON
Register
A2
A1
HVC/A0
SCL
SDA
WP
Memory (16x9)
Wiper0 (V & NV)
Wiper1 (V & NV)
TCON
STATUS
Data EEPROM
(10 x 9-bits)
P0A
P0W
P0B
P1A
P1W
P1B
For Dual Resistor Network
Devices Only
I2C Interface
2008-2013 Microchip Technology Inc. DS22107B-page 3
MCP454X/456X/464X/466X
1.0 ELECTRICAL CHARAC TERISTICS
1.1 Absolute Maximum Ratings†
Voltage on VDD with respect to VSS ...........................................................................................................-0.6V to +7.0V
Voltage on HVC/A0, A1, A2, SCL, SDA and WP with respect to VSS .......................................................-0.6V to 12.5V
Voltage on all other pins (PxA, PxW, and PxB) with respect to VSS ..................................................-0.3V to VDD + 0.3V
Input clamp current, IIK (VI < 0, VI > VDD, VI > VPP ON HV pins)..................... ...... .................................. ..... ...... ...±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) .................................................................................................. ±20 mA
Maximum output current sunk by any Output pin....................................................................................................25 mA
Maximum output current sourced by any Output pin .............................................................................................25 mA
Maximum current out of VSS pin ...........................................................................................................................100 mA
Maximum current into VDD pin..............................................................................................................................100 mA
Maximum current into PXA, PXW & PXB pins ......................................................................................................±2.5 mA
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
Package power dissipation (TA = +50°C, TJ = +150°C)
MSSOP-8.......................................................................................................................................................473 mW
MSSOP-10.....................................................................................................................................................495 mW
DFN-8 (3x3) ......................................................................................................................................................1.76W
DFN-10 (3x3) ....................................................................................................................................................1.87W
TSSOP-14.........................................................................................................................................................1.00W
QFN-16 (4x4)....................................................................................................................................................2.18W
Soldering temperature of leads (10 seconds).......................................................................................................+300°C
ESD protection on all pins 4 kV (HBM),
30 0V (MM)
Maximum Junction Temperatur e (TJ) ...................................................................................................................+150°C
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This
is a stres s ratin g only and fu nctio nal ope ration o f the d evice at th ose or an y other condit ion s above tho se ind icated in
the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended peri-
ods may affect device reliability.
MCP454X/456X/464X/466X
DS22107B-page 4 2008-2013 Microchip Technology Inc.
AC/DC CHARACTERISTICS
DC Characteri sti cs
Standard Operating Conditions (unless otherwise specified)
Operati ng Temperatur e –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters Sym Min Typ Max Units Conditions
Supply Voltage VDD 2.7 — 5.5 V
1.8 — 2.7 V Serial Interface only.
HVC pin voltage
range VHV V
SS —12.5VVV
DD
4.5V The HVC pin will be at one
of three input levels
(VIL, VIH or VIHH). (Note 6)
VSS —V
DD +
8.0V VV
DD <
4.5V
VDD Start Voltage
to ensure Wiper
Reset
VBOR — — 1.65 V RAM retention voltage (VRAM) < VBOR
VDD Rise Rate to
ensure Power-on
Reset
VDDRR (Note 9)V/ms
Delay after device
exits the reset state
(VDD > VBOR)
TBORD —1020µs
Supply Current
(Note 10)IDD — — 600 µA Serial Interface Active,
HVC/A0 = VIH (or VIL) (Note 11)
Write all 0’s to Volatile Wiper 0
VDD = 5.5V, FSCL = 3.4 MHz
— — 250 µA Serial Interface Active,
HVC/A0 = VIH (or VIL) (Note 11)
Write all 0’s to Volatile Wiper 0
VDD = 5.5V, FSCL = 100 kHz
— — 575 µA EE Write Current (Write Cycle)
(Nonvolatile device o nly),
VDD = 5.5V, FSCL = 400 kHz,
Write all 0’s to Nonvolatile Wiper 0
SCL = VIL or VIH
— 2.5 5 µA Serial Interface Inactive,
(Stop condition, SCL = SDA = VIH),
Wiper = 0
VDD = 5.5V, HVC/A0 = VIH
Note 1: Resistance is defined as the resistance between terminal A to terminal B.
2: INL and DNL are measured at VW with VA = VDD and VB = VSS.
3: MCP4XX1 only.
4: MCP4XX2 only, includes VWZSE and VWFSE.
5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
6: This specification by design.
7: Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and
temperature.
8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and
then tested .
9: POR/BOR is not rate dependent.
10: Supply current is ind epe nde nt of curre nt throu gh the res ist or networ k.
11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification.
2008-2013 Microchip Technology Inc. DS22107B-page 5
MCP454X/456X/464X/466X
Resistance
(± 20%) RAB 4.0 5 6.0 k-502 devices(Note 1)
8.0 10 12.0 k-103 devices(Note 1)
40.0 50 60.0 k-503 devices(Note 1)
80.0 100 120.0 k-104 devices(Note 1)
Resol uti on N 257 Taps 8-bit No Missing Cod es
129 Taps 7-bit No Missing Codes
Step Resi stance RS —R
AB /
(256) — 8-bit Note 6
—R
AB /
(128) — 7-bit Note 6
Nominal
Resistance Match |RAB0 - RAB1| /
RAB —0.21.25%MCP46X1 devices only
|RBW0 - RBW1|
/ RBW —0.251.5%MCP46X2 devices only,
Code = Full-Scale
Wiper Resistance
(Note 3, Note 4)RW—75160VDD = 5.5 V, IW = 2. 0 mA , code = 00h
—75300VDD = 2.7 V, IW = 2. 0 mA, code = 00h
Nominal
Resistance
Tempco
RAB/T — 50 — ppm/°C TA = -20°C to +7 0°C
— 100 — ppm/°C TA = -40°C to +85°C
— 150 — ppm/°C TA = -40°C to +125°C
Ratiometeric
Tempco VWB/T — 15 — ppm/°C Code = Mid-scale (80h or 40h)
Resistor Terminal
Input Voltage
Range (Terminals
A, B and W)
VA,VW,VBVss — VDD VNote 5, Note 6
AC/DC CHARACTERISTICS (CONTINUE D)
DC Characteri sti cs
Standard Operating Conditions (unless otherwise specified)
Operati ng Temperatur e –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters Sym Min Typ Max Units Conditions
Note 1: Resistance is defined as the resistance between terminal A to terminal B.
2: INL and DNL are measured at VW with VA = VDD and VB = VSS.
3: MCP4XX1 only.
4: MCP4XX2 only, includes VWZSE and VWFSE.
5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
6: This specification by design.
7: Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and
temperature.
8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and
then tested .
9: POR/BOR is not rate dependent.
10: Supply current is ind epe nde nt of curre nt throu gh the res ist or networ k.
11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification.
MCP454X/456X/464X/466X
DS22107B-page 6 2008-2013 Microchip Technology Inc.
Maximum current
through Terminal
(A, W or B)
Note 6
IT— — 2.5 mA Terminal A IAW,
W = Full-Scale (FS)
— — 2.5 mA Terminal B IBW,
W = Zero Scale (ZS)
— — 2.5 mA Terminal W IAW or IBW,
W = FS or ZS
——1.38mA
Terminal A
and
Terminal B
IAB, VB = 0V,
VA = 5.5V,
RAB(MIN) = 4000
——0.688mA IAB, VB = 0V,
VA = 5.5V,
RAB(MIN) = 8000
——0.138mA IAB, VB = 0V,
VA = 5.5V,
RAB(MIN) = 40000
——0.069mA IAB, VB = 0V,
VA = 5.5V,
RAB(MIN) = 80000
Leakage current
into A, W or B IWL —100—nAMCP4XX1 PxA = PxW = PxB = VSS
—100—nAMCP4XX2 PxB = PxW = VSS
— 100 — nA Terminals Disconnected
(R1HW = R0HW = 0)
AC/DC CHARACTERISTICS (CONTINUE D)
DC Characteri sti cs
Standard Operating Conditions (unless otherwise specified)
Operati ng Temperatur e –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters Sym Min Typ Max Units Conditions
Note 1: Resistance is defined as the resistance between terminal A to terminal B.
2: INL and DNL are measured at VW with VA = VDD and VB = VSS.
3: MCP4XX1 only.
4: MCP4XX2 only, includes VWZSE and VWFSE.
5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
6: This specification by design.
7: Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and
temperature.
8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and
then tested .
9: POR/BOR is not rate dependent.
10: Supply current is ind epe nde nt of curre nt throu gh the res ist or networ k.
11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification.
2008-2013 Microchip Technology Inc. DS22107B-page 7
MCP454X/456X/464X/466X
Full-Scale Error
(MCP4XX1 only)
(8-bit code = 100h,
7-bit code = 80h)
VWFSE -6.0 -0.1 — LSb 5 k 8-bit 3.0V VDD 5.5V
-4.0 -0.1 — LSb 7-bit 3.0V VDD 5.5V
-3.5 -0.1 —LSb 10 k 8-bit 3.0V VDD 5.5V
-2.0 -0.1 —LSb 7-bit 3.0V VDD 5.5V
-0.8 -0.1 — LSb 50 k 8-bit 3.0V VDD 5.5V
-0.5 -0.1 — LSb 7-bit 3.0V VDD 5.5V
-0.5 -0.1 —LSb 100 k 8-bit 3.0V VDD 5.5V
-0.5 -0.1 —LSb 7-bit 3.0V VDD 5.5V
Zero-Scale Error
(MCP4XX1 only)
(8-bit code = 00h,
7-bit code = 00h)
VWZSE —+0.1+6.0LSb5k 8-bit 3.0V VDD 5.5V
— +0.1 +3.0 LSb 7-bit 3.0V VDD 5.5V
—+0.1 +3.5 LSb 10 k 8-bit 3.0V VDD 5.5V
—+0.1 +2.0 LSb 7-bit 3.0V VDD 5.5V
— +0.1 +0.8 LSb 50 k 8-bit 3.0V VDD 5.5V
— +0.1 +0.5 LSb 7-bit 3.0V VDD 5.5V
—+0.1 +0.5 LSb 100 k 8-bit 3.0V VDD 5.5V
—+0.1 +0.5 LSb 7-bit 3.0V VDD 5.5V
Potentiometer
Integral
Non-linearity
INL -1 ±0.5 +1 LSb 8-bit 3.0V VDD 5.5V
MCP4XX1 devices only
(Note 2)
-0.5 ±0.25 +0.5 LSb 7-bit
Potentiometer
Differential
Non-linearity
DNL -0.5 ±0.25 +0.5 LSb 8-bit 3.0V VDD 5.5V
MCP4XX1 devices only
(Note 2)
-0.25 ±0.125 +0.25 LSb 7-bit
AC/DC CHARACTERISTICS (CONTINUE D)
DC Characteri sti cs
Standard Operating Conditions (unless otherwise specified)
Operati ng Temperatur e –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters Sym Min Typ Max Units Conditions
Note 1: Resistance is defined as the resistance between terminal A to terminal B.
2: INL and DNL are measured at VW with VA = VDD and VB = VSS.
3: MCP4XX1 only.
4: MCP4XX2 only, includes VWZSE and VWFSE.
5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
6: This specification by design.
7: Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and
temperature.
8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and
then tested .
9: POR/BOR is not rate dependent.
10: Supply current is ind epe nde nt of curre nt throu gh the res ist or networ k.
11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification.
MCP454X/456X/464X/466X
DS22107B-page 8 2008-2013 Microchip Technology Inc.
Bandwidth -3 dB
(See Figure 2-58,
load = 30 pF)
BW — 2 — MHz 5 k8-bit Code = 80h
— 2 — MHz 7-bit Code = 40h
—1—MHz10k8-bit Code = 80h
— 1 — MHz 7-bit Code = 40h
— 200 — kHz 50 k8-bit Code = 80h
— 200 — kHz 7-bit Code = 40h
— 100 — kHz 100 k8-bit Code = 80h
— 100 — kHz 7-bit Code = 40h
AC/DC CHARACTERISTICS (CONTINUE D)
DC Characteri sti cs
Standard Operating Conditions (unless otherwise specified)
Operati ng Temperatur e –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters Sym Min Typ Max Units Conditions
Note 1: Resistance is defined as the resistance between terminal A to terminal B.
2: INL and DNL are measured at VW with VA = VDD and VB = VSS.
3: MCP4XX1 only.
4: MCP4XX2 only, includes VWZSE and VWFSE.
5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
6: This specification by design.
7: Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and
temperature.
8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and
then tested .
9: POR/BOR is not rate dependent.
10: Supply current is ind epe nde nt of curre nt throu gh the res ist or networ k.
11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification.
2008-2013 Microchip Technology Inc. DS22107B-page 9
MCP454X/456X/464X/466X
Rheostat Integral
Non-linearity
MCP45X1
(Note 4, Note 8)
MCP4XX2 devices
only (Note 4)
R-INL -1.5 ±0.5 +1.5 LSb 5 k8-bit 5.5V, IW = 900 µA
-8.25 +4.5 +8.25 LSb 3.0V, IW = 480 µA
(Note 7)
-1.125 ±0.5 +1.125 LSb 7 -bit 5.5V, IW = 900 µA
-6.0 +4.5 +6.0 LSb 3.0V, IW = 480 µA
(Note 7)
-1.5 ±0.5 +1.5 LSb 10 k8-bit 5.5V, IW = 450 µA
-5.5 +2.5 +5.5 LSb 3.0V, IW = 240 µA
(Note 7)
-1.125 ±0.5 +1.125 LSb 7 -bit 5.5V, IW = 450 µA
-4.0 +2.5 +4.0 LSb 3.0V, IW = 240 µA
(Note 7)
-1.5 ±0.5 +1.5 LSb 50 k8-bit 5.5V, IW = 90 µA
-2.0 +1 +2.0 LSb 3.0V, IW = 48 µA
(Note 7)
-1.125 ±0.5 +1.125 LSb 7 -bit 5.5V, IW = 90 µA
-1.5 +1 +1.5 LSb 3.0V, IW = 48 µA
(Note 7)
-1.0 ±0.5 +1.0 LSb 100 k8-bit 5.5V, IW = 45 µA
-1.5 +0.25 +1.5 LSb 3.0V, IW = 24 µA
(Note 7)
-0.8 ±0.5 +0.8 LSb 7-bit 5.5V, IW = 45 µA
-1.125 +0.25 +1.125 LSb 3.0V, IW = 24 µA
(Note 7)
AC/DC CHARACTERISTICS (CONTINUE D)
DC Characteri sti cs
Standard Operating Conditions (unless otherwise specified)
Operati ng Temperatur e –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters Sym Min Typ Max Units Conditions
Note 1: Resistance is defined as the resistance between terminal A to terminal B.
2: INL and DNL are measured at VW with VA = VDD and VB = VSS.
3: MCP4XX1 only.
4: MCP4XX2 only, includes VWZSE and VWFSE.
5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
6: This specification by design.
7: Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and
temperature.
8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and
then tested .
9: POR/BOR is not rate dependent.
10: Supply current is ind epe nde nt of curre nt throu gh the res ist or networ k.
11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification.
MCP454X/456X/464X/466X
DS22107B-page 10 2008-2013 Microchip Technology Inc.
Rheostat
Differential
Non-linearity
MCP45X1
(Note 4, Note 8)
MCP4XX2 devices
only
(Note 4)
R-DNL -0.5 ±0.25 +0.5 LSb 5 k8-bit 5.5V, IW = 900 µA
-1.0 +0.5 +1.0 LSb 3.0V, IW = 480 µA
(Note 7)
-0.375 ±0.25 +0.375 LSb 7-bit 5.5V, IW = 900 µA
-0.75 +0.5 +0.75 LSb 3.0V, IW = 480 µA
(Note 7)
-0.5 ±0.25 +0.5 LSb 10 k8-bit 5.5V, IW = 450 µA
-1.0 +0.25 +1.0 LSb 3.0V, IW = 240 µA
(Note 7)
-0.375 ±0.25 +0.375 LSb 7-bit 5.5V, IW = 450 µA
-0.75 +0.5 +0.75 LSb 3.0V, IW = 240 µA
(Note 7)
-0.5 ±0.25 +0.5 LSb 50 k8-bit 5.5V, IW = 90 µA
-0.5 ±0.25 +0.5 LSb 3.0V, IW = 48 µA
(Note 7)
-0.375 ±0.25 +0.375 LSb 7-bit 5.5V, IW = 90 µA
-0.375 ±0.25 +0.375 LSb 3.0V, IW = 48 µA
(Note 7)
-0.5 ±0.25 +0.5 LSb 100 k8-bit 5.5V, IW = 45 µA
-0.5 ±0.25 +0.5 LSb 3.0V, IW = 24 µA
(Note 7)
-0.375 ±0.25 +0.375 LSb 7-bit 5.5V, IW = 45 µA
-0.375 ±0.25 +0.375 LSb 3.0V, IW = 24 µA
(Note 7)
Capacitance (PA)C
AW — 75 — pF f =1 MHz, Code = Full-Scale
Capacitance (Pw)C
W— 120 — pF f =1 M Hz, Code = Full-Scale
Capacitance (PB)C
BW — 75 — pF f =1 MHz, Code = Full-Scale
AC/DC CHARACTERISTICS (CONTINUE D)
DC Characteri sti cs
Standard Operating Conditions (unless otherwise specified)
Operati ng Temperatur e –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters Sym Min Typ Max Units Conditions
Note 1: Resistance is defined as the resistance between terminal A to terminal B.
2: INL and DNL are measured at VW with VA = VDD and VB = VSS.
3: MCP4XX1 only.
4: MCP4XX2 only, includes VWZSE and VWFSE.
5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
6: This specification by design.
7: Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and
temperature.
8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and
then tested .
9: POR/BOR is not rate dependent.
10: Supply current is ind epe nde nt of curre nt throu gh the res ist or networ k.
11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification.
2008-2013 Microchip Technology Inc. DS22107B-page 11
MCP454X/456X/464X/466X
Digital Inputs/Outputs (SDA, SCK, HVC/A0, A1, A2, WP)
Schmitt Trigger
High-Input
Threshold
VIH 0.45 VDD — — V All
Inputs
except
SDA
and
SCL
2.7V VDD 5.5V
(Allows 2.7V Digital VDD with
5V Analog VDD)
0.5 VDD ——V 1.8V VDD 2.7V
0.7 VDD —V
MAX VSDA
and
SCL
100 kHz
0.7 VDD —V
MAX V400kHz
0.7 VDD —V
MAX V1.7MHz
0.7 VDD —V
MAX V3.4Mhz
Schmitt Trigger
Low-Input
Threshold
VIL ——0.2V
DD V All inputs except SDA and SCL
-0.5 — 0.3VDD VSDA
and
SCL
100 kHz
-0.5 — 0.3VDD V400kHz
-0.5 — 0.3VDD V1.7MHz
-0.5 — 0.3VDD V3.4Mhz
Hysteresis of
Schmitt Trigger
Inputs (Note 6)
VHYS —0.1V
DD — V All inputs except SDA and SCL
N.A. — — V
SDA
and
SCL
100 kHz VDD < 2.0V
N.A. — — V VDD 2.0V
0.1 VDD ——V 400 kHz VDD < 2.0V
0.05 VDD ——V V
DD 2.0V
0.1 VDD ——V 1.7MHz
0.1 VDD ——V 3.4Mhz
High-Voltage Input
Entry Voltage VIHHEN 8.5 — 12.5 (6) V T hreshold for WiperLock™ Technology
High-Voltage Input
Exit Voltage VIHHEX ——V
DD +
0.8V (6) V
High-Volt a ge Lim it VMAX ——12.5
(6) V Pin can tolerate VMAX or less.
AC/DC CHARACTERISTICS (CONTINUE D)
DC Characteri sti cs
Standard Operating Conditions (unless otherwise specified)
Operati ng Temperatur e –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters Sym Min Typ Max Units Conditions
Note 1: Resistance is defined as the resistance between terminal A to terminal B.
2: INL and DNL are measured at VW with VA = VDD and VB = VSS.
3: MCP4XX1 only.
4: MCP4XX2 only, includes VWZSE and VWFSE.
5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
6: This specification by design.
7: Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and
temperature.
8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and
then tested .
9: POR/BOR is not rate dependent.
10: Supply current is ind epe nde nt of curre nt throu gh the res ist or networ k.
11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification.
MCP454X/456X/464X/466X
DS22107B-page 12 2008-2013 Microchip Technology Inc.
Output Low
Voltage (SDA) VOL V
SS —0.2V
DD VV
DD < 2.0V, IOL = 1 mA
VSS —0.4 VV
DD 2.0V, IOL = 3 mA
Weak Pull-up /
Pull-down Current IPU — — 1.75 mA Internal VDD pull-up, VIHH pull-down
VDD = 5.5V, VIHH = 12.5V
— 170 — µA HVC pin, VDD = 5.5V, VHVC = 3V
HVC Pull-up /
Pull-down
Resistance
RHVC —16—kVDD = 5.5V, VHVC = 3V
Input Leakage Cur-
rent IIL -1 — 1 µA VIN = VDD and VIN = VSS
Pin Capacitance CIN, COUT —10—pFf
C = 3.4 MHz
RAM (Wiper) Value
Value Range N 0h — 1FFh hex 8-bit device
0h — 1FFh hex 7-bit device
TCON POR/BOR
Value NTCON 1FFh hex All Terminals connected
EEPROM
Endurance Endurance —1M—Cycles
EEPROM Range N 0h — 1FFh hex
Initial Fac tory
Setting N 80h hex 8-bit WiperLock Technology = Off
40h hex 7-bit WiperLock Technology = Off
EEPROM
Programming Write
Cycle Time
tWC —510ms
Power Requireme nts
Power Supply
Sensitivity
(MCP45X2 and
MCP46X2 only)
PSS — 0.0015 0.0035 %/% 8-bit VDD = 2.7V to 5.5V,
VA = 2.7V, Code = 80h
— 0.0015 0.0035 %/% 7-bit VDD = 2.7V to 5.5V,
VA = 2.7V, Code = 40h
AC/DC CHARACTERISTICS (CONTINUE D)
DC Characteri sti cs
Standard Operating Conditions (unless otherwise specified)
Operati ng Temperatur e –40°C TA +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters Sym Min Typ Max Units Conditions
Note 1: Resistance is defined as the resistance between terminal A to terminal B.
2: INL and DNL are measured at VW with VA = VDD and VB = VSS.
3: MCP4XX1 only.
4: MCP4XX2 only, includes VWZSE and VWFSE.
5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
6: This specification by design.
7: Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and
temperature.
8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and
then tested .
9: POR/BOR is not rate dependent.
10: Supply current is ind epe nde nt of curre nt throu gh the res ist or networ k.
11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification.
2008-2013 Microchip Technology Inc. DS22107B-page 13
MCP454X/456X/464X/466X
FIGURE 1-1: I2C Bus Start/Stop Bits Timing Waveforms.
TABLE 1-1: I2C BUS START/STOP BITS REQUIREMENTS
I2C AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operati ng Temperatur e –40 C TA +125C (Extended)
Operati ng Volt age VDD range is described in AC/DC characteristics
Param.
No. Symbol Characteristic Min Max Units Conditions
FSCL Standard mode 0 100 kHz Cb = 400 pF, 1. 8V - 5.5V
Fast mode 0 400 kHz Cb = 400 pF, 2.7V - 5.5 V
High-Speed 1.7 0 1.7 MHz Cb = 400 pF, 4.5V - 5.5V
High-Speed 3.4 0 3.4 MHz Cb = 100 pF, 4.5V - 5.5V
D102 Cb Bus c apacitive
loading 100 kH z mode — 400 pF
400 kHz mode — 400 pF
1.7 MHz mode — 400 pF
3.4 MHz mode — 100 pF
90 TSU:STA START condition 100 kHz mode 4700 — ns Only relevant for repeated
START condition
Setup time 400 kHz mode 600 — ns
1.7 MHz mode 160 — ns
3.4 MHz mode 160 — ns
91 THD:STA START condition 100 kHz mode 4000 — ns After this period the first
clock pulse is generated
Hold time 400 kHz mode 600 — ns
1.7 MHz mode 160 — ns
3.4 MHz mode 160 — ns
92 TSU:STO STOP cond ition 100 kHz mo de 4000 — ns
Setup time 400 kHz mode 600 — ns
1.7 MHz mode 160 — ns
3.4 MHz mode 160 — ns
93 THD:STO STOP condition 100 kHz mode 4000 — ns
Hold time 400 kHz mode 600 — ns
1.7 MHz mode 160 — ns
3.4 MHz mode 160 — ns
91 93
SCL
SDA
START
Condition STOP
Condition
90 92
MCP454X/456X/464X/466X
DS22107B-page 14 2008-2013 Microchip Technology Inc.
FIGURE 1-2: I2C Bus Data Timing.
90 91 92
100 101
103
106 107
109 109 110
102
SCL
SDA
In
SDA
Out
TABLE 1-2: I2C BUS DATA REQUIREMENTS (SLAVE MODE)
I2C AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40C TA +125C (Extended)
Operating Voltage VDD range is described in AC/DC characteristics
Param.
No. Sym Characteristic Min Max Units Conditions
100 THIGH Clock high time 100 kHz mode 4000 — ns 1.8V-5.5V
400 kHz mo de 600 — ns 2.7V-5.5V
1.7 MHz mo de 120 ns 4.5V-5.5V
3.4 MHz mo de 6 0 — ns 4.5V-5.5V
101 TLOW Clock low time 100 kHz mode 4700 — ns 1.8V-5.5V
400 kHz mo de 1300 — ns 2.7V-5.5V
1.7 MHz mo de 320 ns 4.5V-5.5V
3.4 MHz mo de 160 — ns 4.5V-5.5V
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(minimum 30 0 ns) of the falli ng edge of SCL to av oid unin tended generati on of START or STOP condit ions.
2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the
requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not
stretch th e LO W period of the SCL signal. If such a de vic e do es stretc h the LOW peri od of the SCL signal ,
it must output the next data bit to the SDA line.
TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before
the SCL line is released.
3: The MCP46X1/MCP46X2 device must provide a data hold time to bridge the undefined part between VIH
and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but
must be tested in order to ensure that the output data will meet the setup and hold specifications for the
receiving device.
4: Use Cb in pF for the calculations.
5: Not tested.
6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do
not unintentionally create a Start or Stop condition.
7: Ensured by the TAA 3.4 MHz specification test.
2008-2013 Microchip Technology Inc. DS22107B-page 15
MCP454X/456X/464X/466X
102A (5) TRSCL SCL rise time 100 kHz mode — 1000 ns Cb is specified to be from
10 to 400 pF (100 pF maxi-
mum for 3.4 MHz mode)
400 kHz mode 20 + 0.1Cb 300 ns
1.7 MHz mode 20 80 ns
1.7 MHz mode 20 160 ns After a Repeated Start con-
dition or an Acknowledge
bit
3.4 MHz mode 10 40 ns
3.4 MHz mode 10 80 ns After a Repeated Start
condition or an Acknowl-
edge bit
102B (5) TRSDA SDA rise time 100 kHz mode — 1000 ns Cb is specified to be from
10 to 400 pF (100 pF max
for 3.4 MHz mode)
400 kHz mode 20 + 0.1Cb 300 ns
1.7 MHz mode 20 160 ns
3.4 MHz mode 10 80 ns
103A (5) TFSCL SCL fall time 100 kHz mode — 300 ns Cb is specified to be from
10 to 400 pF (100 pF max
for 3.4 MHz mode)
400 kHz mode 20 + 0.1Cb 300 ns
1.7 MHz mode 20 80 ns
3.4 MHz mode 10 40 ns
103B (5) TFSDA SDA fall time 100 kHz mode — 300 ns Cb is specified to be from
10 to 400 pF (100 pF max
for 3.4 MHz mode)
400 kHz mode 20 + 0.1Cb (4) 300 ns
1.7 MHz mode 20 160 ns
3.4 MHz mode 10 80 ns
106 THD:DAT Data input hold
time 100 kHz mode 0 — ns 1.8V-5.5V, Note 6
400 kHz mode 0 — ns 2.7V-5.5V, Note 6
1.7 MHz mode 0 — ns 4.5V-5.5V, Note 6
3.4 MHz mode 0 — ns 4.5V-5.5V, Note 6
TABLE 1-2: I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)
I2C AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40C TA +125C (Extended)
Operating Voltage VDD range is described in AC/DC characteristics
Param.
No. Sym Characteristic Min Max Units Conditions
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(minimum 30 0 ns) of the falling edge of SCL to av oid unin tended generati on of STAR T or STOP condition s.
2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the
requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not
stretch th e LO W period of the SCL signal. If suc h a de vic e do es stretch the LO W peri od of the SCL sig nal ,
it must output the next data bit to the SDA line.
TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before
the SCL line is released.
3: The MCP46X1/MCP46X2 device must provide a data hold time to bridge the undefined part between VIH
and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but
must be tested in order to ensure that the output data will meet the setup and hold specifications for the
receiving device.
4: Use Cb in pF for the calculations.
5: Not tested.
6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do
not unintentionally create a Start or Stop condition.
7: Ensured by the TAA 3.4 MHz specification test.
MCP454X/456X/464X/466X
DS22107B-page 16 2008-2013 Microchip Technology Inc.
107 TSU:DAT Data input setup
time 100 kHz mode 250 — ns Note 2
400 kHz mode 100 — ns
1.7 MHz mode 10 — ns
3.4 MHz mode 10 — ns
109 TAA Output valid
from clock 100 kHz mode — 3450 ns Note 1
400 kHz mode — 900 ns
1.7 MHz mode — 150 ns Cb = 100 pF,
Note 1, Note 7
— 310 ns Cb = 400 pF,
Note 1, Note 5
3.4 MHz mode — 150 ns Cb = 100 pF, Note 1
110 TBUF Bus free time 100 kHz mode 4700 — ns Time the bus must be free
before a new transmission
can start
400 kHz mode 1300 — ns
1.7 MHz mode N.A. — ns
3.4 MHz mode N.A. — ns
TSP Input filter spike
suppression
(SDA and SCL)
100 kHz mode — 50 ns Philips Spec sta tes N.A.
400 kHz mode — 50 ns
1.7 MHz mode — 10 ns Spike suppression
3.4 MHz mode — 10 ns Spike suppression
TABLE 1-2: I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)
I2C AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40C TA +125C (Extended)
Operating Voltage VDD range is described in AC/DC characteristics
Param.
No. Sym Characteristic Min Max Units Conditions
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(minimum 30 0 ns) of the falling edge of SCL to av oid unin tended generati on of STAR T or STOP condition s.
2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the
requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not
stretch th e LO W period of the SCL signal. If such a de vic e do es stretc h the LOW peri od of the SCL signal ,
it must output the next data bit to the SDA line.
TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before
the SCL line is released.
3: The MCP46X1/MCP46X2 device must provide a data hold time to bridge the undefined part between VIH
and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but
must be tested in order to ensure that the output data will meet the setup and hold specifications for the
receiving device.
4: Use Cb in pF for the calculations.
5: Not tested.
6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do
not unintentionally create a Start or Stop condition.
7: Ensured by the TAA 3.4 MHz specification test.
2008-2013 Microchip Technology Inc. DS22107B-page 17
MCP454X/456X/464X/466X
TEMPE RATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Ran ge TA-40 — +125 °C
Operati ng Temperature Ra nge TA-40 — +125 °C
Storage Temperature Range TA-65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 8L-DFN (3x3) JA —56.7—°C/W
Thermal Resistance, 8L-MSOP JA —211—°C/W
Thermal Resistance, 8L-SOIC JA — 149.5 — °C/W
Thermal Resistance, 10L-DFN (3x3) JA —57—°C/W
Thermal Resistance, 10L-MSOP JA —202—°C/W
Thermal Resistance, 14L-MSOP JA —N/A—°C/W
Thermal Resistance, 14L-SOIC JA —95.3—°C/W
Thermal Resistance, 16L-QFN JA —47—°C/W
MCP454X/456X/464X/466X
DS22107B-page 18 2008-2013 Microchip Technology Inc.
NOTES:
2008-2013 Microchip Technology Inc. DS22107B-page 19
MCP454X/456X/464X/466X
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-1: Device Current (IDD) vs. I2C
Frequency (fSCL) and Ambient Temperature
(VDD = 2.7V and 5.5V).
FIGURE 2-2: Device Current (ISHDN) and
VDD. (HVC = VDD) vs. Ambient Temperature.
FIGURE 2-3: Write Current (IWRITE) vs.
Ambient Temperature.
FIGURE 2-4: HVC Pull-up/Pull-down
Resistance (RHVC) and Current (IHVC) vs. HVC
Input Voltage (VHVC) (VDD = 5.5V).
FIGURE 2-5: HVC High Input Entry/Exit
Threshold vs. Ambient Temperature and VDD.
Note: The g r ap hs and t ables prov id ed followi ng thi s n ote are a sta tis tic al s umm ar y b as ed on a limite d n um ber of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0
50
100
150
200
250
300
350
400
450
-40 0 40 80 120
Temperature (°C)
IDD (uA)
3.4MHz, 5.5V
3.4MHz, 2.7V 1.7MHz, 5.5V
1.7MHz, 2.7V 400kHz, 5.5V
100kHz, 5.5V
400kHz, 2.7V 100kHz, 2.7V
0.5
1
1.5
2
2.5
3
-40 0 40 80 120
Temperature (°C)
Istandby (uA)
5.5V
2.7V
300
320
340
360
380
400
420
-40 0 40 80 120
Te mper at ure (° C)
IWRITE (µA)
5.5V
0
50
100
150
200
250
2345678910
VHVC (V)
RHVC (kOhms)
-1000
-800
-600
-400
-200
0
200
400
600
800
1000
IHVC (µA)
IHVC
RHVC
0
2
4
6
8
10
12
-40-200 20406080100120
Ambi ent Temperature (°C)
HVC VPP Threshold (V)
2.7V Ex it
5.5V Exit
2.7 V Entr y
5.5V Entry
MCP454X/456X/464X/466X
DS22107B-page 20 2008-2013 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-6: 5k
Pot Mode – RW (
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
FIGURE 2-7: 5k
Pot Mode – RW (
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
FIGURE 2-8: 5k
Rheo Mode – RW (
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperatu re (VDD = 5.5V).
FIGURE 2-9: 5k
Rheo Mode – RW (
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperatu re (VDD = 3.0V).
20
40
60
80
100
120
0 32 64 96 128 160 192 224 256
Wiper Setting (decimal)
Wiper Resistance (R W
)
(ohms)
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
-40°C 25°C
85°C
125°C
20
60
100
140
180
220
260
300
0 32 64 96 128 160 192 224 256
Wiper Setting (decimal)
Wiper Resistance (R W
)
(ohms)
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
-40°C 25°C 85°C
RW
125°C
20
40
60
80
100
120
0 32 64 96 128 160 192 224 256
Wiper Setting (decimal)
Wiper Resistance (R W
)
(ohms)
-1.25
-0.75
-0.25
0.25
0.75
1.25
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
R
W
-40°C
25°C
85°C
125°C
20
60
100
140
180
220
260
300
0 32 64 96 128 160 192 224 256
Wiper Setting (decimal)
Wiper Resistance (R W
)
(ohms)
-2
0
2
4
6
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
-40°C
25°C
85°C125°C
2008-2013 Microchip Technology Inc. DS22107B-page 21
MCP454X/456X/464X/466X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-10: 5k
– Nominal Resistance
(
) vs. Ambient Temperature and VDD.FIGURE 2-11: 5k
– RWB (
) vs. Wiper
Setting and Ambient Temperature.
5050
5100
5150
5200
5250
5300
-40 0 40 80 120
Ambient Temp eratur e (°C)
Nominal Resistance (RAB
)
(Ohms)
2.7V
5.5V
0
1000
2000
3000
4000
5000
6000
0 32 64 96 128 160 192 224 256
Wiper Set t ing (decim al)
RWB (Ohms)
-40°C
25°C
85°C
125°C
MCP454X/456X/464X/466X
DS22107B-page 22 2008-2013 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-12: 5k
– Low-Voltage
Decrement Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
FIGURE 2-13: 5k
– Low-Voltage
Decrement Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
FIGURE 2-14: 5k
– Power-Up Wiper
Response Time (20 ms/Div).
FIGURE 2-15: 5k
– Low-Voltage
Increment Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
FIGURE 2-16: 5k
– Low-Voltage
Increment Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
2008-2013 Microchip Technology Inc. DS22107B-page 23
MCP454X/456X/464X/466X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-17: 10 k
Pot Mode – RW (
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
FIGURE 2-18: 10 k
Pot Mode – RW (
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
FIGURE 2-19: 10 k
Rheo Mode – RW (
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperatu re (VDD = 5.5V).
FIGURE 2-20: 10 k
Rheo Mode – RW (
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperatu re (VDD = 3.0V).
20
40
60
80
100
120
0 25 50 75 100 125 150175 200 225250
Wiper Setting (decimal)
Wiper Resistance (R W
)
(ohms)
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
Error (LSb)
-40C Rw 25C Rw 8 5C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25 C DN L 85C DN L 125C DNL
INL
DNL
RW
-40°C
25°C
85°C
125°C
20
60
100
140
180
220
260
300
0 32 64 96 128 160 192 224 256
Wiper Setting (decimal)
Wiper Resistance (R W
)
(ohms)
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
-40°C
25°C
85°C
125°C
20
40
60
80
100
120
0 32 64 96 128 160 192 224 256
Wiper Setting (decimal)
Wiper Resistance (R W
)
(ohms)
-1
-0.5
0
0.5
1
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
-40°C
25°C85°C
125°C
20
60
100
140
180
220
260
300
0 25 50 75 100 125 150 175 200225 250
Wiper Setting (decimal)
Wiper Resistance (R W
)
(ohms)
-2
-1
0
1
2
3
4
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL RW
-40°C
25°C85°C
125°C
MCP454X/456X/464X/466X
DS22107B-page 24 2008-2013 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-21: 10 k
– Nominal Resistance
(
) vs. Ambient Temperature and VDD.FIGURE 2-22: 10 k
– RWB (
) vs. Wiper
Setting and Ambient Temperature.
9850
9900
9950
10000
10050
10100
10150
10200
10250
10300
-40 0 40 80 120
Ambient Temperature (°C)
Nominal Resistance (R AB
)
(Ohms)
2.7V
5.5V
1.8V
0
2000
4000
6000
8000
10000
12000
0 32 64 96 128 160 192 224 256
Wiper Setting (decimal)
RWB (O h ms)
-40°C
25°C
85°C
125°C
2008-2013 Microchip Technology Inc. DS22107B-page 25
MCP454X/456X/464X/466X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-23: 10 k
– Low-Voltage
Decrement Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
FIGURE 2-24: 10 k
– Low-Voltage
Decrement Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
FIGURE 2-25: 10 k
– Power-Up Wiper
Response Time (1 µs/Div).
FIGURE 2-26: 10 k
– Low-Voltage
Increment Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
FIGURE 2-27: 10 k
– Low-Voltage
Increment Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
MCP454X/456X/464X/466X
DS22107B-page 26 2008-2013 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-28: 50 k
Pot Mode – RW (
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
FIGURE 2-29: 50 k
Pot Mode – RW (
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
FIGURE 2-30: 50 k
Rheo Mode – RW (
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperatu re (VDD = 5.5V).
FIGURE 2-31: 50 k
Rheo Mode – RW (
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperatu re (VDD = 3.0V).
20
40
60
80
100
120
0 32 64 96 128 160 192 224 256
Wiper Setting (decimal)
Wiper Resistance (R W)
(ohms)
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
-40°C
25°C
85°C
125°C
20
60
100
140
180
220
260
300
0 32 64 96 128 160 192 224 256
Wiper Setting (decimal)
Wiper Resistance (R W)
(ohms)
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
-40°C
25°C
85°C
125°C
20
40
60
80
100
120
0 32 64 96 128 160 192 224 256
Wiper Setting (decimal)
Wiper Resistance (R W)
(ohms)
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
-40°C
25°C
85°C
125°C
20
60
100
140
180
220
260
300
0 32 64 96 128 160 192 224 256
Wiper Setting (decimal)
Wiper Resistance (R W
)
(ohms)
-1
-0.75
-0.5
-0.25
0
0.25
0.5
0.75
1
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
-40°C
25°C
85°C
125°C
2008-2013 Microchip Technology Inc. DS22107B-page 27
MCP454X/456X/464X/466X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-32: 50 k
– Nominal Resistance
(
) vs. Ambient Temperature and VDD.FIGURE 2-33: 50 k
– RWB (
) vs. Wiper
Setting and Ambient Temperature.
49000
49500
50000
50500
51000
51500
52000
52500
-40 0 40 80 120
Ambient Temperature (°C)
Nominal Resist ance (R AB
)
(Ohms)
2.7V
1.8V
5.5V
0
10000
20000
30000
40000
50000
60000
0 32 64 96 128 160 192 224 256
Wiper Setting (decimal)
RWB (Ohms)
-40°C
25°C
85°C
125°C
MCP454X/456X/464X/466X
DS22107B-page 28 2008-2013 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-34: 50 k
– Low-Voltage
Decrement Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
FIGURE 2-35: 50 k
– Low-Voltage
Decrement Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
FIGURE 2-36: 50 k
– Power-Up Wiper
Response Time (1 µs/Div).
FIGURE 2-37: 50 k
– Low-Voltage
Increment Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
FIGURE 2-38: 50 k
– Low-Voltage
Increment Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
2008-2013 Microchip Technology Inc. DS22107B-page 29
MCP454X/456X/464X/466X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-39: 100 k
Pot Mode – RW (
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
FIGURE 2-40: 100 k
Pot Mode – RW (
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
FIGURE 2-41: 100 k
Rheo Mode – RW
(
), INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperatu re (VDD = 5.5V).
FIGURE 2-42: 100 k
Rheo Mode – RW
(
), INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperatu re (VDD = 3.0V).
20
40
60
80
100
120
0 32 64 96 128 160 192 224 256
Wiper Setting (decimal)
Wiper Resistance (R W
)
(ohms)
-0.2
-0.1
0
0.1
0.2
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
-40°C
25°C
85°C
125°C
20
60
100
140
180
220
260
300
0 32 64 96 128 160 192 224 256
Wiper Setting (decimal)
Wiper Resistance (R W
)
(ohms)
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
-40°C
25°C
85°C
125°C
20
40
60
80
100
120
0 32 64 96 128 160 192 224 256
Wiper Setting (decimal)
Wiper Resistance (R W
)
(ohms)
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
-40°C
25°C85°C
125°C
20
60
100
140
180
220
260
300
0 32 64 96 128 160 192 224 256
Wiper Setting (decimal)
Wiper Resistance (Rw)
(ohms)
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
-40°C
25°C85°C
125°C
MCP454X/456X/464X/466X
DS22107B-page 30 2008-2013 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-43: 100 k
– Nominal
Resistance (
) vs. Ambient Temperature and
VDD.
FIGURE 2-44: 100 k
– RWB (
) vs. Wiper
Setting and Ambient Temperature.
98500
99000
99500
100000
100500
101000
101500
102000
102500
103000
103500
-40 0 40 80 120
Ambient Temp erature (°C)
Nominal Resist ance (R AB
)
(Ohms)
2.7V
5.5V
1.8V
0
20000
40000
60000
80000
100000
120000
0 32 64 96 128 160 192 224 256
Wiper Setting (decimal)
Rwb (Ohms)
-40°C
25°C
85°C
125°C
2008-2013 Microchip Technology Inc. DS22107B-page 31
MCP454X/456X/464X/466X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-45: 100 k
– Low-Voltage
Decrement Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
FIGURE 2-46: 100 k
– Low-Voltage
Decrement Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
FIGURE 2-47: 100 k
– Low-Voltage
Increment Wiper Settling Time (VDD =5.5V)
(1 µs/Div).
FIGURE 2-48: 100 k
– Low-Voltage
Increment Wiper Settling Time (VDD = 2.7V)
(1 µs/Div)
MCP454X/456X/464X/466X
DS22107B-page 32 2008-2013 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-49: Resistor Network 0 to
Resistor Network 1 RAB (5 k
) Mismatch vs. VDD
and Temperature.
FIGURE 2-50: Resistor Network 0 to
Resistor Network 1 RAB (10 k
) Mismatch vs.
VDD and Temperature.
FIGURE 2-51: Resistor Network 0 to
Resistor Network 1 RAB (50 k
) Mismat ch vs.
VDD and Temperature.
FIGURE 2-52: Resistor Network 0 to
Resistor Network 1 RAB (100 k
) Mismatch vs.
VDD and Temperature.
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.1
-40 0 40 80 120
Temperature (°C)
%
5.5V
3.0V
-0.04
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0.04
-40 0 40 80 120
Temperature (°C)
%
5.5V
3.0V
0
0.02
0.04
0.06
0.08
0.1
0.12
-40 0 40 80 120
Temperature (°C)
%
5.5V
3.0V
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0.04
0.05
-40 10 60 110
Temperature (°C)
%
5.5V
3.0V
2008-2013 Microchip Technology Inc. DS22107B-page 33
MCP454X/456X/464X/466X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-53: VIH (SD A, SCL) vs. VDD and
Temperature.
FIGURE 2-54: VIL (SDA, SCL) vs. VDD and
Temperature.
FIGURE 2-55: VOL (SDA) vs. VDD and
Temperature (IOL = 3 mA).
1
1.5
2
2.5
3
3.5
4
-40 0 40 80 120
Temperature (°C)
VIH (V)
5.5V
2.7V
1
1.5
2
-40 0 40 80 120
Temperature (°C)
VIL (V)
5.5V
2.7V
50
70
90
110
130
150
170
190
210
230
-40 0 40 80 120
Temperature (°C)
VOL (mV)
5.5V
2.7V
MCP454X/456X/464X/466X
DS22107B-page 34 2008-2013 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C,
VDD = 5V, VSS = 0V.
FIGURE 2-56: Nominal EE PROM Write
Cycle Time vs. VDD and Temperature.
FIGURE 2-57: POR/BOR Trip Point vs.
VDD and Temperature.
2.1 Test Circuits
FIGURE 2-58: -3 db Gain vs. Frequency
Test.
FIGURE 2-59: RBW and RW Measurement.
3.0
3.2
3.4
3.6
3.8
4.0
4.2
-40 0 40 80 120
Temperature (°C)
tWC (ms)
0
0.2
0.4
0.6
0.8
1
1.2
-40 0 40 80 120
Temperature (°C)
VDD (V)
2.7V
5.5V
+
-
VOUT
2.5V DC
+5V
A
B
W
Offset
GND
VIN
A
B
W
IW
VW
floating
RBW = VW/IW
VA
VB RW = (VW-VA)/IW
2008-2013 Microchip Technology Inc. DS22107B-page 35
MCP454X/456X/464X/466X
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
Additional descriptions of the device pins follow.
TABLE 3-1: PINOUT DESCRIPTION FOR THE MCP454X/456X/464X/466X
Pin
Weak
Pull-up/
down (1)S tandard Func tion
Single Dual
Symbol I/O Buffer
Type
Rheo Pot (1)Rheo Pot
8L 8L 10L 14L 16L
1 1 1 1 16 HVC/A0 I HV w/ST “smart” High Voltage Command /
Address 0.
2 2 2 2 1 SCL I HV w/ST No I2C clock inpu t.
3 3 3 3 2 SDA I/O HV w/ST No I2C serial data I/O. Open Drain
output
44443, 4 V
SS — P — Ground
— — 5 5 5 P1B A Analog No Potentiometer 1 Terminal B
— — 6 6 6 P1W A Analog No Potentiometer 1 Wiper Terminal
— — — 7 7 P1A A Analog No Potentiometer 1 Terminal A
— 5 — 8 8 P0 A A Analog No Potentiom eter 0 Terminal A
5 6 7 9 9 P0W A Analog No Potentiometer 0 Wiper Terminal
6 7 8 10 10 P0 B A Analog No Potentiometer 0 Terminal B
———1112 WP I HV w/ST “smart” Hardware EEPROM Write
Protect
— — — 12 13 A2 I HV w/ST “smart” Address 2
7 — 9 13 14 A1 I HV w/ST “smart” Address 1
8 8 10 14 15 VDD — P — Positive Power Supply Input
— — — — 11 NC — — — No Connection
9 9 11 — 17 EP — — — Exposed Pad (Note 2)
Legend: HV w/ST = High Voltage tolerant input (with Schmidtt trigger input)
A = Analog pins (Potentiometer terminals) I = digital input (high Z)
O = digital output I/O = Input / Output
P = Power
Note 1: The pin’s “smart” pull-up shuts off while the pin is forced low. This is done to reduce the standby and shut-
down current.
2: The DFN and QFN packages have a contact on the bottom of the package. This contact is conductively
connec ted to the die su bst rate, and ther efore sh ould be uncon nected or conne cted to the sam e groun d as
the device’s VSS pin.
MCP454X/456X/464X/466X
DS22107B-page 36 2008-2013 Microchip Technology Inc.
3.1 High Voltage Command / Address 0
(HVC/A0)
The HVC/A0 pin is the Address 0 input for the I2C
interfac e as we ll as th e High Voltage Co mm an d pi n. At
the devic e’ s POR/BOR , the value of the A0 ad dress bit
is latched. This input, along with the A2 and A1 pins,
completes the device address. This allows up to eight
MCP45xx/46xx devices on a single I2C bus.
During normal operation, the the voltage on this pin
determines if the I2C command is a normal command
or a High Voltage command (when HVC/A0 = VIHH).
3.2 Serial Clock (SCL)
The SCL pin is the serial interfaces Serial Clock pin.
This pin is connected to the Host Controllers SCL pin.
The MCP45XX/46XX is a slave device, so its SCL pin
accepts only external clock signals.
3.3 Serial Data (SDA)
The SDA pin is the serial interfaces Serial Data pin.
This pin is connected to the Host Controllers SDA pin.
The SDA pin is an open-drain N-channel driver.
3.4 Ground (VSS)
The VSS pin is the device ground reference.
3.5 Potentiometer Terminal B
The terminal B pin is connected to the internal
potentiometer ’s terminal B.
The potentiometer’s terminal B is the fixed connection
to the Ze ro Sc al e w i per va lue of the digital potentiom e-
ter. This corresponds to a wiper value of 0x00 for both
7-bit and 8-bit devices.
The terminal B pin does not have a polarity relative to
the terminal W or A pins. The terminal B pin can
support b oth positive and negative cu rrent. The volt age
on terminal B must be between VSS and VDD.
MCP46XX devices have two terminal B pins, one for
each resistor network.
3.6 Potentiometer Wiper (W) Terminal
The termi nal W pin is con nected to the int ernal po ten ti-
ometer’s terminal W (the wiper). The wiper terminal is
the adju st able termi nal of the digit al potenti ometer. The
terminal W pin does not have a polarity relative to
terminals A or B pins. The terminal W pin can support
both positive and negative current. The voltage on
terminal W must be between VSS and VDD.
MCP46XX devices have two terminal W pins, one for
each resistor network.
3.7 Potentiometer Terminal A
The terminal A pin is available on the MCP4XX1
devices, and is connected to the internal potentiome-
ter’s terminal A.
The potentiometer’s terminal A is the fixed connection
to the Full-Scale wiper value of the digital potentiome-
ter. This corre sponds to a wiper valu e of 0x100 for 8-b it
devices or 0x80 for 7-bit devices.
The terminal A pin does not have a polarity relative to
the terminal W or B pins. The terminal A pin can
support b oth positive and negative curr ent. The volt age
on terminal A must be between VSS and VDD.
The terminal A pin is not available on the MCP4XX2
devices, and the internally terminal A signal is floating.
MCP46X1 devices have two terminal A pins, one for
each resistor network.
3.8 Write Protect (WP)
The WP pin is used to force the nonvolatile memory to
be write protected.
3.9 Address 2 (A2)
The A2 pin is the I2C interface’s Address 2 pin. Along
with the A1 and A0 pins, up to 8 MCP45XX/46XX
devices can be on a single I2C bus.
3.10 Address 1 (A1)
The A2 pin is the I2C interface’s Address 1 pin. Along
with the A2 and A0 pins, up to 8 MCP45XX/46XX
devices can be on a single I2C bus.
3.11 Positive Power Supply Input (VDD)
The VDD pin is the device’s positive power supply input.
The input power supply is relative to VSS.
While the device VDD < Vmin (2.7V), the electrical
perfor mance of the d evice may not m eet the dat a sheet
specifications.
3.12 No Connect (NC)
These pins should be either connected to VDD or VSS.
3.13 Exposed Pad (EP)
This p ad i s condu ctively connect ed to t he device’ s sub-
strate. Th is p ad sh ould be tied to the sam e pote ntial a s
the VSS pin (or left unconnected). This pad could be
used to assist as a heat sink for the device when con-
nected to a PCB heat sink.
2008-2013 Microchip Technology Inc. DS22107B-page 37
MCP454X/456X/464X/466X
4.0 FUNCTIONAL OVERVIEW
This Data Sheet covers a family of thirty-two Digital
Potentiometer and Rheostat devices that will be
referred to as MCP4XXX. The MCP4XX1 devices are
the Potentiometer configuration, while the MCP4XX2
devices are the Rheostat configuration.
As the Device Block Diagram shows, there are four
main functional blocks. These are:
•POR/BOR Operation
•Memory Map
•Resistor Network
•Serial Interface (I2C)
The POR/BOR operation and the Memory Map are
discus sed i n this secti on and t he Re sisto r Network and
I2C operation are described in their own sections. The
Device Commands commands are discussed in
Section 7.0 “Device Commands”.
4.1 POR/BOR Operation
The Power-on Reset is the case where the device has
power applied to it, starting from the VSS level. The
Brown-out Reset occurs when power is applied to the
device , and tha t po wer (vol tag e) drops below the s pec-
ified range.
The device’s RAM retention voltage (VRAM) is lower
than the POR/BOR voltage tri p point (VPOR/VBOR). Th e
maximum VPOR/VBOR voltage is less than 1.8V.
When VPOR/VBOR < VDD < 2.7V, the electrical
performance may not meet the data sheet
specifications. In this region, the device is capable of
reading and writing to its EEPROM and incrementing,
decrementing, reading and writing to its volatile
memory if the proper serial command is executed.
4.1.1 POWER-ON RESET
When the device powers up, the device VDD will cross
the VPOR/VBOR vo lta ge. Onc e the VDD voltage c ros se s
the VPOR/VBOR voltage the following happens:
• Volatile wiper register is loaded with value in the
corresponding nonvolatile wiper register
• The TCON register is loaded its default value
• The device is capable of digital operation
4.1.2 BROWN-OUT RESET
When the device powers down, the device VDD will
cross the VPOR/VBOR voltage.
Once the VDD voltage decreases below the VPOR/VBOR
voltage the following happens:
• Serial Inte rfac e is disabled
• EEPROM Writes are disabled
If the VDD voltage decreases below the VRAM voltage
the following happens:
• Volatile wiper registers may become corrupted
• TCON register may become corrupted
As the voltage recovers above the VPOR/VBOR volta ge
see Section 4.1.1 “Power-on Reset”.
Serial commands not completed due to a brown-out
conditi on m ay ca us e the memory loca tio n (vol ati le an d
nonvolatile) to become corrupted.
4.2 Memory Map
The device memory is 1 6 loc at ions that are 9-bits wide
(16x9 bits). This memory space contains both volatile
and nonvolatile locations (see Table 4-1).
TABLE 4-1: MEMORY MAP
Address Function Memory Type
00h Volatile Wip er 0 RAM
01h Volatile Wip er 1 RAM
02h Nonvolatile Wiper 0 EEPROM
03h Nonvolatile Wiper 1 EEPROM
04h Volatile TCON Register RAM
05h Status Register RAM
06h Data EEPROM EEPROM
07h Data EEPROM EEPROM
08h Data EEPROM EEPROM
09h Data EEPROM EEPROM
0Ah Data EEPROM EEPROM
0Bh Data EEPROM EEPROM
0Ch Data EEPROM EEPROM
0Dh Data EEPROM EEPROM
0Eh Data EEPROM EEPROM
0Fh Data EEPROM EEPROM
MCP454X/456X/464X/466X
DS22107B-page 38 2008-2013 Microchip Technology Inc.
4.2.1 NONVOLAT I LE ME MORY
(EEPROM)
This memory can be grouped into two uses of nonvol-
atile memory. These are:
•General Pur pose Registers
•Nonvolatile Wiper Registers
The nonvolatile wipers starts functioning below the
devi ces VPOR/VBOR trip point.
4.2.1.1 General Purpose Registers
These locations allow the user to store up to 10 (9-bit)
locations worth of information.
4.2.1.2 Nonvolatile Wiper Registers
These locations contain the wiper values that are
loaded into the corresponding volatile wiper register
whene ver the device ha s a POR/BOR event . There are
up to two registers, one for each resistor network.
The nonvolatile wiper register enables stand-alone
operatio n of the device (without Mi crocontroller co ntrol)
after being programmed to the desired value.
4.2.1.3 Factor y Initia li zat ion of Nonvol atile
Memory (EEPROM)
The Nonvolatile Wiper values will be initialized to
mid-scale value. This is shown in Table 4-2.
The General purpose EEPROM memory will be
programmed to a default value of 0xFF.
It is good practice in the manufacturing flow to
configure the device to your desired settings.
TABLE 4-2: DEFAULT FACTORY
SETTINGS SELECTION
4.2.1.4 Special Features
There are three nonvolatile bits that are not directly
mapped into the address space. These bits control the
following functions:
• EEPROM Write Protect
• WiperLock Technology for Nonvolatile Wiper 0
• WiperLock Technology for Nonvolatile Wiper 1
The opera tion of Wip erLock Technology is d iscussed in
Section 5.3. The state of the WL0, WL1, and WP bits
is reflected in the STATUS register (see Register 4-1).
EEPROM Write Protect
All internal EEPROM memory can be Write Protected.
When EEPROM memory is Write Protected, Write
commands to the internal EEPROM are prevented.
Write Protect (WP) can be enabled/disabled by two
methods. These are:
•External WP
Hardware pin (MCP46X1 devices
only)
• Nonvolatile configuration bit
High Voltage commands are required to enable and
disable the nonvolatile WP bit. These commands are
shown in Section 7.8 “Modify Write Protect or Wip-
erLock Technology (High Voltage)”.
To write to EEPROM, b oth the ex ternal W P pin an d the
internal WP EEPROM bit must be disabled. Write
Protect does not block commands to the volatile
registers.
4.2.2 VOLATI LE ME MORY (RA M)
There are four Volatile Memory locations. These are:
• Volatile Wiper 0
• Volatile Wiper 1
(Dual Resistor Network devices only)
• S tatus Register
• Terminal Control (TCON) Register
The volatile memory starts functioning at the RAM
retention voltage (VRAM).
Resistance
Code
Typical
RAB Value
Default POR
Wiper Setting
Wiper
Code
WiperLock™
Technology and
Wr ite Protect Settin g
8-bit 7-bit
-502 5.0 kMid-scale 80h 40h Disabled
-103 10.0 kMid-scale 80h 40h Disabled
-503 50.0 kMid-scale 80h 40h Disabled
-104 100.0 kMid-scale 80h 40h Disabled
2008-2013 Microchip Technology Inc. DS22107B-page 39
MCP454X/456X/464X/466X
4.2.2.1 Status (STATUS) Register
This register contains four status bits. These bits show
the state of the WiperLock bits, the Write Protect bit,
and if an EEPROM write cycle is active. The STATUS
register can be accessed via the READ commands.
Register 4-1 describes each STATUS register bit.
The STATUS register is placed at Address 05h.
REGISTER 4-1: STATUS REGISTER (ADDRESS = 0x05)
R-1 R-1 R-1 R-1 R-1 R-0 R-x R-x R-x
D8:D4 EEWA WL1 (1) WL0 (1) WP (1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 8-4 D8:D4: Reserved. Forced to “1”
bit 3 EEWA: EEPROM Write Active Status bit
This bit indicates if the EEPROM Write Cycle is occurring.
1 = An EEPROM Write cycle is currently occurring. Only serial commands to the Volatile memory
locations are allowed (addresses 00h, 01h, 04h, and 05h)
0 = An EEPROM Write cycle is NOT currently occurring
bit 2 WL1: WiperLock Status bit for Resistor Network 1 (Refer to Section 5.3 “WiperLock™ Technology”
for further information)
WiperLock (WL) prevents the Volatile and Nonvolatile Wiper 1 addresses and the TCON register bits
R1HW, R1A, R1W, and R1B from be ing written to. H igh Volt age comma nds are req ui red to enab le an d
disable WiperLock Technology.
1 = Wiper and TCON register bits R1HW, R1A, R1W, and R1B of Resistor Network 1 (Pot 1) are
“Locked” (Write Protected)
0 = Wiper and TCON of Resistor Network 1 (Pot 1) can be modified
Note: The WL1 bit always reflects the result of the last programming cycle to the nonvolatile WL1
bit. After a POR or BOR event, the WL1 bit is loaded with the nonvolatile WL1 bit value.
bit 1 WL0: WiperLock Status bit for Resistor Network 0 (Refer to Section 5.3 “WiperLock™ Technology”
for further information)
The WiperL ock Technolog y bit s (WLx) prev ent s the Volati le and Non volat ile Wip er 0 addres ses a nd the
TCON register bits R0HW, R0A, R0W, and R0B from being written to. High Voltage commands are
required to enable and disable WiperLock Technology.
1 = Wiper and TCON register bits R0HW, R0A, R0W, and R0B of Resistor Network 0 (Pot 0) are
“Locked” (Write Protected)
0 = Wiper and TCON of Resistor Network 0 (Pot 0) can be modified
Note: The WL0 bit always reflects the result of the last programming cycle to the nonvolatile WL0
bit. After a POR or BOR event, the WL0 bit is loaded with the nonvolatile WL0 bit value.
Note 1: Requires a High Voltage command to modify the state of this bit (for nonvolatile devices only). This bit is
not directly written, but reflects the system state (for this feature).
MCP454X/456X/464X/466X
DS22107B-page 40 2008-2013 Microchip Technology Inc.
bit 0 WP: EEPROM Write Protect Status bit (Refer to the section EEPROM Write Protect for further
information)
This bit indicates the status of the write protection on the EEPROM memory. When Write Protect is
enabled, writes to all nonvolatile memory are prevented. This includes the General Purpose EEPROM
memory, and the nonvolatile Wiper registers. Write Protect does not block modification of the volatile
wiper register values or the volatile TCON register value (via Increment, Decrement, or Write
commands).
This status bit is an OR of the devices Write Protect pin (WP) and the internal nonvolatile WP bit. High
Voltage commands are required to enable and disable the internal WP EEPROM bit.
1 = EEPROM memory is Write Protected
0 = EEPROM memory can be written
REGISTER 4-1: STATUS REGISTER (ADDRESS = 0x05) (CONTINUED)
Note 1: Requires a High Voltage command to modify the state of this bit (for nonvolatile devices only). This bit is
not directly written, but reflects the system state (for this feature).
2008-2013 Microchip Technology Inc. DS22107B-page 41
MCP454X/456X/464X/466X
4.2.2.2 Terminal Control (TCON) Register
This register cont ains eight control bits. Four bits are for
Wiper 0, and four bits are for Wiper 1. Register 4-2
describes each bit of the TCON register.
The state of each resistor network terminal connection
is individually controlled. That is, each terminal
connec tion (A, B and W) c an be individu ally conne cted/
discon nected f rom the r esist or network. This al lows th e
system to minimize the currents through the digital
potentiometer.
The value that is written to this register will appear on
the resistor network terminals when the serial
comma nd has comple ted.
When the WL1 bit is enabled, writes to the TCON
register bits R1HW, R1A, R1W, and R1B are inhibited.
When the WL0 bit is enabled, writes to the TCON
register bits R0HW, R0A, R0W, and R0B are inhibited.
On a POR/BOR this register is loaded with 1FFh
(9-bits), for all terminals connected. The Host
Controller needs to detect the POR/BOR event and
then update the Volati le TCON regi ste r valu e.
Additionally, there is a bit which enables the operation
of General Call commands.
MCP454X/456X/464X/466X
DS22107B-page 42 2008-2013 Microchip Technology Inc.
REGISTER 4-2: TCON BITS (ADDRESS = 0x04) (1)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
GCEN R1HW R1A R1W R1B R0HW R0A R0W R0B
bit 8 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 8 GCEN: General Call Enable bit
This bit specifies if I2C General Call commands are accepted
1 = Enable Device to “Accept” the General Call Address (0000h)
0 = The General Call Address is disabled
bit 7 R1HW: Resistor 1 Hardware Configuration Control bit
This bit forces Resistor 1 into the “shutdown” configuration of the Hardware pin
1 = Resistor 1 is NOT forced to the hardware pin “shutdown” configuration
0 = Resistor 1 is forced to the hardware pin “shutdown” configuration
bit 6 R1A: Resistor 1 Terminal A (P1A pin) Connect Control bit
This bit connects/disconnects the Resistor 1 Terminal A to the Resistor 1 Network
1 = P1A pin is connected to the Resistor 1 Network
0 = P1A pin is disconnected from the Resistor 1 Network
bit 5 R1W: Resistor 1 Wiper (P1W pin) Connect Control bit
This bit connects/disconnects the Resistor 1 Wiper to the Resistor 1 Network
1 = P1W pin is connected to the Resistor 1 Network
0 = P1W pin is disconnected from the Resistor 1 Network
bit 4 R1B: Resistor 1 Terminal B (P1B pin) Connect Control bit
This bit connects/disconnects the Resistor 1 Terminal B to the Resistor 1 Network
1 = P1B pin is connected to the Resistor 1 Network
0 = P1B pin is disconnected from the Resistor 1 Network
bit 3 R0HW: Resistor 0 Hardware Configuration Control bit
This bit forces Resistor 0 into the “shutdown” configuration of the Hardware pin
1 = Resistor 0 is NOT forced to the hardware pin “shutdown” configuration
0 = Resistor 0 is forced to the hardware pin “shutdown” configuration
bit 2 R0A: Resistor 0 Terminal A (P0A pin) Connect Control bit
This bit connects/disconnects the Resistor 0 Terminal A to the Resistor 0 Network
1 = P0A pin is connected to the Resistor 0 Network
0 = P0A pin is disconnected from the Resistor 0 Network
bit 1 R0W: Resistor 0 Wiper (P0W pin) Connect Control bit
This bit connects/disconnects the Resistor 0 Wiper to the Resistor 0 Network
1 = P0W pin is connected to the Resistor 0 Network
0 = P0W pin is disconnected from the Resistor 0 Network
bit 0 R0B: Resistor 0 Terminal B (P0B pin) Connect Control bit
This bit connects/disconnects the Resistor 0 Terminal B to the Resistor 0 Network
1 = P0B pin is connected to the Resistor 0 Network
0 = P0B pin is disconnected from the Resistor 0 Network
Note 1: These bits do not affect the wiper register values.
2008-2013 Microchip Technology Inc. DS22107B-page 43
MCP454X/456X/464X/466X
5.0 RESISTOR NETWORK
The Resistor Network has either 7-bit or 8-bit resolu-
tion. Each Resistor Network allows zero scale to
full-scale connections. Figure 5-1 shows a block dia-
gram for the resistive network of a device.
The Resistor Network is made up of several parts.
These include:
• Resistor Ladder
•Wiper
• Shutdown (Terminal Connections)
Devices have either one or two resistor networks,
These are referred to as Pot 0 and Pot 1.
FIGURE 5-1: Resistor Block Diagram.
5.1 Resistor Ladder Module
The resistor ladder is a series of equal value resistors
(RS) with a connection point (tap) between the two
resistors. The total number of resistors in the series
(ladder) determines the RAB resistance (see
Figure 5-1). The end points of the resistor ladder are
connected to analog switches which are connected to
the device Terminal A and Terminal B pins. The RAB
(and RS) resistance has small variations over voltage
and temperature.
For an 8-bit device, there are 256 resistors in a string
between terminal A and terminal B. The wiper can be
set to t ap onto any of these 256 re sistors thus providing
257 possible settings (including terminal A and terminal
B).
For a 7-bit device, there are 128 resistors in a string
between terminal A and terminal B. The wiper can be
set to t ap onto any of these 128 re sistors thus providing
129 possible settings (including terminal A and terminal
B).
Equation 5-1 shows the calculation for the step
resistance.
EQUATION 5-1: RS CALCULATION
RS
A
RS
RS
RS
B
256
255
254
1
0
RW (1)
W
(01h)
Analog Mux
RW (1) (00h)
RW (1) (FEh)
RW (1) (FFh)
RW (1) (100h)
Note 1: The wiper resistance is dependent on
several factors including, wiper code,
device VDD, Terminal voltages (on A, B,
and W), and temperature.
Also for the same conditions, each tap
selection resistance has a small variation.
This RW variation has greater effects on
some specifications (such as INL) for the
smaller resistance devices (5.0 k)
compared to larger resistance devices
(100.0 k).
RAB
8-Bit
N = 128
127
126
1
0
(01h)
(00h)
(7Eh)
(7Fh)
(80h)
7-Bit
N =
RSRAB
256
-------------=
RSRAB
128
--------------=
8-bit Device
7-bit Device
MCP454X/456X/464X/466X
DS22107B-page 44 2008-2013 Microchip Technology Inc.
5.2 Wiper
Each tap point (between the RS resistors) is a
connection point for an analog switch. The opposite
side of the analog switch is connected to a common
signal which is connected to the Terminal W (Wiper)
pin.
A value in the volatile wiper register selects which
analog switch to close, connecting the W terminal to
the selected node of the resistor ladder.
The wiper can connect directly to Terminal B or to
Terminal A. A zero-scale con nectio n, conne ct s the Ter-
minal W (wiper) to Terminal B (wiper setting of 0 00h). A
full-scale connection, connects the Terminal W (wiper)
to Terminal A (wiper setting of 100h or 80h). In these
configurations, the only resistance between the Termi-
nal W and the other Terminal (A or B) is that of the an a-
log switches.
A wiper setting value greater than full-scale (wiper
setting of 100h for 8- bit dev ic e or 8 0h for 7 - bi t de vi ce s)
will also be a Full-Scale setting (Terminal W (wiper)
connected to Terminal A). Table 5-1 illustrates the full
wiper setting map.
Equation 5-2 illustrates the calculation used to deter-
mine the resi stance between the wiper and termin al B.
EQUATION 5-2: RWB CALCULATION
TABLE 5-1: VOLATILE WIPER VALUE VS.
WIPER POSITION MAP
5.3 Wiper Lock™ Technology
The MCP4XXX device’s WiperLock technology allows
application-specific calibration settings to be secured in
the EEPROM witho ut requi ring th e use of an additi onal
write-pr otect pi n. There are two WiperL ock Technolog y
configuration bits (WL0 and WL1). These bits prevent
the Nonvolatile and Volatile addresses and bits for the
specified resistor network from being written.
The WiperLock technology prevents the serial
commands from doing the following:
• Changing a volatile wiper value
• Writing to a nonvolatile wiper memory location
• Changing the volatile TCON register value
For either Resistor Network 0 or Resistor Network 1
(Potx), the WLx bit controls the following:
• Nonvolatile Wiper Register
• Volatile Wiper Register
• V olatile TCON register bits RxHW , RxA, RxW , and
RxB
High Voltage commands are required to enable and
disable WiperLock. Please refer to the Modify Write
Protect or WiperLock Technology (High Voltage)
command for opera t io n.
5.3.1 POR/BOR OPERATION WHEN
WIPERLOCK TECHNOLOGY
ENABLED
The WiperLock Technology state is not affected by a
POR/BOR event. A POR/BOR event will load the
V o latile Wiper regi ster value with the Nonvolati le Wiper
register value, refer to Section 4.1.
Wiper Setting Properties
7-bit Pot 8-bit Pot
3FFh
081h 3FFh
101h Reserv ed (Ful l-Scale (W = A)),
Increment and Decrement
commands ignored
080h 100h Full-Scale (W = A),
Increment commands ignored
07Fh
041h 0FFh
081 W = N
040h 080h W = N (Mid-Scale)
03Fh
001h 07Fh
001 W = N
000h 000h Zero Scale (W = B)
Decrement command ignored
RWB RABN
256
--------------R
W
+=
N = 0 to 256 (decimal)
RWB RABN
128
--------------R
W
+=
N = 0 to 128 (decimal)
8-bit Device
7-bit Device
TABLE 5-2: DEFAULT FACTORY
SETTING S SE LECT ION
Resistance
Code
Typical
RAB Value
Factory Default POR
Wiper Set ting
Wiper Code
8-bit 7-bit
-502 5.0 kMid-scale 80h 40h
-103 10.0 kMid-scale 80h 40h
-503 50.0 kMid-scale 80h 40h
-104 100.0 kMid-scale 80h 40h
2008-2013 Microchip Technology Inc. DS22107B-page 45
MCP454X/456X/464X/466X
5.4 Shutdown
Shutdown is used to minimize the device’s current
consum ption. The MCP4XXX achi eves this t hrough the
Terminal Control Register (TCON).
5.4.1 TERMINAL CONTROL REGISTER
(TCON)
The Terminal Control (TCON) register is a volatile
register used to configure the connection of each
resistor network terminal pin (A, B, and W) to the
Resistor Network. This bits are described in
Register 4-2.
When the RxHW bit is a “0”, the selected resistor net-
work is forced into the following state:
• The PxA terminal is disconnected
• The PxW terminal is sim ul taneously connec ted to
the PxB terminal (see Figure 5-2)
• The Serial I nter face is NOT disabled , and all
Serial Interface activity is executed
• Any EEPROM write cycles are completed
Alternate low power configurations may be achieved
with the RxA, RxW, and RxB bits.
FIGURE 5-2: Resistor Network Shutdown
Configuration.
5.4.2 INTERACTION OF RxHW BIT AND
RxA, RxW, AND RxB BITS (TCON
REGISTER)
Using the T CON bi t s a llo w s ea ch resi stor network (Pot
0 and Pot 1) to be individually “shutdown”.
The state of the RxHW bit does NOT corrupt the other
bit values in the TCON register nor the value of the
Volatile Wiper Registers. When the Shutdown mode is
exited (RxHW changes state from “0” to “1”):
• The device returns to the Wiper setting specified
by the Volatile Wiper value
• The RxA, RxB, and RxW bits return to controlling
the terminal connection state of that resistor net-
work
Note 1: The Rx HW bits are id entical t o th e Rx H W
bits of the MCP41XX/42XX devices. The
MCP42XX devices also have a SHDN
pin which forces the resistor network into
the same state as that resistor networks
RxHW bit.
2: When RxHW = “0”, the st ate of the TCON
register RxA, RxW, and RxB bits is over-
ridden (ignored). When the state of the
RxHW bit returns to “1”, the TCON
register Rx A, RxW, and RxB bit s return to
controlling the terminal connection state.
In other words, the RxHW bit does not
corrupt the state of the RxA, RxW, and
RxB bits.
A
B
W
Resistor Network
MCP454X/456X/464X/466X
DS22107B-page 46 2008-2013 Microchip Technology Inc.
NOTES:
2008-2013 Microchip Technology Inc. DS22107B-page 47
MCP454X/456X/464X/466X
6.0 SERIAL INTERFACE (I2C)
The MCP45XX/46XX devices support the I2C serial
protocol. The MCP45XX/46XX I2C’s module operates
in Slave mode (does not generate the serial clock).
Figure 6-1 shows a typical I2C Interface connecti on. All
I2C interface signals are high-voltage tolerant.
The MCP45XX/46XX devices use the two-wire I2C
serial i nte rfac e. Th is int erfa ce c an ope rate in s t an da rd,
fast or High-Speed mode. A device that sends data
onto the bus is defined as transmitter, and a device
receivi ng dat a as receiver. The bu s has to be co ntrolled
by a master device which generates the serial clock
(SCL), controls the bus access and generates the
START and STOP conditions. The MCP45XX/46XX
device works as slave. Both master and slave can
operate as transmitter or receiver, but the master
devi ce det ermine s whi ch mo de is ac tiva ted. Co mmun i-
cation is initiated by the master (microcontroller) which
sends the START bit, followed by the slave address
byte. The first byte transmitted is always the slave
address byte, which contains the device code, the
address bits, and the R/W bit.
Refer to the Phillips I2C document for more details of
the I2C specifications.
FIGURE 6-1: Typical I2C Interface Block
Diagram.
6.1 Signal Descriptions
The I2C interface uses up to five pins (signals). These
are:
• SDA (Serial Data)
• SCL (Serial Clock)
• A0 (Address 0 bit)
• A1 (Address 1 bit)
• A2 (Address 2 bit)
6.1.1 SERIAL DATA (SDA)
The Serial Data (SDA) signal is the data signal of the
device. The value on this pin is latched on the rising
edge of the SCL signal when the signal is an input.
With the exception of the ST AR T and STO P conditions ,
the high or low state of the SDA pin can only change
when th e cloc k signal on the SC L pin is low. During th e
high period of the clock the SDA pin’s value (high or
low) must be stable. Changes in the SDA pin’s value
while the SCL pin is HIGH will be interpreted as a
START or a STOP condition.
6.1.2 SERIAL CLOCK (SCL)
The Serial Clock (SCL) signal is the clock signal of the
device. The rising edge of the SCL signal latches the
value on the SDA pin. The MCP45XX/46XX supports
three I2C interface clock modes:
• Standard Mode: clock rates up to 100 kHz
• Fast Mode: clock rates up to 400 kHz
• High-Speed Mode (HS mode): clock rates up to
3.4 MHz
The MCP4XXX will not strech the clock signal (SCL)
since memory read acceses occur fast enough.
Depending on the clock rate mode, the interface will
display different characteristics.
6.1.3 THE ADDRESS BITS (A2:A1:A 0)
There are up to three har dware pins used to specify the
device address. The number of adress pins is
determined by the part number.
Address 0 is multiplexed with the High Voltage
Command (HVC) functi on. So the state of A0 is latche d
on the MCP4XXX’s POR/BOR event.
The st ate of the A2 an d A1 pins should be static , that is
they should be tied high or tied low.
6.1.3.1 The High Voltage Command (HVC)
Signal
The High Voltage Command (HVC) signal is multi-
plexed w i th Add res s 0 (A0 ) and is used to indicate th at
the command, or sequence of commands, are in the
High Voltage mode. High Voltage commands allow the
device’s WiperLock Technology and write protect
features to be enabled and disabled.
The HVC pin has an internal resistor connection to the
MCP45XX/46XXs internal VDD signal.
SCL
SCL
MCP4XXX
SDA
SDA
HVC/A0 (2)
I/O (1)
Host
Controller
Typical I2C Interface Connections
Note 1: If High voltage commands are desired,
some type of external circuitry needs to
be implemented.
2: These pins have internal pull-ups. If
faster rise times are required, then
external pull-ups should be added.
3: This pin could be tied high, low, or
connected to an I/O pin of the Host
Controller.
A1 (2, 3)
A2 (2, 3)
MCP454X/456X/464X/466X
DS22107B-page 48 2008-2013 Microchip Technology Inc.
6.2 I2C Operation
The MCP45XX/46XX’s I2C module is compatible with
the Phil ips I2C speci fication. The follo wing li sts s ome of
the modules features:
• 7-bit slave addressing
• Supports three clock rate modes:
- Standard mode, clock rates up to 100 kHz
- Fast mode, clock rates up to 400 kHz
- High-speed mode (HS mode), clock rates up
to 3.4 MHz
• Support Multi-Master Applications
• General call addressing
• Internal weak pull-ups on interface signals
The I2C 10-bit addressing mode is not supported.
The Philips I2C specification only defines the field
types, field lengths, timings, etc. of a frame. The frame
content defines the behavior of the device. The frame
content for the MCP4XXX is defined in Section 7.0.
6.2.1 I2C BIT STATES AND SEQUENCE
Figure 6-8 shows t he I2C transf er sequenc e. The seria l
clock is generated by the master. The following defini-
tions are used for the bit states:
• Start bit (S)
• Data bit
• Acknowledge (A) bit (driven low) /
No Ac knowledge (A) bit (not driven low)
• Repeated Start bit (Sr)
• Stop bit (P)
6.2.1.1 Start Bit
The S t art bit (see Figure 6-2) indi cates t he begin ning of
a dat a transfer sequ ence. The S t art bit is de fined as the
SDA signal falling when the SCL signal is “High”.
FIGURE 6-2: Start Bit.
6.2.1.2 Data Bit
The SD A signal m ay cha nge st ate whil e the SC L signa l
is Low. While the SCL signal is High, the SDA signal
MUST be stable (see Figure 6-5).
FIGURE 6-3: Data Bit.
6.2.1.3 Acknowledge (A) Bit
The A bit (see Figure 6-4) is typically a response from
the receiving device to the transmitting device.
Depend ing on the context of the transfer sequenc e, the
A bit may indicate different things. Typically the Slave
device will supply an A response after the Start bit and
eight “data” bits have been received. An A bit has the
SDA signal low.
FIGURE 6-4: Acknowledge Waveform.
Not A (A) Response
The A bit has the SDA signal high. Table 6-1 shows
some of the conditions where the Slave Device will
issue a Not A (A).
If an error cond ition occurs (s uch as an A instea d of A),
then an START bit must be issued to reset the
comma nd st ate machine.
TABLE 6-1: MCP45XX/MCP4 6XX A / A
RESPONSES
SDA
SCL S
1st Bit 2nd Bit
SDA
SCL Data Bit
1st Bit 2nd Bit
Event Acknowledge
Bit
Response Comment
General Call A Only if GCEN bit is
set
Slave Address
valid A
Slave Address
not valid A
Device Mem-
ory Address
and specified
command
(AD3:AD0 and
C1:C0) are an
invalid combi-
nation
AAfter device has
received address
and command
Communica-
tion during
EEPROM write
cycle
A After device has
received address
and command,
and valid condi-
tions for EEPROM
write
Bus Collision N.A. I2C Module
Resets, or a “Don’t
Care” if the colli-
sion oc cu rs on the
Masters “Start bit” .
A
8
D0
9
SDA
SCL
2008-2013 Microchip Technology Inc. DS22107B-page 49
MCP454X/456X/464X/466X
6.2.1.4 Repeated Start Bit
The Repeated Start bit (see Figure 6-5) indicates the
current M aster Device wi shes to contin ue comm unicat-
ing with the current Slave Device without releasing the
I2C bus. T he Repea ted Star t condit ion is the same as
the Start condition, except that the Repeated Start bit
follows a Start bit (with the Data bits + A bit) and not a
Stop bit.
The Start bit is the beginning of a data transfer
sequence and is defined as the SDA signal falling when
the SCL signal is “High”.
FIGURE 6-5: Repeat Start Condition
Waveform.
6.2.1.5 Stop Bit
The Stop bit (see Figure 6-6) Indicates the end of the
I2C Dat a T ransfer Se quence. Th e S top bit i s defined a s
the SDA signal rising when the SCL signal is “High”.
A Stop bit resets the I2C interface of all MCP4XXX
devices.
FIGURE 6-6: Stop Condition Receive or
Transmit Mode.
6.2.2 CLOCK STRETCHING
“Clock Stretching” is something that the receiving
device can do, to allow additional time to “respond” to
the “data” that has been received.
The MCP4XXX will not strech the clock signal (SCL)
since memory read acceses occur fast enough.
6.2.3 ABORTING A TRANSMISSION
If any part of the I2C transmission does not meet the
command format, it is abort ed. This can be intentionally
accom plished wi th a STAR T or ST OP conditi on. This i s
done so that noisy transmissions (usually an extra
START or STOP condition) are aborted before they
corrupt the device.
FIGURE 6-7: Typic al 8- Bit I2C Waveform Format.
FIGURE 6-8: I2C Data St ates and Bit Sequence.
Note 1: A bus collision during the Repeated Start
conditi on oc curs if:
• SDA is sampled low when SCL goes
from low to high.
• SCL goe s low befo re SDA i s asserted
low. This may indicate that another
master is attempting to transmit a
data "1".
SDA
SCL
Sr = Repeated Start
1st Bit
SCL
SDA A / A
P
1st Bit
SDA
SCL
S2nd Bit 3rd Bit 4th Bit 5th Bit 6th Bit 7th Bit 8th Bit PA / A
SCL
SDA
START
Condition STOP
Condition
Data allowed
to change Data or
A valid
MCP454X/456X/464X/466X
DS22107B-page 50 2008-2013 Microchip Technology Inc.
6.2.4 ADDRESSING
The addres s byte is the firs t byte receive d following the
START condition from the master device. The address
cont ain s fou r (o r m ore ) fi xed b it s a nd (up to) three us er
defined hardware address bits (pins A2, A1, and A0).
These 7-bits address the desired I2C device. The
A7:A4 address bits are fixed to “0101” and the device
appends the value of following three address pins (A2,
A1, A0). Address pins that are not present on the
device are pulled up (a bit value of ‘1’).
Since there are up to three adress bits controlled by
hardware pins, there may be up to eight MCP4XXX
devices on the same I2C bus.
Figure 6-9 shows the sl ave addres s byte forma t, whic h
contains the seven address bits. There is also a read/
write bit. Table 6-2 shows the fixed address for device .
Hardware Address Pins
The hardware address bits (A2, A1, and A0)
corresp ond to t he lo gic level on t he asso ciated address
pins. This allows up to eight devices on the bus.
These pin s have a we ak pull-up enab led when th e VDD
< VBOR. The weak pull-up utilizes the “smart” pull-up
technology and e xhibits the same characteristics as the
High-voltage tolerant I/O structure.
The state of the A0 address pin is latch on POR/BOR.
This is required since High Voltage commands force
this pin (HVC/A0) to the VIHH level.
FIGURE 6-9: Slave Address Bits in the
I2C Control Byte.
TABLE 6-2: DEVICE SLAVE ADDRESSES
6.2.5 SLOPE CONTROL
The MCP45XX/46XX implements slope control on the
SDA output.
As the device transitions from HS mode to FS mode,
the slope control parmameter will change from the HS
specification to the FS specification.
For Fast (F S) and H igh -Speed (HS) modes, the device
has a spike suppression and a Schmidt trigger at SDA
and SCL inputs.
Device Address Comment
MCP45X1 ‘0101 11’b + A0 Supports up to 2
devices. Note 1
MCP45X2 ‘0101 1’b + A1:A0 Supports up to 4
devices. Note 1
MCP46X1 ‘0101’b + A2:A1:A0 Supports up to 8
devices. Note 1
MCP46X2 ‘0101 1’b + A1:A0 Supports up to 4
devices. Note 1
Note 1: A0 is used for High-Voltage commands
and the value is latched at POR.
SA6A5A4A3A2 A1 A0 R/W A/A
Start
bit
Slave Address
R/W bit
A bit (controlled by slave device)
R/W = 0 = write
R/W = 1 = read
A = 0 = Slave Device Acknowledges byte
A = 1 = Slave Device does not Acknowledge byte
“0” “1” “0” “1”See Table 6-2
2008-2013 Microchip Technology Inc. DS22107B-page 51
MCP454X/456X/464X/466X
6.2.6 HS MODE
The I2C specification requires that a high-speed mode
device must be ‘activated’ to operate in high-speed
(3.4 Mbit/s) mode. This is done by the Master sending
a special address byte following the START bit. This
byte is referred to as the high-speed Master Mode
Code (HSMMC).
The MCP45XX/46XX device does not acknowledge
this byte. However, upon receiving this command, the
devi ce switch es to HS mo de. The devic e can now com-
municate at up to 3.4 Mbit/s on SDA and SCL lines.
The de vic e will swit ch ou t of t he HS mod e on th e ne xt
STOP condition.
The master code is sent as follows:
1. START condition (S)
2. High-Speed Master Mode Code (0000 1XXX),
The XXX bits are unique to the high-speed (HS)
mode Master.
3. No Acknowledge (A)
After switching to the High-Speed mode, the next
transferre d by te i s t he I2C c ontr ol b yte , w hi ch spe ci fie s
the device to communicate with, and any number of
data bytes plus acknowledgements. The Master
Device can then either issue a Repeated Start bit to
address a differe nt device (at High-S p eed) or a S top b it
to return to Fas t/S tand ard bus speed. After t he S t op bit,
any other Master Device (in a Multi-Master system) can
arbitrate for the I2C bus.
See Figure 6-10 for an illustration of the HS mode com -
mand sequence.
For more information on the HS mode, or other I2C
modes, please refer to the Phillips I2C specification.
6.2.6.1 Slope Control
The slope control on the SDA output is different
betwee n the Fa st/Stand ard Speed and the Hig h-Speed
Clock modes of the interface.
6.2.6.2 Pulse Gobbler
The pulse gobbler on the SCL pin is automatically
adjusted to suppress spikes < 10 ns during HS mode.
FIGURE 6-10: HS Mod e Sequence.
SA ‘0 0 0 0 1 X X X’b Sr A
‘Slave Address’ A/A“Data”
P
S = Start bit
Sr = Repeated Start bit
A = Acknowledge bit
A = Not Acknowledge bit
R/W = Read/Write bit
R/W
P = Stop bit (Stop condition terminates HS Mode)
F/S-mode HS-mode
HS-mode continues
F/S-mode
Sr A
‘Slave Add ress’R/W
HS Select Byte Control Byte Command/D ata Byte(s)
Control Byte
MCP454X/456X/464X/466X
DS22107B-page 52 2008-2013 Microchip Technology Inc.
6.2.7 GENERAL CALL
The General Call is a method that the “Master” device
can communicate with all other “Slave” devices. In a
Multi-Master application, the other Master devices are
operating in Slave mode. The General Call address
has two documented formats. These are shown in
Figure 6-11. We h ave adde d a MCP4 5XX/46XX format
in this figure as well.
This will allow customers to have multiple I2C Digital
Potentiometers on the bus and have them operate in a
synchronous fashion (analogous to the DAC Sync pin
functionality). If these MCP45XX/46XX 7-bit com-
mands conflict with other I2C devices on the bus, then
the cus tom er w il l n eed two I2C buss es a nd ens ure that
the devices are on the correct bus for their desired
application functionality.
Dual Pot devices can not update both Pot0 and Pot1
from a single command. To address this, there are
Gener al Ca ll co mman ds f or th e Wi per 0, Wip er 1, and
the TCON registers.
Table 6-3 shows the General Call Commands. Three
commands are specified by the I2C specification and
are not applicable to the MCP45XX/46XX (so com-
mand is Not Acknowledged) The MCP45XX/46XX
General Call Commands are Acknowledge. Any other
command is Not Acknowledged.
TABLE 6-3: GENERAL CALL COMMANDS
Note: Onl y one General Call command per is sue
of the General C all control byte. Any addi-
tional G eneral Cal l commands are ignore d
and Not Acknowledged.
7-bit
Command
(1, 2, 3) Comment
‘1000 00d’b Write Next Byte (Third Byte) to Volatile
Wiper 0 Register
‘1001 00d’b Write Next Byte (Third Byte) to Volatile
Wiper 1 Register
‘1100 00d’b Write Next Byte (Third Byte) to TCON
Register
‘1000 010’b
or
‘1000 01 1’b
Increment Wiper 0 Register
‘1001 010’b
or
‘1001 01 1’b
Increment Wiper 1 Register
‘1000 100’b
or
‘1000 101’b
Decrement Wiper 0 Register
‘1001 100’b
or
‘1001 101’b
Decrement Wiper 1 Register
Note 1: Any other code is Not Acknowledged.
These codes may be used by other
devices on the I2C bus.
2: The 7-bit com mand al ways app ends a “0”
to form 8-bits. .
3: “d” is the D8 bit for the 9-bit write value.
2008-2013 Microchip Technology Inc. DS22107B-page 53
MCP454X/456X/464X/466X
FIGURE 6-11: General Call Formats.
0000S 0000 XXXXXA XX0AP
General Call Address
Second Byte
“7-bit Comm an d”
Reserved 7-bit Commands (By I2C Specification - Philips # 9398 393 40011, Ver. 2.1 January 2000)
‘0000 011’b - Reset and write programmable part of slave address by hardware.
‘0000 010’b - Write programmable part of slave address by hardware.
‘0000 000’b - NOT Allowed
MCP45XX/MCP46XX 7-bit Commands
‘1000 01x’b - Increment Wiper 0 Register.
‘1001 01x’b - Increment Wiper 1 Register.
The Following is a Microchip Extension to this General Call Format
0000S 0000 XXXXXAXd0A
General Call Address
Second Byte
“7-bit Command”
MCP45XX/MCP46XX 7-bit Commands
‘1000 00d’b - Write Next Byte (Third Byte) to Volatile Wiper 0 Register.
‘1001 00d’b - Write Next Byte (Third Byte) to Volatile Wiper 1 Register.
ddddd dddAP
Thi rd Byt e
The Following is a “Hardware General Call” Format
0000S0000 XXXXXA XX1A
General Call Addr ess
Second Byte
“7-bit Command”
XXXXX XXXAP
n occurrenc es of (Data + A)
This indi cates a “Hardware General Call”
MCP45XX/MCP46XX will ignore this byte and
all following bytes (and A), until
‘1000 10x’b - Decrement Wiper 0 Register.
‘1001 10x’b - Decrement Wiper 1 Register.
‘1100 00d’b - Write Next Byte (Third Byte) to TCON Register.
a Stop bit (P) is encountered.
“0” for General Call Command
MCP454X/456X/464X/466X
DS22107B-page 54 2008-2013 Microchip Technology Inc.
NOTES:
2008-2013 Microchip Technology Inc. DS22107B-page 55
MCP454X/456X/464X/466X
7.0 DEVICE COMMANDS
The MCP4XXX’ s I2C command formats a re specified in
this section. The I2C protocol does not specify how
commands are formatted.
The MCP4XXX supports four basic commands.
Depending on the location accessed, this determines
the commands that are supported.
For the Volatile Wiper R egist ers, th ese com mands are:
• Write Data
• Read Data
•Increment Data
•Decrement Data
For the Nonvolatile wiper EEPROM, general purpose
data EEPROM, and the TCON Register these com-
mands are:
• Write Data
• Read Data
These commands have formats for both a single
command or continuous commands. These commands
are shown in Table 7-1.
Each command has two operational states. The
operational state determines if the device commands
control the special features (Write Protect and Wiper-
Lock Technology). These operational states are
referred to as:
• Normal Serial Commands
• High-Volt a ge Seria l Comm an ds
TABLE 7-1: I2C COMMANDS
Normal serial comm an ds are thos e where the HVC pi n
is driven to VIH or VIL. With High-Voltage Serial Com-
mands, the HVC pin is driven to VIHH. In each mode,
there are four possibl e com mands .
Additionally, there are two commands used to enable
or disable the special features (Wr ite Protect and Wiper
Lock Technology) of the device. The commands are
special cases of the Increment and Decrement
High-Volta ge Seria l Co mmand.
Table 7-2 shows the supported commands for each
memory location.
Table 7-3 shows an overview of all the device com-
mands an d their interac tion with other de vice feature s.
7.1 Command Byte
The MCP4XXX’s Command Byte has three fields: the
Address, the Command Operation, and 2 Data bits,
see Figure 7-1. Currently only one of the data bits is
defined (D 8).
The device memory is accessed when the Master
sends a proper Command Byte to select the desired
operation. The memory location getting accessed is
contained in the Command Byte’s AD3:AD0 bits. The
action desired is contained in the Command Byte’s
C1:C0 bits, see Table 7-1. C1:C0 determines if the
desired memory location will be read, written,
Incremented (wiper setting +1) or Decremented (wiper
setting -1). The Increment and Decrement commands
are only valid on the volatile wiper registers, and in
High Voltage commands to enable/disable WiperLock
Technol ogy and Software Write Protect.
If the Address bits and Command bits are not a valid
combination, then the MCP4XXX will generate a Not
Acknow ledge pulse to indi ca te the in valid comb ina tion.
The I2C Master device must then force a Start Condi-
tion to reset the MCP4XXX’s 2C module.
D9 and D8 are the most significant bits for the digital
potentiometer’s wiper setting. The 8-bit devices utilize
D8 as t heir MSb while t he 7- bit dev ices uti lize D7 (from
the data byte) as it’s MSb.
FIGURE 7-1: Command Byte Format.
Command # of Bit
Clocks (1)
Operates on
Volatile/
Nonvolatile
memory
Operation Mode
Write Data Single 29 Both
Continuous 18n + 11 Volatile Only
Read Data Single 29 Both
Random 48 Both
Continuous 18n + 11 Both (2)
Increment
(3) Single 20 Volatile Only
Continuous 9n + 11 Volatile Only
Decrement
(3) Single 20 Volatile Only
Continuous 9n + 11 Volatile Only
Note 1: “n” indicates the number of times the
command operation is to be repeated .
2: This command is useful to determine if a
nonvolatile memory write cycle has
completed.
3: High Voltage Increment and Decrement
commands on select nonvolatile memory
locations enable/disable WiperLock
Technology and the software Write
Protect feature.
AA
D
3
A
D
2
A
D
1
A
D
0
C
1C
0D
9D
8A
MCP4XXX
COMMAND BYTE
00 = Write Data
01 = Increment
MSbits (Data)
10 = Decrement
11 = Read Data
Command Operation bits
Memory Address
MCP454X/456X/464X/466X
DS22107B-page 56 2008-2013 Microchip Technology Inc.
TABLE 7-2: MEMORY MAP AND THE SUPPORTED COMMANDS
Address Command Operation Data
(10-bits) (1) Comment
Value Function
00h Volatile Wiper 0 Write Data nn nnnn nnnn
Read Data (3) nn nnnn nnnn
Increment Wiper —
Decrement Wiper —
01h Volatile Wiper 1 Write Data nn nnnn nnnn
Read Data (3) nn nnnn nnnn
Increment Wiper —
Decrement Wiper —
02h Non Volatile Wiper 0 Write Data nn nnnn nnnn
Read Data (3) nn nnnn nnnn
High Voltage Increment — Wiper Lock 0 Disable
High Voltage Decrement — Wiper Lock 0 Enable
03h Non Volatile Wiper 1 Write Data nn nnnn nnnn
Read Data (3) nn nnnn nnnn
High Voltage Increment — Wiper Lock 1 Disable
High Voltage Decrement — Wiper Lock 1 Enable
04h (2) Volatile TCON Register Write Data nn nnnn nnnn
Read Data (3) nn nnnn nnnn
05h (2) Status Register Read Data (3) nn nnnn nnnn
06h (2) Data EEPROM Write Data nn nnnn nnnn
Read Data (3) nn nnnn nnnn
07h (2) Data EEPROM Write Data nn nnnn nnnn
Read Data (3) nn nnnn nnnn
08h (2) Data EEPROM Write Data nn nnnn nnnn
Read Data (3) nn nnnn nnnn
09h (2) Data EEPROM Write Data nn nnnn nnnn
Read Data (3) nn nnnn nnnn
0Ah (2) Data EEPROM Write Data nn nnnn nnnn
Read Data (3) nn nnnn nnnn
0Bh (2) Data EEPROM Write Data nn nnnn nnnn
Read Data (3) nn nnnn nnnn
0Ch (2) Data EEPROM Write Data nn nnnn nnnn
Read Data (3) nn nnnn nnnn
0Dh (2) Data EEPROM Write Data nn nnnn nnnn
Read Data (3) nn nnnn nnnn
0Eh (2) Data EEPROM Write Data nn nnnn nnnn
Read Data (3) nn nnnn nnnn
0Fh Data EEPROM Write Data nn nnnn nnnn
Read Data (3) nn nnnn nnnn
High Voltage Increment — Write Protect Disable
High Voltage Dec rement — Write Protect Enable
Note 1: The Data Memory is only 9-bits wide, so the MSb is ignored by the device.
2: Increment or Decrement commands are invalid for these addresses.
3: I2C read operation will read 2 bytes, of which the 10-bits of data are contained within.
2008-2013 Microchip Technology Inc. DS22107B-page 57
MCP454X/456X/464X/466X
7.2 Data Byte
Only the Read Command and the Write Command
have Data Byte(s).
The Write command concatenates the 8-bits of the
Data Byte with the one data bit (D8) contained in the
Command Byte to form 9-bits of data (D8:D0). The
Command Byte format supports up to 9-bits of data so
that the 8-bit resistor network can be set to Full-Scale
(100h or greater). This allows wiper connections to
Terminal A and to Terminal B. The D9 bit is currently
unused.
7.3 Error Condition
If the four a ddress bit s received (AD 3:AD0) and the tw o
command bits received (C1:C0) are a valid combina-
tion, the MCP4XXX will Acknowledge the I2C bus.
If the address bits and command bits are an invalid
combinati on, then the MCP4XXX wil l Not Acknowledge
the I2C bus.
Once an error condition has occurred, any following
commands are ignored until the I2C bus is reset with a
Start Condition.
7.3.1 ABORTING A TRANSMISSION
A Restart or Stop condition in the expected data bit
position will abort the current command sequence and
data will not be written to the MCP4XXX.
TABLE 7-3: COMMANDS
Command Name Writes
Value in
EEPROM
Operates on
Volatile/
Nonvolatile
memory
High
Voltage
(VIHH) on
HVC pin?
Impact on
WiperLock or
Write Prot ect
Works
when
Wiper is
“locked”?
Write Data Yes (1) Both — unlocked
(1) No
Read Data — Both — unlocked (1) No
Increment Wiper — Volatile Only — unlocked
(1) No
Decrement Wiper — Volatile Only — unlocked
(1) No
High Voltage Write Data Yes Both Yes unchanged No
High Voltage Read Data — Both Yes unchanged Yes
High Voltage Incr ement Wiper — Volatile Only Yes unchanged No
High Voltage Decrement Wiper — Volatile Only Yes unchanged No
Modify Write Protect or WiperLock
Technol ogy (High Voltage) - Enable — (2) Nonvolatile Only
(2) Yes locked/
protected(2) Yes
Modify Write Protect or WiperLock
Technol ogy (High Voltage) - Disable — (3) Nonvolatile Only
(3) Yes unlocked/
unprotected(3) Yes
Note 1: This command will only complete, if wiper is “unlocked” (WiperLock Technology is Disabled).
2: If the command is executed using address 02h or 03h, that corresponding wiper is locked or
if with address 0Fh, then Write Protect is enabled.
3: If the command is executed using with address 02h or 03h, that corresponding wiper is unlocked or
if with address 0Fh, then Write Protect is disabled.
MCP454X/456X/464X/466X
DS22107B-page 58 2008-2013 Microchip Technology Inc.
7.4 Wr it e Data
Normal and High Vo ltage
The Write Co mm and can be i ss ue d to bo th the Volatile
and Nonvolatile memory locations. The format of the
command, see Figure 7-2, includes the I2C Control
Byte, an A bi t, the MCP4XXX Co mmand B yte, an A b it,
the MCP4XXX Data Byte, an A bit, and a Stop (or
Restart) condition. The MCP4XXX generates the A / A
bits.
A Write command to a Volatile memory location
changes that location after a properly formatted Write
Command and the A / A clock have been received.
A Wri te command to a Nonvo latile memo ry location wil l
only start a write cycle after a properly formatted Write
Command have been received and the Stop condition
has occurred.
7.4.1 SINGLE WRITE TO VOLATILE
MEMORY
For volatile memory locations, data is written to the
MCP4XXX after every byte transfer (during the
Acknowledge). If a Stop or Restart condition is gener-
ated during a data transfer (before the A), the data will
not be written to the MCP4XXX. After the A bit, the
master can initiate the next sequence with a Stop or
Restart condition.
Refer to Figure 7-2 for the byte write sequence.
7.4.2 SINGLE WRITE TO NONVOLATILE
MEMORY
The sequence to write to a single nonvolatile memory
locatio n is the same as a single write to vo latile memory
with th e excepti on that the EEP ROM write cycle (twc) is
started after a properly formatted command, including
the Stop bit, is received. After the Stop condition
occurs, the serial interface may immediately be
re-enabled by initiating a Start condition.
During an EEPROM write cycle, access to volatile
memory (addresses 00h, 0 1h, 0 4h, and 05h) is allowed
when using the appropriate command sequence.
Commands that address nonvolatile memory are
ignored until the EEPROM write cycle (twc) comple t es.
This allows the Host Controller to operate on the
Volatile Wiper registers, the TCON register, and to
Read the Status Register. The EEWA bit in the Status
register indicates the status of an EEPROM Write
Cycle.
Once a write command to a Nonvolatile memory
location h as been received, no other co mmands should
be received before the Stop condition occurs.
Figure 7-2 show the waveform for a single write.
7.4.3 CONTINUOUS WRITES TO
VOLA TI LE MEMO RY
A continuous writ e mo de of operat io n is po ss ibl e w he n
writing to the volatile memory registers (address 00h,
01h, and 04h). This continuous write mode allows
writes without a Stop or Restart condition or repeated
transmissions of the I2C Control Byte. Figure 7-3
shows the sequence for three continuous writes. The
writes do not need to be to the same volatile memory
address. The sequence ends with the master sending
a STOP or RESTART condition.
7.4.4 CONTINUOUS WRITES TO
NONVOLATI LE MEMORY
If a continuous write is attempted on Nonvolatile
memory, the missi ng S top cond ition will cau se the com-
mand to be an error condition (A). A S tart bit is required
to reset the command state machine.
7.4.5 THE HIGH VOLTAGE COMMAND
(HVC) SIGNAL
The High Voltage Command (HVC) signal is
multipl exed with Addres s 0 (A0) and i s use d to i ndica te
that the command, or sequence of commands, are in
the High Voltage operational state. High Voltage
commands allow the device’s WiperLock Technology
and write protect features to be enabled and disabled.
The HVC pin has an internal resistor connection to the
MCP45XX/46XXs internal VDD signal.
Note: Writes t o ce rtai n m em ory l oc at i ons w i ll be
dependant on the state of the WiperLock
Technology bits and the Write Protect bit.
2008-2013 Microchip Technology Inc. DS22107B-page 59
MCP454X/456X/464X/466X
FIGURE 7-2: I2C Write Sequence.
FIGURE 7-3: I2C Continuous Volatile Wiper Write.
Control Byte WRITE Command Write Data bits
1010SA2A1A00 0
ADAD AD AD
A0xD8AD3D7 D6 D5 D4 D2 D1 D0 A P
0123
Fixed
Address Variable
Address
Device
Memory
Address Command Write “Data” bits
Write bit
STOP bit
Control Byte WRITE Command Write Data bits
1010SA2A1A00 0A0xD8AD3D7 D6 D5 D4 D2 D1 D0 A
Fixed
Address Variable
Address
Device
Memory
Address Command Write “Data” bits
WRITE Command Write Data bits
00xD8A D3D7 D6 D5 D4 D2 D1 D0 A
WRITE Command Write Data bits
00xD8A D3D7 D6 D5 D4 D2 D1 D0 A P
Write bit
AD AD AD AD
0123
ADAD AD AD
0123
ADAD AD AD
0123
Note: Only functions when writin g the vola tile wipe r regis ters (AD3 :AD0 = 00h , 01h, and 04h)
or the TCON register
MCP454X/456X/464X/466X
DS22107B-page 60 2008-2013 Microchip Technology Inc.
7.5 Read Data
Normal and High Vo ltage
The Rea d Comma nd can be issu ed to bot h the Volatile
and Nonvolatile memory locations. The format of the
comma nd, see Figure 7-4, includes the S tart condition,
I2C Control Byte (with R/W bit set to “0”), A bit,
MCP4XXX Command Byte, A bit, followed by a
Repea ted S t art bit, I2C Control Byte (with R/W bit set to
“1”), and the MCP4XXX transmitting the requested
Data High Byte, and A bit, the Data Low Byte, the Mas-
ter generating the A, and Stop condition.
The I2C Control Byte requires the R/W bit equal to a
logic one (R/W = 1) to generate a read sequence. The
memory location read will be the last address
cont ained in a val id write MCP4XXX Comm and Byte or
address 00h if no wri te opera tions have o ccurred s ince
the device was reset (Power-on Reset or Brown-out
Reset).
During a write cycle (Write or High Voltage Write to a
Nonvolatile memory location) the Read command can
only r ead th e V ol atile memory locatio ns. By r eading the
Status Register (04h), the Host Controller can
determi ne when the wr ite cy c le has compl eted (via the
state of the EEWA bit).
Read operations initially include the sa me address byte
sequen ce as the write sequ ence (shown in Figure 6-9).
This sequence is followed by another control byte
(includ ing th e Start co nditio n and Ackowle dge) w ith th e
R/W bit equal to a logic one (R/W = 1) to indicate a
read. The MCP4XXX will then transmit the data con-
ta ined in the ad dressed reg ister . Th is is followe d by the
master generating an A bit in prepar ation for more data,
or an A bi t fo ll o wed by a Stop. T he s equ en c e i s en d ed
with th e ma st er generatin g a Stop or Res t a r t co ndi tio n.
The internal address pointer is maintained. If this
address pointer is for a nonvolatile memory address
and th e read cont ro l byte a ddr esse s the de vice duri ng
a Nonv ola til e W r i te Cy cle (tWC) the dev ic e wil l res pon d
with an A bit.
7.5.1 SINGLE READ
Figure 7-4 show the waveforms for a single read.
For single reads the master sends a STOP or
RESTART condi tion a fter the da ta b yte is sent from the
slave.
7.5.1.1 Random Read
Figure 7-5 shows the sequence for a Random Reads.
Refer to Figure 7-5 for the random byte read
sequence.
7.5.2 CONTINUOUS READS
Continuous reads allows the device’s memory to be
read quic kly . Continuous reads are possible to all mem -
ory locations. If a nonvolatile memory write cycle is
occurring, then Read commands may only access the
volatile memory locations.
Figure 7-6 shows the sequence for three continuous
reads.
For continuous reads, instead of transmitting a Stop
or Restart condition after the data transfer, the master
reads the next data byte. The sequence ends with the
master N o t Ack no wledging and then se ndi ng a Stop or
Restart.
7.5.3 THE HIGH VOLTAGE COMMAND
(HVC) SIGNAL
The High Voltage Command (HVC) signal is
multipl exed with Addres s 0 (A0) and i s use d to i ndica te
that the command, or sequence of commands, are in
the High Voltage mode. High Voltage commands allow
the device’s WiperLock Technology and write protect
features to be enabled and disabled.
The HVC pin has an internal resistor connection to the
MCP4XXXs internal VDD signal.
7.5.4 IGNOR ING AN I2C TRANSMISSION AND
“FALLING OFF” THE BUS
The MCP4XXX expects to receive entire, valid I2C
comma nds and w il l ass um e an y command not defined
as a valid command is due to a bus corruption and will
enter a passive high condition on the SDA signal. All
signals will be ignored until the next valid Start
condition and Control Byte are received.
2008-2013 Microchip Technology Inc. DS22107B-page 61
MCP454X/456X/464X/466X
FIGURE 7-4: I2C Read (Last Memory Address Accessed).
FIGURE 7-5: I2C Random Read.
STOP bit
Control Byte
1010SA2A1A01A
Fixed
Address Variable
Address
Read bits
P
00000 0 0D8A
1
Read bit
D3D7 D6 D5 D4 D2 D1 D0 A2
Read Data bits
Note 1: Master Device is responsible for A / A signal. If a A signal occurs, the MCP45XX/46XX will
abort this transfer and release the bus.
2: The Maste r Device wi ll Not Acknowledge, and the MC P45XX/46XX will relea se the bus so the
Master Device can generate a Stop or Repeated Start condition.
3: The MCP4 5xx/4 6xx ret ains the last “Dev ice Mem ory Address ” that it has receive d. This is the
MCP45XX/46XX does not “corrupt” the “Device Memory Address” after Repeated Start or
Stop conditions.
4: The Device Memory Address pointer defaults to 00h on POR and BOR conditions.
STOP bit
Control Byte READ Command
1010SA2A1A00 1
ADAD ADAD
A1xXASr
0
1
2
3
Fixed
Address Variable
Address
Device
Memory
Address Command
Control Byte Read bits
P
00000 0 0D8A
1
Write bit
D3D7 D6 D5 D4 D2 D1 D0 A2
1010 A2A1A01A
Read bit
Repeated Start bit
Read Data bits
Note 1: Master Device is responsible for A / A signal. If a A signal occurs, the MCP45XX/46XX will
abort this transfer and release the bus.
2: The Maste r Device wi ll Not Acknowledge, and the MC P45XX/46XX will relea se the bus so the
Master Device can generate a Stop or Repeated Start condition.
3: The MCP45XX/46XX retains the last “Device Memory Address” that it has received. This is
the MCP4 5XX/46XX does n ot “corrup t” the “Devi ce Memory Addre ss” af ter Repea ted Start or
Stop conditions.
MCP454X/456X/464X/466X
DS22107B-page 62 2008-2013 Microchip Technology Inc.
FIGURE 7-6: I2C Continuous Reads.
STOP bit
Control Byte
1010SA2A1A01A
Fixed
Address Variable
Address
Read bits
00000 00D8A
1
Read bit
D3D7 D6 D5 D4 D2 D1 D0 A1
Read Data bits
00000 0 0D8A
1D3D7 D6 D5 D4 D2 D1 D0 A1
P
00000 0 0D8A
1D3D7 D6 D5 D4 D2 D1 D0 A2
Read Data bits
Read Data bits
Note 1: Master Device is responsible for A / A signal. If a A signal occurs, the MCP45XX/46XX will
abort this transfer and release the bus.
2: The Maste r Device wi ll Not Acknowledge, and the MC P45XX/46XX will relea se the bus so the
Master Device can generate a Stop or Repeated Start condition.
2008-2013 Microchip Technology Inc. DS22107B-page 63
MCP454X/456X/464X/466X
7.6 Increment Wiper
Normal and High Voltage
The Increment Command provide a quick and easy
method to modify the potentiometer’s wiper by +1 with
minimal overhead. The Increment Command will only
function on the volatile wiper setting memory locations
00h and 01h. The Increment Command to Nonvolatile
addresses will be ignored and will generate a A.
When executing an Increment Command, the volatile
wiper setting will be altered from n to n+1 for each
Increment Command received. The value will incre-
ment up to 100h m ax on 8-bit devices and 80h on 7-b it
devices. If multiple Increment Commands are received
after th e value has reached 100h (or 80h), the value will
not be incremented further. Table 7-4 shows the
Incr ement Co mmand ve rsus the current volatil e wiper
value.
The Increment Command will most commonly be
performed on the Volatile Wiper locations until a
desired condition is met. The value in the V olatile Wiper
register would nee d to be re ad u si ng a Re ad o per atio n
in order to write the new setting to the corresponding
Nonvo latile wip er memory u sing a W rite operation . The
MCP4XXX is responsible for generating the A bits.
Refer to Figure 7-7 for the Increment Command
sequence. The sequence is terminated by the Stop
condition. So when executing a continuous command
string, the Increment command can be followed by any
other valid command. This means that writes do not
need to be to the same volatile memory address.
The advantage of using an Increment Command
instead of a read-modify-write series of commands is
speed a nd simplicit y . The wiper will transition af ter each
Command Acknowledge when accessing the volatile
wiper registers.
TABLE 7-4: INCREMENT OPERATION VS.
VOLATILE WIP ER VALUE
7.6.1 THE HIGH VOLTAGE COMMAND
(HVC) SIGNAL
The High Voltage Command (HVC) signal is multi-
plexed w i th Add res s 0 (A0 ) and is used to indicate th at
the command, or sequence of commands, are in the
High Voltage mode. Signals > VIHH (~8.5V) on the
HVC/A0 pin puts MCP45XX/46XX devices into High
Voltage mode. High Voltage commands allow the
device’s WiperLock Technology and write protect
features to be enabled and disabled.
The HVC pin has an internal resistor connection to the
MCP45XX/46XXs internal VDD signal.
FIGURE 7-7: I2C Increment Command Sequence.
Note: Table 7-2 shows the valid addresses for
the Increment Wiper command. Other
addresses are i nvalid.
Note: The command sequence can go from an
increment to any other valid command for
the specified address. Issuing an incre-
ment or decrement to a nonvolatile loca-
tion wil l ca use an error conditio n (A will be
generated).
Current Wiper
Setting Wipe r (W)
Properties
Increment
Command
Operates?
7-bit
Pot 8-bit
Pot
3FFh
081h 3FFh
101h Reserved
(Full-Scale (W = A)) No
080h 100h Full-Scale (W = A) No
07Fh
041h 0FFh
081 W = N
040h 080h W = N (Mid-Scale) Yes
03Fh
001h 07Fh
001 W = N
000h 000h Zero Scale (W = B) Yes
Note: There is a required delay af ter the HVC pin
is driven to the VIHH level to the 1st edge
of the SCL pin.
Control Byte INCR Command (n+1) INCR Co mmand (n+2)
1010SA2A1A00 0
ADAD AD AD
A1xXA0
AD AD AD AD 1x XAP
(2)
0
1
2
34321
Fixed
Address Variable
Address
Device
Memory
Address Command
Write bit
Note 1: Increment Comma nd (I NCR) on ly fu nctio ns whe n a ccess ing the v ol atile wiper reg -
isters (AD3:AD0 = 0h and 1h).
2: This co mmand sequen ce does not need to terminate (us ing the Stop bit ) and can
change to any other desired command sequence (Increment, Read, or Write).
MCP454X/456X/464X/466X
DS22107B-page 64 2008-2013 Microchip Technology Inc.
7.7 Decrement Wi per
Normal and High Voltage
The Decrement Command provide a quick and easy
method to modify the potentiometer’s wiper by -1 with
minimal overhead. The Decrement Command will only
function on the volatile wiper setting memory locations
00h and 01h. Decrement Commands to Nonvolatile
addresses will be ignored and will generate an A bit.
When executing a Decrement Command, the volatile
wiper setting will be altered from n to n-1 for each
Decrement Command received. The value will
decrement down to 000h min. If multiple Decrement
Commands are received after the value has reached
000h, the value will not be decremented further.
Table 7-5 shows the Increment Command versus the
current volatile wiper value.
The Decrement Command will most commonly be
performed on the Volatile Wiper locations until a
desired condition is met. The value in the Volatile Wiper
register would nee d to be re ad u si ng a Re ad o per atio n
in order to write the new setting to the corresponding
Nonvolatile wiper memory using a Write operation. The
MCP4XXX is responsible for generating the A bits.
Refer to Figure 7-8 for the Decrement Command
sequence. The sequence is terminated by the Stop
condition. So when executing a continuous command
string, the Increment command can be followed by any
other valid command. This means that writes do not
need to be to the same volatile memory address.
The advantage of using an Decrement Command
instead of a read-modify-write series of commands is
speed a nd simplicit y . The wiper will transition af ter each
Command Acknowledge when accessing the volatile
wiper registers.
TABLE 7-5: DECREMENT OPERATION VS.
VOLATILE WIP ER VALUE
7.7.1 THE HIGH VOLTAGE COMMAND
(HVC) SIGNAL
The High Voltage Command (HVC) signal is
multipl exed with Addres s 0 (A0) and i s use d to i ndica te
that the command, or sequence of commands, are in
the High Voltage mode. Signals > VIHH (~8.5V) on the
HVC/A0 pin puts MCP45XX/46XX devices into High
Voltage mode. High Voltage commands allow the
device’s WiperLock Technology and write protect
features to be enabled and disabled.
The HVC pin has an internal resistor connection to the
MCP45XX/46XXs internal VDD signal.
FIGURE 7-8: I2C Decrement Command Sequence.
Note: Table 7-2 shows the valid addresses for
the Decrement Wiper command. Other
addresses are i nvalid.
Note: The command sequence can go from an
increment to any other valid command for
the specified address. Issuing an
increment or decrement to a nonvolatile
location will cause an error condition (A
will be generated).
Current Wiper
Setting Wipe r (W)
Properties
Decrement
Command
Operates?
7-bit
Pot 8-bit
Pot
3FFh
081h 3FFh
101h Reserved
(Full-Scale (W = A)) No
080h 100h Full-Scale (W = A) Yes
07Fh
041h 0FFh
081 W = N
040h 080h W = N (Mid-Scale) Yes
03Fh
001h 07Fh
001 W = N
000h 000h Zero Scale (W = B) No
Note: There is a required delay af ter the HVC pin
is driven to the VIHH level to the 1st edge
of the SCL pin.
Control Byte DECR Command (n-1) DECR Command (n-2)
1010SA2A1A00 1
ADAD AD AD
A0XXA1
AD AD AD AD 0XXAP
(2)
0
1
23 4321
Fixed
Address Variable
Address
Device
Memory
Address Command
Write bit
Note 1: Decrement Command (DECR) only functions when accessing the volatile wiper
registers (AD3:AD0 = 0h and 1h).
2: This co mmand sequen ce does not need to terminate (us ing the Stop bit ) and can
change to any other desired command sequence (INCR, Read, or Write).
2008-2013 Microchip Technology Inc. DS22107B-page 65
MCP454X/456X/464X/466X
7.8 Modify W rite Protect or WiperLock
Technology (High Voltage)
Enable and Disable
These commands are special cases of the High Volt-
age Decrement Wiper and the High Voltage Incre-
ment Wiper commands to the nonvolatile memory
locations 02h, 03h, and 0Fh. This command is used to
enable or disable either the software Write Protect,
wiper 0 WiperLock Technology, or wiper 1 WiperLock
Technology. Table 7-6 shows the memory addresses,
the High Voltage command and the result of those
commands on the nonvolatile WP, WL0, 0r WL1 bits.
7.8.1 SINGLE MODIFY (ENABLE OR
DISABLE) WRITE PROTECT OR
WIPERLOCK TECHNOLOGY (HIGH
VOLTAGE)
Figure 7-9 (Disable) and Figure 7-10 (Enable) show
the formats for a single Modify Write Protect or Wiper-
Lock Technology command.
A Modify Write Protect or WiperLock Technology
Command will only start an EEPROM write cycle (twc)
after a properly formatted Command has been
received and the Stop conditio n occurs.
During an EE PROM write cycle, o nl y s eri al com ma nd s
to Volatile mem ory (addre sses 00h, 01 h, 04h, and 05h)
are accepted. All other serial commands are ignored
until the EEPROM write cycle (twc) completes. This
allows the Host Controller to operate on the Volatile
Wiper registers and the TCON register, and to Read
the S tatus Register . The EEW A bit in the S tatus register
indicates the status of an EEPROM Write Cycle.
TABLE 7-6: ADDRESS MAP TO MODIFY WRITE PROTECT AND WIPERLOCK TECHNOLOGY
FIGURE 7-9: I2C Disable Command Sequence.
FIGURE 7-10: I2C Enable Command Sequence.
Memory
Address
Commands and Result
High Voltage Decrement Wiper High Voltage I ncrem ent Wiper
00h Wiper 0 register is incremented Wiper 0 register is incremented
01h Wiper 1 register is decremented Wiper 1 register is incremented
02h WL0 is enabled WL0 is disabled
03h WL1 is enabled WL1 is disabled
04h (1) TCON register not changed TCON register not changed
05h - 0Eh (1) Reserved Reserved
0Fh WP is enabled WP is disabled
Not e 1: Reserved add resses: Increment or Decrement commands are invalid for these addresses.
Control Byte Disab le Co mm an d
1010SA2A1A00 0
AD AD AD AD
A1XXA
P
1
2
3
Fixed
Address Variable
Address
Device
Memory
Address Command (Increment)
Write bit
0
Control Byte Enable Command
1010SA2A1A00 1
AD ADAD AD
A0XXA
P
0
1
2
3
Fixed
Address Variable
Address
Device
Memory
Address Comma nd (Dec rem ent)
Wri te bit
MCP454X/456X/464X/466X
DS22107B-page 66 2008-2013 Microchip Technology Inc.
NOTES:
2008-2013 Microchip Technology Inc. DS22107B-page 67
MCP454X/456X/464X/466X
8.0 APPLICATIONS EX AMPLES
Nonvolatile digital potentiometers have a multitude of
practical uses in modern electronic circuits. The most
popular uses include precision calibration of set point
threshol ds , senso r trimmin g, LCD bia s trim ming , audi o
attenuation, adjustable power supplies, motor control
overcurrent trip setting, adjustable gain amplifiers and
offset trimming. The MCP454X/456X/464X/466X
devices can be used to replace the common mechani-
cal trim pot in applications where the operating and
term inal vol tages are w ithi n CM OS pro ces s lim itati ons
(VDD = 2.7V to 5.5V).
8.1 Using Shutdown
Figure 8-1 shows a possible application circuit where
the independent terminals could be used. Disconnect-
ing the wiper allows the transistor input to be taken to
the Bias voltage level (disconnecting A and or B may be
des ired to re duce system curren t). Disc onnec ting Ter -
minal A modifies the transistor input by the RBW rheo-
stat value to the Co mm on B. D is con necting Terminal B
modifie s the tran sis to r input by the RAW rheostat valu e
to the Common A. The Common A and Common B
connections could be connected to VDD and VSS.
FIGURE 8-1: Example Application Circuit
using Terminal Disconnects.
8.2 Software Reset Sequence
At times it may become necessary to perform a Soft-
ware Reset Sequence to ensure the MCP45XX/46XX
device is in a correct and known I2C Interface state.
This technique only resets the I2C state machine.
This is useful if the MCP45XX/46XX device powers up
in an inco rrect sta te (due to ex cessive b us nois e, .. .), or
if the Master Device is reset during communication.
Figure 8-2 shows the commun ication sequence to sof t-
ware reset the device.
FIGURE 8-2: Software Reset Sequence
Format.
The 1st Start bit will cause the device to reset from a
state in which it is expecting to receive data from the
Master Device. In this mode, the device is monitoring
the data bus in Receive mode and can detect the Start
bit forces an internal Reset.
The nine bits of ‘1’ are used to force a Reset of those
device s that cou ld not be res et by the prev ious S tar t bit.
This occurs only if the MCP45XX/46XX is driving an A
bit on the I2C bus, or is in output mode (from a Read
command) and is driving a data bit of ‘0’ onto the I2C
bus. In both of thes e case s, the previo us Start bi t coul d
not be generated due to the MCP45XX/46XX holding
the bus low. By sending out nine ‘1’ bits, it is ensured
that the de vi ce will s ee a A bit (the Mas ter Devi ce doe s
not dr iv e th e I2C bu s low t o ac kn ow l edge the da t a se nt
by the MCP45XX/46XX), which also forces the
MCP45XX /46XX to reset.
The 2nd Start bit is sent to address the rare possibility
of an erroneous write. This could occur if the Master
Device was reset while sending a Write command to
the MCP45XX/46XX, AND then as the Master Device
returns to nor mal operation and issues a S tart condition
while the MCP45XX/46XX is issuing an Acknowledge.
In this cas e, if the 2nd S t art bit is not sent (and the Stop
bit was sent) the MCP45XX/46XX could initiate a write
cycle.
The S top bit terminate s the current I2C bus a ctivity. The
MCP45XX /46XX wait to dete ct the next Sta rt conditio n.
This sequence does not effect any other I2C devices
which may be on the bus, as they should disregard this
as an invalid command.
Balance Bias
W
B
Input
Input
To base
of Transistor
(or Amplifier)
A
Common B
Common A
Note: This technique is document ed in AN1028.
Note: The potential for this erroneous write
ONLY occurs if the Master Device is reset
while sending a Write command to the
MCP45XX/46XX.
S‘1’‘1’‘1’‘1’‘1’‘1’‘1’‘1’ S P
Start bit Nine bits of ‘1’
Start bit
Stop bit
MCP454X/456X/464X/466X
DS22107B-page 68 2008-2013 Microchip Technology Inc.
8.3 Using the General Call Command
The use of the General C all Address Inc rement, Decr e-
ment, or Write commands is analogous to the “Load”
feature (LDAC pin) on some DACs (such as the
MCP4921). This allows all the devices to “Update” the
output level “at the same time”.
For some applications, the ability to update the wiper
values “at th e s ame tim e” m ay be a requiremen t, s inc e
the delay from writing to one wiper value and then the
next may cause application issues. A po ssible e xample
would be a “tun ed” cir cuit th at uses several MCP45XX/
46XX in rheostat configuration. As the system condition
changes (temperature, load, ...) these devices need to
be changed (incremented/decremented) to adjust for
the sys tem change . These change s will ei ther be in the
same direction or in opposite directions. With the
Potentiometer device, the customer can either select
the PxB terminals (same direction) or the PxA
terminal(s) (opposite direction).
Figure 8-4 shows that the update of six devices takes
6*TI2CDLY time in “normal” operation, but only
1*TI2CDLY time in “General Call” operation.
Figure 8-3 shows two I2C bus configurations. In many
cases, the single I2C bus configuration will be
adequate. For applications that do not want all the
MCP45XX/46XX devices to do General Call sup port, or
have a conflict with General Call commands, the
multiple I2C bus configuration would be used.
FIGURE 8-3: Typical Appl ication I2C Bus
Configurations.
FIGURE 8-4: Example Comparison of “Normal Operation” vs. “General Call Operation” wiper
Updates.
Note: The application system may need to
partition the I2C bus into multiple busses to
ensure that the MCP45XX/46XX General
Call commands do not conflict with the
General Call com m and s th at the other I2C
devices may have defined. Also, if only a
portion of the MCP45XX/46XX devices are
to require this synchronous operation,
then the devices that should not receive
these c ommands sh ould be on the secon d
I2C bus.
Single I2C Bus Configuration
Host
Controller
Devi ce 1 Device 3 Device n
Device 2 Device 4
Multiple I2C Bus Configuration
Host
Controller
Device 1a Devi ce 3a Device na
Device 2a Device 4a
Device 1b Device 3b Device nb
Devi ce 2b Device 4b
Bus b
Bus a
Device 1n Device 3n Device nn
Device 2n Device 4n
Bus n
Normal Operation
General Call Operation
INC
POT01 INC
POT02 INC
POT03 INC
POT04 INC
POT05 INC
POT06
TI2CDLY TI2CDLY TI2CDLY TI2CDLY TI2CDLY
TI2CDLY = Time from one I2C command completed to completing the next I2C command.
INC
POTs 01-06 INC
POTs 01-06 INC
POTs 01-06 INC
POTs 01-06 INC
POTs 01-06 INC
POTs 01-06
TI2CDLY TI2CDLY TI2CDLY TI2CDLY TI2CDLY
TI2CDLY
TI2CDLY
2008-2013 Microchip Technology Inc. DS22107B-page 69
MCP454X/456X/464X/466X
8.4 Implementing Log Steps with a
Linear Digital Potentiometer
In audio volume control applications, the use of
logarithmic steps is desirable, since the human ear
hears in a logarithmic manner. The use of a linear
potentiometer can approximate a log potentiometer,
but with fewer steps. An 8-bit potentiometer can
achieve fourteen 3 dB log steps plus a 100% (0 dB)
and a mute setting.
Figure 8-5 shows a block diagram of one of the
MCP45x1 resistor networks being us ed to a ttenuate a n
input s ignal . In thi s ca se, th e atten uat ion wil l be g roun d
referenced. Terminal B can be connected to a common
mode voltage, but the voltages on the A, B and Wiper
terminals must not exceed the MCP45x1’s VDD/VSS
voltage limits.
FIGURE 8-5: Signal Attenuation Block
Diagram - Ground Referenced.
Equation 8-1 shows the equation to calculate voltage
dB gain ratios for the digital potentiometer, while
Equation 8-2 shows the equation to calculate
resist ance dB gain ratios. These two equat ions assume
that the B terminal is connected to ground.
If terminal B is not directly resistively connected to
ground, then this terminal B to ground resistance
(RB2GND) must be included into the calculation.
Equation 8-3 shows this equation.
EQUATION 8-1: dB CALCULATIONS
(VOLTAGE)
EQUATION 8-2: dB CALCULATIONS
(RESISTANCE) - CASE 1
EQUATION 8-3: dB CALCULATIONS
(RESISTANCE) - CASE 2
Table 8-1 shows the codes that can be used for 8-bit
digit al potent iometers to implem ent the l og attenua tion.
The table shows the wiper codes for -3 dB, -2 dB, and
-1 dB attenuation steps. This table also shows the
calcul ated atten uation ba sed on t he wipe r code’ s line ar
step. Calculated attenuation values less than the
desired attenuation are shown with red text. At lower
wiper code values, the attenuation may skip a step, if
this occurs the next attenuation value is colored
magenta to h ighlight that a s kip occurre d. For ex ample,
in the -3 dB column the -48 dB value is highlighted
since the -45 dB step could not be implemented (there
are no wiper codes between 2 and 1).
P0A
MCP45X1
P0W
P0B
L = 20 * log10 (VOUT / VIN)
dB VOUT / VIN Ratio
-3 0.70795
-2
-1 0.79433
0.89125
L = 20 * log10 (RBW / RAB)
Terminal B connected to Ground (see Figure 8-5)
L = 20 * log10 ( (RBW + RB2GND) / (RAB + RB2GND) )
Te rminal B through RB2GND to Ground
MCP454X/456X/464X/466X
DS22107B-page 70 2008-2013 Microchip Technology Inc.
TABLE 8-1: LINEAR TO LOG ATTENUATION FOR 8-BIT DIGITAL POTENTIOMETERS
# of
Steps
-3 dB Steps -2 dB Steps -1 dB Steps
Desired
Attenuation Wiper
Code
Calculated
Attenuation
(1)
Desired
Attenuation Wiper
Code
Calculated
Attenuation
(1)
Desired
Attenuation Wiper
Code
Calculated
Attenuation
(1)
0 0 dB 256 0 dB 0 dB 256 0 dB 0 dB 256 0 dB
1 -3 dB 181 -3.011 dB -2 dB 203 -2.015 dB -1 dB 228 -1.006 dB
2 -6 dB 128 -6.021 dB -4 dB 162 -3.975 dB -2 dB 203 -2.015 dB
3-9dB91-8.984 dB -6 dB 128 -6.021 dB -3 dB 181 -3.011 dB
4 -12 dB 64 -12.041 dB -8 dB 102 -7.993 dB -4 dB 162 -3.975 dB
5 -15 dB 46 -14.910 dB -10 dB 81 -9.995 dB -5 dB 144 -4.998 dB
6 -18 dB 32 -18.062 dB -12 dB 64 -12.041 dB -6 dB 128 -6.021 dB
7 -21 dB 23 -20.930 dB -14 dB 51 -14.013 dB -7 dB 114 -7.027 dB
8 -24 dB 16 -24.082 dB -16 dB 41 -15.909 dB -8 dB 102 -7.993 dB
9 -27 dB 11 -27.337 dB -18 dB 32 -18.062 dB -9 dB 91 -8.984 dB
10 -30 dB 8 -30.103 dB -20 dB 26 -19.865 dB -10 dB 81 -9.995 dB
11 -33 dB 6 -32.602 dB -22 dB 20 -22.144 dB -11 dB 72 -11.018 dB
12 -36 dB 4 -36.124 dB -24 dB 16 -24.082 dB -12 dB 64 -12.041 dB
13 -39 dB 3 -38.622 dB -26 dB 13 -25.886 dB -13 dB 57 -13.047 dB
14 -42 dB 2 -42.144 dB -28 dB 10 -28.165 dB -14 dB 51 -14.013 dB
15 -48 dB 1 -48.165 dB -30 dB 8 -30.103 dB -15 dB 46 - 14.910 dB
16 Mute 0 Mute -32 dB 6 -32.602 dB -16 dB 41 -15.909 dB
17 -34 dB 5 -34.185 dB -17 dB 36 -17.039 dB
18 -36 dB 4 -36.124 dB -18 dB 32 -18.062 dB
19 -38 dB 3 -38.622 dB -19 dB 29 -18.917 dB
20 -42 dB 2 -42.144 dB -20 dB 26 -19.865 dB
21 -48 dB 1 -48.165 dB -21 dB 23 - 20.930 dB
22 Mute 0 Mute -22 dB 20 -22.144 dB
23 -23 dB 18 -23.059 dB
24 -24 dB 16 -24.082 dB
25 -25 dB 14 -25.242 dB
26 -26 dB 13 -25.886 dB
27 -27dB 11 -27.337 dB
28 -28 dB 10 -28.165 dB
29 -29 dB 9 -29.080 dB
30 -30 dB 8 -30.103 dB
31 -31 dB 7 -31.263 dB
32 -33 dB 6-32.602 dB
33 -34 dB 5 -34.185 dB
34 -36 dB 4 -36.124 dB
35 -39 dB 3-38.622 dB
36 -42 dB 2 -42.144 dB
37 -48 dB 1 -48.165 dB
38 Mute 0 Mute
Note 1: Attenuation valu es do not includ e errors from Dig ital Pote ntiometer errors, such as Ful l Scale Error or Zer o
Scale Error.
2008-2013 Microchip Technology Inc. DS22107B-page 71
MCP454X/456X/464X/466X
8.5 Design Consider ations
In the design of a system with the MCP4XXX devices,
the following considerations should be taken into
account:
•Power Supply Conside ration s
•Layout Considerations
8.5.1 POWER SUPPLY
CONSIDERATIONS
The typical application will require a bypass capacitor
in order to filter high-frequency noise, which can be
induced onto the power supply's traces. The bypass
capacitor helps to minimize the effect of these noise
sources on signal integrity. Figure 8-6 illustrates an
appropria te bypass strategy.
In this example, the recommended bypass capacitor
value is 0.1 µF. This capacitor should be placed as
close (within 4 mm) to the device power pin (VDD) as
possible.
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, VDD and
VSS should reside on the analog plane.
FIGURE 8-6: Typic al Mic r ocontroll er
Connections.
8.5.2 LAYOUT CONSIDERATIONS
Several layout considerations may be applicable to
your application. These may include:
•Noise
•Footprint Compatibility
•PCB Area Requirements
8.5.2.1 Noise
Inductively-coupled AC transients and digital switching
noise c an degra de the in put and output s ignal integri ty,
potentially masking the MCP4XXX’s performance.
Careful board layout minimizes these effects and
increases the Signal-to-Nois e Ratio (SNR). Multi-layer
boards utilizing a low-inductance ground plane,
isolated inputs, isolated outputs and proper decoupling
are crit ical to achieving the per formance that the silico n
is capable of providing. Particularly harsh
environments may require shielding of critical signals.
If low noise is desired, breadboards and wire-wrapped
boards are not recommended.
8.5.2.2 Footprint Compatibility
The sp ecification of the MCP4XXX pinout s was done to
allow system s to be desig ned to easi ly supp ort the use
of either the dual (MCP46XX) or quad (MCP44XX)
device.
Figure 8-7 shows ho w the du al pinou t devices fit on th e
quad device footprint. For the Rheostat devices, the
dual device is in the MSOP package, so the footprints
would need to be offset from each other.
FIGURE 8-7: Quad Pinout (TSSOP
Package) vs. Dual Pinout.
VDD
VDD
VSS VSS
MCP454X/456X/
464X/466X
0.1 µF
PIC® Microcontroller
0.1 µF
SCL
SDA
W
B
A
1
2
3
417
18
19
20
RESET
A1
WP
VDD
MCP44X1 Quad Pote ntio me ters
TSSOP
5
6
714
15
16
P0W
P0B
P0A
P1A
P1W
P1B
VSS
HVC/A0
SDA
SCL
MCP44X2 Quad Rheostat
1
2
3
411
12
13
14
P0B
A1
P0W
VDD
TSSOP
5
6
78
9
10
P2W
P1W
P2B
P3B
P3W
P1B
VSS
HVC/A0
SDA
SCL
8
9
10
P3B
P3W
P3A
12
12
P2W
P2A
P2B
11
MCP42X1 Pinout (1)
MCP42X2 Pino ut
Note 1: Pin 15 (RESET) is the Ad dress A2 (A 2)
pin on the MCP46 x1 device.
MCP454X/456X/464X/466X
DS22107B-page 72 2008-2013 Microchip Technology Inc.
Figure 8-8 shows possible layout implementations for
an application to support the quad and dual options on
the same PCB.
FIGURE 8-8: Layout to Support Quad and
Dual Devices.
8.5.2.3 PCB Area Requirements
In some applications, PCB area is a criteria for device
selection. Table 8-2 shows the package dimensions
and area for the different package options. The table
also shows the relative area factor compared to the
smallest area. For space critical applications, the QFN
package would be the suggested package.
TABLE 8-2: PACKAGE FOOTPRINT (1)
8.5.3 RESISTOR TEMPCO
Characterization curves of the resistor temperature
coefficient (Tempco) are shown in Figure 2-10,
Figure 2-21, Figure 2-32, and Figure 2-43.
These curves show that the resistor network is
designed to correct for the change in resistance as
temperature increases. This technique reduces the
end-to-en d chan ge in RAB resista nce.
8.5.4 HIGH VOLTAGE TOLERANT PINS
High V o ltage supp ort (VIHH) on the Serial Interface pins
supports user configuration of the Nonvolatile
EEPROM, Write Protect, and WiperLock feature.
Potentiometers Devices
Rheostat Devices
MCP44X1
MCP46X1
MCP44X2
MCP46X2
Package Package Footp r int
Pins
Type
Code
Dimensions
(mm)
Area (mm2)
Relative Area
XY
8MSOP MS 3.00 4.90 14.70 1.63
DFN (3x3) MF 3.00 3.00 9.00 1
10 MSOP UN 3.00 4.90 14.70 1.63
DFN (3x3) MF 3.00 3.00 9.00 1
14 TSSOP ST 5.10 6.40 32.64 3.62
QFN (4x4) ML 4.0 0 4.00 1 6.00 1.78
16 TSSOP(2)ST 6.60 6.40 42.24 3.63
QFN (4x4) (2)ML 4.00 4.00 16.00 1.78
Note 1: Does not include recommended land
pattern dimensions.
2: These packages are for the Quad output
devices (MCP44x1).
Note: In m any ap plica tions , the H igh Voltage will
only be present at the manufacturing
stage so as to “lock” the Nonvolatile wiper
value (after calibration) and the contents
of the EEPROM. This ensures that since
High Voltage is not present under normal
operating conditions, that these values
can not be modifi ed.
2008-2013 Microchip Technology Inc. DS22107B-page 73
MCP454X/456X/464X/466X
9.0 DEVICE OPTIONS
Additional, custom devices are available. These
devices have weak pull-up resistors on the SDA and
SCL pins. This is useful for applications where the
wiper value is pro grammed during manufacture and n ot
modified by the system during normal operation.
Please contact your local sales office for current infor-
mation and minimum volume requirements.
9.1 Custom Options
The cust om device will have a “P” (for Pull -up) after th e
resist ance v ersion in the Produc t Identificati on System .
These d evices will not b e availa ble throug h Microc hip’ s
online Microchip Direct nor Microchip’s Sample
systems.
Example part number:
MCP4641-103PE/ST
MCP454X/456X/464X/466X
DS22107B-page 74 2008-2013 Microchip Technology Inc.
NOTES:
2008-2013 Microchip Technology Inc. DS22107B-page 75
MCP454X/456X/464X/466X
10.0 DEVELOPMENT SUPPORT
10.1 Development Tools
Several development tools are available to assist in
your design and evaluation of the MCP45XX/46XX
devices. The currently available tools are shown in
Table 10-1.
These boards may be purchased directly from the
Microchip web site at www.microchip.com.
10.2 Technical Documentation
Several additional technical documents are available to
assist you in your design and development. These
technical documents include Application Notes,
Technical Briefs, and Design Guides. Table 10-2
shows some of these documents.
TABLE 10-1: DEVELOPMENT TOOLS
TABLE 10-2: TECHNICAL DOCUMENTATION
Board Name Part # Supported Devices
MCP46XX PICTail Plus Daughter Board (2) MCP46XXDM-PTPLS MCP46XX
MCP46XX Evaluation Board MCP46XXEV MCP4631/41/51/61
MCP43XX Evaluation Board MCP43XXEV MCP4331/41/51/61
MCP4XXX Digit al Pote ntio me ter Daug hter Board (1) MCP4XXXDM-DB MCP42XXX, MCP42XX, MCP46XX,
MCP4021, and MCP4011
8-pin SOIC/MSOP/TSSOP/DIP Evaluation Board SOIC8EV Any 8-pin device in DIP, SOIC,
MSOP, or TSSOP package
14-pin SOIC/MSOP/DIP Evaluation Board SOIC14EV Any 14-pin device in DIP, SOIC, or
MSOP pac kage
Note 1: Requires the use of a PICDEM Demo Board (see User’s Guide for details)
2: Requires the use of the PIC24 Explorer 16 Demo Board (see User’s Guide for details)
3: The desired MCP46XX device (in MSOP package) must be soldered onto the extra board.
Application
Note Number Title Literature #
TB3073 Implementing a 10-bit Digital Potentiometer using a Quad 8-bit Digital Potentiometer
Technical Brief DS93073
AN1316 Using Digital Potentiometers for Programmable Amplifier Gain DS01316
AN1080 Understanding Digital Potentiometers Resistor Variations DS01080
AN737 Using Digital Potentiometers to Design Low Pass Adjustable Filters DS00737
AN692 Using a Digital Potentiometer to Optimize a Precision Single-Supply Photo Detect DS00692
AN691 Optimizing the Digital Potentiometer in Precision Circuits DS00691
AN219 Comparing Digital Potentiometers to Mechanical Potentiometers DS00219
— Digital Poten tio meter Design Gu ide DS2201 7
— Signal Cha in Design Gu ide DS21825
MCP454X/456X/464X/466X
DS22107B-page 76 2008-2013 Microchip Technology Inc.
NOTES:
2008-2013 Microchip Technology Inc. DS22107B-page 77
MCP454X/456X/464X/466X
11.0 PACKAGING INFORMATION
11.1 Package Marking Information
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanu me ric trac ea bil ity code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this pa ckage.
Note: In the even t the full Mic rochip part nu mber ca nn ot be marked o n one lin e, it wil l
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
8-Lead DFN (3x3) Example:
Part Number Code Part Number Code
MCP4541-502E/MF DACJ MCP4542-502E/MF DACP
MCP4541-103E/MF DACK MCP4542-103E/MF DACQ
MCP4541-104E/MF DACM MCP4542-104E/MF DACS
MCP4541-503E/MF DACL MCP4542-503E/MF DACR
MCP4561-502E/MF DADB MCP4562-502E/MF DADF
MCP4561-103E/MF DADC MCP4562-103E/MF DADG
MCP4561-104E/MF DADE MCP4562-104E/MF DADJ
MCP4561-503E/MF DADD MCP4562-503E/MF DADH
DACJ
E841
256
XXXX
XYWW
NNN
8-Lead MSOP
XXXXXX
YWWNNN
Example
454113
841256
Part Number Code Part Number Code
MCP4541-103E/MS 454113 MCP4542-103E/MS 454213
MCP4541-104E/MS 454114 MCP4542-104E/MS 454214
MCP4541-502E/MS 454152 MCP4542-502E/MS 454252
MCP4541-503E/MS 454153 MCP4542-503E/MS 454253
MCP4561-103E/MS 456113 MCP4562-103E/MS 456213
MCP4561-104E/MS 456114 MCP4562-104E/MS 456214
MCP4561-502E/MS 456152 MCP4562-502E/MS 456252
MCP4561-503E/MS 456153 MCP4562-503E/MS 456253
MCP454X/456X/464X/466X
DS22107B-page 78 2008-2013 Microchip Technology Inc.
Package Marking Information (Continued)
10-Lead DFN (3x3) Example:
Part Number Code Part Number Code
MCP4642-502E/MF AAFA MCP4662-502E/MF AAQA
MCP4642-103E/MF AAGA MCP4662-103E/MF AARA
MCP4642-104E/MF AAJA MCP4662-104E/MF AATA
MCP4642-503E/MF AAHA MCP4662-503E/MF AASA
AAFA
0841
256
XXXX
YYWW
NNN
10-Lead MSOP
XXXXXX
YWWNNN
Example
463252
841256
Part Number Code Part Number Code
MCP4642-502E/UN 464252 MCP4662-502E/UN 466252
MCP4642-103E/UN 464213 MCP4662-103E/UN 466213
MCP4642-104E/UN 464214 MCP4662-104E/UN 466214
MCP4642-503E/UN 464253 MCP4662-503E/UN 466253
14-Lead TSSOP (MCP4641, MCP4661)
XXXXXXXX
YYWW
NNN
Example
4641502E
0841
256
XXXXX
16-Lead QFN (MCP4641, MCP4661)
XXXXXX
YWWNNN
Example
XXXXXX
4641
502
841256
E/ML^^
3
e
2008-2013 Microchip Technology Inc. DS22107B-page 79
MCP454X/456X/464X/466X
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP454X/456X/464X/466X
DS22107B-page 80 2008-2013 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2008-2013 Microchip Technology Inc. DS22107B-page 81
MCP454X/456X/464X/466X
!"#$
%
MCP454X/456X/464X/466X
DS22107B-page 82 2008-2013 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2008-2013 Microchip Technology Inc. DS22107B-page 83
MCP454X/456X/464X/466X
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP454X/456X/464X/466X
DS22107B-page 84 2008-2013 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2008-2013 Microchip Technology Inc. DS22107B-page 85
MCP454X/456X/464X/466X
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP454X/456X/464X/466X
DS22107B-page 86 2008-2013 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2008-2013 Microchip Technology Inc. DS22107B-page 87
MCP454X/456X/464X/466X
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP454X/456X/464X/466X
DS22107B-page 88 2008-2013 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
UN
2008-2013 Microchip Technology Inc. DS22107B-page 89
MCP454X/456X/464X/466X
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
UN
MCP454X/456X/464X/466X
DS22107B-page 90 2008-2013 Microchip Technology Inc.
10-Lead Plastic Micro Small Outline Package (UN) [MSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2008-2013 Microchip Technology Inc. DS22107B-page 91
MCP454X/456X/464X/466X
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP454X/456X/464X/466X
DS22107B-page 92 2008-2013 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2008-2013 Microchip Technology Inc. DS22107B-page 93
MCP454X/456X/464X/466X
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP454X/456X/464X/466X
DS22107B-page 94 2008-2013 Microchip Technology Inc.
&'()) !"#($
%
%
D
E
N
2
1
EXPOSED
PAD
D2
E2
2
1
e
b
K
N
NOTE 1
A3
A1
A
L
TOP VIEW BOTTOM VIEW
2008-2013 Microchip Technology Inc. DS22107B-page 95
MCP454X/456X/464X/466X
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP454X/456X/464X/466X
DS22107B-page 96 2008-2013 Microchip Technology Inc.
NOTES:
2008-2012 Microchip Technology Inc. DS22107B-page 97
MCP454X/456X/464X/466X
APPENDIX A: REVIS I ON HISTORY
Revision B (February 2013)
The following is the list of modifications:
1. Updated the DFN package pinout on pag e 1.
2. Up da t ed th e A bso l ute Ma ximu m Rati ng s † page
format and added Total Power Dissipation
values for each package type.
3. Updated the typical thermal package resistance
values f or the 8L -D FN (3 x3 ) a nd 8L-SOIC pack-
ages in the Temperature characteristics table.
4. Added new Figure 2-59 to Section 2.1 “Test
Circuits”.
5. Cor rec ted val ues in Figure 5-1.
6. Added description of wiper value on POR/BOR
(Section 5.2 “Wiper”).
7. Removed Section 8.1.
8. Added Section 8.4 “Implementing Log Steps
with a Linear Digit a l Potentiom ete r”.
9. Added Section 8.5.2.2 “Footprint Compatibil-
ity”.
10. Added Section 8.5.2.3 “PCB Area Require-
ments”.
11. Updated Table 8-2.
12. Enhanced the listing of development tools and
technical documentation in Section 10.0
“Developm ent supp ort”.
13. Updated Table 10-1 and Table 10-2.
14. Updated Section 11.0 “Packaging Informa-
tion” with package available landing pattern
diagrams.
Revision A (November 2008)
• Original Rel ease of this Document.
MCP454X/456X/464X/466X
DS22107B-page 98 2008-2012 Microchip Technology Inc.
NOTES:
2008-2013 Microchip Technology Inc. DS22107B-page 99
MCP454X/456X/464X/466X
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: MCP4541: Single Nonvolatile 7-bit Potentiometer
MCP4541T: Single Nonvolatile 7-bit Potentiometer
(Tape and Reel )
MCP4542: Single Nonvolatile 7-bit Rheostat
MCP4542T: Single Nonvolatile 7-bit Rheostat
(Tape and Reel )
MCP4561: Single Nonvolatile 8-bit Potentiometer
MCP4561T: Single Nonvolatile 8-bit Potentiometer
(Tape and Reel )
MCP4562: Single Nonvolatile8-bit Rheostat
MCP4562T: Single Nonvolatile 8-bit Rheostat
(Tape and Reel )
MCP4641: Dual Nonvolatile 7-bit Potentiometer
MCP4641T: Dual Nonvolatile 7-bit Potentiometer
(Tape and Reel )
MCP4642: Dual Nonvolatile 7-bit Rheostat
MCP4642T: Dual Nonvolatile 7-bit Rheostat
(Tape and Reel )
MCP4661: Dual Nonvolatile 8-bit Potentiometer
MCP4661T: Dual Nonvolatile 8-bit Potentiometer
(Tape and Reel )
MCP4662: Dual Nonvolatile8-bit Rheostat
MCP4662T: Dual Nonvolatile 8-bit Rheostat
(Tape and Reel )
Resis tance Vers ion : 502 = 5 k
103 = 10 k
503 = 50 k
104 = 100 k
Temperature Range: E = -40°C to +125°C
Package: MF = Plastic Dual Flat No-lead (3x3 DFN), 8/10-lead
ML = Plastic Quad Flat No-lead (QFN), 16-lead
MS = Plastic Micro Small Outline (MSOP), 8-lead
ST = Plastic Thin Shrink Small Outline (TSSOP), 14-lead
UN = Plastic Micro Small Outline (MSOP), 10-lead
PART NO. X/XX
PackageTemperature
Range
Device
Examples:
a) MCP4541-502E/XX: 5 k 8LD Device
b) MCP4541-103E/XX: 10 k, 8-LD Device
c) MCP4541-503E/XX: 50 k, 8LD Device
d) MCP4541-104E/XX: 100 k, 8LD Device
e) MCP4541T-104E/XX: T/R, 100 k, 8LD Device
a) MCP4542-502E/XX: 5 k 8LD Device
b) MCP4542-103E/XX: 10 k, 8-LD Device
c) MCP4542-503E/XX: 50 k, 8LD Device
d) MCP4542-104E/XX: 100 k, 8LD Device
e) MCP4542T-104E/XX: T/R, 100 k, 8LD Device
a) MCP4561-502E/XX: 5 k 8LD Device
b) MCP4561-103E/XX: 10 k, 8-LD Device
c) MCP4561-503E/XX: 50 k, 8LD Device
d) MCP4561-104E/XX: 100 k, 8LD Device
e) MCP4561T-104E/XX: T/R, 100 k, 8LD Device
a) MCP4562-502E/XX: 5 k 8LD Device
b) MCP4562-103E/XX: 10 k, 8-LD Device
c) MCP4562-503E/XX: 50 k, 8LD Device
d) MCP4562-104E/XX: 100 k, 8LD Device
e) MCP4562T-104E/XX: T/R, 100 k, 8LD Device
a) MCP4641-502E/XX: 5 k 8LD Device
b) MCP4641-103E/XX: 10 k, 8-LD Device
c) MCP4641-503E/XX: 50 k, 8LD Device
d) MCP4641-104E/XX: 100 k, 8LD Device
e) MCP4641T-104E/XX: T/R, 100 k, 8LD Device
a) MCP4642-502E/XX: 5 k 8LD Device
b) MCP4642-103E/XX: 10 k, 8-LD Device
c) MCP4642-503E/XX: 50 k, 8LD Device
d) MCP4642-104E/XX: 100 k, 8LD Device
e) MCP4642T-104E/XX: T/R, 100 k, 8LD Device
a) MCP4661-502E/XX: 5 k 8LD Device
b) MCP4661-103E/XX: 10 k, 8-LD Device
c) MCP4661-503E/XX: 50 k, 8LD Device
d) MCP4661-104E/XX: 100 k, 8LD Device
e) MCP4661T-104E/XX: T/R, 100 k, 8LD Device
a) MCP4662-502E/XX: 5 k 8LD Device
b) MCP4662-103E/XX: 10 k, 8-LD Device
c) MCP4662-503E/XX: 50 k, 8LD Device
d) MCP4662-104E/XX: 100 k, 8LD Device
e) MCP4662T-104E/XX: T/R, 100 k, 8LD Device
XX = MF for 8/10-lead 3x3 DFN
= ML for 16-lead QFN
= MS f or 8-le ad MS OP
= ST for 14-lead TSSOP
= UN for 10-lead MSOP
XXX
Resistance
Version
MCP454X/456X/464X/466X
DS22107B-page 100 2008-2013 Microchip Technology Inc.
NOTES:
2008-2013 Microchip Technology Inc. DS22107B-page 101
Information contained in this publication regarding device
applications a nd the lik e is provided only f or yo ur convenience
and may be supers ed ed by u pda t es . It is y our responsibil it y to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlas h
and UNI/O are registered trademarks of Microchip T echnology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Stor age Technology is a registered trademark of
Microchip Te chnology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONIT OR, FanSense, HI-TIDE , In-Circuit Seria l
Programm ing, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Tec hnology Germ any II GmbH & C o. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2008-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62077-032-0
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its f amily of products is one of the most secure famili es of its kind on the market t oday, when used i n the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS22107B-page 102 2008-2013 Microchip Technology Inc.
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