QP7025
Doc#QP7025 rev 0.doc
2945 Oakmead Village Ct, Santa Clara, CA 95051 • Phone: (408) 737-0992 • Fax: (408) 736—8708 • Internet: www.qpsemi.com
QP7025 High-Speed 8K x 16 Dual-Port Static RAM
General Description
The QP7025 is a CMOS Fast 8K x 16 Dual-Port Static RAM (SRAM). QP Semiconductor designed the QP7025 to be a
direct replacement for the IDT7025. It is designed to be used as a stand-alone 128K-bit Dual-Port RAM or as a
combination MASTER/SLAVE Dual-Port RAM for 32-bit or larger (wider) word systems. Applications requiring a 32-bit
or wider memory system can use the MASTER/SLAVE Dual-Port RAM approach to achieve full-speed, error free
operation without additional discrete logic.
The QP7025 supports asynchronous access for reads or writes to any location in memory via two independent ports
with separate control, address, and I/O pins that function identically to the IDT7025 that it replaces. The QP7025 has an
automatic power down feature controlled by the appropriate Chip Enable (CE) pin that puts each port in a very low
standby power mode.
The QP7025 utilizes CMOS high-performance technology which allows the devices to typically operate on only 750mW
of power. Low-power (L) versions offer battery backup data retention capability with typical power consumption of 10μW
from a 2V source.
The QP7025 is available in a hermetic ceramic 84-pin PGA and a ceramic 84-pin Flatpack. Military grade product is
manufactured in compliance with the latest revision of MIL-PRF-38535 QML, making it ideally suited to military
temperature applications demanding the highest level of performance and reliability.
Features
- True Dual-Ported memory cells which allow simultaneous reads of the same memory location
- High-speed access
o Military: 35/45/55/70ns
o Industrial: 20/25ns
- Low-power operation
o QP7025S
Active: 750mW (typ.)
Standby: 0.2mW (typ.)
o QP7025L
Active: 750mW (typ.)
Standby: 0.2mW (typ.)
- Separate upper-byte and lower-byte control for multiplexed bus compatibility
- Expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device
o M/S = H for BUSY output flag on Master
o M/S = L for BUSY input on Slave
o Interrupt Flag
o On-chip port arbitration logic
- Full on-chip hardware support of semaphore signaling between ports
- Fully asynchronous operation from either port
- Battery backup operation—2V data retention
- TTL-compatible, single 5V (±10%) power supply
- Packages: 84-pin PGA & 84-pin Flatpack
- Industrial temperature range (–40°C to +85°C) is available
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QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Page 2 of 21
Block Diagram
Notes:
(Master): BUSY is output; (Slave): BUSY is input.
Outputs and INT outputs are non-tri-stated push-pull.
Functional Description
Left Port Right Port Functional Description
CE L CE R Chip Enable
R/ W L R/ W R Read/Write Enable
OE L OE R Output Enable
A0L – A12L A
0R – A12R Address
I/O0L – I/O15L I/O0R – I/O15R Data Input/Output
SEML SEMR Semaphore Enable
UB L UB R Upper Byte Select
LB L LB R Lower Byte Select
INT L INT R Interrupt Flag
BUSY L BUSY R Busy Flag
M / S Master Slave Select
VCC Power- All VCC pins must be connected to a power supply
GND Ground- All GND pins must be connected to a good ground
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Connection Diagrams
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Connection Diagrams
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Absolute Maximum Ratings /1
Condition Rating Units
Power Supply and Input Voltage -0.5 to +7.0 Volts DC
Storage Temperature Range -65 to +150 °C
Output Current 50 mA
Maximum Power Dissipation (PD) 2.2 W
Lead Temperature (soldering, 10 seconds) +260 ºC
Junction Temperature (TJ) +150 ºC
DC Input and Output Voltage Range -0.5 to VCC +0.5 Volts DC
Output Voltage Applied in High Z State -0.5 to VCC +0.5 Volts DC
/1Stresses above the AMR may cause permanent damage to the device. Extended operation at the maximum levels may degrade
performance and affect reliability.All voltages referenced to GND, unless otherwise specified.
Recommended Operating Conditions /1
Condition Rating Units Notes
Supply Voltage Range (VCC) 4.5 to 5.5 Volts DC
High-Level Input Voltage (VIH) 2.2 to 6.0 Volts DC
Low-Level Input Voltage (VIL) -0.5 to +0.8 Volts DC
Case Operating Range (Tc) -55C to +125 ºC
/1Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in
accordance with method 5004 of MIL-STD-883.
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ELECTRICAL PERFORMANCE CHARACTERISTICS-DC
Test Symbol Conditions
-55ºC ≤TA≤+125ºC
4.5 V ≤ VCC ≤ 5.5 V
Unless Otherwise Specified
Min Typ Max Unit
Output Low Voltage VOL VCC = 4.5V, IOL= 4mA,
VIH = 2.2V, VIL= 0.8V 0.4 V
Output High Voltage VOH VCC= 4.5V, IOH= -4mA,
VIH= 2.2V, VIL=0.8V 2.4 V
Input Leakage Current ILI VCC= 5.5V
VIN= GND to VCC 5
μA
Output Leakage Current ILO VCC= 5.5V, CE =VIH,
VIN = GND to VCC
5
μA
Dynamic Operating Current
(both ports active) ICC1
Outputs Open,
VCC = 5.5V, f= fmax /1,
SEM ≥VIH, CE ≤VIL
150 250 mA
Standby Supply Current
(both ports) TTL Inputs ICC2
SEM R = SEM L ≥ VIH,
CE R = CE L ≥ VIH,
VCC = 5.5V, f= fmax /1
8 25 mA
Standby Supply Current
(one port) TTL Inputs ICC3
Active ports outputs open
SEM R = SEM L ≥ VIH,
CE R = CE L ≥ VIH, Opposite Port = VIL,
VCC = 5.5V, f= fmax \1
85 160 mA
Full Standby Supply Current
(both ports) CMOS Inputs ICC4
SEM R= SEM L ≥ Vcc– 0.2V,
both ports CE R = CE L ≥ VCC– 0.2V,
VIN ≤ 0.2V or VIN ≥ Vcc – 0.2V,
VCC = 5.5V, f= 0 \2
0.04 5 mA
Full Standby Supply Current
(one port) CMOS Inputs ICC5
Active ports outputs open
SEM R= SEM L≥ VCC – 0.2 V,
one port CE R = CE L ≥ VCC– 0.2V,
opposite port < 0.2 V
VIN ≤ 0.2V or VIN ≥ Vcc – 0.2 V,
VCC = 5.5V, f= fmax \1
80 150 mA
Input Capacitance CIN VIN = 0 V, VCC = 5.0V,
f = 1MHz, TA = 25°C /3 11 pF
Output Capacitance COUT VOUT = 0 V, VCC = 5.0 V,
f = 1MHz, TA = 25°C /3 11 pF
1/ At fMAX, address and data inputs (excluding OE) are cycling at the maximum frequency of read cycle of 1/tAVAV, and using AC test
conditions of input levels of GND to 3.0 V.
2/ f = 0 Hz means no address or control lines change
3/ Measured at initial qualification only
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ELECTRICAL PERFORMANCE CHARACTERISTICS-Data Retention
Test Symbol Conditions
Conditions
-55ºC ≤TA≤+125ºC
4.5 V ≤ Vcc ≤ 5.5 V
Unless Otherwise Specified
Min Typ Max Unit
Data Retention Voltage
(“L” Series Devices Only) VDR CE ≥ VCC– 0.2V, VCC = 2.0 V
VIN ≥ VCC– 0.2V or ≤ 0.2 V
2.0 V
Data Retention Current
(“L” Series Devices Only) ICCDR CE ≥ VCC– 0.2V, VCC = 2.0 V
VIN ≥ VCC– 0.2V or ≤ 0.2 V
5 1000
μA
Chip Deselect to Data
Retention Time /4
(“L” Series Devices Only) tCDR
CE ≥ VCC – 0.2V, Vcc = 2.0V
VIN ≥ Vcc – 0.2V or ≤ 0.2V /5
See output test load figures
0 ns
Operation Recovery Time
/4
(“L” Series Devices Only) tR
CE ≥ VCC – 0.2V, Vcc = 2.0V
VIN ≥ Vcc – 0.2V or ≤ 0.2V /5
See output test load figures
tAVAV ns
/4 Parameter tested at initial characterization and after design change. Parameter guaranteed per limits in table.
/5 Measurement assumption: transition times ≤ 5 ns, input levels from GND to 3.0 V, timing ref levels of 1.5 V and output load per AC
Output Test Load Type I shown herein.
Data Retention Mode Timing
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ELECTRICAL PERFORMANCE CHARACTERISTICS- Read Cycle
Description Symbol Conditions
-55ºC ≤TA≤+125ºC
4.5 V ≤ Vcc ≤ 5.5 V
Unless Otherwise Specified
Min Max Unit
S or L 70 70
S or L 55 55
S or L 45 45
Read Cycle Time /6 tAVAV
S or L 35 35
ns
S or L 70 70
S or L 55 55
S or L 45 45
Address Access Time /6 tAVQV
S or L 35 35
ns
Semaphore Flag Update Pulse SEM or OE tSOP ALL 15
ns
S or L 70 70
S or L 55 55
S or L 45 45
Chip Enable Access time /7 tELQV
S or L 35 35
ns
S or L 70 70
S or L 55 55
S or L 45 45
Byte Enable Access time /7 tABE
S or L 35 35
ns
Chip Enable to Pwr Up /6, /8 tELPU ALL 0
ns
Chip Disable to Pwr Down /6, /8 tEHPD ALL 50 ns
Output Enable Access Time /7 tOLQV ALL 20
ns
Output Hold from Addr Change tAVQX ALL 3
ns
Output- Low Z tOLQX ALL 3
ns
S or L 70 30
S or L 55 25
S or L 45 20
Output- High Z tOLQZ
S or L 35 15
ns
/6 Measurement assumption: transition times ≤ 5 ns, input levels from GND to 3.0 V, timing ref levels of 1.5 V and output load per AC
Output Test Load Type I shown herein.
/7 To access RAM: CE = L, SEM = H, UB or LB = L
/8 Parameter tested at initial characterization and after design change. Parameter guaranteed per limits in table.
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ELECTRICAL PERFORMANCE CHARACTERISTICS- Write Cycle
Description Symbol Conditions
-55ºC ≤TA≤+125ºC
4.5 V ≤ Vcc ≤ 5.5 V
Unless Otherwise Specified
Min Max Unit
S or L 70 70
S or L 55 55
S or L 45 45
Write Cycle tAVAV
S or L 35 35
ns
S or L 70 50
S or L 55 45
S or L 45 40
Chip Enable to End-of-Write /9 /12 tELWH
S or L 35 30
ns
S or L 70 50
S or L 55 45
S or L 45 40
Address valid to End of Write /12 tAVWH
S or L 35 30
ns
Address Set-up /9, /12 tAVWL ALL 0
ns
S or L 70 50
S or L 55 40
S or L 45 35
Write Pulse /12 tWLWH
S or L 35 30
ns
Write Recovery /12 tWHAX ALL 0
ns
S or L 70 40
S or L 55 30
S or L 45 25
Data Valid to End of Write /12 tDVWH
S or L 35 25
ns
S or L 70 30
S or L 55 25
S or L 45 20
Output High Z tWLQZ
S or L 35 15
ns
Data Hold Time /10, /12 tWHDX ALL 0
ns
S or L 70 30
S or L 55 25
S or L 45 20
Write Enable to Output (in High Z) /11 tWLQZ
S or L 35 15
ns
Output Active from End of Write /10 tWHQX ALL 0
ns
SEM Flag- Write to Read Time /12 tSWRD ALL 10
ns
SEM Flag Contention Window /12 tSPS ALL 10
ns
/9 To access RAM: CE = H, SEM = H, UB or LB = L To access Semaphore: CE = h, SEM = H, UB or LB = L. Either
condition must be valid for the entire tEL:WH time.
/10 tWHDX < tWHQX
/11 Transition measured at steady-state high level -500mV or steady-state low level +500mV on the output from the 1.5 V level on
the input; CL = 5 pF (ref AC Output Test Load Type II shown herein).
/12 Measurement assumption: transition times ≤ 5 ns, input levels from GND to 3.0 V, timing ref levels of 1.5 V and output load per
AC Output Test Load Type I shown herein.
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ELECTRICAL PERFORMANCE CHARACTERISTICS- BUSY Timing
Description Symbol Conditions
-55ºC ≤TA≤+125ºC
4.5 V ≤ Vcc ≤ 5.5 V
Unless Otherwise Specified
M/ S = vIH /12
Min Max Unit
S or L 70 45 ns
S or L 55 45 ns
S or L 45 35 ns
BUSY Access Time from Address
Match
tBAA
S or L 35 35 ns
S or L 70 40 ns
S or L 55 40 ns
S or L 45 30 ns
BUSY Disable Time from Address Not
Matched
tBDA
S or L 35 30 ns
S or L 70 40 ns
S or L 55 40 ns
S or L 45 30 ns
BUSY Access Time from Chip Enable
Low
TBAC
S or L 35 30 ns
S or L 70 35 ns
S or L 55 35 ns
S or L 45 25 ns
BUSY Disable Time from Chip Enable
High
TBDC
S or L 35 25 ns
Arbitration priority Set-up Time TAPS ALL 5 ns
BUSY Disable to Chip Enable High TBDD ALL 35 ns
Write Hold after BUSY tWH ALL 25 ns
/12 Measurement assumption: transition times ≤ 5 ns, input levels from GND to 3.0 V, timing ref levels of 1.5 V and output load per
AC Output Test Load Type I shown herein.
ELECTRICAL PERFORMANCE CHARACTERISTICS- BUSY Timing
Description Symbol Conditions
-55ºC ≤TA≤+125ºC
4.5 V ≤ Vcc ≤ 5.5 V
Unless Otherwise Specified
M/ S = vIL /12
Min Max Unit
BUSY Input to Write tWB ALL 0 ns
Write Hold After BUSY tWH ALL 25 ns
/12 Measurement assumption: transition times ≤ 5 ns, input levels from GND to 3.0 V, timing ref levels of 1.5 V and output load per
AC Output Test Load Type I shown herein.
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ELECTRICAL PERFORMANCE CHARACTERISTICS- Port-to-Port Delay Timing
Description Symbol Conditions
-55ºC ≤TA≤+125ºC
4.5 V ≤ Vcc ≤ 5.5 V
Unless Otherwise Specified
Min Max Unit
S or L 70 95
S or L 55 80
S or L 45 70
Write Pulse to Data Delay tWDD
S or L 35 60
ns
S or L 70 80
S or L 55 65
S or L 45 55
Write Data Valid to Read Data Delay tDDD
S or L 35 45
ns
ELECTRICAL PERFORMANCE CHARACTERISTICS- Interrupt Timing
Description Symbol Conditions
-55ºC ≤TA≤+125ºC
4.5 V ≤ Vcc ≤ 5.5 V
Unless Otherwise Specified
Min Max Unit
Address Set-up Time tAS ALL 0 ns
Write Recovery Time tWR ALL 0 ns
S or L 70 50
S or L 55 40
S or L 45 35
Interrupt Set Time tNS
S or L 35 30
ns
S or L 70 50
S or L 55 40
S or L 45 35
Interrupt Reset Time tinr
S or L 35 30
ns
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AC Output Test Load
Type I Type II
(tOLQX tWLQZ tWHQX)
AC TEST CONDITIONS
Input Pulse levels GND to 3.0 V
Input rise & fall times (tr & tf) ≤ 5ns
Input timing reference levels 1.5 V
Output reference levels 1.5 V
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Read Cycle Timing
Notes on read operation:
1. SEM = VIH
2. Start of valid data dependant upon which timing becomes effective last (tABE, tOLQV, tELQV, tAVQV, tBDD)
3. Timing dependant upon which signal asserted last ( OE ,CE,LB OR UB ).
4. Timing dependant upon which signal de-asserted first ( OE ,CE,LB OR UB ).
5. tBDD delay is required only in the case where opposite port is completing a write operation to the same address location. For
simultaneous read operations, BUSY has no relation to valid output data.
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Write Cycle No 1 Timing- R/ W Controlled (see notes 1, 3, 5, 8)
Write Cycle No 2 Timing- CE , UB , LB Controlled (see notes 1, 3, 5, 8)
Notes on Write Cycle
1. R/ W or CE or UB and LB must be high during all address transitions.
2. A write occurs during the overlap (tELWH or tWLWH) of a low UB or LB and a low CE and a low R/ W for memory array
write cycle.
3. tWHAX is measured from the earlier of CE or R/ W (or SEM or R/ W ) going high to the end of the write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the
CE or SEM low transition occurs simultaneously with or after the R/ W low transition, the outputs remain in the high
impedance state.
6. Timing dependant upon which enable signal is asserted last.
7. Timing dependant upon which enable signal is de-asserted first.
8. For Write Cycle No.1, if OE is low during R/ W controlled write cycle, the write pulse width must be the larger of tWLWH or
(tWLQZ + tDVWH) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDVWH. If OE is high
during the R/ W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified
tWLWH.
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Semaphore Read After Write Timing
Notes
1. CE = VIH or UB ;LB = VIH for period of above timing for both the read and write operation.
2. All inputs and outputs equal to the same semaphore value for DATAOUT VALID condition.
Semaphore Write Contention Timing
Notes:
1. DOR = DOL, CE R = CE L = H, semaphore flag is released from both sides (reads as one from both sides) at cycle start.
2. ‘A’ may either be the left or right port. ‘B’ is the opposite port from ‘A’
3. This parameter is measured from R/ WA or SEMA going high to R/ WB or SEMB going high.
4. If tSPS is violated, semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
5. CE = H for the duration of the Semaphore Read After Write Timing (both read and write cycle)
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Interrupt Timing
Notes
1. All timing is the same for left and right ports.
2. Port ‘A’ may be either the left or right port.
3. See Interrupt Truth Table
4. Timing is dependant upon which enable signal is asserted last ( CE or R/ W )
5. Timing is dependant upon which enable signal is de-asserted first ( CE or R/ W )
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Busy Arbitration ( CE Controlled) (M/ S = H)
Busy Arbitration Cycle (Address Match Controlled) (M/ S = H)
Notes:
1. All timing is the same for left and right ports. Port ‘A’ may be either the left or right port. Port ‘B’ is the port opposite from ‘A’.
2. If tAPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side the busy
signal will be asserted.
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Write with Port - to - Port Delay (M/S = L)
Slave Write (M/ S = L)
Power-Up / Power-Down Timing
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Truth Table: Non-contention read write control
Inputs Outputs
CE R/W OE UB LB SEM I/O8-15 I/O0-7 Mode
H X X X X H High-Z High-Z Deselected: Power-down
X X X H H H High-Z High-Z Both Bytes Deselected
L L X L H H DATAIN High-Z Write to Upper Byte Only
L L X H L H High-Z DATAIN Write to Lower Byte Only
L L X L L H DATAIN DATAIN Write to Both Bytes
L H L L H H DATAOUT High-Z Read Upper Byte Only
L H L H L H High-Z DATAOUT Read Lower Byte Only
L H L L L H DATAOUT DATAOUT Read Both Bytes
X X H X X X High-Z High-Z Outputs Disabled
Notes:
1. Read/Write controls are separate for independent left and right address ports (A0L – A12L and A0R – A12R)
Truth Table: Semaphore Read/Write Control
Inputs Outputs
CE R/W OE UB LB SEM I/O8-15 I/O0-7 Mode
H H L X X L DATA
OUT DATA
OUT Read semaphore flag data out
X H L H H L DATA
OUT DATA
OUT Read semaphore flag data out
H ↑ X X X L DATAIN DATAIN Write I/O0 into semaphore flag
X ↑ X H H L DATAIN DATAIN Write I/O0 into semaphore flag
L X X L X L - - -
L X X X L L - - -
Notes:
1. Semaphore flags are addressed by A0 – A2
2. Semaphore Flags are written via I/O0 and read from I/O0 – I/O15.
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Truth Table: Address BUSY Arbitration
Outputs Inputs
CE L CE R A0L – A12L
A0R – A12R BUSY L BUSY R
Function
X X No Match H High-Z Normal
H X Match H High-Z Normal
X H Match H High-Z Normal
L L Match High-Z DATAIN Write Inhibit
2
Truth Table: Interrupt Flag
Left Port Right Port
R/ W L CE L OE L A0L –
A12L INT L R/ W R CE R OE R A0R –
A12R INT R
Function
L L X 1FFF X X X X X L
Set right INT R flag
X X X X X X L L 1FFF H
Reset right INT R flag
X X X X L L L X 1FFE X
Set left INT L flag
X L L 1FFE H X X X X X
Set left INT L flag
Notes:
1. Assumes BUSY L = BUSY R = VIH
2. If
BUSY L = VIL, no change
3. If
BUSY R = VIL, no change
1. INT L and INT R must be initialized at power-up
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Ordering Information
Part Number Package (Mil-Std-1835) Generic
5962-9161701MXA CMGA15-PN QP7025S70GB
5962-9161701MYA CQFP84 –See Note 2 QP7025S70FB
5962-9161702MXA CMGA15-PN QP7025L70GB
5962-9161702MYA CQFP84 –See Note 2 QP7025L70FB
5962-9161703MXA CMGA15-PN QP7025S55GB
5962-9161703MYA CQFP84 –See Note 2 QP7025S55FB
5962-9161704MXA CMGA15-PN QP7025L55GB
5962-9161704MYA CQFP84 –See Note 2 QP7025L55FB
5962-9161705MXA CMGA15-PN QP7025S45GB
5962-9161705MYA CQFP84 –See Note 2 QP7025S45FB
5962-9161706MXA CMGA15-PN QP7025L45GB
5962-9161706MYA CQFP84 –See Note 2 QP7025L45FB
5962-9161707MXA CMGA15-PN QP7025S35GB
5962-9161707MYA CQFP84 –See Note 2 QP7025S35FB
5962-9161708MXA CMGA15-PN QP7025L35GB
5962-9161708MYA CQFP84 –See Note 2 QP7025L35FB
Notes:
1. Package outline information and specifications are defined by Mil-Std-1835 package dimension requirements.
2. See SMD 5962-91617 Fig.1 Case Outline ‘Y’ Fig. 1
3. QP Semiconductor supports Source Control Drawing (SCD), and custom package development for this product
family.
4. The listed drawings, Mil-PRF-38535, Mil-Std-883 and Mil-Std-1835 are available online at
http://www.dscc.dla.mil/
5. Additional information is available at our website http://www.qpsemi.com
Document Revision History
Date
Revision
Level
Description
20 June 2010 0 initial release
