REV. B
Information furnished by Analog Devices is believed to be accurate and
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may result from its use. No license is granted by implication or otherwise
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Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
AD5516
*
16-Channel, 12-Bit Voltage-Output DAC
with 14-Bit Increment Mode
*Protected by U.S. Patent No.
FEATURES
High Integration:
16-Channel DAC in 12 mm ⴛ 12 mm CSPBGA
14-Bit Resolution via Increment/Decrement Mode
Guaranteed Monotonic
Low Power, SPI®, QSPI™, MICROWIRE™, and
DSP Compatible
3-Wire Serial Interface
Output Impedance 0.5 ⍀
Output Voltage Range
ⴞ2.5 V (AD5516-1)
ⴞ5 V (AD5516-2)
ⴞ10 V (AD5516-3)
Asynchronous Reset Facility (via RESET Pin)
Asynchronous Power-Down Facility (via PD Pin)
Daisy-Chain Mode
Temperature Range: –40ⴗC to +85ⴗC
APPLICATIONS
Level Setting
Instrumentation
Automatic Test Equipment
Optical Networks
Industrial Control Systems
Data Acquisition
Low Cost I/O
FUNCTIONAL BLOCK DIAGRAM
RFB0
RESET
BUSY
DACGND
AGND
DGND
DCEN
AD5516
DVCC AVCC VDD VSS
VOUT0
RFB1
VOUT1
RFB14
VOUT14
RFB15
VOUT15
ROFFS RFB
DAC
VBIAS
ROFFS RFB
DAC
ROFFS RFB
DAC
ROFFS RFB
DAC
REF_IN
PD
POWER-DOWN
LOGIC
SCLK DIN DOUT SYNC
INTERFACE
CONTROL
LOGIC 7-BIT BUS
ANALOG
CALIBRATION
LOOP
12-BIT BUS
MODE1
MODE2
GENERAL DESCRIPTION
The AD5516 is a 16-channel, 12-bit voltage-output DAC. The
selected DAC register is written to via the 3-wire serial inter-
face. DAC selection is accomplished via address bits A3–A0.
14-bit resolution can be achieved by fine adjustment in Incre-
ment/Decrement Mode (Mode 2). The serial interface operates
at clock rates up to 20 MHz and is compatible with standard
SPI, MICROWIRE, and DSP interface standards. The output
voltage range is fixed at ±2.5 V (AD5516-1), ±5 V (AD5516-2),
and ±10 V (AD5516-3). Access to the feedback resistor in each
channel is provided via the R
FB
0 to R
FB
15 pins.
The device is operated with AV
CC
= 5 V ± 5%, DV
CC
= 2.7 V
to 5.25 V, V
SS
= –4.75 V to –12 V, and V
DD
= +4.75 V to +12 V,
and requires a stable 3 V reference on REF_IN.
PRODUCT HIGHLIGHTS
1. Sixteen 12-bit DACs in one package, guaranteed monotonic.
2. Available in a 74-lead CSPBGA package with a body size of
12 mm ⫻ 12 mm.
5,969,657.
REV. B–2–
AD5516–SPECIFICATIONS
(VDD = +4.75 V to +13.2 V, VSS = –4.75 V to –13.2 V; AVCC = 4.75 V to 5.25 V; DVCC =
2.7 V to 5.25 V; AGND = DGND = DACGND = 0 V; REF_IN = 3 V; All outputs unloaded.
All specifications TMIN to TMAX, unless otherwise noted.)
Parameter
1
A Version
2
Unit Conditions/Comments
DAC DC PERFORMANCE
Resolution 12 Bits
Integral Nonlinearity (INL) ±2LSB max Mode 1
Differential Nonlinearity (DNL) –1/+1.3 LSB max ±0.5 LSB typ, Monotonic; Mode 1
Increment/Decrement Step-Size ±0.25 LSB typ Monotonic; Mode 2 Only
Bipolar Zero Error ±7LSB max
Positive Full-Scale Error ±10 LSB max
Negative Full-Scale Error ±10 LSB max
VOLTAGE REFERENCE
REF_IN
Nominal Input Voltage 3 V
Input Voltage Range
3
2.875/3.125 V min/max
Input Current ±1mA max < 1 nA typ
ANALOG OUTPUTS (V
OUT
0–15)
Output Temperature Coefficient
3, 4
10 ppm/∞C typ of FSR
DC Output Impedance
3
0.5 W typ
Output Range
5
AD5516-1 ±2.5 V typ 100 mA Output Load
AD5516-2 ±5V typ 100 mA Output Load
AD5516-3 ±10 V typ 100 mA Output Load
Resistive Load
3, 6, 7
5kW min
Capacitive Load
3, 6
200 pF
Short Circuit Current
3
7mA typ
DC Power Supply Rejection Ratio
3
–85 dB typ V
DD
= +12 V ± 5%, V
SS
= –12 V ± 5%
DC Crosstalk
3
0.1 LSB max
DIGITAL INPUTS
3
Input Current ±10 mA max ±5 mA typ
Input Low Voltage 0.8 V max DV
CC
= 5 V ± 5%
0.4 V max DV
CC
= 3 V ± 10%
Input High Voltage 2.4 V min DV
CC
= 5 V ± 5%
2V min DV
CC
= 3 V ± 10%
Input Hysteresis (SCLK and SYNC)150 mV typ
Input Capacitance 10 pF max 5 pF typ
DIGITAL OUTPUTS (BUSY, D
OUT
)
3
Output Low Voltage, DV
CC
= 5 V 0.4 V max Sinking 200 mA
Output High Voltage, DV
CC
= 5 V 4 V min Sourcing 200 mA
Output Low Voltage, DV
CC
= 3 V 0.4 V max Sinking 200 mA
Output High Voltage, DV
CC
= 3 V 2.4 V min Sourcing 200 mA
High Impedance Leakage Current (D
OUT
only) ±1mA max DCEN = 0
High Impedance Output Capacitance (D
OUT
only) 5 pF typ DCEN = 0
POWER REQUIREMENTS
Power Supply Voltages
V
DD
4.75/15.75 V min/max
V
SS
–4.75/–15.75 V min/max
AV
CC
4.75/5.25 V min/max
DV
CC
2.7/5.25 V min/max
Power Supply Currents
8
I
DD
5mA max 3.5 mA typ. All Channels Full-Scale.
I
SS
5mA max 3.5 mA typ. All Channels Full-Scale.
AI
CC
17 mA max 13 mA typ
DI
CC
1.5 mA max 1 mA typ
Power-Down Currents
8
I
DD
1mA typ
I
SS
1mA typ
AI
CC
2mA max 200 nA typ
DI
CC
2mA max 200 nA typ
Power Dissipation
8
105 mW typ V
DD
=+5 V, V
SS
=–5 V
NOTES
1
See Terminology section.
2
A Version: Industrial temperature range –40∞C to +85∞C; typical at +25∞C.
3
Guaranteed by design and characterization; not production tested.
4
AD780 as reference for the AD5516.
5
Output range is restricted from V
SS
+ 2 V to V
DD
– 2 V. Output span varies with reference voltage and is functional down to 2 V.
6
Ensure that you do not exceed T
J (MAX)
. See Absolute Maximum Ratings section.
7
With 5 k
W
resistive load, footroom required is as follows: AD5516–1, 2 V; AD5516–2, 2.5 V; AD5516–3, 3 V.
8
Outputs unloaded.
Specifications subject to change without notice.
REV. B
AD5516
–3–
AC CHARACTERISTICS
(VDD = +4.75 V to +13.2 V, VSS = –4.75 V to –13.2 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V;
AGND = DGND = DACGND = 0 V; REF IN = 3 V. All outputs unloaded.
All specifications TMIN to TMAX, unless otherwise noted.)
Parameter
1, 2
A Version
3
Unit Conditions/Comments
Output Voltage Settling Time (Mode 1)
4
100 pF, 5 kW Load Full-Scale Change
AD5516–1 32 s max
AD5516–2 32 s max
AD5516–3 36 s max
Output Voltage Settling Time (Mode 2)
4
100 pF, 5 kW Load, 127 Code Increment
AD5516–1 2.5 s max
AD5516–2 3.35 s max
AD5516–3 7 s max
Slew Rate 0.85 V/s typ
Digital-to-Analog Glitch Impulse 1 nV-s typ 1 LSB Change around Major Carry
Digital Crosstalk 5 nV-s typ
Analog Crosstalk
AD5516–1 1 nV-s typ
AD5516–2 5 nV-s typ
AD5516–3 20 nV-s typ
Digital Feedthrough 1 nV-s typ
Output Noise Spectral Density @ 10 kHz
AD5516–1 150 nV/(Hz)
1/2
typ
AD5516–2 350 nV/(Hz)
1/2
typ
AD5516–3 700 nV/(Hz)
1/2
typ
NOTES
1
See Terminology section.
2
Guaranteed by design and characterization; not production tested.
3
A version: Industrial temperature range –40∞C to +85∞C.
4
Timed from the end of a write sequence and includes BUSY low time.
Specifications subject to change without notice.
Limit at T
MIN
, T
MAX
Parameter
1, 2, 3
(A Version) Unit Conditions/Comments
f
UPDATE1
32 kHz max DAC Update Rate (Mode 1)
f
UPDATE2
750 kHz max DAC Update Rate (Mode 2)
f
CLKIN
20 MHz max SCLK Frequency
t
1
20 ns min SCLK High Pulsewidth
t
2
20 ns min SCLK Low Pulsewidth
t
3
15 ns min SYNC Falling Edge to SCLK Falling Edge Setup Time
t
4
5ns min D
IN
Setup Time
t
5
5ns min D
IN
Hold Time
t
6
0ns min SCLK Falling Edge to SYNC Rising Edge
t
7
10 ns min Minimum SYNC High Time (Standalone Mode)
t
7MODE2
400 ns min Minimum SYNC High Time (Daisy-Chain Mode)
t
8MODE1
10 ns min BUSY Rising Edge to SYNC Falling Edge
t
9MODE2
200 ns min 18th SCLK Falling Edge to SYNC Falling Edge (Standalone Mode)
t
10
10 ns min SYNC Rising Edge to SCLK Rising Edge (Daisy-Chain Mode)
t
114
20 ns max SCLK Rising Edge to D
OUT
Valid (Daisy-Chain Mode)
t
12
20 ns min RESET Pulsewidth
NOTES
1
See Timing Diagrams in Figures 1 and 2.
2
Guaranteed by design and characterization; not production tested.
3
All input signals are specified with tr = tf = 5 ns (10% to 90% of DV
CC
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
4
This is measured with the load circuit of Figure 3.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
(VDD = +4.75 V to +13.2 V, VSS = – 4.75 V to –13.2 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V;
AGND = DGND = DACGND = 0 V. All specifications TMIN to TMAX, unless otherwise noted.)
REV. B–4–
AD5516
TIMING DIAGRAMS
t
12
SCLK
SYNC
DIN
BUSY
RESET
12 1718
t
3
t
7
t
4
t
5
t
2
t
1
t
6
t
9
MODE2
t
8
MODE1
BIT 17 BIT 0
LSBMSB
Figure 1. Serial Interface Timing Diagram
SCLK
SYNC
DIN
DOUT
BUSY
BIT 17 BIT 0 BIT 17 BIT 0
INPUT WORD FOR DEVICE N+1
UNDEFINED INPUT WORD FOR DEVICE N
INPUT WORD FOR DEVICE N
BIT 17 BIT 0
t7 MODE2
t3t2t1
t6
t10
t5
t4
t11
t8 MODE1
LSBMSB
Figure 2. Daisy-Chaining Timing Diagram
TO OUTPUT
PIN C
L
50pF
200AI
OH
200AI
OL
1.6V
Figure 3. Load Circuit for D
OUT
Timing Specifications
REV. B
AD5516
–5–
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5516 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS
1, 2
(T
A
= 25°C, unless otherwise noted.)
V
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V
V
SS
to AGND . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –17 V
AV
CC
to AGND, DACGND . . . . . . . . . . . . . . . –0.3 V to +7 V
DV
CC
to DGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
Digital Inputs to DGND . . . . . . . . . . . –0.3 V to DV
CC
+0.3 V
Digital Outputs to DGND . . . . . . . . . . –0.3 V to DV
CC
+0.3 V
REF_IN to AGND, DACGND . . . . . . –0.3 V to AV
CC
+ 0.3 V
V
OUT
0–15 to AGND . . . . . . . . . . . . V
SS
– 0.3 V to V
DD
+0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
R
FB
0–15 to AGND . . . . . . . . . . . . . V
SS
– 0.3 V to V
DD
+0.3 V
Operating Temperature Range, Industrial . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (T
J
MAX
) . . . . . . . . . . . . . . . . . . . 150°C
74-Lead CSPBGA Package,
JA
Thermal Impedance . . . 41°C/W
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Time at Peak Temperature . . . . . . . . . . . . . 10 sec to 40 sec
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE
Model Function Output Voltage Span Package Option
AD5516ABC-1 16 DACs ±2.5 V 74-Lead CSPBGA
AD5516ABC-2 16 DACs ±5 V 74-Lead CSPBGA
AD5516ABC-3 16 DACs ±10 V 74-Lead CSPBGA
EVAL-AD5516-1EB Evaluation Board
EVAL-AD5516-2EB Evaluation Board
EVAL-AD5516-3EB Evaluation Board
REV. B–6–
AD5516
PIN CONFIGURATION
A
B
C
D
E
F
G
H
J
K
1110987654321
TOP VIEW
A
B
C
D
E
F
G
H
J
K
1110987654321
LL
74-LEAD CSPBGA BALL CONFIGURATION
CSPBGA Ball CSPBGA Ball CSPBGA Ball CSPBGA Ball CSPBGA Ball
Number Name Number Name Number Name Number Name Number Name
NC = Not Internally Connected
A1 NC
A2 NC
A3 RESET
A4 BUSY
A5 DGND
A6 DV
CC
A7 D
OUT
A8 D
IN
A9 SYNC
A10 NC
A11 NC
B1 NC
B2 NC
B3 NC
B4 DCEN
B5 DGND
B6 DGND
B7 NC
B8 NC
B9 SCLK
B10 NC
B11 REF_IN
C1 V
OUT
0
C2 DACGND
C6 NC
C10 AV
CC
1
C11 NC
D1 R
FB
0
D2 DACGND
D10 AV
CC
2
D11 NC
E1 V
OUT
1
E2 NC
E10 AGND1
E11 PD
F1 V
OUT
2
F2 R
FB
1
F10 AGND2
F11 R
FB
14
G1 R
FB
2
G2 R
FB
15
G10 V
OUT
14
G11 R
FB
13
H1 V
OUT
3
H2 V
OUT
15
H10 V
OUT
13
H11 V
OUT
12
J1 R
FB
3
J2 V
OUT
4
J6 NC
J10 R
FB
12
J11 R
FB
11
K1 R
FB
4
K2 V
OUT
5
K3 R
FB
5
K4 NC
K5 V
SS
2
K6 V
SS
1
K7 V
OUT
10
K8 V
OUT
9
K9 R
FB
10
K10 R
FB
9
K11 V
OUT
11
L1 NC
L2 V
OUT
6
L3 R
FB
6
L4 V
OUT
7
L5 NC
L6 V
DD
2
L7 V
DD
1
L8 R
FB
7
L9 V
OUT
8
L10 R
FB
8
L11 NC
PIN FUNCTION DESCRIPTIONS
Mnemonic Function
AGND (1–2) Analog GND Pins
AV
CC
(1–2) Analog Supply Pins. Voltage range from 4.75 V to 5.25 V.
V
DD
(1–2) V
DD
Supply Pins. Voltage range from 4.75 V to 15.75 V.
V
SS
(1–2) V
SS
Supply Pins. Voltage range from –4.75 V to –15.75 V.
DGND Digital GND Pins
DV
CC
Digital Supply Pin. Voltage range from 2.7 V to 5.25 V.
DACGND Reference GND Supply for All 16 DACs
REF_IN Reference Input Voltage for All 16 DACs. The recommended value of REF_IN is 3 V.
V
OUT
(0–15) Analog Output Voltages from the 16 DAC Channels
R
FB
(0–15) Feedback Resistors. For nominal output voltage range, connect each R
FB
to its corresponding V
OUT
. Access to
the feedback resistors enables the user to increase the DAC current drive or generate programmable current
sources. They should not be used for gain adjustment.
SYNC Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is
transferred in on the falling edge of SCLK.
REV. B
AD5516
–7–
TERMINOLOGY
Integral Nonlinearity (INL)
This is a measure of the maximum deviation from a straight line
passing through the endpoints of the DAC transfer function. It is
expressed in LSBs.
Differential Nonlinearity (DNL)
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified DNL of –1 LSB maximum ensures
monotonicity.
Bipolar Zero Error
Bipolar zero error is the deviation of the DAC output from the ideal
midscale of 0 V. It is measured with 10...00 loaded to the DAC.
It is expressed in LSBs.
Positive Full-Scale Error
This is the error in the DAC output voltage with all 1s loaded to
the DAC. Ideally the DAC output voltage, with all 1s loaded to the
DAC registers, should be 2.5 V – 1 LSB (AD5516-1), 5 V – 1 LSB
(AD5516-2), and 10 V – 1 LSB (AD5516-3). It is expressed in LSBs.
Negative Full-Scale Error
This is the error in the DAC output voltage with all 0s loaded to
the DAC. Ideally the DAC output voltage, with all 0s loaded to the
DAC registers, should be –2.5 V (AD5516-1), –5 V (AD5516-2),
and –10 V (AD5516-3). It is expressed in LSBs.
Output Temperature Coefficient
This is a measure of the change in analog output with changes in
temperature. It is expressed in ppm/∞C of FSR.
DC Power Supply Rejection Ratio
DC power supply rejection ratio (PSRR) is a measure of the change
in analog output for a change in supply voltage (V
DD
and V
SS
).
It is expressed in dB. V
DD
and V
SS
are varied ±5%.
DC Crosstalk
This is the dc change in the output level of one DAC at midscale
in response to a full-scale code change (all 0s to all 1s and vice
versa) and output change of another DAC. It is expressed in LSB.
Output Settling Time
This is the time taken from when the last data bit is clocked into
the DAC until the output has settled to within ±0.5 LSB of its
final value (see TPC 7).
Digital-to-Analog Glitch Impulse
This is the area of the glitch injected into the analog output when
the code in the DAC register changes state. It is specified as the
area of the glitch in nV-s when the digital code is changed by
1LSB at the major carry transition (011...11 to 100...00 or
100...00 to 011...11).
Digital Crosstalk
This is the glitch impulse transferred to the output of one DAC at
midscale while a full-scale code change (all 1s to all 0s and vice
versa) is being written to another DAC. It is expressed in nV-s.
Analog Crosstalk
This is the area of the glitch transferred to the output (V
OUT
) of
one DAC due to a full-scale change in the output (V
OUT
) of
another DAC. The area of the glitch is expressed in nV-s.
Digital Feedthrough
This is a measure of the impulse injected into the analog outputs
from the digital control inputs when the part is not being written
to, i.e., SYNC is high. It is specified in nV-s and measured with
a worst-case change on the digital input pins, e.g., from all 0s to
all 1s and vice versa.
Output Noise Spectral Density
This is a measure of internally generated random noise. Random
noise is characterized as a spectral density (voltage per root hertz).
It is measured in nV/(Hz)
1/2
.
PIN FUNCTION DESCRIPTIONS (continued)
Mnemonic Function
SCLK Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock
speeds up to 20 MHz.
D
IN
Serial Data Input. Data must be valid on the falling edge of SCLK.
D
OUT
Serial Data Output. D
OUT
can be used for daisy-chaining a number of devices together or for reading back the
data in the shift register for diagnostic purposes. Data is clocked out on D
OUT
on the rising edge of SCLK and is
valid on the falling edge of SCLK.
DCEN
1
Active High Control Input. This pin is tied high to enable Daisy-Chain Mode.
RESET
2
Active Low Control Input. This resets all DAC registers to power-on value.
PD
1
Active High Control Input. All DACs go into power-down mode when this pin is high. The DAC outputs go into
a high impedance state.
BUSY Active Low Output. This signal tells the user that the analog calibration loop is active. It goes low during conversion.
The duration of the pulse on BUSY determines the maximum DAC update rate, f
UPDATE
. Further writes to the
AD5516 are ignored while BUSY is active.
NOTES
1
Internal pull-down device on this logic input. Therefore it can be left floating and will default to a logic low condition.
2
Internal pull-up device on this logic input. Therefore it can be left floating and will default to a logic high condition.
REV. B–8–
AD5516–Typical Performance Characteristics
DAC CODE
DNL ERROR (LSB)
1.0
0.6
0.2
–0.2
0
–0.4
–0.6
0.8
0.4
–0.8
–1.0 1000 2000 3000 40000
REF_IN = 3V
T
A
= 25ⴗC
TPC 1. Typical DNL Plot
TEMPERATURE (ⴗC)
ERROR (LSB)
3
–40
1
–1
0
–2
–3 –20 0 20 40 80
2
60
REF_IN = 3V
BIPOLAR ZERO ERROR
POSITIVE FS ERROR
NEGATIVE FS ERROR
TPC 4. Bipolar Zero Error and
Full-Scale Error vs. Temperature
VOUT ( V)
3.0
1.0
0
–1.0
–2.0
2.0
–3.0
TIME BASE = 2.5s/DIV
TA = 25ⴗC
REF_IN = 3V
TPC 7. AD5516–1 Full-Scale
Settling Time
DAC CODE
INL ERROR (LSB)
1.0
0.6
0.2
–0.2
0
–0.4
–0.6
0.8
0.4
0
–0.8
–1.0 1000 2000 3000 4000
REF_IN = 3V
T
A
= 25ⴗC
TPC 2. Typical INL Plot
TEMPERATURE (ⴗC)
V
OUT
(V)
0.003
–40
0.002
0.001
–0.001
0
–0.002
–0.003
–20 0 20 40 80
AV
DD
= +12V
AV
SS
= –12V
REF_IN
= 3V
MIDSCALE LOADED
60
TPC 5. V
OUT
vs. Temperature
VOUT
PD
TA = 25ⴗC
REF_IN = 3V
5V/DIV
2V/DIV
2s/DIV
TPC 8. Exiting Power-Down to
Full Scale
TEMPERATURE (ⴗC)
ERROR (LSB)
2.0
–40
1.0
0
–1.0
–0.5
–1.5
–2.0 –20 0 20 40 80
1.5
0.5
60
INL
+VE
DNL
–VE
DNL
REF_IN = 3V
TPC 3. Typical INL Error and DNL
Error vs. Temperature
CURRENT (mA)
V
OUT
(V)
–6
0.002
–4 –2 0 2 64
MIDSCALE
AV
DD
= +12V
AV
SS
= –12V
REF_IN = 3V
T
A
= 25ⴗC
0.0
–0.002
–0.004
–0.006
–0.008
–0.01
0.004
0.006
0.008
0.01
–8 8
TPC 6. V
OUT
Source and Sink
Capability
5V
BUSY
–0.029
–0.031
–0.032
–0.030
–0.033
T
A
= 25ⴗC
REF_IN = 3V
CALIBRATION TIME
NEW
VA L U E
2.5s/DIV
OLD
VA L U E
0V
TPC 9. AD5516–1 Major Code
Transition Glitch Impulse
REV. B
AD5516
–9–
VOUT (V)
FREQUENCY
450
350
250
150
200
100
50
400
300
2.48992.48962.4893
0
TPC 10. AD5516–1 V
OUT
Repeatability;
Programming the Same Code
Multiple Times
FREQUENCY (%)
30
20
0
–10 0 10
10
REF_IN = 3V
T
A
= 25ⴗC
LSBs
TPC 13. Negative Full-Scale Error
Distribution
FREQUENCY (%)
40
20
0
–10 0 10
REF_IN = 3V
T
A
= 25ⴗC
LSBs
TPC 12. Positive Full-Scale
Error Distribution
6
4
5
3
0 1000 1500500 2000 2500
CODE
ERROR (LSB)
3000 3500 4000
2
0
1
REF_IN = 3V
T
A
= 25ⴗC
TPC 15. Accuracy vs. Increment
Step, Using All 12 Mode 2 Bits
FREQUENCY (%)
40
20
0
–10 0 10
REF_IN = 3V
T
A
= 25ⴗC
LSBs
TPC 11. Bipolar Error Distribution
STEP SIZE
ERROR (LSB)
2.5
2.0
1.5
1.0
0.5
0
020406080100 120 130
REF_IN = 3V
T
A
= 25ⴗC
TPC 14. Accuracy vs. Increment Step
REV. B–10–
AD5516
00A3 A2 A1 A0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
MSB LSB
MODE
BITS
ADDRESS
BITS
DATA
BITS
Figure 4. Mode 1 Data Format
01A3 A2 A1 A0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
MSB LSB
MODE
BITS
ADDRESS
BITS
12 INCREMENT
BITS
10A3 A2 A1 A0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
MSB LSB
MODE
BITS
ADDRESS
BITS
12 DECREMENT
BITS
Figure 5. Mode 2 Data Format
FUNCTIONAL DESCRIPTION
The AD5516 consists of sixteen 12-bit DACs in a single pack-
age. A single reference input pin (REF_IN) is used to provide a
3V reference for all 16 DACs. To update a DAC’s output
voltage, the required DAC is addressed via the 3-wire serial
interface. Once the serial write is complete, the selected DAC
converts the code into an output voltage. The output amplifiers
translate the DAC output range to give the appropriate voltage
range (±2.5 V, ±5V, or ±10 V) at output pins V
OUT
0 to V
OUT
15.
The AD5516 uses a self-calibrating architecture to achieve 12-bit
performance. The calibration routine servos to select the appro-
priate voltage level on an internal 14-bit resolution DAC. BUSY
output goes low for the duration of the calibration and further
writes to the AD5516 are ignored while BUSY is low. BUSY low
time is typically 25 ms. Noise during the calibration (BUSY
low period) can result in the selection of a voltage within a
±0.25 LSB band around the normal selected voltage. See TPC 10.
It is essential to minimize noise on REFIN for optimal perfor-
mance. The AD780’s specified decoupling makes it the ideal
reference to drive the AD5516.
Upon power-on, all DACs power up to a reset value (see the
RESET section).
DIGITAL-TO-ANALOG SECTION
The architecture of each DAC channel consists of a resistor
string DAC followed by an output buffer amplifier with offset
and gain. The voltage at the REF_IN pin provides the reference
voltage for all 16 DACs. The input coding to the DACs is offset
binary; this results in ideal output voltages as follows:
AD5516-1:
V
VDV
OUT
REF IN
N
REF IN
=¥¥¥
¥
¥225
32
25
3
__
.–.
AD5516-2:
V
VDV
OUT
REF IN
N
REF IN
=¥¥¥
¥
¥425
32
225
3
__
.–.
AD5516-3:
V
VDV
OUT
REF IN
N
REF IN
=¥¥¥
¥
¥825
32
425
3
__
.–.
Where:
D=decimal equivalent of the binary code that is loaded to
the DAC register, i.e., 0–4095
N=DAC resolution = 12
Table I illustrates ideal analog output versus DAC code.
Table I. DAC Register Contents AD5516-1
MSB LSB Analog Output, V
OUT
1111 1111 1111 V
REF_IN
¥ 2.5/3 – 1 LSB
1000 0000 0000 0 V
0000 0000 0000 –V
REF_IN
¥ 2.5/3
MODES OF OPERATION
The AD5516 has two modes of operation.
Mode 1 (MODE bits = 00): The user programs a 12-bit data-
word to one of 16 channels via the serial interface. This word is
loaded into the addressed DAC register and is then converted
into an analog output voltage. During conversion, the BUSY
output is low and all SCLK pulses are ignored. At the end of a
conversion BUSY goes high, indicating that the update of the
addressed DAC is complete. It is recommended that SCLK is not
pulsed while BUSY is low. Mode 1 conversion takes 25 ms typ.
Mode 2 (MODE bits = 01 or 10): Mode 2 operation allows the
user to increment or decrement the DAC output in 0.25 LSB steps,
resulting in a 14-bit monotonic DAC. The amount by which the
DAC output is incremented or decremented is determined by
Mode 2 bits DB11–DB0, e.g., for a 0.25 LSB increment/decrement
DB11...DB0 = 0000 0000 0001, while for a 2.5 LSB increment/
decrement, DB11...DB0 = 0000 0000 1010. The MODE bits
determine whether the DAC data is incremented (01) or dec-
remented (10). The maximum amount that the user is allowed
to increment or decrement the DAC output is 4095 steps of
0.25 LSB, i.e., DB11...DB0 = 1111 1111 1111. Mode 2 update
takes approximately 1 ms. The Mode 2 feature allows increased
resolution, but overall increment/decrement accuracy varies with
increment/decrement step as shown in TPC 14 and TPC 15.
Mode 2 is useful in applications where greater resolution is
required, for example, in servo applications requiring fine-tune
to 14-bit resolution.
REV. B
AD5516
–11–
SYNC must be taken high and low again for further serial data
transfer. SYNC may be taken high after the falling edge of the
18th SCLK pulse, observing the minimum SCLK falling edge
to SYNC rising edge time, t
6
. If SYNC is taken high before the
18th falling edge of SCLK, the data transfer will be aborted and
the addressed DAC will not be updated. See the timing diagram
in Figure 1.
Daisy-Chain Mode (DCEN = 1)
I
n Daisy-Chain Mode, the internal gating on SCLK is disabled.
The SCLK is continuously applied to the input shift register
when SYNC is low. If more than 18 clock pulses are applied,
the data ripples out of the shift register and appears on the D
OUT
line. This data is clocked out on the rising edge of SCLK and is
valid on the falling edge. By connecting this line to the D
IN
input on the next device in the chain, a multidevice interface is
constructed. Eighteen clock pulses are required for each device
in the system. Therefore, the total number of clock cycles must
equal 18N, where N is the total number of devices in the chain.
See the timing diagram in Figure 2.
When the serial transfer to all devices is complete, SYNC should
be taken high. This prevents any further data being clocked into the
input shift register. A burst clock containing the exact number of
clock cycles may be used and SYNC taken high some time later.
After the rising edge of SYNC, data is automatically transferred
from each device’s input shift register to the addressed DAC.
RESET Function
The RESET function on the AD5516 can be used to reset all
nodes on this device to their power-on reset condition. This is
implemented by applying a low going pulse of 20 ns minimum
to the RESET Pin on the device.
Table III. Typical Power-On Values
Device Output Voltage
AD5516-1 –0.073 V
AD5516-2 –0.183 V
AD5516-3 –0.391 V
BUSY Output
During conversion, the BUSY output is low and all SCLK pulses
are ignored. At the end of a conversion, BUSY goes high indi-
cating that the update of the addressed DAC is complete. It is
recommended that SCLK is not pulsed while BUSY is low.
MICROPROCESSOR INTERFACING
The AD5516 is controlled via a versatile 3-wire serial interface
that is compatible with a number of microprocessors and DSPs.
AD5516 to ADSP-2106x SHARC DSP Interface
The ADSP-2106x SHARC DSPs are easily interfaced to the
AD5516 without the need for extra logic.
The AD5516 expects a t
3
(SYNC falling edge to SCLK falling
edge setup time) of 15 ns min. Consult the ADSP-2106x User
Manual for information on clock and frame sync frequencies for
the SPORT Register and contents of the TDIV and RDIV Registers.
The user must allow 200 ns (min) between two consecutive
Mode 2 writes in Standalone Mode and 400 ns (min) between
two consecutive Mode 2 writes in Daisy-Chain Mode. During a
Mode 2 operation the BUSY signal remains high.
See Figures 4 and 5 for Mode 1 and Mode 2 data formats.
When MODE bits = 11, the device is in No Operation mode.
This may be useful in daisy-chain applications where the user
does not wish to change the settings of the DACs. Simply write
11 to the MODE bits and the following address and data bits
will be ignored.
SERIAL INTERFACE
The AD5516 has a 3-wire interface that is compatible with
SPI/QSPI/MICROWIRE, and DSP interface standards. Data is
written to the device in 18-bit words. This 18-bit word consists
of two mode bits, four address bits, and 12 data bits as shown
in Figure 4.
The serial interface works with both a continuous and burst
clock. The first falling edge of SYNC resets a counter that counts
the number of serial clocks to ensure the correct number of bits
is shifted in and out of the serial shift registers. In order for
another serial transfer to take place, the counter must be reset
by the falling edge of SYNC.
A3–A0
Four address bits (A3 = MSB Address, A0 = LSB). These are
used to address one of 16 DACs.
Table II. Selected DAC
A3 A2 A1 A0 Selected DAC
0000 DAC 0
0001 DAC 1
::::
1111 DAC 15
DB11–DB0
These are used to write a 12-bit word into the addressed DAC
register. Figures 1 and 2 show the timing diagram for a write
cycle to the AD5516.
SYNC FUNCTION
In both Standalone and Daisy-Chain Modes, SYNC is an edge-
triggered input that acts as a frame synchronization signal and
chip enable. Data can only be transferred into the device while
SYNC is low. To start the serial data transfer, SYNC should be
taken low observing the minimum SYNC falling to SCLK falling
edge setup time, t
3
.
Standalone Mode (DCEN = 0)
After SYNC goes low, serial data will be shifted into the device’s
input shift register on the falling edges of SCLK for 18 clock
pulses. After the falling edge of the 18th SCLK pulse, data will
automatically be transferred from the input shift register to the
addressed DAC.
REV. B–12–
AD5516
A data transfer is initiated by writing a word to the TX Register
after the SPORT has been enabled. In write sequences, data is
clocked out on each rising edge of the DSP’s serial clock and
clocked into the AD5516 on the falling edge of its SCLK. The
SPORT transmit control register should be set up as follows:
DTYPE = 00, Right Justify Data
ICLK = 1, Internal Serial Clock
TFSR = 1, Frame Every Word
INTF = 1, Internal Frame Sync
LTFS = 1, Active Low Frame Sync Signal
LAFS = 0, Early Frame Sync
SENDN = 0, Data Transmitted MSB First
SLEN = 10011, 18-Bit Data-Words (SLEN = Serial Word)
Figure 6 shows the connection diagram.
AD5516*
ADSP-2106x*
SYNC
D
IN
SCLK
TFS
DT
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 6. AD5516 to ADSP-2106x Interface
AD5516 to MC68HC11
The serial peripheral interface (SPI) on the MC68HC11 is
configured for Master Mode (MSTR = 1), Clock Polarity Bit
(CPOL) = 0, and the Clock Phase Bit (CPHA) = 1. The SPI is
configured by writing to the SPI Control Register (SPCR)—see
the 68HC11 User Manual. SCK of the 68HC11 drives the SCLK
of the AD5516, the MOSI output drives the serial data line
(D
IN
) of the AD5516. The SYNC signal is derived from a port
line (PC7). When data is being transmitted to the AD5516, the
SYNC line is taken low (PC7). Data appearing on the MOSI
output is valid on the falling edge of SCK. Serial data from the
68HC11 is transmitted in 8-bit bytes with only eight falling
clock edges occurring in the transmit cycle. Data is transmitted
MSB first. In order to transmit 18 data bits, it is important to
left justify the data in the SPDR Register. PC7 must be pulled
low to start a transfer and taken high and low again before any
further read/write cycles can take place. A connection diagram is
shown in Figure 7.
AD5516*
MC68HC11*
SYNC
SCLK
D
IN
PC7
SCK
MOSI
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 7. AD5516 to MC68HC11 Interface
AD5516 to PIC16C6x/7x
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the Clock Polarity Bit (CKP) = 0. This is
done by writing to the Synchronous Serial Port Control Register
(SSPCON). See the PIC16/17 Microcontroller User Manual. In this
example, I/O port RA1 is being used to provide a SYNC signal
and enable the serial port of the AD5516. This microcontroller
transfers only eight bits of data during each serial transfer opera-
tion; therefore, three consecutive write operations are required.
Figure 8 shows the connection diagram.
AD5516*PIC16C6x/7x*
SCLK
DIN
SYNC
SCK/RC3
SDI/RC4
RA1
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 8. AD5516 to PIC16C6x/7x Interface
AD5516 to 8051
A serial interface between the AD5516 and the 80C51/80L51
microcontroller is shown in Figure 9. The AD5516 requires a
clock synchronized to the serial data. The 8051 serial interface
must therefore be operated in Mode 0. TxD of the microcon-
troller drives the SCLK of the AD5516, while RxD drives the
serial data line. P1.1 is a bit programmable pin on the serial port
that is used to drive SYNC. The 80C51/80L51 provides the
LSB first, while the AD5516 expects MSB of the 18-bit word
first. Care should be taken to ensure the transmit routine takes
this into account.
AD5516*
8051*
SCLK
D
IN
SYNC
TxD
RxD
P1.1
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 9. AD5516 to 8051 Interface
When data is to be transmitted to the DAC, P1.1 is taken low.
Data on RxD is valid on the falling edge of TxD, so the clock
must be inverted as the AD5516 clocks data into the input shift
register on the rising edge of the serial clock. The 80C51/80L51
transmits its data in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. As the DAC requires an 18-bit
word, P1.1 must be left low after the first eight bits are transferred
and brought high after the complete 18 bits have been transferred.
DOUT may be tied to RxD for data verification purposes when
the device is in Daisy-Chain Mode.
REV. B
AD5516
–13–
APPLICATION CIRCUITS
The AD5516 is suited for use in many applications, such as level
setting, optical, industrial systems, and automatic test applications.
In level setting and servo applications where a fine-tune adjust is
required, the Mode 2 function increases resolution. The following
figures show the AD5516 used in some potential applications.
AD5516 in a Typical ATE System
The AD5516 is ideally suited for the level setting function in
automatic test equipment. A number of DACs are required to
control pin drivers, comparators, active loads, parametric mea-
surement units, and signal timing. Figure 10 shows the AD5516
in such a system.
DAC
STORED
DATA AND
INHIBIT
PATTERN
PERIOD
GENERATION
AND
DELAY
TIMING
DACs
FORMATTER
COMPARE
REGISTER
SYSTEM BUS
DAC
DAC
DAC
DAC
ACTIVE
LOAD
PARAMETRIC
MEASUREMENT
UNIT
SYSTEM BUS
DAC
DAC
COMPARATOR
DUT
DRIVER
Figure 10. AD5516 in an ATE System
AD5516 in an Optical Network Control Loop
The AD5516 can be used in optical network control applica-
tions that require a large number of DACs to perform a control
and measurement function. In the example shown in Figure 11,
the outputs of the AD5516 are fed into amplifiers and used to
control actuators that determine the position of MEMS mirrors
in an optical switch. The exact position of each mirror is measured
and the readings are multiplexed into an 8-channel, 14-bit ADC
(AD7865). The increment and decrement modes of the DACs are
useful in this application as they allow 14-bit resolution.
The control loop is driven by an ADSP-2106x, a 32-bit
SHARC
®
DSP.
AD5516
0
15
MEMS
MIRROR
ARRAY
0
15
S
E
N
S
O
R
S
ADG609
ⴛ 2
0
7
AD7865
AD8644
ⴛ 2
ADSP-2106x
Figure 11. AD5516 in an Optical Control Loop
AD5516 in a High Current Circuit
Access to the feedback loop of the AD5516 amplifier provides
greater flexibility, e.g., it enables the user to configure the device
as a digitally programmable current source or increase the out-
put drive current. See Figure 12. Note that V
DD
must be chosen
so that the DAC output has enough headroom to drive the
BJT ~ 0.7 V above the maximum output voltage.
AD5516-1 VDD
VDAC VOUT0
RFB0
RVx = – 2.5V TO +2.5V
VDD
VSS
X
Figure 12. AD5516 in a High Current Circuit
Note it is not intended that the R
FB
nodes be used to alter
amplifier gain or for force/sense in remote sense applications.
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure the
rated performance. The printed circuit board on which the AD5516
is mounted should be designed so that the analog and digital
sections are separated and confined to certain areas of the board. If
the AD5516 is in a system where multiple devices require an
AGND-to-DGND connection, the connection should be made at
one point only. The star ground point should be established as
close as possible to the device. For supplies with multiple pins
(AV
CC
1, AV
CC
2), it is recommended to tie those pins together. The
AD5516 should have ample supply bypassing of 10 mF in parallel
with 0.1 mF on each supply located as closely to the package as
possible, ideally right up against the device. The 10 mF capacitors
are the tantalum bead type. The 0.1 mF capacitor should have low
effective series resistance (ESR) and effective series inductance
(ESI), like the common ceramic types that provide a low impedance
path to ground at high frequencies, to handle transient currents
due to internal logic switching.
The power supply lines of the AD5516 should use as large a trace
as possible to provide low impedance paths and reduce the effects
of glitches on the power supply line. Fast switching signals such
as clocks should be shielded with digital ground to avoid radiating
noise to other parts of the board, and should never be run near
the reference inputs. A ground line routed between the D
IN
and
SCLK lines will help reduce crosstalk between them (not required
on a multilayer board as there will be a separate ground plane, but
separating the lines will help). It is essential to minimize noise
on REFIN.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A micro-
strip technique is by far the best, but not always possible with a
double-sided board. In this technique, the component side of
the board is dedicated to ground plane while signal traces are
placed on the solder side.
As is the case for all thin packages, care must be taken to avoid
flexing the package and to avoid a point load on the surface of
the package during the assembly process.
REV. B–14–
AD5516
OUTLINE DIMENSIONS
74-Lead Chip Scale Ball Grid Array [CSPBGA]
(BC-74)
Dimensions shown in millimeters
A
B
C
D
E
F
G
H
J
K
L
11 10 9 8 7 6 5 4 3 2 1
1.00
BSC
1.00 BSC
BOTTOM
VIEW
A1
TOP VIEW
DETAIL A
1.70
MAX
12.00 BSC
SQ
10.00 BSC
SQ
A1 CORNER
INDEX AREA
SEATING
PLANE
DETAIL A
BALL DIAMETER
0.30 MIN
0.70
0.60
0.50
0.20 MAX
COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-192ABD-1
REV. B
AD5516
–15–
Revision History
Location Page
8/03—Data Sheet changed from REV. A to REV. B.
Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Changes to TPC 14 caption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Addition of TPC 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Changes to Mode 2 section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Changes to Figure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Changes to Figure 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
8/02—Data Sheet changed from REV. 0 to REV. A.
Term LFBGA updated to CSPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Addition to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Changes to FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Changes to DIGITAL-TO-ANALOG section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Added AD5516 in a High Current Circuit section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Added Figure 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Updated BC-74 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
C02792–0–8/03(B)
–16–
