K4M281633H - R(B)N/G/L/F
January 2006
1
Mobile SDRAM
• 3.0V & 3.3V power supply.
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation.
• Special Function Support.
-. PASR (Partial Array Self Refresh).
-. Internal TCSR (Temperature Compensated Self Refresh)
-. DS (Driver Strength)
• DQM for masking.
• Auto refresh.
• 64ms refresh period (4K cycle).
• Commercial Temperature Operation (-25°C ~ 70°C).
• Extended Temperature Operation (-25°C ~ 85°C).
• 54Balls FBGA ( -RXXX -Pb, -BXXX -Pb Free).
FEATURES
The K4M281633H is 134,217,728 bits synchronous high data
rate Dynamic RAM organized as 4 x 2,098,152 words by 16 bits,
fabricated with SAMSUNG’s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock and I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst lengths and programmable latencies allow the same
device to be useful for a variety of high band width and high per-
formance memory system applications.
GENERAL DESCRIPTION
ORDERING INFORMATION
- R(B)N/G : Low Power, Extended Temperature(-25°C ~ 85°C)
- R(B)L/F : Low Power, Commercial Temperature(-25°C ~ 70°C)
Notes :
1. In case of 40MHz Frequency, CL1 can be supported.
Part No. Max Freq. Interface Package
K4M281633H-R(B)N/G/L/F75 133MHz(CL3), 111MHz(CL2) LVCMOS 54 FBGA Pb
(Pb Free)
K4M281633H-R(B)N/G/L/F1H 111MHz(CL3), 111MHz(CL2)
K4M281633H-R(B)N/G/L/F1L 111MHz(CL3)
*1
, 83MHz(CL2)
2M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA
Address configuration
Organization Bank Row Column Address
8M x 16 BA0, BA1 A0 - A11 A0 - A8
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELA TION T O SAMSUNG PRODUCTS, AND IS SUBJECT T O CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LI CENSE, EXPRESS OR IMPLI ED, BY EST OPPEL OR OTHER WISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PRO-
VIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products , contact your nearest Samsung of fice.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could
result in loss of life or personal or physical harm, or any military or defense application, or any gove rnmental procurement to which special terms or pro-
visions may apply.
K4M281633H - R(B)N/G/L/F
January 2006
2
Mobile SDRAM
Bank Select
Data Input Register
2M x 16
2M x 16
Sense AMP
Output BufferI/O Control
Column Decoder
Latency & Burst Length
Programming Register
Address Register
Row Buffer
Refresh Counter
Row Decoder Col. Buffer
LRAS
LCBR
LCKE
LRAS LCBR LWE LDQM
CLK CKE CS RAS CAS WE L(U)DQM
LWE
LDQM
DQi
CLK
ADD
LCAS LWCBR
2M x 16
2M x 16
Timing Register
FUNCTIONAL BLOCK DIAGRAM
K4M281633H - R(B)N/G/L/F
January 2006
3
Mobile SDRAM
54Ball(6x9) FBGA
123789
A VSS DQ15 VSSQ VDDQ DQ0 VDD
B DQ14 DQ13 VDDQ VSSQ DQ2 DQ1
C DQ12 DQ11 VSSQ VDDQ DQ4 DQ3
D DQ10 DQ9 VDDQ VSSQ DQ6 DQ5
E DQ8 NC VSS VDD LDQM DQ7
F UDQM CLK CKE CAS RAS WE
G NC A11 A9 BA0 BA1 CS
HA8A7A6A0A1A10
J VSS A5 A4 A3 A2 VDD
Pin Name Pin Function
CLK System Clock
CS Chip Select
CKE Clock Enable
A
0
~ A
11
Address
BA
0
~ BA
1
Bank Select Address
RAS Row Address Strobe
CAS Column Address Strobe
WE Write Enable
L(U)DQM Data Input/Output Mask
DQ
0
~
15
Data Input/Output
V
DD
/V
SS
Power Supply/Ground
V
DDQ
/V
SSQ
Data Output Power/Ground
Package Dimension and Pin Configuration
< Top View*2 >< Bottom View*1 >
521634897
F
E
D
C
B
J
H
G
A
e
D
D
1
E
1
E
< Top View*2 >
z
A
A1
*2: Top View
*1: Bottom View
#A1 Ball Origin Indicator
K4M281633H
SEC
Week
XXXX
Symbol Min Typ Max
A - - 1.00
A
1
0.25 - -
E 7.90 8.00 8.10
E
1
- 6.40 -
D 7.90 8.00 8.10
D
1
- 6.40 -
e - 0.80 -
b 0.45 0.50 0.55
z - - 0.10
[Unit:mm]
b
K4M281633H - R(B)N/G/L/F
January 2006
4
Mobile SDRAM
DC OPERATING CONDITIONS
Recommended operating conditions (V olt age referenced to V
SS
= 0V, T
A
= -25°C ~ 85°C for Extended, -25°C ~ 70°C for Comm erci al)
NOTES :
1. Under all conditions, VDDQ must be less than or equal to VDD.
2. VIH (max) = 5.3V AC.The overshoot voltage duration is ≤ 3ns.
3. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
4. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.
5. Dout is disabled, 0V ≤ VOUT ≤ VDDQ.
Parameter Symbol Min Typ Max Unit Note
Supply voltage V
DD
2.7 3.0 3.6 V 1
V
DDQ
2.7 3.0 3.6 V 1
Input logic high voltage V
IH
2.2 3.0 V
DDQ
+ 0.3 V 2
Input logic low voltage V
IL
-0.3 00.5 V 3
Output logic high voltage V
OH
2.4 - - V I
OH
= -2mA
Output logic low voltage V
OL
- - 0.4 V I
OL
= 2mA
Input leakage current I
LI
-2 - 2 uA 4
CAPACITANCE
(V
DD
= 3.0V & 3.3V, T
A
= 23°C, f = 1MHz, V
REF
=0.9V ± 50 mV)
Pin Symbol Min Max Unit Note
Clock C
CLK
1.5 3.5 pF
RAS, CAS, WE, CS, CKE, DQM C
IN
1.5 3.0 pF
Address C
ADD
1.5 3.0 pF
DQ
0
~ DQ
15
C
OUT
2.0 4.5 pF
ABSOLUTE MAXIMUM RATINGS
NOTES:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Parameter Symbol Value Unit
Voltage on any pin relative to V
ss
V
IN
, V
OUT
-1.0 ~ 4.6 V
Voltage on V
DD
supply relative to V
ss
V
DD
, V
DDQ
-1.0 ~ 4.6 V
Storage temperature T
STG
-55 ~ +150 °C
Power dissipation P
D
1.0 W
Short circuit current I
OS
50 mA
K4M281633H - R(B)N/G/L/F
January 2006
5
Mobile SDRAM
DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= -25 to 85°C for Extended, -25 to 70°C for Commercial)
NOTES:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Internal TCSR can be supported.
In comercial Temp : 45°C/Max 70°C. In extended Temp : 45°C/Max 85°C.
4. It has +/-5 °C tolerance.
5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).
Parameter Symbol Test Condition Version Unit Note
-75 -1H -1L
Operating Current
(One Bank Active) I
CC1
Burst length = 1
t
RC
≥ t
RC
(min)
I
O
= 0 mA 65 65 60 mA 1
Precharge Standby Current in
power-down mode I
CC2
PCKE ≤ V
IL
(max), t
CC
= 10ns 0.5 mA
I
CC2
PS CKE & CLK ≤ V
IL
(max), t
CC
= ∞0.5
Precharge Standby Current
in non power-down mode
I
CC2
NCKE ≥ V
IH
(min), CS ≥ V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns 10
mA
I
CC2
NS CKE ≥ V
IH
(min), CLK ≤ V
IL
(max), t
CC
= ∞
Input signals are stable 5
Active Standby Current
in power-down mode I
CC3
PCKE ≤ V
IL
(max), t
CC
= 10ns 5mA
I
CC3
PS CKE & CLK ≤ V
IL
(max), t
CC
= ∞2
Active Standby Current
in non power-down mode
(One Bank Active)
I
CC3
NCKE ≥ V
IH
(min), CS ≥ V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns 20 mA
I
CC3
NS CKE ≥ V
IH
(min), CLK ≤ V
IL
(max), t
CC
= ∞
Input signals are stable 15 mA
Operating Current
(Burst Mode) I
CC
4
I
O
= 0 mA
Page burst
4Banks Activated
t
CCD
= 2CLKs
70 60 60 mA 1
Refresh Current I
CC
5 t
RC
≥ t
RC
(min) 130 120 120 mA 2
Self Refresh Current I
CC
6CKE ≤ 0.2V
-N/L 330 mA
-G/F
Internal TCSR 45
*4
85/70
°C3
Full Array 200 330
uA
1/2 of Full Array 150 230
1/4 of Full Array 130 190
K4M281633H - R(B)N/G/L/F
January 2006
6
Mobile SDRAM
1200Ω
870Ω
Output
30pF
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Vtt=0.5 x VDDQ
50Ω
Output
30pF
Z0=50Ω
Figure 2. AC Output Load Circuit
Figure 1. DC Output Load Circuit
AC OPERATING TEST CONDITIONS
(V
DD
= 2.7V ∼ 3.6V, T
A
= -25 ~ 85°C for Extended, -25 ~ 70°C for Commercial)
Parameter Value Unit
AC input levels (Vih/Vil) 2.4 / 0.4 V
Input timing measurement reference level 0.5 x V
DDQ
V
Input rise and fall time tr/tf = 1/1 ns
Output timing measurement reference level 0.5 x V
DDQ
V
Output load condition See Figure 2
VDDQ
K4M281633H - R(B)N/G/L/F
January 2006
7
Mobile SDRAM
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
NOTES:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. Minimum tRDL=2CLK and tDAL(= tRDL + tRP) is required to complete both of last data write command(tRDL) and precharge command(tRP).
4. All parts allow every cycle column address change.
5. In case of row precharge interrupt, auto precharge and read burst stop.
6. Maximum burst refresh cycle : 8
Parameter Symbol Version Unit Note
-75 -1H -1L
Row active to row active delay t
RRD
(min) 15 18 18 ns 1
RAS to CAS delay t
RCD
(min) 18 18 24 ns 1
Row precharge time t
RP
(min) 18 18 24 ns 1
Row active time t
RAS
(min) 45 50 60 ns 1
t
RAS
(max) 100 us
Row cycle time t
RC
(min) 63 68 84 ns 1
Last data in to row precharge t
RDL
(min) 2CLK 2
Last data in to Active delay t
DAL
(min) tRDL + tRP - 3
Last data in to new col. address delay t
CDL
(min) 1CLK 2
Last data in to burst stop t
BDL
(min) 1CLK 2
Col. address to col. address delay t
CCD
(min) 1CLK 4
Number of valid output data CAS latency=3 2
ea 5
Number of valid output data CAS latency=2 1
Number of valid output data CAS latency=1 0
K4M281633H - R(B)N/G/L/F
January 2006
8
Mobile SDRAM
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
NOTES :
1. Parameters depend on pr ogrammed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Parameter Symbol -75 -1H -1L Unit Note
Min Max Min Max Min Max
CLK cycle time CAS latency=3 t
CC
7.5
1000
9
1000
9
1000 ns 1
CLK cycle time CAS latency=2 t
CC
9 9 12
CLK cycle time CAS latency=1 t
CC
- - 25
CLK to valid output delay CAS latency=3 t
SAC
5.4 7 7
ns 1,2
CLK to valid output delay CAS latency=2 t
SAC
778
CLK to valid output delay CAS latency=1 t
SAC
- - 20
Output data hold time CAS latency=3 t
OH
2.5 2.5 2.5
ns 2
Output data hold time CAS latency=2 t
OH
2.5 2.5 2.5
Output data hold time CAS latency=1 t
OH
- - 2.5
CLK high pulse width t
CH
2.5 3.0 3.0 ns 3
CLK low pulse width t
CL
2.5 3.0 3.0 ns 3
Input setup time t
SS
2.0 2.5 2.5 ns 3
Input hold time t
SH
1.0 1.0 1.0 ns 3
CLK to output in Low-Z t
SLZ
111ns 2
CLK to output in Hi-Z
CAS latency=3
t
SHZ
5.4 7 7
ns
CAS latency=2 778
CAS latency=1 - - 20
K4M281633H - R(B)N/G/L/F
January 2006
9
Mobile SDRAM
SIMPLIFIED TRUTH TABLE
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
NOTES :
1. OP Code : Operand Code
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are the same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
Parti al self refresh can be issued only after setting partial self refresh mode of EMRS.
4. BA0 ~ BA1 : Bank select addresses.
5. During burst read or write with auto pr echarge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency
is 0), but in read operation, it makes the data- out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2).
COMMAND CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP A11,
A9 ~ A0 Note
Register Mode Register Set H X L L L L X OP CODE 1, 2
Refresh
Auto Refresh HHL L L H X X 3
Self
Refresh
Entry L 3
Exit L H L H H H X X 3
H X X X 3
Bank Active & Row Addr. H X L L H H X V Row Address
Read &
Column Address Auto Precharge Disable H X L H L H X V LColumn
Address
(A0~A8)
4
Auto Precharge Enable H4, 5
Write &
Column Address Auto Precharge Disable H X L H L L X V LColumn
Address
(A0~A8)
4
Auto Precharge Enable H4, 5
Burst Stop H X L H H L X X 6
Precharge Bank Selection H X L L H L X V L X
All Banks X H
Clock Suspend or
Active Power Down Entry H L H X X X XXL V V V
Exit L H X X X X X
Precharge Power Down
Mode
Entry H L H X X X X
X
L H H H
Exit L H H X X X X
L V V V
DQM H X V X 7
No Operation Command H X H X X X X X
L H H H
K4M281633H - R(B)N/G/L/F
January 2006
10
Mobile SDRAM
Register Programmed with Extended MRS
Address BA1 BA0 A11 ~ A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Function Mode Select RFU
*1
DS RFU
*1
PASR
Normal MRS Mode
Test Mode CAS Latency Burst Type Burst Length
A8 A7 Type A6 A5 A4 Latency A3 Type A2 A1 A0 BT=0 BT=1
0 0 Mode Register Set 0 0 0 Reserved 0Sequential 0 0 0 1 1
0 1 Reserved 0 0 1 11Interleave 0 0 1 2 2
1 0 Reserved 0 1 0 2Mode Select 0 1 0 4 4
1 1 Reserved 0 1 1 3BA1 BA0 Mode 0 1 1 8 8
Write Burst Length 1 0 0 Reserved
0 0 Setting
for Nor-
mal MRS
1 0 0 Reserved Reserved
A9 Length 1 0 1 Reserved 1 0 1 Reserved Reserved
0Burst 1 1 0 Reserved 1 1 0 Reserved Reserved
1Single Bit 1 1 1 Reserved 1 1 1 Full Page Reserved
Register Programmed with Normal MRS
Address BA0 ~ BA1 A11 ~ A10/AP A9
*2
A8 A7 A6 A5 A4 A3 A2 A1 A0
Function "0" Setting for
Normal MRS RFU W.B.L Test Mode CAS Latency BT Burst Length
A. MODE REGISTER FIELD TABLE TO PROGRAM MODES
NOTES:
1.RFU(Reserved for future use) should stay "0" during MRS cycle.
2.If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.
Mode Select Driver Strength PASR
BA1 BA0 Mode A6 A5 Driver Strength A2 A1 A0 Size of Refreshed Array
0 0 Normal MRS 0 0 Full 000 Full Array
0 1 Reserved 0 1 1/2 001 1/2 of Full Array
1 0 EMRS for Mobile SDRAM 1 0 Reserved 010 1/4 of Full Array
1 1 Reserved 1 1 Reserved 011 Reserved
Reserved Address 100 Reserved
A11~A10/AP A9 A8 A7 A4 A3 101 Reserved
0 0 0 0 0 0 110 Reserved
111 Reserved
EMRS for PASR(Partial Array Self Ref.) & DS(Driver Strength)
K4M281633H - R(B)N/G/L/F
January 2006
11
Mobile SDRAM
1. In order to save power consumption, Mobile SDRAM has PASR option.
2. Mobile SDRAM supports 3 kinds of PASR in self refresh mode : full array, 1/2 of full array, 1/4 of full array.
BA1=0
Partial Self Refresh Area
1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined.
- Apply VDD before or at the same time as VDDQ.
2. Maintain stable power, stable clock and NOP input cond ition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
6. Issue a extended mode register set command to define DS or PASR operating type of the device after normal MRS.
The device is now ready for the operation selected by EMRS.
For operating with DS or PASR , set DS or PASR mode in EMRS setting stage.
In order to adjust another mode in the state of DS or PASR mode, additional EMRS set is required but power up sequence is not
needed again at this time. In that case, all banks have to be in idle state prior to adjusting EMRS set.
BA0=0 BA1=0
BA0=0 BA1=0
BA0=1
BA1=1
BA0=1
BA1=1
BA0=0
BA1=1
BA0=1
BA1=1
BA0=0
BA1=0
BA0=1
BA1=0
BA0=0 BA1=0
BA0=1
BA1=1
BA0=1
BA1=1
BA0=0
Partial Array Self Refresh
B. POWER UP SEQUENCE
Internal Temperature Compensated Self Refresh (TCSR)
- Full Array - 1/2 Array - 1/4 Array
Note :
1. In order to save power consumption, Mobile-DRA M includes the internal temperature sensor and control units to control the self
refresh cycle automatically according to the two temperatu re range : 45 °C and 85 °C(for Extended), 70 °C(for Commercial).
2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored.
3. It has +/-5 °C tolerance.
Temperature Range
Self Refresh Current (Icc6)
Unit
-N/L -G/F
Full Array 1/2 of Full Array 1/4 of Full Array
85/70 °C *3 330 330 230 190 uA
45 °C200 150 130
K4M281633H - R(B)N/G/L/F
January 2006
12
Mobile SDRAM
C. BURST SEQUENCE
1. BURST LENGTH = 4
Initial Address Sequential Interleave
A1 A0
0 0 0 1 2 3 0 1 2 3
0 1 1 2 3 0 1 0 3 2
1 0 2 3 0 1 2 3 0 1
1 1 3 0 1 2 3 2 1 0
2. BURST LENGTH = 8
Initial Address Sequential Interleave
A2 A1 A0
0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6
0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5
0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4
1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3
1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2
1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1
1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0
