HN29WT800 Series,HN29WB800 Series 1048576-Word x 8-bit / 524288-word x 16-bit CMOS Flash Memory ADE-203-537(Z) Preliminary Rev. 0.0 Jun. 14, 1996 Description The Hitachi HN29WT800 Series, HN29WB800 Series are 1-Mword x 8-bit/512-kword x 16-bit CMOS Flash Memory with DINOR (D Ivided bitline NOR) type memory cells, that realize programming and erase capabilities with a single 3.3 V power supply. The built-in Sequence Controller allows Automatic Program/Erase without complex external control. HN29WT800 Series, HN29WB800 Series enable the low power and high performance systems such as mobile, personal computing and communication products. Features * On-board single power supply (VCC): VCC = 3.3 V 0.3 V * Access time: 80/100/120 ns (max) * Low power dissipation: ICC = 30 mA (max) (Read) ICC = 200 A (max) (Standby) ICC = 40 mA (max) (Program) ICC = 40 mA (max) (Erase) ICC = 1 A (typ) (Deep powerdown) * Automatic page programming: Programming time: 25 ms (typ) Program unit: 128 word This product is compatible with M5M29FB/T800xx by Ltd. Mitsubishi. Preliminary: This document contains information on a new product. Specifications and information contained herein are subject to change without notice. HN29WT800 Series, HN29WB800 Series * Automatic erase: Erase time: 50 ms (typ) Erase unit: Boot block; 8-kword/16-kbyte x 1 Parameter block; 4-kword/8-kbyte x 2 Main block; 16-kword/32-kbyte x 1 32-kword/64-kbyte x 15 * Block boot: HN29WT800 Series: Top boot HN29WB800 Series: Bottom boot * Other functions: Software command control Selective block lock Program suspend/Resume Erase suspend/Resume Status register read Sleep * Compatible with M5M29FB/T800xx by Ltd. Mitsubishi Ordering Information Type No. Access time Package HN29WT800FP-8 HN29WT800FP-10 HN29WT800FP-12 80 ns 100 ns 120 ns 44-pin plastic SOP (FP-44D) HN29WB800FP-8 HN29WB800FP-10 HN29WB800FP-12 80 ns 100 ns 120 ns HN29WT800T-8 HN29WT800T-10 HN29WT800T-12 80 ns 100 ns 120 ns HN29WB800T-8 HN29WB800T-10 HN29WB800T-12 80 ns 100 ns 120 ns HN29WT800R-8 HN29WT800R-10 HN29WT800R-12 80 ns 100 ns 120 ns HN29WB800R-8 HN29WB800R-10 HN29WB800R-12 80 ns 100 ns 120 ns 2 2 12 x 20.0 mm 48-pin plastic TSOP I (TFP-48D) 2 12 x 20.0 mm 48-pin plastic TSOP I (Reverse) (TFP-48DR) HN29WT800 Series, HN29WB800 Series Pin Arrangement 3 HN29WT800 Series, HN29WB800 Series HN29WT800FP Series HN29WB800FP Series NC A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE V SS OE I/O0 I/O8 I/O1 I/O9 I/O2 I/O10 I/O3 I/O11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 (TOP VIEW) Pin Arrangement (cont.) 4 RP WE A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE V SS I/O15/A-1 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 V CC HN29WT800 Series, HN29WB800 Series HN29WT800T Series HN29WB800T Series A15 1 48 A14 2 47 BYTE A13 3 46 V SS A12 4 45 I/O15/A-1 A11 5 44 I/O7 A10 6 43 I/O14 A9 7 42 I/O6 A8 8 41 I/O13 NC 9 40 I/O5 NC 10 39 I/O12 WE 11 38 I/O4 RP NC 12 37 13 36 V CC I/O11 A16 WP 14 35 I/O3 RDY/Busy A18 15 34 I/O10 16 33 I/O2 A17 17 32 I/O9 A7 18 31 I/O1 A6 19 30 I/O8 A5 A4 20 29 21 28 I/O0 OE A3 22 27 A2 23 26 V SS CE A1 24 25 A0 (TOP VIEW) HN29WT800R Series HN29WB800R Series A16 1 48 A15 BYTE 2 47 A14 V SS 3 46 A13 I/O15/A-1 4 45 A12 I/O7 5 44 A11 I/O14 6 43 A10 A9 I/O6 7 42 I/O13 8 41 A8 I/O5 9 40 NC I/O12 10 39 NC I/O4 11 38 WE V CC 12 37 RP I/O11 13 36 NC I/O3 14 35 WP I/O10 15 34 RDY/Busy I/O2 16 33 A18 I/O9 17 32 A17 18 31 A7 I/O8 19 30 A6 I/O0 20 29 A5 OE 21 28 A4 V SS 22 27 A3 CE 23 26 A2 A0 24 25 A1 I/O1 (TOP VIEW) 5 HN29WT800 Series, HN29WB800 Series Pin Description Pin name Function A-1 to A-18 Address I/O0 to I/O15 Input/output CE OE WE RP RDY/Busy WP BYTE Chip enable Output enable Write enable Reset/Powerdown Ready/Busy Write protect Byte enable VCC Power supply VSS Ground NC No connection 6 HN29WT800 Series, HN29WB800 Series Block Diagram 128-word page buffer Boot block 8-kword Parameter block1 4-kword A8 to A18 X-address buffer X-decorder Parameter block2 4-kword Main block 16-kword Main block 32-kword Main block 32-kword A0 to A7 Y-address buffer Y-gate /Sens AMP Y-decorder Status/ID register Multiplexer CE OE WE CUI WSM WP Input/output buffers RP BYTE RDY/BYTE V CC I/O0 I/O15/A-1 V SS CUI: Command User Interface WSM: Write State Machine 7 HN29WT800 Series, HN29WB800 Series Memory Map HN29WT800 Series Memory Map x 8 (Byte mode) x 16 (word mode) FC000H to FFFFFH 7E000H to 7FFFFH FA000H to F8FFFH 7D000H to 7DFFFH F8000H to F9FFFH x 8 (Byte mode) x 16 (word mode) 8-kword boot block F0000H to FFFFFH 78000H to 7FFFFH 32-kword main block 4-kword parameter block E0000H to EFFFFH 70000H to 77FFFH 32-kword main block 7C000H to 7CFFFH 4-kword parameter block D0000H to DFFFFH 68000H to 6FFFFH 32-kword main block F0000H to F7FFFH 78000H to 7BFFFH 16-kword main block C0000H to CFFFFH 60000H to 67FFFH 32-kword main block E0000H to EFFFFH 70000H to 77FFFH 32-kword main block B0000H to BFFFFH 58000H to 5FFFFH 32-kword main block D0000H to DFFFFH 68000H to 6FFFFH 32-kword main block A0000H to AFFFFH 50000H to 57FFFH 32-kword main block C0000H to CFFFFH 60000H to 67FFFH 32-kword main block 90000H to 9FFFFH 48000H to 4FFFFH 32-kword main block B0000H to BFFFFH 58000H to 5FFFFH 32-kword main block 80000H to 8FFFFH 40000H to 47FFFH 32-kword main block A0000H to AFFFFH 50000H to 57FFFH 32-kword main block 70000H to 7FFFFH 38000H to 3FFFFH 32-kword main block 90000H to 9FFFFH 48000H to 4FFFFH 32-kword main block 60000H to 6FFFFH 30000H to 37FFFH 32-kword main block 80000H to 8FFFFH 40000H to 47FFFH 32-kword main block 50000H to 5FFFFH 28000H to 2FFFFH 32-kword main block 70000H to 7FFFFH 38000H to 3FFFFH 32-kword main block 40000H to 4FFFFH 20000H to 27FFFH 32-kword main block 60000H to 6FFFFH 30000H to 37FFFH 32-kword main block 30000H to 3FFFFH 18000H to 1FFFFH 32-kword main block 50000H to 5FFFFH 28000H to 2FFFFH 32-kword main block 20000H to 2FFFFH 10000H to 17FFFH 32-kword main block 40000H to 4FFFFH 20000H to 27FFFH 32-kword main block 10000H to 1FFFFH 08000H to 0FFFFH 32-kword main block 30000H to 3FFFFH 18000H to 1FFFFH 32-kword main block 08000H to 0FFFFH 04000H to 07FFFH 16-kword main block 20000H to 2FFFFH 10000H to 17FFFH 32-kword main block 06000H to 07FFFH 03000H to 03FFFH 10000H to 1FFFFH 08000H to 0FFFFH 32-kword main block 04000H to 05FFFH 02000H to 02FFFH 00000H to 07FFFH 32-kword main block 00000H to 0FFFFH A- 1 to 18 (Byte mode) 8 HN29WB800 Series Memory Map A 0 to A18 (Word mode) 00000H to 03FFFH A- 1 to 18 (Byte mode) 00000H to 07FFFH A 0 to A18 (Word mode) 4-kword parameter block 4-kword parameter block 8-kword boot block HN29WT800 Series, HN29WB800 Series Mode Selection Word Mode (BYTE = VIH) Mode Pin Read Array CE VIL Status register Lock bit status 1 Identifier (Maker)* ,* 1 2 Identifier (Device)* ,* Output disable Standby Command write* 3 OE VIL Deep powerdown Program VIH RP VIH RDY/Busy I/O0 to I/O15 VOH (High-Z) Dout 5 VIL VIL VIH VIH x* Status Register Data VIL VIL VIH VIH x Lock bit data (I/O6) VIL VIL VIH VIH VOH (High-Z) 07H VIL VIL VIH VIH VOH (High-Z) 85H/86H*6 VIL VIL VIH VIH x High-Z x High-Z VIH 4 WE VIL x VIH x VIL VIH x Command/Data in Erase VIL VIH VIL VIH VIH x Command Others VIL VIH VIL VIH x Command x x x VIL VOH (High-Z) High-Z Notes: 1. The command programming mode is used to output the identifier code. Refer to the table of Software Command Definition. 2. A0 = VIL 3. A0 = VIH 4. Refer to the table of Software Command Definition. Programming and erase operation begins after mode setting by command input. 5. x can be VIL or VIH for control pins, and VOL or VOH (High-Z) for RDY/Busy pin. The RDY/Busy is an open drain output pin and indicates status of the internal WSM. When low, it indicates the WSM is Busy performing an operation. A pull-up resistor of 10 k to 100 k is required to allow the RDY/Busy signal to transition high indicating a Ready WSM condition. 6. 85H: HN29WT800 Series, 86H: HN29WB800 Series. 9 HN29WT800 Series, HN29WB800 Series BYTE Mode (BYTE = V ) IL Mode Pin CE OE WE RP RDY/Busy Read Array VIL VIL VIH VIH VOH (High-Z) Dout Status register VIL VIL VIH VIH x* Status Register Data Lock bit status VIL VIL VIH VIH x Lock bit data (I/O6) VIL VIL VIH VIH VOH (High-Z) 07H VIL VIL VIH VIH VOH (High-Z) 85H/86H* VIL VIH VIH VIHx High-Z VIH x x VIH x High-Z Program VIL VIH VIL VIH x Command/Data in Erase VIL VIH VIL VIH x Command Others VIL VIH VIL VIH x Command x x x VIL VOH (High-Z) High-Z 1 Identifier (Maker)* ,* 1 2 Identifier (Device)* ,* Output disable Standby Command write* 4 Deep powerdown 3 5 I/O0 to I/O7 6 Notes: 1. The command programming mode is used to output the identifier code. Refer to the table of Software Command Definition. 2. A0 = VIL 3. A0 = VIH 4. Refer to the table of Software Command Definition. Programming and erase operation begins after mode setting by command input. 5. x can be VIL or VOH for control pins, and VOL or VOH (High-Z) for RDY/Busy pin. The RDY/Busy is an open drain output pin and indicates status of the internal WSM. When low, it indicates the WSM is Busy performing an operation. A pull-up resistor of 10 k to 100 k is required to allow the RDY/Busy signal to transition high indicating a Ready WSM condition. 6. 85H: HN29WT800 Series, 86H: HN29WB800 Series. 10 HN29WT800 Series, HN29WB800 Series Software Command Definition First bus cycle Second bus cycle Third bus cycle Command Operation mode Operation Address Data Operation Address Data Address Data mode mode (I/O7 (I/O7 (I/O7 1 to I/O0) to I/O0) to I/O0)* Read array Write (memory) x FFH Read identifier codes Write x 90H Read IA* ID* Read status Write register x 70H Read x SRD*3 Clear status Write register x 50H Page program*5 Write x 41H Write WA0* Block erase Write x 20H Write BA*6 D0H Suspend Write x B0H Resume Write x D0H Read lock bit status Write x 71H Read BA I/O6* Lock bit Write program/co nfirm x 77H Write BA D0H Erase all unlocked blocks Write x A7H Write x D0H Sleep*8 Write x F0H 2 2 4 WD0* 4 Write WA1 WD1 7 Notes: 1. In the word mode, upper byte data (I/O8 to I/O15) is ignored. 2. IA = Identifier address, A0 = VIL (Manufacture code), A0 = VIH (Device code), ID = ID code, BYTE = VIL: A-1, A1 to A18 = VIL, BYTE = VIH: A1 to A18 = VIL. 3. SRD = Status register data 4. WA = Write address, WD = Write data 5. BYTE = VIL: Write address and write data must be provided sequentially from 00H to FFH for A-1 to A6. Page size is 256 byte (256-byte x 8-bit). BYTE = VIH: Write address and write data must be provided sequentially from 00H to 7FH for A0 to A6. Page size is 128 word (128-word x 16-bit). 6. BA = Block address (A16 to A20), (Addresses except block address must be VIH) 7. I/O6 provides block lock status, I/O6 = 1: Block unlocked, I/O6 = 0: Block locked. 8. Sleep command (F0H) put the device into the sleep mode after completing the current operation. The active current is reduced to deep powerdown levels. The Read Array command (FFH) must be written to get the device out of sleep mode. 11 HN29WT800 Series, HN29WB800 Series Block Locking (TSOP package) RP WP Lock bit (internally) Write protection provided VIL x x All blocks locked (Deep powerdown mode) VHH x x All blocks unlocked VIH VIL 0 Blocks locked (Depend on lock bit data) VIH VIL 1 Blocks unlocked (Depend on lock bit data) VIH VIH x All blocks unlocked Note: I/O6 provided lock status of each block after writing the Read lock status command (71H). WP pin must not be switched during performing Read/Write operations or WSM busy (WSMS = 0). Block Locking (SOP package) RP Lock bit (internally) Write protection provided VIL x All blocks locked (Deep powerdown mode) VHH x All blocks unlocked VIH 0 Blocks locked (Depend on lock bit data) VIH 1 Blocks unlocked (Depend on lock bit data) Note: I/O6 provided lock status of each block after writing the Read lock status command (71H). Status Register Data (SRD) Symbol Function Definition SR. 7 (I/O7) Write state machine status 1 = Ready 0 = Busy SR. 6 (I/O6) Suspend status 1 = Suspend 0 = Operation in progress/completed SR. 5 (I/O5) Erase status 1 = Error 0 = Successful SR. 4 (I/O4) Program status 1 = Error 0 = Successful SR. 3 (I/O3) Block status after program 1 = Error 0 = Successful SR. 2 (I/O2) Reserved The function and the definition for these bits are to be SR. 1 (I/O1) Reserved determined. These bits should be masked out when the status register is polled. SR. 0 (I/O0) Device sleep status 1 = Device in sleep 0 = Device not in sleep Note: The RDY/Busy is an open dran output pin and indicates status of the internal WSM. When low, it indicates that the WSM is Busy performing an operation. A pull-up resistor of 10k to 100k is required to allow the RDY/Busy signal to transition high indicating a Ready WSM condition. I/O3 indicates the block status after the page programming. When I/O3 is High, the page has the over-programmed cell. If over-program occures, the device is block failed. However, if I/O3 is High, please try the block erase to the block. The block may revive. 12 HN29WT800 Series, HN29WB800 Series Device Identifier Mode The device identifier mode allows the reading out of binary codes that identify manufacturer and type of device, from outputs of Flash Memory. By this mode, the device will be automatically matched its own corresponding erase and programming algorithm. HN29WT800 Series, HN29WB800 Series Identifier Code Pins A0 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Hex. data Manufacturer code 0 0 0 0 0 0 1 1 1 07H Device code (T series) 1 1 0 0 0 0 1 0 1 85H Device code (B series) 1 1 0 0 0 0 1 1 0 86H Notes: 1. Device identifier code can be read out by using the read identified codes command. 2. In the word mode, the same data as I/O7 to I/O0 is read out from I/O15 to I/O8. 3. A9 = VHH mode. A9 = 11.5 V to 13.0 V. Set A9 to VHH min 200 ns before falling edge of CE in ready status. Min 200 ns after return to VHH, device can't be accessed. A1 to A8, A10 to A18, CE, OE, = VIL, WE = VIH, I/O15/A-1 = VIL (BYTE = L). Operations of the HN29WT800 Series, HN29WB800 Series The HN29WT800 Series, HN29WB800 Series include on-chip program/erase control circuitry. The Write State Machine (WSM) controls block erase and page program operations. Operational modes are selected by the commands written to the Command User Interface (CUI). The Status Register indicates the status of the WSM and when the WSM successfully completes the desired program or block erase operation. A Deep Powerdown mode is enabled when the RP pin is at VSS minimizing power consumption. Read: The HN29WT800 Series, HN29WB800 Series have three read modes, which accesses to the memory array, the Device Identifier and the Status Register. The appropriate read command are required to be written to the CUI. Upon initial device powerup or after exit from deep powerdown, the HN29WT800 Series, HN29WB800 Series automatically reset to read array mode. In the read array mode, low level input to CE and OE, high level input to WE and RP, and address signals to the address inputs (A0 to A18) output the data of the addressed location to the data input/output (I/O0 to I/O15). Write: Writes to the CUI enable reading of memory array data, device identifiers and reading and clearing of the Status Register, they also enable block erase and program. The CUI is written by bringing WE to low level, while CE is at low level and OE is at high level. Addresses and data are latched on the earlier rising edge of WE and CE. Standard micro-processor write timings are used. Output Disable:When OE is at VIH output from the device is disabled. Data input/output are in a high impedance (High-Z) state. 13 HN29WT800 Series, HN29WB800 Series Standby:When CE is at VIH, the device is in the standby mode and its power consumption is reduced. Data input/output are in a high impedance (High-Z) state. If the memory is deselected during block erase or program, the internal control circuits remain active and the device consume normal active power until the operation completes. Deep Powerdown:When RP is at VIL, the device is in the deep powerdown mode and its power consumption is substantially low. During read modes, the memory is deselected and the data input/output are in a high impedance (High-Z) state. After return from powerdown, the CUI is reset to Read Array and the Status Register is cleared to value 80H. During block erase or program modes, RP low will abort either operation. Memory array data of the block being altered become invalid. Functional Description The device operations are selected by writing specific software command into the CUI. Read Array Command (FFH): The device is in read array mode on initial device power up and after exit from deep power down, or by writing FFH to the CUI. The device remains in Read Array mode until the other commands are written. Read Device Identifier Command (90H):Though PROM programmers can normally read device identifier codes by raising A9 to high voltage, multiplexing high voltage onto address lines is not desired for microprocessor system. It is an other means to read device identifier codes that Read Device Identifier Code Command (90H) is written to the command latch. Following the write of the Read Device Identifier command of 90H, the manufacturer code and the device code can be read from addresses 00000H and 00001H, respectively. Read Status Register Command (70H): The Status Register is read after writing the read status register command of 70H to the CUI. The contents of Status Register are latched on the later falling edge of OE or CE. So CE or OE must be toggled every status read. Clear Status Register Command (50H): The Erase Status and Program Status bits are set to High by the Write State Machine and can be reset by the Clear Status Register command of 50H. These bits indicates various failure conditions. Block Erase/Confirm Command (20H/D0H): Automated block erase is initiated by writing the Block Erase of 20H followed by the Confirm command of D0H. An address within the block to be erased is required. The WSM executes iterative erase pulse application and erase verify operation. Suspend/Resume Command (B0H/D0H): Writing the suspend command of B0H during block erase operation interrupts the block erase operation and allows read out from another block of memory. Writing the suspend command of B0H during program operation interrupts the program operation and allows read out from another block of memory. The device continues to output status register data when read, after the suspend command is written to it. Polling the WSM status and suspend status bits will determine when the erase operation or program operation has been suspended. At this point, writing of the read array command to the CUI enables reading data from blocks other than that which is suspended. When the resume command of D0H is written to the CUI, the WSM will continue with the erase or program processes. 14 HN29WT800 Series, HN29WB800 Series Page Program Command (41H): Page program allows fast programming of 128-word of data. Writing of 41H initiates the page program operation. From 2nd cycle to 129th cycle write data must be serially inputted. Address A6 to A0 have to be incremented from 00H to 7FH. After completion of data loading, the WSM controls the program pulse application and verify operation. Basically re-program must not be done on a page which has already programmed. Data Protection: The HN29WT800 Series, HN29WT800 Series provide selective block locking of memory blocks. Each block has an associated nonvolatile lock-bit which determines the lock status of the block. In addition, the HN29WT800 Series, HN29WT800 Series have a master write protect pin (WP) which prevents any modifications to memory blocks whose lock-bits are set to Low, when WP is low. When WP is high or RP is VHH, all blocks can be programmed or erased regardless of the state of lock-bits, and the lock-bits are cleared to High by erase. Power Supply Voltage: When the power supply voltage (VCC) is less than 2.2 V, the device is set to the Readonly mode. A delay time of 2 s is required before any device operation is initiated. The delay time is measured from the time VCC reaches VCC min (3.0 V). During powerup, RP = VSS is recommended. Falling in Busy status is not recommended for possibility of damaging the device. Absolute Maximum Ratings Parameter Symbol Value Unit Notes VCC voltage VCC -0.2 to +4.6 V 1 All input and output voltages except VCC, A9, Vin, Vout -0.6 to +4.6 V 1, 2 A9, RP supply voltage VHH, VID -0.6 to +14.0 V 1, 2 Operating temperature range Topr 0 to +70 C Storage temperature range Tstg -65 to +125 C Storage temperature under bias Tbias -10 to +80 C RP Notes: 1. Relative to VSS. 2. Minimum DC voltage is -0.5 V on input/output pins. During transition, this level may undershoot to -2.0 V for periods < 20 ns. Maximum DC voltage on input/output pins are VCC +0.5 V which, during transitions, may overshoot to VCC +1.5 V for periods < 20 ns. Capacitance (Ta = 25C, f = 1 MHz) Parameter Symbol Min Typ Max Unit Test conditions Input capacitance Cin -- -- 8 pF Vin = 0 V Output capacitance Cout -- -- 12 pF Vout = 0 V 15 HN29WT800 Series, HN29WB800 Series DC Characteristics (VCC = 3.3 V 0.3 V, Ta = 0 to +70C) Parameter Symbol Min Typ Max Unit Test conditions Input leakage current ILI -1 -- 1 A Vin = VSS to VCC Output leakage current ILO -10 -- 10 A Vout = VSS to VCC Standby VCC current ISB1 -- 50 200 A ISB2 -- 1 5 A Vin = VIH/VIL CE = RP = WP = VIH Vin = VSS or VCC, CE = RP = WP = V 0.3 V Vin = V /V , RP = V Vin = V or V , RP = V 0.3 V Vin = V /V , CE = V , RP = OE = V , f = 10 Mhz, CC Deep powerdown VCC current Read VCC current ISB3 -- 5 15 A ISB4 -- 1 5 A ICC1 -- 7 30 mA IH IL SS IH IL CC IL SS IL IH lout = 0 mA Write VCC current ICC2 -- -- 30 mA Vin = VIH/VIL, CE = WE = V IL , ICC3 -- -- 40 mA Erasing VCC current ICC4 -- -- 40 mA Suspend VCC current ICC5 -- -- 200 A RP all block unlocked current IRP -- -- 100 A RP = OE = V Vin = V /V , CE = RP = WP = V Vin = V /V , CE = RP = WP = V Vin = V /V , CE = RP = WP = V RP = V max A9 intelligent identifier voltage IID -- -- 100 A A9 = VIDmax A9 intelligent identifier voltage VID 11.4 12.0 12.6 V RP unlocked voltage VHH 11.4 12.0 12.6 V Input voltage VIL -0.5 -- 0.8 V VIH 2.0 -- VCC + 0.5 V VOL -- -- 0.45 V IOL= 5.8 mA VOH1 0.85 -- x VCC -- V IOH= -2.5 mA VOH2 VCC- -- 0.4 -- V IOH= -100 A VLKO 1.5 2.5 V IH Programming VCC current Output voltage 2 Low VCC lock-out voltage* -- IH IL IH IH IL IH IH IL IH HH Notes: 1. All currents are RMS unless otherwise noted. Typical values at V CC= 3.3 V, Ta = 25C. 2. To protect initiation of write cycle during VCC powerup/powerdown, a write cycle is locked out for VCC less than VLKO If VCC is less than VLKO Write State Machine is reset to read mode. When the Wirte State Machine is in Busy state, if VCC is less than VLKO, the alternation of memory contents may occur. 16 HN29WT800 Series, HN29WB800 Series AC Characteristics (VCC = 3.3 V 0.3 V, Ta = 0 to + 70C) Test Conditions * * * * * * Input pulse levels: VIL = 0 V, VIH = 3.0 V Input rise and fall time : 10 ns (HN29WT/WB800-10/12 Series) : 5 ns (HN29WT/WB800-8 Series) Output load : 1 TTL gate + 50 pF (Including scope and jig.) (HN29WT/WB800-10/12 Series) : 1 TTL gate + 30 pF (Including scope and jig.) (HN29WT/WB800-8 Series) Reference levels for measuring timing: 1.5 V VCC Powerup/Powerdown Timing Parameter Symbol Min Typ Max Unit RP = VIH setup time from VCC min tVCS 2 -- -- s Note: During powerup/powerdown, by the noise pulses on control pins, the device has possibility of accidental erasure or programming. The device must be protected against initiation of write cycle for memory contents during powerup/powerdown. The delay time of min 2 s is always required before read operation or write operation is initiated from the time V CC reaches VCC min during powerup/powerdown. By holding RP VIL, the contents of memory is protected during VCC powerup/powerdown. During powerup, RP must be held VIL for min 2 s from the time VCC reaches VCC min. During powerdown, RP must be held VIL until VCC reaches VSS. RP doesn't have latch mode, so RP must be held VIH during read operation or erase/program operation. Read/Write inhibit VCC Read/Write inhibit Read/Write inhibit tVSC RP CE tPS tPS WE 17 HN29WT800 Series, HN29WB800 Series Read Operation HN29WT800/HN29WB800 -8 -10 -12 Parameter Symbol Min Max Min Max Min Max Unit Read cycle time tRC 80 -- 100 -- 120 -- ns Address to output delay tACC -- 80 -- 100 -- 120 ns tCE -- 80 -- 100 -- 120 ns tOE -- 40 -- 50 -- 60 ns tRP -- 300 -- 300 -- 600 ns tDF -- 25 -- 25 -- 30 ns Address to output hold tOH 0 -- 0 -- 0 -- ns OE hold from WE high tOEH 80 -- 100 -- 120 -- ns tOEH 0 -- 0 -- 0 -- ns tPWH 0 -- 0 -- 0 -- ns tPHZ -- 150 -- 150 -- 300 ns tBCD -- 5 -- 5 -- 5 ns tBAD -- 5 -- 5 -- 5 ns tBYTE -- 80 -- 100 -- 120 ns tBHZ -- 25 -- 25 -- 30 ns CE to output delay OE to output delay RP access time CE or OE high to output float* 1 Status register read in busy OE hold from WE high Other read RP recovery time before read RP low to output High-Z CE low to BYTE high or low Address to BYTE high or low BYTE to output delay BYTE low to output High-Z Notes: 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. 2. Timing measurements are made under read timing waveform. 18 HN29WT800 Series, HN29WB800 Series Read Timing Waveform (Byte Mode or Word Mode) Address Address valid t RC CE OE t DF t OEH t OE WE t CE t PWH t OH Output valid I/O t PWH t PHZ RP 19 HN29WT800 Series, HN29WB800 Series Read Timing Waveform (Byte Mode, Word Mode Switch) A0 to A18 Address valid Address valid t ACC t DF CE t CE t CE t BAD OE t BYTE t BYTE t OH BYTE t BCD t BAD High-Z Output valid I/O0 to I/O7 Valid t BHZ Output valid t ACC High-Z Valid I/O8 to I/O14 I/O15/A-1 A-1 Note : When BYTE = High, CE = OE = Low, I/O15/A-1 is output status, At this time, input signal must not be applied. 20 I/O15 A-1 HN29WT800 Series, HN29WB800 Series Command Write Operation HN29WT800/HN29WB800 -8 -10 -12 Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit Write cycle time tWC 80 -- -- 100 -- -- 120 -- -- ns Address setup time tAS 50 -- -- 50 -- -- 50 -- -- ns Address hold time tAH 10 -- -- 10 -- -- 10 -- -- ns Data setup time tDS 50 -- -- 50 -- -- 50 -- -- ns Data hold time tDH 10 -- -- 10 -- -- 10 -- -- ns CE setup time tCS 0 -- -- 0 -- -- 0 -- -- ns CE hold time tCH 0 -- -- 0 -- -- 0 -- -- ns Write pulse width tWP 60 -- -- 60 -- -- 60 -- -- ns Write pulse high time tWPH 20 -- -- 20 -- -- 20 -- -- ns WE setup time tWS 0 -- -- 0 -- -- 0 -- -- ns WE hold time tWH 0 -- -- 0 -- -- 0 -- -- ns CE pulse width tCEP 60 -- -- 60 -- -- 60 -- -- ns CE pulse high time tCEPH 20 -- -- 20 -- -- 20 -- -- ns Duration of program operation tDAP -- 25 120 -- 25 120 -- 25 120 ms Duration of block erase operation tDAE -- 50 600 -- 50 600 -- 50 600 ms BYTE high or low setup time tBS 50 -- -- 50 -- -- 50 -- -- ns BYTE high or low hold time 80 -- -- 100 -- -- 120 -- -- ns RP high recovery to WE low tPS 500 -- -- 500 -- -- 500 -- -- ns Block lock setup to write enable high tBLS 80 -- -- 100 -- -- 120 -- -- ns tWPS 80 -- -- 100 -- -- 120 -- -- ns tBLH 0 -- -- 0 -- -- 0 -- -- ns tWPH 0 -- -- 0 -- -- 0 -- -- ns WE high to RDY/Busy low tWHRL -- -- 80 -- -- 100 -- -- 120 ns CE high to RDY/Busy low tEHRL -- -- 80 -- -- 100 -- -- 120 ns Block lock hold from valid SRD tBH Note: Read operation parameters during command write operations mode are the same as during read timing waveform. Typical values at VCC = 3.3 V, Ta = 25C. 21 HN29WT800 Series, HN29WB800 Series Erase and Program Performance Parameter Min Typ Max Unit Main block write time (Page mode -- 6.4 38.4 s Page write time -- 25 120 ms Block erase time -- 50 600 ms Note: Typical values at VCC = 3.3 V, Ta = 25 C. These values exclude system level overhead. Page Program Timing Waveform (WE control) Page program Read status Write read register array command Address valid A7 to A18 BYTE=Low (A-1 to A6) BYTE=High (A0 to A6) 00H 00H 02H to FEH FFH 00H 01H 02H to 7FH 7FH tAS tWC t AH t CE CE tCH tCS OE t WP tOE t OEH t DAP t WPH WE t DH t DS 41H I/O Din Din Din Din SRD t WHRL RDY/Busy tBS tBH BYTE V HH RP WP 22 t BLS t BLH t WPS t WPH tPS FFH HN29WT800 Series, HN29WB800 Series Page Program Timing Waveform (CE control) Read status register Page program A7 to A18 Write read array command Address valid BYTE=Low (A-1 to A6) 00H 01H 02H to FEH FFH BYTE=High (A0 to A6) 00H 01H 02H to 7FH 7FH t AS t WC t AH t CE CE t CEPH t OE t WH OE t OEH t CEP t DAP t WS WE t DS t DH 41H Din Din Din Din SRD FFH I/O t EHRL RDY/Busy t BH t BS BYTE t BLS V HH RP t BLH t PS t WPS t WPH WP 23 HN29WT800 Series, HN29WB800 Series Write Timing Waveform for Erase Operations (WE control) Program Erase Address Read status register Write read array command Address valid t WC t AS t AH t CE CE t CS OE t CH t OE t WP t OEH t WPH t DAE WE t DS t DH 20H D0H SRD I/O t WHRL RDY/Busy t BS t BH BYTE t BLS t BLH t WPS t WPH V HH t PS RP WP 24 FFH HN29WT800 Series, HN29WB800 Series Write Timing Waveform for Erase Operations (CE control) Program Erase Read status register Write read array command Address valid Address t AS t WC t AH t CE CE t t OE t t CEPH t t WH OEH t CEP OE DAE WS WE t DS t DH 20H D0H SRD FFH I/O t EHRL RDY/Busy t BS t BH BYTE t BLH t BLS V HH RP t PS t WPS t WPH WP 25 HN29WT800 Series, HN29WB800 Series Page Program Flowchart START Write 41h n=0 n=n+1 Write Address n, Data n n=FFH? or n=7FH? NO YES Status register read SR.7=1? NO Write B0H? YES Full status check if desired Suspend loop Write D0H Page program completed 26 YES NO HN29WT800 Series, HN29WB800 Series Block Erase Flowchart START Write 20H Write D0H Block Address Status register read SR.7=1? NO Write B0H? NO YES YES Full status check if desired Suspend loop Write D0H Block erase completed YES 27 HN29WT800 Series, HN29WB800 Series Full Status Check Procedure Status register read SR.4=1? and SR.5=1? YES Command sequence error NO SR.5=1? NO Block erase error YES SR.4=1? YES Successful (Block erase,program) 28 NO SR.3=1? YES Program error (Page,lock bit) NO Program error (Block) HN29WT800 Series, HN29WB800 Series Suspend/Resume Flowchart START Write B0H Suspend Status register read SR.7=1? NO YES SR.6=1? NO Program/erase completed YES Write FFH Read array data Done reading NO YES Write D0H Resume Operation resume 29 HN29WT800 Series, HN29WB800 Series Lock Bit Program Flowchart START Write 77H Write D0H block address SR.7=1? NO YES SR.4=1? YES Lock bit program successful 30 NO Lock bit program failed HN29WT800 Series, HN29WB800 Series Operation Status and Effective Command Read/standby state Read status register Clear status register 50H Sleep state Read device identifier 71H Read lock bit status 90H Read device identifier Read lock bit status 71H 90H Read array Read status register F0H FFH (Sleep) Setup state 77H 41H Page program setup WDi 1=0-255 Inernal state D0H D0H other Program and verify F0H Request sleep Erase all unlocked blocks setup Block erase setup Lock bit program setup D0H other other Erase and verify Read status register Read status register return B0H D0H D0H B0H Ready Is request sleep ? Read status register 70H YES 50H Clear status register Read device identifier F0H Read lock status 71H 90H Request sleep return Read array FFH 31 HN29WT800 Series, HN29WB800 Series Package Dimensions HN29WT800FP/HN29WB800FP Series (FP-44D) 28.50 28.70 Max 23 1 22 12.60 44 1.72 0.17 - 0.05 3.00 Max 11.8 - 0.3 0.09 Min 0 - 10 1.27 1.27-0.10 0.80 - 0.20 0.10 0.12 M HN29WT800T/HN29WB800T Series (TFP-44D) 12.0 48 25 18.4 12.4 Max 20.0 - 0.3 1 24 0.55 0.2 - 0.1 0.08 M 1.20 Max 32 0.10 0.18 Max 0.08 Min 0.17 - 0.05 0-5 0.45 max 0.5 - 0.1 HN29WT800 Series, HN29WB800 Series HN29WT800R/HN29WB800R Series (TFP-48DR) 12.0 48 25 18.4 12.4 Max 20.0 - 0.3 1 24 0.55 0.2 - 0.1 0.08 M 1.20 Max 0.18 Max 0.08 Min 0.17 - 0.05 0-5 0.45 max 0.5 - 0.1 0.10 33 HN29WT800 Series, HN29WB800 Series Notice When using this document, keep the following in mind: 1. 2. 3. 4. 5. 6. 34 This document may, wholly or partially, be subject to change without notice. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. 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