HN29WT800FP-8 - Hitachi Semiconductor

HN29WT800 Series,HN29WB800 Series

1048576-Word x 8-bit / 524288-word x 16-bit CMOS Flash

Memory

ADE-203-537(Z)

Preliminary

Rev. 0.0

Jun. 14, 1996

Description

The Hitachi HN29WT800 Series, HN29WB800 Series are 1-Mword x 8-bit/512-kword x 16-bit CMOS

Flash Memory with DINOR (D Ivided bitline NOR) type memory cells, that realize programming and

erase capabilities with a single 3.3 V power supply. The built-in Sequence Controller allows Automatic

Program/Erase without complex external control. HN29WT800 Series, HN29WB800 Series enable the

low power and high performance systems such as mobile, personal computing and communication

products.

Features

• On-board single power supply (VCC): VCC = 3.3 V ± 0.3 V

• Access time: 80/100/120 ns (max)

• Low power dissipation:

 ICC = 30 mA (max) (Read)

 ICC = 200 µA (max) (Standby)

 ICC = 40 mA (max) (Program)

 ICC = 40 mA (max) (Erase)

 ICC = 1 µA (typ) (Deep powerdown)

• Automatic page programming:

 Programming time: 25 ms (typ)

 Program unit: 128 word

This product is compatible with M5M29FB/T800xx by Ltd. Mitsubishi.

Preliminary: This document contains information on a new product. Specifications and information contained

herein are subject to change without notice.

HN29WT800 Series, HN29WB800 Series

• Automatic erase:

 Erase time: 50 ms (typ)

 Erase unit: Boot block; 8-kword/16-kbyte x 1

 Parameter block; 4-kword/8-kbyte x 2

 Main block; 16-kword/32-kbyte x 1

 32-kword/64-kbyte x 15

• Block boot:

 HN29WT800 Series: Top boot

 HN29WB800 Series: Bottom boot

• Other functions:

 Software command control

 Selective block lock

 Program suspend/Resume

 Erase suspend/Resume

 Status register read

 Sleep

• Compatible with M5M29FB/T800xx by Ltd. Mitsubishi

Ordering Information

Type No. Access time Package

HN29WT800FP-8

HN29WT800FP-10

HN29WT800FP-12

80 ns

100 ns

120 ns

44-pin plastic SOP (FP-44D)

HN29WB800FP-8

HN29WB800FP-10

HN29WB800FP-12

80 ns

100 ns

120 ns

HN29WT800T-8

HN29WT800T-10

HN29WT800T-12

80 ns

100 ns

120 ns

12 x 20.0 mm2 48-pin plastic TSOP I (TFP-48D)

HN29WB800T-8

HN29WB800T-10

HN29WB800T-12

80 ns

100 ns

120 ns

HN29WT800R-8

HN29WT800R-10

HN29WT800R-12

80 ns

100 ns

120 ns

12 x 20.0 mm2 48-pin plastic TSOP I (Reverse)

(TFP-48DR)

HN29WB800R-8

HN29WB800R-10

HN29WB800R-12

80 ns

100 ns

120 ns

HN29WT800 Series, HN29WB800 Series

Pin Arrangement

HN29WT800 Series, HN29WB800 Series

I/O4

VI/O11

I/O3

I/O2

I/O10 I/O5

I/O12

I/O1

I/O9 I/O6

I/O13

I/O0

I/O8 I/O7

I/O14

OE V

I/O15/A-1

CE A16

BYTE

A1 A14

A15

A3 A12

A13

A5 A10

A11

A17

A7 A8

A18 RP

SSSS

HN29WT800FP Series

HN29WB800FP Series

(TOP VIEW)

144

243

441

639

837

10 35

12 33

14 31

16 29

18 27

20 25

22 23

Pin Arrangement (cont.)

HN29WT800 Series, HN29WB800 Series

I/O8

I/O0

A17

A7 I/O9

I/O1

RDY/Busy

A18 I/O10

I/O2

BYTE

I/O3

A11

A10

A13

A12

A15

A14 A16

HN29WT800T Series

HN29WB800T Series

(TOP VIEW)

A2 23

24 A0

I/O11

I/O5

I/O4

I/O12

I/O6

I/O13

I/O7

I/O14

I/O15/A-1

(TOP VIEW)

I/O0 29

I/O2

I/O1

I/O8

I/O9

I/O3

I/O10

I/O11

HN29WB800R Series

HN29WT800R Series

I/O4

I/O12

I/O5

I/O13

I/O15/A-1

I/O7

I/O6

I/O14

A16

BYTE

RDY/Busy

A17

A18

A10

A14

A12

A11

A13

A15

HN29WT800 Series, HN29WB800 Series

Pin Description

Pin name Function

A-1 to A-18 Address

I/O0 to I/O1 5 Input/output

Chip enable

Output enable

Write enable

Reset/Powerdown

RDY/

Busy

Ready/

Busy

Write protect

BYTE

Byte enable

VCC Power supply

VSS Ground

NC No connection

HN29WT800 Series, HN29WB800 Series

Block Diagram

X-address

buffer X-decorder

Main block 32-kword

Main block 16-kword

Parameter block1 4-kword

Boot block 8-kword

128-word page buffer

Parameter block2 4-kword

Y-decorder

Y-address

buffer

Status/ID register

CUI WSM

Y-gate /Sens AMP

Multiplexer

Input/output buffers

A8 to A18

A0 to A7

BYTE

RDY/BYTE

I/O0

CUI: Command User Interface

WSM: Write State Machine

I/O15/A-1

HN29WT800 Series, HN29WB800 Series

Memory Map

HN29WT800 Series Memory Map

32-kword main block00000H to 0FFFFH

32-kword main block10000H to 1FFFFH

00000H to 07FFFH

32-kword main block20000H to 2FFFFH

08000H to 0FFFFH

32-kword main block30000H to 3FFFFH

10000H to 17FFFH

32-kword main block40000H to 4FFFFH

18000H to 1FFFFH

32-kword main block50000H to 5FFFFH

20000H to 27FFFH

32-kword main block60000H to 6FFFFH

28000H to 2FFFFH

32-kword main block70000H to 7FFFFH

30000H to 37FFFH

32-kword main block80000H to 8FFFFH

38000H to 3FFFFH

32-kword main block90000H to 9FFFFH

40000H to 47FFFH

32-kword main block

A0000H to AFFFFH

48000H to 4FFFFH

32-kword main block

B0000H to BFFFFH

50000H to 57FFFH

32-kword main block

C0000H to CFFFFH

58000H to 5FFFFH

32-kword main block

D0000H to DFFFFH 68000H to 6FFFFH

32-kword main block

E0000H to EFFFFH 70000H to 77FFFH

16-kword main block

F0000H to F7FFFH 78000H to 7BFFFH

F8000H to F9FFFH 7C000H to 7CFFFH

4-kword parameter blockFA000H to F8FFFH 7D000H to 7DFFFH

8-kword boot blockFC000H to FFFFFH 7E000H to 7FFFFH

x 8 (Byte mode) x 16 (word mode)

4-kword parameter block

60000H to 67FFFH

C0000H to CFFFFH

B0000H to BFFFFH

A0000H to AFFFFH

90000H to 9FFFFH

80000H to 8FFFFH

70000H to 7FFFFH

08000H to 0FFFFH

06000H to 07FFFH

04000H to 05FFFH

D0000H to DFFFFH

E0000H to EFFFFH

F0000H to FFFFFH

x 8 (Byte mode)

HN29WB800 Series Memory Map

00000H to 03FFFH

32-kword main block

00000H to 07FFFH

20000H to 27FFFH

18000H to 1FFFFH

10000H to 17FFFH

08000H to 0FFFFH

40000H to 47FFFH

38000H to 3FFFFH

30000H to 37FFFH

28000H to 2FFFFH

32-kword main block

68000H to 6FFFFH

60000H to 67FFFH

58000H to 5FFFFH

50000H to 57FFFH

48000H to 4FFFFH

78000H to 7FFFFH

70000H to 77FFFH

x 16 (word mode)

8-kword boot block

4-kword parameter block

16-kword main block

32-kword main block

40000H to 4FFFFH

50000H to 5FFFFH

60000H to 6FFFFH

10000H to 1FFFFH

20000H to 2FFFFH

30000H to 3FFFFH

02000H to 02FFFH

03000H to 03FFFH

04000H to 07FFFH

A- 1 to 18 (Byte mode) A 0 to A18 (Word mode)



A- 1 to 18 (Byte mode) A 0 to A18 (Word mode)



HN29WT800 Series, HN29WB800 Series

Mode Selection

Word Mode (

BYTEBYTE

= VIH)

Mode

CECE OEOE WEWE RPRP

RDY/

BusyBusy

I/O0 to I/O15

Read

Array VIL VIL VIH VIH

VOH (High-Z)

Dout

Status register VIL VIL VIH VIH

x*5

Status Register

Data

Lock bit status VIL VIL VIH VIH

Lock bit data (I/O6)

Identifier (Maker)*1,*2VIL VIL VIH VIH

VOH (High-Z)

07H

Identifier (Device)*1,*3VIL VIL VIH VIH

VOH (High-Z)

85H/86H*6

Output disable

VIL VIL VIH VIH

High-Z

Standby

VIH xxV

High-Z

Command write*4

Program VIL VIH VIL VIH

Command/Data in

Erase VIL VIH VIL VIH

Command

Others VIL VIH VIL VIH

Command

Deep powerdown

xxxV

VOH (High-Z)

High-Z

Notes: 1. The command programming mode is used to output the identifier code. Refer to the table of

Software Command Definition.

2. A0 = VIL

3. A0 = VIH

4. Refer to the table of Software Command Definition. Programming and erase operation begins

after mode setting by command input.

5. x can be VIL or VIH for control pins, and VOL or VOH (High-Z) for RDY/

Busy

pin. The RDY/

Busy

an open drain output pin and indicates status of the internal WSM. When low, it indicates the

WSM is Busy performing an operation. A pull-up resistor of 10 k to 100 kΩ is required to allow

the RDY/

Busy

signal to transition high indicating a Ready WSM condition.

6. 85H: HN29WT800 Series, 86H: HN29WB800 Series.

HN29WT800 Series, HN29WB800 Series

BYTEBYTE

Mod e (

BYTEBYTE

= VIL)

Mode

CECE OEOE

WEWE

RPRP

RDY/

BusyBusy

I/O0 to I/O7

Read

Array VIL VIL

VIH

VIH VOH (High-Z) Dout

Status register VIL VIL

VIH

VIH x*5Status Register

Data

Lock bit status VIL VIL

VIH

VIH x Lock bit data

(I/O6)

Identifier (Maker)*1,*2VIL VIL

VIH

VIH VOH (High-Z) 07H

Identifier (Device)*1,*3VIL VIL

VIH

VIH VOH (High-Z) 85H/86H*6

Output disable

VIL VIH

VIH

VIHx High-Z

Standby

VIH x

VIH x High-Z

Command write*4

Program VIL VIH

VIL

VIH x Command/Data in

Erase VIL VIH

VIL

VIH x Command

Others VIL VIH

VIL

VIH x Command

Deep powerdown

IL VOH (High-Z) High-Z

Notes: 1. The command programming mode is used to output the identifier code. Refer to the table of

Software Command Definition.

2. A0 = VIL

3. A0 = VIH

4. Refer to the table of Software Command Definition. Programming and erase operation begins

after mode setting by command input.

5. x can be VIL or VOH for control pins, and VOL or VOH (High-Z) for RDY/

Busy

pin. The RDY/

Busy

an open drain output pin and indicates status of the internal WSM. When low, it indicates the

WSM is Busy performing an operation. A pull-up resistor of 10 k to 100 kΩ is required to allow

the RDY/

Busy

signal to transition high indicating a Ready WSM condition.

6. 85H: HN29WT800 Series, 86H: HN29WB800 Series.

HN29WT800 Series, HN29WB800 Series

Software Command Definition

First bus cycle Second bus cycle Third bus cycle

Command

Oper-

ation

mode

Address Data

(I/O7

to I/O0)*1

Operation

mode Address Data

(I/O7

to I/O0)

Operation

mode

Address Data

(I/O7

to I/O0)

Read array

(memory)

Write x FFH

Read

identifier

codes

Write x 90H Read IA*2ID*2

Read status

Write x 70H Read x SRD*3

Clear status

Write x 50H

Page

program*5

Write x 41H Write WA0*4WD0*4

Write

WA1 WD1

Block erase

Write x 20H Write BA*6D0H

Suspend

Write x B0H

Resume

Write x D0H

Read lock

bit status

Write x 71H Read BA I/O6*7

Lock bit

program/co

nfirm

Write x 77H Write BA D0H

Erase all

unlocked

blocks

Write x A7H Write x D0H

Sleep*8

Write x F0H

Notes: 1. In the word mode, upper byte data (I/O8 to I/O15) is ignored.

2. IA = Identifier address, A0 = VIL (Manufacture code), A0 = VIH (Device code), ID = ID code,

BYTE

= VIL: A-1, A1 to A18 = VIL,

BYTE

= VIH: A1 to A18 = VIL.

3. SRD = Status register data

4. WA = Write address, WD = Write data

BYTE

= VIL: Write address and write data must be provided sequentially from 00H to FFH for A-1

to A6. Page size is 256 byte (256-byte x 8-bit).

BYTE

= VIH: Write address and write data must be provided sequentially from 00H to 7FH for A0 to

A6. Page size is 128 word (128-word x 16-bit).

6. BA = Block address (A16 to A20), (Addresses except block address must be VIH)

7. I/O6 provides block lock status, I/O6 = 1: Block unlocked, I/O6 = 0: Block locked.

8. Sleep command (F0H) put the device into the sleep mode after completing the current

operation. The active current is reduced to deep powerdown levels. The Read Array command

(FFH) must be written to get the device out of sleep mode.

HN29WT800 Series, HN29WB800 Series

Block Locking (TSOP package)

RP WP Lock bit (internally) Write protection provided

VIL x x All bl ocks lo cked (Deep powerdown mode)

VHH x x A ll bl ocks unlocked

VIH VIL 0 Blocks locked (Depend on l ock bit data)

VIH VIL 1 Blocks unlocked (Depend on l ock bit data)

VIH VIH x All blocks unlocked

Note: I/O6 provided lock status of each block after writing the Read lock status command (71H).

must not be switched during performing Read/Write operations or WSM busy (WSMS = 0).

Block Locking (SOP package)

RP Lock bit (internally) Write protection provided

VIL x All bl ocks lo cked (Deep powerdown mode)

VHH x A ll bl ocks unlocked

VIH 0 Blocks locked (Depend on l ock bit data)

VIH 1 Blocks unlocked (Depend on l ock bit data)

Note: I/O6 provided lock status of each block after writing the Read lock status command (71H).

Status Register Data (SRD)

Symbol

Function Definition

SR. 7 (I/O7)

Write state machine status 1 = Ready 0 = Busy

SR. 6 (I/O6)

Suspend status 1 = Suspend 0 = Operation in progress/completed

SR. 5 (I/O5)

Erase status 1 = Error 0 = Successful

SR. 4 (I/O4)

Program status 1 = Error 0 = Successful

SR. 3 (I/O3)

Block status after program 1 = Error 0 = Successful

SR. 2 (I/O2)

Reserved The function and the definition for these bits are to be

SR. 1 (I/O1)

Reserved determined. These bits should be masked out when the status

SR. 0 (I/O0)

Device sl eep status 1 = Device i n sleep 0 = Device not in sleep

Note: The RDY/

Busy

is an open dran output pin and indicates status of the internal WSM. When low, it

indicates that the WSM is Busy performing an operation. A pull-up resistor of 10kΩ to 100kΩ is

required to allow the RDY/

Busy

signal to transition high indicating a Ready WSM condition.

I/O3 indicates the block status after the page programming. When I/O3 is High, the page has the

over-programmed cell. If over-program occures, the device is block failed. However, if I/O3 is High,

please try the block erase to the block. The block may revive.

HN29WT800 Series, HN29WB800 Series

Device Identifier Mode

The device identifier mode allows the reading out of binary codes that identify manufacturer and type of device,

from outputs of Flash Memory. By this mode, the device will be automatically matched its own corresponding

erase and programming algorithm.

HN29WT800 Series, HN29WB800 Series Identifier Code

Pins A0 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Hex. data

Manufacturer code 0 0 0 0 0 0 1 1 1 07H

Device code (T series) 1 1 0 0 0 0 1 0 1 85H

Device code (B series) 1 1 0 0 0 0 1 1 0 86H

Notes: 1. Device identifier code can be read out by using the read identified codes command.

2. In the word mode, the same data as I/O7 to I/O0 is read out from I/O15 to I/O8.

3. A9 = VHH mode. A9 = 11.5 V to 13.0 V. Set A9 to VHH min 200 ns before falling edge of

ready status. Min 200 ns after return to VHH, device can't be accessed. A1 to A8, A10 to A18,

, = VIL, WE = VIH, I/O15/A-1 = VIL (

BYTE

= L).

Operations of the HN29WT800 Series, HN29WB800 Series

The HN29WT800 Series, HN29WB800 Series include on-chip program/erase control circuitry. The Write State

Machine (WSM) controls block erase and page program operations. Operational modes are selected by the

commands written to the Command User Interface (CUI). The Status Register indicates the status of the WSM

and when the WSM successfully compl etes the desired program or block era se operati on. A Dee p Powerdown

mode is en ab led w h en the

pin is at VSS minimizin g p o w er co nsumption .

Read: The HN29WT800 Series, HN29WB800 Series have three read modes, which accesses to the memory

array, the Device Identifier and the Status Register. The appropriate read command are required to be written to

the CUI. Upon initial device powerup or after exit from deep powerdown, the HN29WT800 Series,

HN29WB800 Seri es aut omati call y reset to read array mode. In t he read a rray mode, low level input to

and

, high level input to

and

, and address signals to the address inputs (A0 to A18) output the dat a of the

addressed location to the data input/output (I/O0 to I/O15).

Write: Writes to the CUI enable reading of memory array data, device identifiers and reading and clearing of

the Status Register, they also enable block erase and program. The CUI is written by bringing

to low level,

while

is at lo w lev el an d

is at high level. Addresses and data are latched on the earlier rising edge of

and

. Stan dar d micr o- p ro cessor write timings ar e u s ed .

Output Disable:When

is at V

IH output from the device is disabled. Data input/output are in a high

impedan ce (High-Z) s tate.

HN29WT800 Series, HN29WB800 Series

Standby:When

is at VIH, the device is in the standby mode and its power consumption is reduced. Data

input/output are in a high impedance (High-Z) state. If the memory is deselected during block erase or program,

the internal control circuits remain active and the device consume normal active power until the operation

completes.

Deep Po w erdown : Wh en

is at VIL, the devic e is in the dee p powerdown mode and its power consumption is

substantially low. During read modes, the memory is deselected and the data input/output are in a high

impedance (High-Z) state. After return from powerdown, the CUI is reset to Read Array and the Status Register

is cleared to value 80H. During block erase or program modes,

low will abort either operation. Memory

array data of the block being altered become invalid.

Functional Description

The dev ice o per atio ns are selected by writing s p ecif ic s o f tw ar e comman d in to th e C U I .

Read Array Command (FFH): The device is in read arr ay mo de o n in itial dev ice p o w er up an d after ex it from

deep power down, or by writing FFH to the CUI. The device remains in Read Array mode until the other

command s ar e w r itten .

Read Device Identifier Command (90H):Though PROM programmers can normally read device identifier

codes by raising A9 to high voltage, multiplexing high voltage onto address lines is not desired for

microprocessor system. It is an other means to read device identifier codes that Read Device Identifier Code

Command (90H) is written to the command latch. Following the write of the Read De vice Identifier command

of 90H, the manufacturer code and the device code can be read from addresses 00000H and 00001H,

respectively.

Read Status Register Command (70H): The Status Register is read after writing the read status register

command of 70H to the CUI. The contents of Status Register are latched on the later falling edge of

must be toggled every status read.

Clear Status Register Command (50H): The Eras e S tatu s an d P r o gr am S t atus bits ar e s et to H ig h by th e Write

State Machine and can be reset by the Clear Status Register command of 50H. These bits indicates various

failur e con d itio ns.

Block Erase/ Confi rm Command (20H/D0H): Automated block erase is initiated by writing the Block Erase

of 20H followed by the Confirm command of D0H. An address within the block to be erased is required. The

WSM ex ecu tes iter ativ e erase puls e app licatio n and er as e v er ify o p eratio n .

Suspend/Resume Command (B0H/D0H): Writing the suspend command of B0H during block erase operation

interrupts the block erase operation and allows read out from another block of memory. Writing the suspend

comm and of B0H during progra m opera t i on int e rrupts the progra m ope ra t ion a nd a ll ows rea d out from a not her

block of memory. The devic e continue s to output stat us register dat a when read, after t he suspend comma nd is

written to it. Polling the WSM status and suspend status bits will determine when the erase operation or

program operation has been suspended. At this point, writing of the read array command to the CUI enables

reading data from blocks other than that which is suspended. When the resume command of D0H is written to

the CU I , th e WS M will continu e w ith th e erase or pr og r am p ro ces ses.

HN29WT800 Series, HN29WB800 Series

Page Program Command (41H): Page program allows fas t programming of 128-w ord of data. Writing of 41H

initiates the page program operation. From 2nd cycle to 129th cycle write data must be serially inputted.

Address A6 to A0 have to be incremented from 00H to 7FH. After completion of data loading, the WSM

controls the program pulse application and verify operation. Basically re-program must not be done on a page

which has already programmed.

Data Protection: The HN29WT800 Series, HN29WT800 Series provide selective block locking of memory

blocks. Each block has an associated nonvolatile lock-bit which determines the lock status of the block. In

addition, the HN29WT800 Series, HN29WT800 Series have a master write protect pin (

) which prevents

any modifi cat ions to mem ory blocks whose lock-bits are set to Low, when

is low. When

is high or

is VHH, al l blocks ca n be program med or era sed re gardless of the sta te of lock-bi ts, and t he lock-bit s are cle ared

to High by erase.

Power Supply Voltage: When the power supply vol ta ge (VCC) is less than 2.2 V, the device is set to the Read-

only mo d e. A d elay time o f 2 µs is r eq u ired b efo r e an y d ev ice o per atio n is initiated. The delay time is measured

fro m the time VCC reaches VCC min (3.0 V). During powerup,

= VSS is recommended. Falling in Busy status is

not r ecommen d ed fo r p ossibility of d amag ing th e d evi ce.

Absolute Maximum Ratings

Parameter Symbol Value Unit Notes

VCC voltage VCC -0.2 to + 4 .6 V 1

All input and output voltages except VCC, A9 ,

Vin, Vo u t -0.6 to + 4 .6 V 1, 2

A9,

supply voltage VHH, VID -0 .6 to + 1 4 .0 V 1, 2

Operating temperature range Topr 0 to +70 °C

Storage temperature range Tstg -65 to +125 °C

Storage temperature under bias Tbias -10 to +80 °C

Notes: 1. Relative to VSS.

2. Minimum DC voltage is -0.5 V on input/output pins. During transition, this level may undershoot

to -2.0 V for periods < 20 ns. Maximum DC voltage on input/output pins are VCC +0.5 V which,

during transitions, may overshoot to VCC +1.5 V for periods < 20 ns.

Capacitance (Ta = 25°°C, f = 1 MHz)

Parameter Symbol Min Typ Max Unit

Test conditions

Input capacitance Cin — — 8 pF

Vin = 0 V

Output capacitance Cout — — 12 pF

Vout = 0 V

HN29WT800 Series, HN29WB800 Series

DC Characteristics (VCC = 3.3 V ± 0.3 V, Ta = 0 to +70°°C)

Parameter Symbol Min Typ Max Unit Test conditions

Input leakage current ILI -1 — 1 µA Vin = VSS to VCC

Output leakage current ILO -10 — 10 µA Vout = VSS to VCC

Standby VCC current ISB1 — 50 200 µA Vin = VIH/VIL

= VIH

ISB2 —1 5 µA Vin = VSS or VCC,

= VCC ± 0.3 V

Deep powerdown VCC current ISB3 —5 15µA Vin = VIH/VIL,

= VIL

ISB4 —1 5 µA Vin = VSS or VCC,

= VSS ± 0.3 V

Read VCC current ICC1 — 7 30 mA Vin = VIH/VIL,

= VIL,

= VIH, f = 10 Mhz,

lout = 0 mA

Write VCC current I CC2 — — 30 mA Vin = VIH/VIL,

= VIL,

= VIH

Programming VCC current ICC3 — — 40 mA Vin = VIH/VIL,

= VIH

Erasing VCC current ICC4 — — 40 mA Vin = VIH/VIL,

= VIH

Suspend VCC current ICC5 — — 200 µA Vin = VIH/VIL,

= VIH

all block unlocked current IRP — — 100 µA

= VHHmax

A9 intelligent identifier voltage IID — — 100 µA A9 = VIDmax

A9 intelligent identifier voltage VID 11.4 12.0 12.6 V

RP unlocked voltage VHH 11.4 12.0 12.6 V

Input voltage VIL -0.5 — 0.8 V

VIH 2.0 — VCC

0.5

Output voltage VOL — — 0.45 V IOL= 5.8 mA

VOH1 0.85

x VCC

——V I

OH= -2.5 mA

VOH2 VCC-

0.4 ——V I

OH= -100 µA

Low VCC lock-out voltage*2VLKO 1.5 — 2.5 V

Notes: 1. All currents are RMS unless otherwise noted. Typical values at VCC= 3.3 V, Ta = 25°C.

2. To protect initiation of write cycle during VCC powerup/powerdown, a write cycle is locked out for

VCC less than VLKO If VCC is less than VLKO Write State Machine is reset to read mode. When the

Wirte State Machine is in Busy state, if VCC is less than VLKO, the alternation of memory contents

may occur.

HN29WT800 Series, HN29WB800 Series

AC Characteristics (VCC = 3.3 V ± 0.3 V , T a = 0 to + 7 0°°C)

Test Conditions

• Input pulse levels: VIL = 0 V, VIH = 3.0 V

• Input rise and fall time : ≤ 10 ns (HN29WT/WB800-10/12 Series)

• : ≤ 5 ns (HN29WT/WB800-8 Series)

• Output load : 1 TTL gate + 50 pF (Including scope and jig.) (HN29WT/WB800-10/12 Series)

• : 1 TTL gate + 30 pF (Including scope and jig.) (HN29WT/WB800-8 Series)

• Reference levels for measuring timing: 1.5 V

VCC Powerup/Powerdown Timing

Parameter Symbol Min Typ

Max

Unit

RP = VIH setup ti me fro m V CC min tVCS 2—— µs

Note: During powerup/powerdown, by the noise pulses on control pins, the device has possibility of

accidental erasure or programming. The device must be protected against initiation of write cycle

for memory contents during powerup/powerdown. The delay time of min 2 µs is always required

before read operation or write operation is initiated from the time VCC reaches VCC min during

powerup/powerdown. By holding RP VIL, the contents of memory is protected during VCC

powerup/powerdown. During powerup, RP must be held VIL for min 2 µs from the time VCC reaches

VCC min. During powerdown, RP must be held VIL until VCC reaches VSS. RP doesn't have latch

mode, so RP must be held VIH during read operation or erase/program operation.

Read/Write inhibit

tVSC

tPS tPS

HN29WT800 Series, HN29WB800 Series

Read Operation

HN29WT800/HN29WB800

-8 -10 -12

Parameter Symbol Min Max Min Max Min

Max

Unit

Read cycle time tRC 80 — 100 — 120 — ns

Address to output delay tACC — 80 — 100 —

120

to output delay tCE — 80 — 100 —

120

to output delay tOE —40—50—

access time tRP — 300 — 300 —

600

high to output float*1tDF —25— 25—

Address to output hold tOH 0—0—0 — ns

hold from

high

Status register read in busy tOEH 80 — 100 — 120 — ns

hold from

high

Other read tOEH 0—0 —0 — ns

recovery time before read tPWH 0—0 —0 — ns

low to output High-Z tPHZ — 150 — 150 —

300

low to

BYTE

high or low tBCD —5 —5 —

Address to

BYTE

high or low tBAD —5 —5 —

BYTE

to output delay tBYTE — 80 — 100 —

120

BYTE

low to output High-Z tBHZ —25—25—

Notes: 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no

longer driven.

2. Timing measurements are made under read timing waveform.

HN29WT800 Series, HN29WB800 Series

Read Timing Waveform (Byte Mode or Word Mode)

I/O

Address valid

Output valid

Address

tRC

tOEH

tOE

tCE

tPWH

PHZ

tPWH

HN29WT800 Series, HN29WB800 Series

Read Timing Waveform (Byte Mode, Word Mode Switch)

BYTE

I/O8 to I/O14

A0 to A18

ACC

I/O15/A-1

Address valid Address valid

A-1 I/O15 A-1

Valid

Output valid

High-Z

Output valid

I/O0 to I/O7 High-Z

BAD

BCD

BYTE BYTE

ACC

BHZ

BAD

Note : When BYTE = High, CE = OE = Low, I/O15/A-1 is output status,

At this time, input signal must not be applied.

HN29WT800 Series, HN29WB800 Series

Command Write Operation

HN29WT800/HN29WB800

-8 -10

-12

Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit

Write cycle time tWC 80 — — 100 — — 120 — — ns

Address setup time tAS 50 — — 50 — — 50 — — ns

Address hold time tAH 10 — — 10 — — 10 — — ns

Da ta s e tu p time tDS 50 — — 50 — — 50 — — ns

Data hold time tDH 10 — — 10 — — 10 — — ns

CE s e tu p ti me tCS 0——0——0——ns

CE hold time tCH 0——0——0——ns

Write pulse width tWP 60 — — 60 — — 60 — — ns

Write pulse high time tWPH 20 — — 20 — — 20 — — ns

WE s e tu p ti me tWS 0——0——0——ns

WE hold time tWH 0——0——0——ns

CE pulse width tCEP 60 — — 60 — — 60 — — ns

CE pulse hi gh time tCEPH 20 — — 20 — — 20 — — ns

Duration of program

operation tDAP — 25 120 — 25 120 — 25 120 ms

Duration of block erase

operation tDAE — 50 600 — 50 600 — 50 600 ms

BYTE high or low setup time tBS 50 — — 50 — — 50 — — ns

BYTE high or low hold time tBH 80 — — 100 — — 120 — — ns

RP h igh re c o ve ry to WE low tPS 500 — — 500 — — 500 — — ns

Block lo ck setup to write

enable high tBLS 80 — — 100 — — 120 — — ns

tWPS 80 — — 100 — — 120 — — ns

Block lock hol d from valid

SRD tBLH 0——0——0——ns

WPH 0——0——0——ns

WE h i g h to RDY /B u s y l o w tWHRL — — 80 — — 100 — — 120 ns

CE high to RDY/Busy low tEHRL — — 80 — — 100 — — 120 ns

Note: Read operation parameters during command write operations mode are the same as during read

timing waveform. Typical values at VCC = 3.3 V, Ta = 25°C.

HN29WT800 Series, HN29WB800 Series

Erase and Program Performance

Parameter Min Typ

Max

Unit

Main block write time (Page mode — 6.4

38.4

Page write time — 25

120

Block erase time — 50

600

Note: Typical values at VCC = 3.3 V, Ta = 25 C. These values exclude system level overhead.

Page Program Timing Waveform (

WEWE

control)

A7 to A18 Address valid

Page program

00H

01H

BYTE=Low

(A0 to A6)

I/O

RDY/Busy

BYTE

BYTE=High

(A-1 to A6)

Read status

Write read

00H 02H to FEH FFH

00H 02H to 7FH 7FH

41H Din Din SRD FFHDin Din

DHDS

WPS WPH

BLH

WHRL

WPH

WP DAP

OEH

WC AS AH

ttt

BLS

HN29WT800 Series, HN29WB800 Series

Page Program Timing Waveform (

CECE

control)

A7 to A18

Address valid

Page program

01H

BYTE=Low

(A0 to A6)

I/O

RDY/Busy

BYTE

BYTE=High

(A-1 to A6)

Read status

Write read

00H 02H to FEH FFH

00H 02H to 7FH 7FH

41H Din Din SRD FFH

Din Din

DHDS

WPS WPH

BLS BLH

EHRL

CEP DAP

OEH

WC AS AH

CEPH



HN29WT800 Series, HN29WB800 Series

Write Timing Waveform for Erase Operations (

WEWE

control)

Address

Address valid

Program Erase

I/O

RDY/Busy

BYTE

Read status

Write read

20H D0H SRD FFH

DHDS

WPS WPH

BLS BLH

WHRL

WPH DAE

OEH

AS AH

HN29WT800 Series, HN29WB800 Series

Write Timing Waveform for Erase Operations (

CECE

control)

Address

Program Erase

I/O

RDY/Busy

BYTE

Read status

Write read

Address valid

tAS

tAH

tCE

CEP

tWH

CEPH

OEH

DAE

DS DH

EHRL

BS BH

BLS

tBLH

WPS

tWPH

20H D0H SRD FFH

HN29WT800 Series, HN29WB800 Series

Page Program Flowchart

START

Write 41h

n=0

Write

Address n, Data n

n=FFH?

Page program

completed

Full status check

if desired

SR.7=1?

Status register read

n=7FH?

Write B0H?

n=n+1

Suspend loop

Write D0H

YES

HN29WT800 Series, HN29WB800 Series

Block Erase Flowchart

START

Write 20H

Write D0H

Block Address

Block erase

completed

Full status check

if desired

SR.7=1?

Status register read

Write B0H?

Suspend loop

Write D0H

YES

HN29WT800 Series, HN29WB800 Series

Full Status Check Procedure

and

Successful

(Block erase,program)

SR.4=1? NONO

YES

Program error

(Page,lock bit)

YES

Block erase error

Status register

read

Command sequence error

(Block)

Program error

YES

SR.5=1?

SR.3=1?

SR.4=1?

SR.5=1?

HN29WT800 Series, HN29WB800 Series

Suspend/Resume Flowchart

START

Write B0H

Status register read

Operation

resume

SR.6=1? NO

YES

SR.7=1? NO

Write FFH

Read array data

Write D0H

Done NO

YES

completed

Program/erase

reading

YES

Suspend

Resume

HN29WT800 Series, HN29WB800 Series

Lock Bit Program Flowchart

START

Write 77H

Write D0H

Lock bit program

successful

SR.4=1? NO

YES

SR.7=1? NO

failed

YES

Lock bit program

block address

HN29WT800 Series, HN29WB800 Series

Operation Status and Effective Command

Read/standby state

Read status



Read device

identifier



Read lock bit

status



Read array



71H



F0H

FFH



90H



50H



Clear status



Read device

identifier



90H

Read lock bit

status



71H



Sleep state

Setup state



Page program

setup



41H

Lock bit program

setup



77H

Block erase

setup



Erase all unlocked

blocks setup



Inernal state



WDi

1=0-255



D0H

other



other



D0H

D0H



Read status



Program and

verify

Request sleep

D0H



(Sleep)



F0H



return B0H

B0H



D0H



Read status



Erase and verify

Clear status



Read status



Read device

identifier



Read array



71H



FFH



90H



Read status

Request sleep

F0H



return

Read lock status

70H



50H



Ready



Is request

sleep ?



YES



HN29WT800 Series, HN29WB800 Series

Package Dime ns ions

HN29WT800FP/HN29WB800FP Series (FP-44D)

12.60

28.50

28.70 Max

122

3.00 Max

0.09 Min

0.17 – 0.05

0.80 – 0.20

1.27–0.10

0 - 10

11.8 – 0.3 

0.10

1.27

0.12 M

1.72

HN29WT800T/HN29WB800T Series (TFP-44D)

12.0

12.4 Max

48 25

241

1.20 Max

0.10

0.55

0.2 – 0.1 0.08 M

18.4

0.17 – 0.05

0 - 5

20.0 – 0.3 

0.08 Min

0.18 Max

0.5 – 0.1 

0.45 max

HN29WT800 Series, HN29WB800 Series

HN29WT800R/HN29WB800R Series (TFP-48DR)

12.0

12.4 Max

48 25

241

1.20 Max

0.10

0.55

0.2 – 0.1 0.08 M

18.4

0.17 – 0.05

0 - 5

20.0 – 0.3 

0.08 Min

0.18 Max

0.5 – 0.1 

0.45 max

HN29WT800 Series, HN29WB800 Series

Notice

When using this document, keep the following in mind:

1. This document may, wholly or partially, be subject to change without notice.

2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or

part of this document without Hitachi's permission.

3. Hitachi will not be held responsible for any damage to the user that may result from accidents or

any other reasons during operation of the user's unit according to this document.

4. Circuitry and other examples described herein are meant merely to indicate the characteristics and

performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any

intellectual property claims or other problems that may result from applications based on the

examples described herein.

5. No license is granted by implication or otherwise under any patents or other rights of any third

party or Hitachi, Ltd.

6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL

APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales

company. Such use includes, but is not limited to, use in life support systems. Buyers of

Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to

use the products in MEDICAL APPLICATIONS.