Features * * * * * * * * * * * * * * * * * * * 8-bit Resolution 1 Gsps (Min.) Sampling Rate ADC Gain Adjust 2 GHz Full Power Input Bandwidth Fs = 1 Gsps, Fin = 20 MHz: - SINAD = 45 dB (7.4 Effective Bits) SFDR = 58 dBc Fs = 1 Gsps, Fin = 500 MHz: - SINAD = 44 dB (7.2 Effective Bits) SFDR = 56 dBc Fs = 1 Gsps, Fin = 1000 MHz (-3 dB Fs): - SINAD = 42 dB (7.0 Effective Bits) SFDR = 52 dBc 2 Tone IMD: -53 dBc (489 MHz and 490 MHz) at 1 Gsps DNL = 0.3 LSB INL = 0.7 LSB Low Bit Error Rate (10-13) at 1 Gsps Very Low Input Capacitance: 0.4 pF (Die Form) 500 mVpp Differential or Single-ended Analog Inputs Differential or Single-ended 50 ECL Compatible Clock Inputs ECL or LVDS/HSTL Output Compatibility Data Ready Output with Asynchronous Reset Gray or Binary Selectable Output Data; NRZ Output Mode Power Consumption: 3.4 W at TJ = 90 C Dual Power Supply: 5 V Radiation Tolerance Oriented Design (150 Krad (Si) Measured) 1 Gsps 8-bit A/D Converter JTS8388B Description The JTS8388B is a monolithic 8-bit analog-to-digital converter, designed for digitizing wide bandwidth analog signals at very high sampling rates of up to 1 Gsps. The JTS8388B uses an innovative architecture, including an on-chip Sample and Hold (S/H), and is manufactured with an advanced high-speed bipolar process. The on-chip S/H features a 2 GHz full power input bandwidth, providing excellent dynamic performance in undersampling applications (High IF digitizing). Applications * Digital Sampling Oscilloscopes * Satellite Receiver * Electronic Countermeasures/Electronic Warfare * Direct RF Down-conversion Screening * Standard Die Flow * Mil-PRF-38535, QML Level Q for Package Version * Space Screening According to ESA/SCC 9000 2104A-BDC-09/03 1 Simplified Block Diagram Figure 1. Simplified Block Diagram GAIN Master/Slave Track & Hold VIN, VINB G=2 T/H G=1 T/H G=1 Resistor Chain Analog Encoding Block 4 Interpolation Stages 4 5 Regeneration Latches 4 5 Error Correction & Decode Logic CLK CLKB Clock Buffer 8 Output Latches & Buffers 8 DRRB DR, DRB Functional Description GORB DATA, DATAB OR, ORB The JTS8388B is an 8-bit 1 Gsps ADC based on an advanced high-speed bipolar technology featuring a cutoff frequency of 25 GHz. The JTS8388B includes a front-end master/slave Track and Hold stage (Sample and Hold), followed by an analog encoding stage and interpolation circuitry. Successive banks of latches regenerate the analog residues into logical data before entering an error correction circuitry and a resynchronisation stage followed by 75 differential output buffers. The JTS8388B works in a fully differential mode from analog inputs up to digital outputs. The JTS8388B features a full power input bandwidth of 2 GHz. The control pad GORB is provided to select either the gray or binary data output format. The gain control pad is provided in order to adjust the ADC gain. The JTS8388B uses only vertical isolated NPN transistors together with oxide-isolated polysilicon resistors, providing enhanced radiation tolerance (more than 100 kRad total dose expected radiation). 2 JTS8388B 2104A-BDC-09/03 JTS8388B Specifications Absolute Maximum Ratings Parameter Symbol Comments Value Unit Positive supply voltage VCC GND to 6 V Digital negative supply voltage DVEE GND to -5.7 V Digital positive supply voltage VPLUSD GND - 0.3 to 2.8 V VEE GND to -6 V DVEE to VEE 0.3 V VIN or VINB -1 to 1 V VIN - VINB -2 to 2 V Negative supply voltage Maximum difference between negative supply voltages Analog input voltages Maximum difference between VIN and VINB Digital input voltage VD GORB -0.3 to VCC 0.3 V Digital output current IO Conditions: -3V < VOUT < 0.5 V 20 mA Digital input voltage VD DRRB VEE -0.3 to 0.9 V Digital output voltage VO VPLUSD -3 to VPLUSD -0.5 V VCLK or VCLKB -3 to 1.5 V VCLK - VCLKB -2 to 2 V Maximum junction temperature TJ 135 C Storage temperature Tstg -65 to 150 C Tleads 300 C Clock input voltage Maximum difference between VCLK and VCLKB Lead temperature (soldering 10 s) Note: Absolute maximum ratings are limiting values, to be applied individually, while other parameters are within specified operating conditions. Long exposure to maximum ratings may affect device reliability. The use of a thermal heat sink is mandatory (MCM fixture). Recommended Conditions of Use Parameter Positive supply voltage Symbol Comments VCC VPLUSD ECL output compatibility VPLUSD LVDS output compatibility Min. Typ. Max. Unit 4.75 5 5.25 V 0 V Positive digital supply voltage Negative supply voltages VEE, DVEE 1.4 2.4 2.6 V -5.25 -5.0 -4.75 V 3 2104A-BDC-09/03 Recommended Conditions of Use (Continued) Parameter Symbol Comments Min. Typ. Max. Unit Differential analog input voltage (full-scale) VIN, VINB VIN - VINB 50 differential or single-ended 113 450 125 500 137 550 mV mVpp PCLK PCLKB 50 single-ended clock input 3 4 10 dBm TJ Civil: "C" grade Industrial: "V" grade Military: "M" grade Clock input power level Operating temperature range 0 to 90 -40 to 105 -55 to 125 C Electrical Operating Characteristics VEE = DVEE = -5 V; VCC = 5 V; VIN - VINB = 500 mVpp full-scale differential input Digital outputs 75 or 50 differentially terminated; TJ (typical) = 70C. Full temperature range: -55C < TJ < 125C Parameter Symbol Temp Test Level Min. Resolution Typ. Max. 8 Unit bits Analog Inputs -125 -125 125 125 mV mV 250 mV mV Full-scale input voltage range (differential mode) (0 V common mode voltage) VIN VINB Full IV Full-scale input voltage range (single-ended input option) VIN VINB Full IV Analog input capacitance (die) CIN IV 0.4 pF Input bias current IIN IV 10 A Input resistance RIN IV 1 M Full power input bandwidth FPBW IV 1.8 GHz Small signal input bandwidth (10% full-scale) SSBW IV 2 GHz -250 0 Clock Inputs ECL or specified clock input power level in dBm Logic compatibility for clock inputs (1) ECL clock inputs voltages (VCLK or VCLKB) Logic 0 voltage Logic 1 voltage Logic 0 current Logic 1 current VIL VIH IIL IIH Full Full Full Full 10 dBm 5 5 dBm into 50 Clock input power level 4 V V A A -1.1 Clock input power level into 50 termination Clock input capacitance (die) -1.5 3 CCLK 4 0.4 pF JTS8388B 2104A-BDC-09/03 JTS8388B Electrical Operating Characteristics (Continued) VEE = DVEE = -5 V; VCC = 5 V; VIN - VINB = 500 mVpp full-scale differential input Digital outputs 75 or 50 differentially terminated; TJ (typical) = 70C. Full temperature range: -55C < TJ < 125C Parameter Symbol Temp Test Level Min. Typ. Max. Unit Digital Outputs Logic compatibility for digital outputs (depending on the value of VPLUSD) (2) ECL or LVDS Differential output voltage swings 75 open transmission lines (ECL Levels) 75 differentially terminated 50 differentially terminated Full IV 1.5 0.7 0.54 1.620 0.825 0.660 V V V -1.54 V V -1.34 V V Output levels (assuming VPLUSD = 0 V) 75 open transmission lines (3) logic 0 voltage logic 1 voltage VOL VOH 25C IV -0.88 -1.62 -0.8 Output levels (assuming VPLUSD = 0 V) 75 differentially terminated (3) Logic 0 voltage Logic 1 voltage VOL VOH 25C IV -1.07 -1.41 -1 Output levels (assuming VPLUSD = 0 V) 50 differentially terminated (3) Logic 0 voltage Logic 1 voltage VOL VOH II -1.2 -1.45 -1.15 -1.32 V V II, IV 4.75 1.4 5 0 2.4 2.6 5.25 V V V 385 115 445 145 mA mA -5 -4.75 V II, IV 165 135 200 180 mA mA II, IV 3.4 4.1 4.1 4.3 W W IV 0.5 25C Power Requirements Positive supply voltage Positive supply current analog digital (ECL) digital (LVDS) VCC VPLUSD analog digital ICC IPLUSD Negative supply voltage Negative supply current Nominal power dissipation Power supply rejection ratio (4) VEE analog digital II, IV Full AIEE DIEE PD PSRR Full IV -5.25 mV/V 5 2104A-BDC-09/03 Electrical Operating Characteristics (Continued) VEE = DVEE = -5 V; VCC = 5 V; VIN - VINB = 500 mVpp full-scale differential input Digital outputs 75 or 50 differentially terminated; TJ (typical) = 70C. Full temperature range: -55C < TJ < 125C Parameter Symbol Temp Test Level DNL Full Min. Typ. Max. Unit I, IV 0.35 0.5 0.6 0.7 LSB LSB I, IV 0.7 0.9 1 1.2 LSB LSB DC Accuracy Differential non-linearity (4)(5) Integral non-linearity (4)(5) No missing codes INL (5) Full Full Guaranteed over specified temperature range Full I IV -10 -11 -2 -2 10 11 % Fs % Fs Full IV 100 125 150 ppm/C Full I IV -26 -30 -5 -5 26 30 mV mV Full IV 10-13 Error/ sample TS IV 0.5 ns ORT IV 0.5 ns Gain error Gain error drift Input offset voltage Transient Performance Bit error rate (4)(6) Fs = 1 Gsps Fin = 143 MHz ADC settling time (4) VIn - VinB = 400 mVpp Overvoltage recovery time (4) 6 BER JTS8388B 2104A-BDC-09/03 JTS8388B Electrical Operating Characteristics (Continued) VEE = DVEE = -5 V; VCC = 5 V; VIN - VINB = 500 mVpp full-scale differential input Digital outputs 75 or 50 differentially terminated; TJ (typical) = 70C. Full temperature range: -55C < TJ < 125C Parameter Symbol Temp Test Level Min. Typ. Max. Unit AC Performance Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), binary output data format, TJ = 70C, unless otherwise specified. Signal to noise and distortion ratio (4) Fs = 1 Gsps Fin = 20 MHz Fs = 1 Gsps Fin = 500 MHz Fs = 1 Gsps Fin = 1000 MHz (-1 dBFs) SINAD Full IV 43 42 40 45 44 42 dB dB dB IV 7.0 6.6 6.2 7.2 6.8 6.4 Bits Bits Bits IV 42 41 41 45 44 44 dB dB dB (4) Effective number of bits Fs = 1 Gsps Fin = 20 MHz Fs = 1 Gsps Fin = 500 MHz Fs = 1 Gsps Fin = 1000 MHz (-1 dBFs) ENOB Full (4) Signal to noise ratio Fs = 1 Gsps Fin = 20 MHz Fs = 1 Gsps Fin = 500 MHz Fs = 1 Gsps Fin = 1000 MHz (-1 dBFs) SNR Full (4) Total harmonic distortion Fs = 1 Gsps Fin = 20 MHz Fs = 1 Gsps Fin = 500 MHz Fs = 1 Gsps Fin = 1000 MHz (-1 dBFs) THD Full IV -54 -50 -46 -50 -46 -42 dBc dBc dBc -52 -47 -42 -45 dBc dBc dBc dBc -47 dBc (4) Spurious free dynamic range Fs = 1 Gsps Fin = 20 MHz Fs = 1 Gsps Fin = 500 MHz Fs = 1 Gsps Fin = 1000 MHz (-1 dBFs) Fs = 1 Gsps Fin = 1000 MHz (-3 dBFs) Two tone intermodulation distortion FIN1 = 489 MHz at Fs = 1 Gsps FIN2 = 490 MHz at Fs = 1 Gsps SFDR Full IV -57 -52 -47 -50 IMD Full IV -53 (4) 7 2104A-BDC-09/03 Electrical Operating Characteristics (Continued) VEE = DVEE = -5 V; VCC = 5 V; VIN - VINB = 500 mVpp full-scale differential input Digital outputs 75 or 50 differentially terminated; TJ (typical) = 70C. Full temperature range: -55C < TJ < 125C Parameter Symbol Temp Test Level Min. Typ. Max. Unit Switching Performance and Characteristics - See Figures 2 and 3 on page 9 Maximum clock frequency (binary output coding) Fs 1 1.4 Gsps Maximum clock frequency (Gray output coding) Fs 1 1.9 Gsps Minimum clock frequency Fs IV Minimum clock pulse width (high) TC1 IV 0.285 0.500 50 ns Minimum clock pulse width (low) TC2 IV 0.350 0.500 50 ns (4) TA IV 100 250 400 ps Jitter IV 0.4 0.6 ps (rms) Aperture delay Aperture uncertainty (4)(7) Data output delay (3)(4)(9)(10) Output rise/fall time for data (20% - 80%) (9) Output rise/fall time for data ready (20% - 80%) Data ready output delay (4)(8)(9)(10) (9) Full IV 1150 1360 1660 ps TR/TF Full IV 250 350 550 ps TR/TF Full IV 250 350 550 ps TDR Full IV 1110 1320 1620 ps 720 1000 ps 40 40 40 ps 460 460 460 ps TRDR (11) TODTDR See timing diagram at 1 Gsps TD1 Data pipeline delay TPD 8 Msps TOD Data ready reset relay Notes: 10 Full IV IV 4 Clock cycles 1. The clock inputs may be indifferently entered in differential or single-ended mode, using ECL levels or 4 dBm typical power level into the 50 termination resistor of the in-phase clock input. (4 dBm into 50 clock input correspond to 10 dBm power level for the clock generator). 2. Differential output buffers are internally loaded by 75 W resistors. Buffer bias current = 11 mA 3. Specified loading conditions for digital outputs: * 50 or 75 W controlled impedance traces properly 50/75 W terminated, or unterminated 75 W controlled impedance traces. * Controlled impedance traces far-end loaded by 1 standard ECLinPS register from Motorola(R) (e.g.: 10E452) (typical input parasitic capacitance of 1.5 pF including package and ESD protections). 4. See "Definitions of Terms" on page 28. 5. Histogram testing based on sampling of a 10 MHz sinewave at 50 Msps 6. Output error amplitude < 4 LSB around worst code 7. Maximum jitter value obtained for single-ended clock input 8. At 1 Gsps, 50/50 clock duty cycle, TC2 = 500 ps (TC1). TDR - TOD = -100 ps (typ) does not depend on the sampling rate. 9. Termination load parasitic capacitance derating values: * 50 or 75 W controlled impedance traces properly 50 /75 W terminated: 60 ps / pF or 75 ps per additional ECLinPS load. * Unterminated (source terminated) 75W controlled impedance lines: 100 ps / pF or 150 ps per additional ECLinPS termination load. 10. Apply proper 50/75 W impedance traces propagation time derating values: 6 ps / mm (155 ps/inch) for TSEV8388B Evaluation Board. 11. Values for TOD and TDR track each other over temperature (1 percent variation for TOD - TDR per 100 degrees Celsius temperature variation). Therefore, TOD - TDR variation over temperature is negligible. Moreover, the internal (on-chip) and package skews between each Data TOD and TDR effect can be considered negligible. Consequently, minimum values for TOD and TDR are never more than 100 ps apart. The same is true for the TOD and TDR maximum values. See "Applying the JTS8388B" on page 30. JTS8388B 2104A-BDC-09/03 JTS8388B Figure 2. JTS8388B Timing Diagram (1 Gsps Clock Rate) Data Ready Reset, Clock Held at LOW Level TA= 250 ps (VIN, VINB) X N X N-1 X N+5 X N+4 X N+3 X N+2 X N+1 TC=1000 ps TC1 TC2 (CLK, CLKB) TPD: 4.0 Clock periods 1360 ps DIGITAL OUTPUTS DATA N- 5 1000 ps DATA N-4 TO D = 3160 ps DATA N-3 DATA N-2 DATA N-1 DATA N TD1=TC1 + TDR -TOD = TC1-40 ps = 460 ps TDR = 1320 ps TDR = 1320 ps DATA N+1 DATA READY (DR, DRB) TD2 = TC2 + TOD-TDR = TC2 + 40 ps = 540 ps TRDR=720 ps DRRB 1 ns (min) Figure 3. JTS8388B Timing Diagram (1 Gsps Clock Rate) Data Ready Reset, Clock held at HIGH Level TA= 250 ps (VIN, VINB) X N X N-1 X N+1 X N+2 X N+5 X N+4 X N+3 TC=1000 ps TC1 TC2 (CLK, CLKB) DIGITAL OUTPUTS TOD = 1360 ps TPD: 4.0 Clock periods 1360 ps DATA N-5 1000 ps DATA N-4 TDR = 1320 ps TDR = 1320 ps DATA N-3 DATA N-2 DATA N-1 DATA N DATA N+1 TD1=TC1 + TDR-TOD = TC1 - 40 ps = 460 ps DATA READY (DR, DRB) TRDR=720 ps TD2 = TC2 + TOD-TDR = TC2 + 40 ps = 540 ps DRRB 1ns (min) 9 2104A-BDC-09/03 Table 1. Explanation of Test Levels Level Description D 100% wafer tested at 25 C(2) I 100% production tested at 25 C(2) (for packaged device) II 100% production tested at 25 C(2), and sample tested at specified temperatures III Sample tested only at specified temperatures IV Parameter is guaranteed by design and characterization testing (thermal steady-state conditions at specified temperature) V Parameter is a typical value only VI 100% production tested over specified temperature range Notes: 1. Only min. and max. values are guaranteed (typical values issue from characterization results) 2. Unless otherwise specified, all tests are pulsed tests: therefore TJ = TC = TA Table 2. Wafer Screening JTS8388B chip Parameter Temperature Min. Max. Unit 0.6 LSB 1 LSB DC accuracy at 50 Mpsps/10 MHz DNL 25 C(1) INL No missing codes Guaranteed AC performance TBD 25 C(1) SNR ENOB Note: 10 45 dB 7.1 bit 1. Unless otherwise specified, all tests are pulsed tests: therefore TJ = TC = TA JTS8388B 2104A-BDC-09/03 JTS8388B Functions Description Name Function VCC Positive power supply VEE Analog negative power supply VPLUSD Digital positive power supply GND Ground VIN, VINB Differential analog inputs CLK, CLKB Differential clock inputs VCC = 5 V VPLUSD = 0 V (ECL) VPLUSD= 2.4 V (LVDS) OR VIN ORB VINB CLK <D0:D7> <D0B:D7B> Differential output data port CLKB DR; DRB Differential data ready outputs GAIN OR; ORB Out-of-range outputs GORB GAIN ADC gain adjust DIOD/ DRRB GORB Gray or binary digital output select DIOD/DRRB Die junction temp. measurement/ asynchronous data ready reset JTS8388B D0 D7 D0B D7B 16 DR DRB DVEE= -5 V VEE= -5 V GND Table 3. Digital Coding NRZ (Non Return to Zero) mode, ideal coding: does not include gain, offset, and linearity voltage errors. Digital Output Binary GORB = VCC or floating Gray GORB = GND Out of Range > Positive full-scale + 1/2 LSB 11111111 10000000 1 251 mV 249 mV Positive full-scale + 1/2 LSB Positive full-scale - 1/2 LSB 11111111 11111110 10000000 10000001 0 0 126 mV 124 mV Positive 1/2 scale + 1/2 LSB Positive1/2 scale - 1/2 LSB 11000000 10111111 10100000 11100000 0 0 1 mV -1 mV Bipolar zero + 1/2 LSB Bipolar zero - 1/2 LSB 10000000 01111111 11000000 01000000 0 0 -124 mV -126 mV Negative 1/2 scale + 1/2 LSB Negative 1/2 scale - 1/2 LSB 01000000 00111111 01100000 00100000 0 0 -249 mV -251 mV Negative full-scale + 1/2 LSB Negative full-scale - 1/2 LSB 00000001 00000000 00000001 00000000 0 0 < -251 mV < Negative full-scale - 1/2 LSB 00000000 00000000 1 Differential Analog Input Voltage Level > 251 mV 11 2104A-BDC-09/03 Chip Description Table 4. JTS8388B Chip Functions Description Symbol Pad Number Function GND 20, 24, 26, 28, 33, 35, 37 Analog ground Pads n20, 24, 26, 28, 37 are double Pads n 26, 33, 35 are single 14 bonding wires are available for analog ground access VPLUSD 1, 11 Digital positive supply (0 V for ECL compatibility, 2.4 V for LVDS compatibility). 2 double pads VCC 19, 21, 23, 30, 39, 40 5 V analog supply VEE 22, 29, 31 -5 V analog supply DVEE 6 -5 V digital supply VIN 34 In-phase (+) analog input signal of the differential Sample & Hold preamplifier VINB 36 Inverted phase (-) analog input signal CLK 25 In-phase (+) ECL clock input CLKB 27 Inverted phase (-) ECL clock input D0, D1, D2, D3, D4, D5, D6, D7 16, 14, 12, 9, 4, 2, 45, 43 In-phase (+) digital outputs D0 is the LSB. D7 is the MSB D0B, D1B, D2B, D3B, D4B, D5B, D6B, D7B 17, 15, 13, 10, 5, 3, 46, 44 Inverted phase (-) digital outputs. D0B is the inverted LSB. D7B is the inverted MSB OR 41 In-phase (+) out-of-range output Out-of-range goes high on the leading edge of code 0 or code 256 ORB 42 Inverted phase (-) out-of-range output DR 7 In-phase (+) output of Data Ready signal DRB 8 Inverted phase (-) output of Data Ready signal GORB 18 Gray or binary select output format control pad * Binary output format if GORB is floating or tied at VCC * Gray output format if GORB is connected to ground (0 V) GAIN 38 ADC gain adjust pad DIOD/DRRB 32 DIOD: die junction temperature measurement pad Can be left floating or grounded if not used DRRB: asynchronous data ready reset function 12 JTS8388B 2104A-BDC-09/03 JTS8388B J Table 5. JTS8388B Chip Pad List, Coordinates and Corresponding Functions Pad Number PosX PosY Chip Pad Function 1 880 1365 VPLUSD Positive digital supply 2 670 1365 D5 In-phase (+) digital output, bit 5 (D7 is the MSB: Bit 7, D0 is the LSB: Bit 0) 3 510 1365 D5B Inverted phase (-) digital output, bit 5 4 350 1365 D4 In-phase (+) digital output, bit 4 5 190 1365 D4B Inverted phase (-) digital output, bit 4 6 -20 1365 DVEE -5 V digital supply 7 -230 1365 DR In-phase (+) data ready 8 -390 1365 DRB Inverted Phase (-) data ready 9 -550 1365 D3 In-phase (+) digital output, bit 3 10 -710 1365 D3B Inverted phase (-) digital output, bit 3 11 -920 1365 VPLUSD Positive digital supply 12 -1085 1115 D2 In-phase (+) digital output, bit 2 13 -1085 955 D2B Inverted phase (-) digital output, bit 2 14 -1085 795 D1 In-phase (+) digital output, bit 1 15 -1085 635 D1B Inverted phase (-) digital output, bit 1 16 -1085 475 D0 In-phase (+) digital output, bit 0, least significant bit 17 -1085 315 D0B Inverted phase (-) digital output, bit 0, least significant bit 18 -1085 155 GORB Gray or binary data output format select 19 -1085 -55 VCC 5 V supply double pad 20 -1085 -325 GND Analog ground double pad 21 -1085 -595 VCC 5 V supply double pad 22 -1085 -865 VEE -5 V analog supply double pad 23 -1085 -1135 VCC 5 V supply double pad 24 -905 -1365 GND Analog ground double pad 25 -655 -1365 CLK In-phase (+) clock input double pad 26 -455 -1365 GND Analog ground 27 -255 -1365 CLKB Inverted phase (-) clock input double pad 28 -5 -1365 GND Analog ground double pad 29 245 -1365 VEE -5 V analog supply double pad 30 495 -1365 VCC 5 V supply double pad 31 745 -1365 VEE -5 V analog supply double pad 32 945 -1365 DIOD/DRRB Diode input for TJ monitoring / input for asynchronous data ready reset 33 1085 -1195 GND Analog ground 34 1085 -995 VIN In-phase (+) analog input 35 1085 -795 GND Analog ground double pad (3) double pad double pad (3) (2) double pad 13 2104A-BDC-09/03 Table 5. JTS8388B Chip Pad List, Coordinates and Corresponding Functions (Continued) Pad Number PosX PosY Chip Pad Function 36 1085 -595 VINB Inverted phase (-) analog input double pad 37 1085 -345 GND Analog ground double pad 38 1085 -145 GAIN ADC gain adjust input 39 1085 55 VCC 5 V supply 40 1085 265 VCC 5 V supply 41 1085 425 OR In-phase (+) out-of-range digital output 42 1085 585 ORB Inverted phase (-) out-of-range digital output 43 1085 745 D7 In-phase (+) digital output, bit 7, most significant bit 44 1085 905 D7B Inverted phase (-) digital output, bit 7 45 1085 1065 D6 In-phase (+) digital output, bit 6 46 1085 1225 D6B Inverted phase (-) digital output, bit 6 Note: double pad 1. Coordinates are relative to pad centers. The coordinates origin (0, 0) is at the center of the die. All dimensions are given in microns. Pad 1 is one pointed at by the arrow in Figure 4 on page 15 Distance between pad (glass window) and inner edge of seaf-ring: 40 m. Die size (inner edge of seal-ring: (-1175, -1455) (1175, 1455). Die size (including scribe line): (-1230, -1510) (1230, 1510) (2.46 x 3.02 mm2). Actual die size (after separation): (-1220, -1500) (1220, 1500) (2.44 mm x 3.00 mm). 2. GORB tied to VCC or floating: binary output data format. GORB tied to GND: gray output data format. 3. The common mode level of the output buffers is 1.2 V below the positive digital supply. For ECL compatibility the positive digital supply must be set at 0 V (ground). For LVDS compatibility (output common mode at 1.2 V) the positive digital supply must be set at 2.4 V. If the subsequent LVDS circuitry can withstand a lower level for input common mode, it is recommended to lower the positive digital supply level in the same proportion in order to spare power dissipation. 14 JTS8388B 2104A-BDC-09/03 JTS8388B Figure 4. JTS8388B Chip Pads Designation Die size: 2.44 x 3.00 mm (after separation); die area: 7.32 mm2 11 VPLUSD 10 9 8 D3B D3 DRB 7 DR 6 DVEE 5 4 D4B D4 3 2 1 D5B D5 VPLUSD 46 D6B 12 45 D2 D6 13 44 D2B D7B 14 43 D1 D7 15 42 D1B ORB 16 41 D0 OR 17 40 D0B VCC 18 GORB 39 VCC 19 VCC 38 GAIN 20 37 GND GND 21 36 VCC VINB 35 GND 22 VEE 34 VIN 23 33 VCC GND GND 24 CLK 25 GND 26 CLKB 27 GND 28 VEE 29 VCC 30 VEE 31 DIOD/DRRB 32 15 2104A-BDC-09/03 Table 6. Die Mechanical Information Mask Reference Description VH25B rev B Die size Between scribe line axis After separation 2.46 mm x 3.02 mm 2.44 mm x 3.00 mm Pad size (single pad) (double pad) 100 m x 100 m 200 m x 100 m Die thickness 380 m 20 m Back side metallization None Metallization Number of layers Material Diffusion barrier Thickness 3 Ti/TiN Al-Si-Cu TiN (on top) Ti/TiN Metal 1: 600 nm; Metal 2 & Metal 3: 800 nm Pad metallization(1)(2) Ti/TiN Al-Si-Cu TiN (Metal 2) Ti/TiN Al-Si-Cu (Metal 3) Passivation Oxide/Nitride (SiO2/SiN2): 300 nm / 550 nm Back side potential -5 V Die transistor count 4450 Die attach Epoxy Ag filled high conductivity glue Bond wire Al or Au 30 m diameter Qualification package CQFP68 (with restriction on electrical performance) Notes: 16 1. The top TiN layer is etched in one step together with the passivation layer. 2. The pad is a sandwich of Metal 2 and Metal 3 over field oxyde. JTS8388B 2104A-BDC-09/03 JTS8388B Typical Characterization Results Static Linearity Fs = 50 Msps; Fin = 10 MHz Figure 5. Integral Non-linearity Clock frequency = 50 Msps Positive peak: 0.78 LSB Signal frequency = 10 MHz Negative peak: -0.73 LSB Figure 6. Differential Non-linearity Clock frequency = 50 Msps Positive peak: 0.3 LSB Signal frequency = 10 MHz Negative peak: -0.39 LSB 17 2104A-BDC-09/03 Effective Number of Bits Versus Power Supplies Variation Figure 7. Effective Number of Bits (ENOB) = f (VEEA); Fs = 500 Msps; Fin = 100 MHz 8 7 ENOB 6 5 4 3 2 -7 -6.5 -6.0 -5.5 -5.0 -4.5 -4.0 VEEA (V) Figure 8. Effective Number of Bits = (ENOB) f (VCC); Fs = 500 Msps; Fin = 100 MHz 8 7 ENOB 6 5 4 3 2 3 4 5 6 7 VCC (V) 18 JTS8388B 2104A-BDC-09/03 JTS8388B Typical FFT Results Figure 9. Fs = 1 Gsps; Fin = 20 MHz Figure 10. Fs = 1 Gsps; Fin = 495 MHz Figure 11. Fs = 1 Gsps; Fin = 995 MHz; -3 dB Full-scale Input 19 2104A-BDC-09/03 Spurious Free Dynamic Range Versus Input Amplitude Sampling frequency Fs = 1 Gsps; Input frequency Fin = 995 MHz; Gray or binary output coding Figure 12. Reconstructed Signal and Signal Spectrum at Fs = 1 Gsps, Fin = 995 MHz, Full-scale Full Scale ENOB = 6.7 SINAD = 41.5 dB SNR = 44.8 dB THD = -44.4 dBc SFDR = -45 dBc Figure 13. Reconstructed Signal and Signal Spectrum at Fs = 1 Gsps, Fin = 995 MHz, -3 dB Full-scale -3 dB Full Scale ENOB = 6.7 20 SINAD = 41.5 dB SNR = 44.8 dB THD = -44.4 dBc SFDR = -45 dBc JTS8388B 2104A-BDC-09/03 JTS8388B Dynamic Performance Versus Analog Input Frequency Fs = 1 Gsps; Fin = 0 up to 1800 MHz; full-scale input (Fs); Fs -3 dB, Fs -10 dB Clock duty cycle 50/50, binary/gray output coding, fully differential or single-ended analog and clock inputs Figure 14. ENOB Versus Analog Input Frequency 8 ENOB (dB) 7 10 dB FS 6 -3 dB FS 5 FS 4 3 0 200 400 600 800 1000 1200 1400 1600 1800 Input Frequency (MHz) Figure 15. SNR Versus Analog Input Frequency 50 48 46 44 FS SNR (dB) 42 40 -3 dB FS 38 36 -10 dB FS 34 32 30 0 200 400 600 800 1000 1200 1400 1600 1800 Input Frequency (MHz) Figure 16. SFDR Versus Analog Input Frequency -20 -25 FS SFDR (dBc) -30 -35 -3 dB FS -40 -45 -10 dB FS -50 -55 -60 0 200 400 600 800 1000 1200 1400 1600 1800 2000 Input Frequency (MHz) 21 2104A-BDC-09/03 Figure 17. ENOB Versus Sampling Frequency Analog input frequency: Fin = 500 MHz and Nyquist conditions (Fin = Fs/2) Clock duty cycle 50/50, binary output coding 8 Fin = Fs/2 (ENOB) Effective Number of Bits 7 Fin = 500 MHz 6 5 4 3 2 0 100 200 300 400 500 600 700 800 900 1000110012001300140015001600 Sampling Frequency (Msps ) Figure 18. SFDR Versus Sampling Frequency Analog input frequency: Fin = 500 MHz and Nyquist conditions (Fin = Fs/2) Clock duty cycle 50/50, binary output coding -20 -25 SFDR ( dBc ) -30 -35 -40 -45 -50 Fin = Fs/2 -55 Fin = 500 MHz -60 0 100 200 300 400 500 600 700 800 900 1000110012001300140015001600 Sampling Frequency (Msps) 22 JTS8388B 2104A-BDC-09/03 JTS8388B JTS8388B ADC Performances Versus Junction Temperature Figure 19. ENOB Versus Junction Temperature Effective number of bits versus junction temperature Fs = 1 Gsps ; Fin = 500 MHz ; Duty cycle = 50% 8 ENOB (bits) 7 6 5 4 3 -40 -20 0 20 40 60 80 100 120 140 160 o Temperature ( C) Figure 20. SNR Versus Junction Temperature Signal to noise ratio versus junction temperature Fs = 1 Gsps ; Fin = 507 MHz ; differential clock, single-ended analog input (Vin = -1dBFs) 46 SNR (dB) 45 44 43 42 -40 -20 0 20 40 60 80 100 120 140 o Temperature ( C) 23 2104A-BDC-09/03 Figure 21. THD Versus Junction Temperature Total harmonic distorsion versus junction temperature Fs = 1 Gsps ; Fin = 507 MHz ; differential clock, single-ended analog input (Vin = -1dBFs) 53 THD (dB) 51 49 47 45 43 -60 -40 -20 0 20 40 60 80 100 120 140 120 140 160 o Temperature ( C) Figure 22. Power Consumption Versus Junction Temperature Power consumption versus junction temperature Fs = 1 Gsps ; Fin = 500 MHz ; Duty cycle = 50% Power Consumption (W) 5 4 3 2 1 0 -40 -20 0 20 40 60 80 100 o Temperature ( C) 24 JTS8388B 2104A-BDC-09/03 JTS8388B Figure 23. Typical Full Power Input Bandwidth at -3 dB (-2 dBm Full Power Input) 400 0 600 800 1000 Frequency (MHz) 1200 1400 1600 1800 2000 2200 Magnitude (dB) -1 -2 -3 -4 -5 -6 ADC Step Response Test pulse input characteristics: 20% to 80% input full-scale and rise time 200 ps mV Figure 24. Test Pulse Digitized with 20 GHz DSO Vpp ~ 260 mV Tr ~ 240 ps 50 mV/div 500 ps/div Time (ns) 25 2104A-BDC-09/03 Figure 25. Same Test Pulse Digitized with JTS8388B ADC 200 ADC Code 150 Tr ~ 280 ps 50 codes/div (Vpp ~ 260 mV) 500 ps/div 100 ADC calculated rise time : between 150 and 200 ps 50 0 0 Note: 26 0.5 1.0 1.5 2.0 2.5 Time (ns) 3.0 3.5 4.0 4.5 5.0 Ripples are due to the test setup (they are present on both measurements) JTS8388B 2104A-BDC-09/03 JTS8388B Jitter Performance Sampling frequency Fs = 500 Msps; Input frequency Fin = 1900 MHz Figure 26. Single-ended Analog and Clock Inputs 0 -20 Magnitude (dB) -40 -60 -80 -100 -120 0 100 200 Frequency (MHz) Figure 27. Single-ended Analog and Clock Inputs 192 Magnitude (code) Total jitter (including ADC and test setup) = 420 Fs RMS ADC jitter < 400 Fs RMS 128 64 0 Fs 27 2104A-BDC-09/03 Definitions of Terms Table 7. Definitions of Terms Term Description BER Bit Error Rate Probability to exceed a specified error threshold for a sample. An error code is a code that differs by more than 4 LSB from the correct code BW Full-power Input Bandwidth The analog input frequency at which the fundamental component in the digitally reconstructed output has fallen by 3 dB with respect to its low frequency value (determined by FFT analysis) for input at full-scale DG Differential Gain The peak gain variation (in percent) at five different DC levels for an AC signal of 20% fullscale peak to peak amplitude. FIN = 5 MHz (TBC) DNL Differential Nonlinearity The differential non-linearity for an output code (i) is the difference between the measured step size of code (i) and the ideal LSB step size. DNL (i) is expressed in LSBs. DNL is the maximum value of all DNL (i). DNL error specification of less than 1 LSB guarantees that there are no missing output codes and that the transfer function is monotonic DP Differential Phase The peak phase variation (in degrees) at five different DC levels for an AC signal of 20% fullscale peak to peak amplitude. FIN = 5 MHz (TBC) ENOB Effective Number of Bits IMD Inter Modulation Distortion The two tones intermodulation distortion (IMD) rejection is the ratio of either input tone to the worst third order intermodulation products. The input tones levels are at - 7dB full-scale INL Integral Non-linearity The integral non-linearity for an output code (i) is the difference between the measured input voltage at which the transition occurs and the ideal value of this transition. INL (i) is expressed in LSBs, and is the maximum value of all INL (i) JITTER Aperture Uncertainty The sample to sample variation in aperture delay. The voltage error due to jitter depends on the slew rate of the signal at the sampling point Noise Power Ratio The NPR is measured to characterize the ADC's performance in response to broad bandwidth signals. When using a notch-filtered broadband white-noise generator as the input to the ADC under test, the Noise to Power Ratio is defined as the ratio of the average out-of-notch to the average in-notch power spectral density magnitudes for the FFT spectrum of the ADC output sample test. (NRZ) Non Return to Zero When the input signal is larger than the upper bound of the ADC input range, the output code is identical to the maximum code and the out-of-range bit is set to logic one. When the input signal is smaller than the lower bound of the ADC input range, the output code is identical to the minimum code, and the out-of-range bit is set to logic one (it is assumed that the input signal amplitude remains within the absolute maximum ratings) ORT Overvoltage Recovery Time Time to recover 0.2% accuracy at the output, after a 150% full-scale step applied on the input is reduced to midscale PSRR Power Supply Rejection Ratio PSRR is the ratio of input offset variation to a change in power supply voltage Spurious Free Dynamic Range The ratio expressed in dB of the RMS signal amplitude, set at 1 dB below full-scale, to the RMS value of the next highest spectral component (peak spurious spectral component). SFDR is the key parameter for selecting a converter to be used in a frequency domain application (radar systems, digital receiver, network analyzer...). It may be reported in dBc (i.e., degrades as signal level is lowered), or in dBFS (i.e. always related back to converter full-scale) NPR SFDR 28 A SINAD - 1.76 + 20 log ----------V 2ENOB = -------------------------------------------------------------------6.02 Where A is the actual input amplitude and V is the full-scale range of the ADC under test JTS8388B 2104A-BDC-09/03 JTS8388B Definitions of Terms Table 7. Definitions of Terms (Continued) SINAD Signal to Noise and Distortion Ratio The ratio expressed in dB of the RMS signal amplitude, set to 1 dB below full-scale, to the RMS sum of all other spectral components, including the harmonics except DC SNR Signal to Noise Ratio The ratio expressed in dB of the RMS signal amplitude, set to 1 dB below full-scale, to the RMS sum of all other spectral components excluding the five first harmonics TA Aperture Delay The delay between the rising edge of the differential clock inputs (CLK,CLKB) (zero crossing point), and the time at which (VIN, VINB) is sampled TC Encoding Clock Period TC1 = minimum clock pulse width (high) TC = TC1 + TC2 TC2 = minimum clock pulse width (low) TD1 Time Delay from Data to Data Ready TD1 is the time difference between Data to Data ready TD2 Time Delay from Data Ready to Data General expression is TD1 = TC1 + TDR - TOD with TC = TC1 + TC2 = 1 encoding clock period TF Fall Time Time delay for the output data signals to fall from 80% to 20% of delta between the low level and high level THD Total Harmonic Distortion The ratio expressed in dBc of the RMS sum of the first five harmonic components, to the RMS value of the measured fundamental spectral component TOD Digital Data Output Delay The delay from the falling edge of the differential clock inputs (CLK, CLKB) (zero crossing point) to the next point of change in the differential output data (zero crossing) with a specified load TPD Pipeline Delay The number of clock cycles between the sampling edge of an input data and the associated output data being made available (not taking in account the TOD). For the JTS8388B the TPD is 4 clock periods TR Rise Time Time delay for the output data signals to rise from 20% to 80% of delta between the low level and high level TRDR Data Ready Reset Delay Delay between the falling edge of the Data Ready output asynchronous Reset signal (DDRB) and the reset to digital zero transition of the Data Ready output signal (DR) TS Settling Time Time delay to achieve 0.2% accuracy at the converter output when an 80% full-scale step function is applied to the differential analog input 29 2104A-BDC-09/03 Applying the JTS8388B Timing Information Timing Values for JTS8388B Timing values are given at chip inputs/outputs, taking into account pad and ESD protection capacitance, 2 mm (30 um diameter) bonding wire per pad, and specified termination loads. Propagation delays in 50/75 impedance traces are not taken into account for TOD and TDR. Apply proper derating values corresponding to termination topology. The min/max timing values are valid over the full temperature range in the following conditions: Propagation Time Considerations * Specified termination load (differential output Data and Data Ready): 50 resistor in parallel with 1 standard ECLinPS register from Motorola(R) (e.g. 10E452). Typical ECLinPS inputs show a typical input capacitance of 1.5 pF (including package and ESD protections). When addressing an output DMUX, if some digital outputs do not have the same termination load, apply the corresponding derating value given below. * Output termination load derating values for TOD and TDR: ~ 60 ps/pF or 75 ps per additional ECLinPS load. * Propagation time delay derating values also have to be applied for TOD and TDR: ~6 ps/mm (155 ps/inch) for the TSEV8388B Evaluation Board. Apply the proper time delay derating value if a different dielectric layer is used. TOD and TDR timing values are given from pad to pad and do not include the additional propagation times between die pads and input/output termination loads. For the TSEV8388B Chip Evaluation Board, the propagation time delay is 6 ps/mm (155 ps/inch) corresponding to 3.4 (at 10 GHz) dielectric constant of the RO4003 used for the board. If a different dielectric layer is used (for instance teflon), use appropriate propagation time values. TD does not depend on propagation times because it is a differential data (TD is the time difference between Data Ready output delay and digital data output delay). TD is also the most straightforward data to measure, again because it is differential: TD can be measured directly onto termination loads, with matched oscilloscope probes. TOD - TDR Variation Over Temperature Values for TOD and TDR track each other over temperature (1 percent variation for TOD - TDR per 100 degrees celsius temperature variation). Therefore, TOD - TDR variation over temperature is negligible. Moreover, the internal (onchip) and package skews between each data TOD and TDR effect can be considered negligible. Consequently, minimum values for TOD and TDR are never more than 100 ps apart. The same is true for the TOD and TDR maximum values. In other words: 30 * If TOD is at 950 ps, TDR will not be at 1420 ps (maximum time delay for TDR) * If TOD is at 1460 ps, TDR will not be at 910 ps (minimum time delay for TDR) However, external TOD - TDR values may be dictated by total digital data skews between each TOD (each digital data) and TDR: MCM board, bonding wires and differences in output line lengths, and mismatches in output termination impedance. JTS8388B 2104A-BDC-09/03 JTS8388B The external (on board) skew effect has not been taken into account for the specification of the minimum and maximum values for TOD-TDR. Principle of Operation The analog input is sampled on the rising edge of the external clock input (CLK,CLKB) after a TA (aperture delay) of typically 250 ps. The digitized data is available after 4 clock periods latency (pipeline delay (TPD)), on the clock's rising edge, after 1160 ps typical propagation delay TOD. The Data Ready differential output signal frequency (DR, DRB) is half the external clock frequency, that is it switches at the same rate as the digital outputs. The Data Ready output signal (DR, DRB) switches on the external clock's falling edge after a propagation delay TDR of typically 1120 ps. A Master Asynchronous Reset input command DRRB (ECL-compatible single-ended input) is available for initializing the differential Data Ready output signal (DR, DRB). This feature is mandatory in certain applications using interleaved ADCs or using a single ADC with demultiplexed outputs. Without Data Ready signal initialization, it is impossible to store the output digital data in a defined order. Principle of Data Ready Signal Control by DRRB Input Command Data Ready Output Signal Reset The Data Ready signal is reset on the falling edge of the DRRB input command, on the ECL logical low level (-1.8 V). DRRB may also be tied to VEE = -5 V for Data Ready output signal Master Reset. As long as DRRB remains at a logical low level, (or tied to VEE = -5 V), the Data Ready output remains at a logical zero and is independent of the external free-running encoding clock. The Data Ready output signal (DR, DRB) is reset to logical zero after TRDR = 720 ps typical. TRDR is measured between the -1.3 V point of the falling edge of the DRRB input command and the zero crossing point of the differential Data Ready output signal (DR, DRB). The Data Ready Reset command may be a pulse of 1 ns minimum time width. Data Ready Output Signal Restart The Data Ready output signal restarts on the DRRB command's rising edge, ECL logical high levels (-0.8 V). DRRB may also be grounded, or may be allowed to float, for a normal free-running Data Ready output signal. The Data Ready signal restart sequence depends on the logical level of the external encoding clock, at a DRRB rising edge instant. * The DRRB rising edge occurs when the external encoding clock input (CLK,CLKB) is LOW: The Data Ready output's first rising edge occurs after half a clock period on the clock falling edge, after a delay time TDR = 1120 ps already defined above. * The DRRB rising edge occurs when the external encoding clock input (CLK,CLKB) is HIGH: 31 2104A-BDC-09/03 The Data Ready output's first rising edge occurs after one clock period on the clock falling edge, and a delay TDR = 1120 ps. Consequently, as the analog input is sampled on the clock's rising edge, the first digitized data corresponding to the first acquisition (N) after a Data Ready signal restart (rising edge) is always strobed by the third rising edge of the Data Ready signal. The time delay (TD1) is specified between the last point of a change in the differential output data (zero crossing point) to the rising or falling edge of the differential Data Ready signal (DR, DRB) (zero crossing point). Analog Inputs (VIN) (VINB) * For normal initialization of the Data Ready output signal, the external encoding clock signal frequency and level must be controlled. The minimum encoding clock sampling rate for the ADC is 10 Msps and consequently the clock cannot be stopped. * One single pad is used for both the DRRB input command and die junction temperature monitoring. The pad denomination will be DRRB/DIOD (on the former version the denomination was DIOD). * Temperature monitoring and Data Ready control by DRRB is not possible simultaneously. The analog input full-scale range is 0.5 V (Vpp), or -2 dBm into the 50 termination resistor. In the differential mode input configuration, that means 0.25 V on each input, or 125 mV around 0 V. The input common mode is ground. The typical input capacitance is 0.4 pF in die form (JTS8388B), not taking into account the bond wires capacitance. The input capacitance is mainly due to the pad capacitance, as the ESD protections are not connected (but present) on the inputs. Figure 28. Differential Inputs Voltage Span [mV] VIN 125 500 mV Full-scale Analog Input 250 mV VINB -250 mV -125 0V t (VIN, VINB) = 250 mV = 500 mV diff Differential Versus SingleThe JTS8388B can operate at full speed without any performance degradation in either ended Analog Input Operation a differential or single-ended configuration. This is explained by the fact that the ADC uses a high-input impedance differential preamplifier stage, (preceding the Sample and Hold stage), which has been designed in order to be entered either in differential or single-ended mode. This is true so long as the out-of-phase analog input pad VINB is 50 terminated very closely to one of the neighboring shield ground pads (33, 35, 37), which constitute the local ground reference for the in-phase analog input pad (VIN). 32 JTS8388B 2104A-BDC-09/03 JTS8388B Thus, the differential analog input preamplifier will fully reject the local ground noise (and any capacitively and inductively coupled noise) as common mode effects. In a typical single-ended configuration, enter on the (VIN) input pad, with the inverted phase input pad (VINB) grounded through the 50 termination resistor. In a single-ended input configuration, the in-phase input amplitude is 0.5 V, centered on 0 V (or -2 dBm into 50 ). The inverted phase input is at ground potential through the 50 termination resistor. Figure 29. Typical Single Ended Analog Input Configuration [mV] VIN or VINB double pad (pins 54, 55 or 56, 57) VIN 250 500 mV Full-scale Analog Input VIN or VINB 500 mV VINB = 0 V VINB -250 50 (on package) 1M 3 pF t VIN = 250 mV = 500 mV diff Clock Inputs (CLK) (CLKB) 50 Reverse Termination The JTS8388B can be clocked at full speed without noticeable performance degradation in either the differential or single-ended configuration. This is explained by the fact the ADC uses a differential preamplifier stage for the clock buffer, which has been designed to be entered either in a differential or single-ended mode. Single-ended Clock Input (Ground Common Mode) Although the clock inputs were intended to be driven differentially with nominal -0.8 V/-1.8 V ECL levels, the JTS8388B clock buffer can manage a single-ended sinewave clock signal centered around 0 V. This is the most convenient clock input configuration as it does not require the use of a power splitter. No performance degradation (e.g. due to timing jitters) is observed in this particular single-ended configuration up to 1.2 Gsps Nyquist conditions (Fin = 600 MHz). This is true so long as the inverted phase clock input pad is 50 terminated very closely to one of the neighboring shield ground pads, which constitutes the local ground reference for the in-phase clock input. Thus, the JTS8388B differential clock input buffer will fully reject the local ground noise (and any capacitively and inductively coupled noise) as common mode effects. Moreover, a very low-phase noise sinewave generator must be used for enhanced jitter performance. The typical in-phase clock input amplitude is 1 V, centered on a 0 V (ground) common mode. This corresponds to a typical clock input power level of 4 dBm into the 50 termination resistor. Do not exceed 10 dBm to avoid saturation of the preamplifier input transistors. The inverted phase clock input is grounded through the 50 termination resistor. 33 2104A-BDC-09/03 Figure 30. Single-ended Clock Input (Ground Common Mode) VLCLK common mode = 0 V; VCLKB = 0 V; 4 dBm typical clock input power level (into 50 termination resistor CLK or CLKB double pad (pins 37, 38 or 39, 40) [V] 0.5 V VCLK CLK or CLKB VCLK = 0 V 1M 50 (on package) 0.4 pF VCLK -0.5 V Note: t 50 reverse termination Do not exceed 10 dBm into the 50 termination resistor for single clock input power level. Differential ECL Clock Input The clock inputs can be driven differentially with nominal -0.8 V/-1.8 V ECL levels. In this mode, a low-phase noise sinewave generator can be used to drive the clock inputs, followed by a power splitter (hybrid junction) in order to obtain 180 degrees outof-phase sinewave signals. Biasing tees can be used for offsetting the common mode voltage to ECL levels. Note: As the biasing tees propagation times are not matching, a tunable delay line is required in order to ensure the signals are 180 degrees out-of-phase especially at fast clock rates in the Gsps range. Figure 31. Differential Clock Inputs (ECL Levels) [mV] -0.8 V CLK or CLKB double pad (pins 37, 38 or 39, 40) VCLK VCLKB CLK or CLKB Common mode = -1.3 V 1M 50 (on package) 0.4 pF -2 V -1.8 V 34 t 50 reverse termination JTS8388B 2104A-BDC-09/03 JTS8388B Single Ended ECL Clock Input In a single-ended configuration enter on the CLK (resp. CLKB) pad, with the inverted phase clock input pad CLKB (respectively CLK) connected to -1.3 V through the 50 termination resistor. The in-phase input amplitude is 1 V, centered on a -1.3 V common mode. Figure 32. Single-ended Clock Input (ECL) [V] VCLK -0.8 V VCLKB = -1.3 V -1.8 V t VCLK common mode = -1.3 V, VCLKB = -1.3 V Clock Signal Duty Cycle Adjust At fast sampling rates, (1 Gsps and above), the device performance (especially the SNR) can be improved by tuning the clock duty cycle (CLK, CLKB). In a single-ended configuration, when using a sinewave clock generator, the clock signal duty cycle can be easily adjusted by simply offsetting the in-phase clock signal using a biasing tee, (as the out of phase clock input is at ground level). Figure 33. Single-ended Clock Input (In-phase Clock Input Common Mode Shifted) [V] 0.5 V VCLK = 180 mV VCLKB = (0 V) 40 % -0.5 V 60 % t VCLK common mode = -180 mV, VCLKB = 0 V Note: 1. Do not exceed 10 dBm into the 50 termination resistor for single clock input power level. 2. For an input CLK signal of 4 dBm into 50 , the typical offset value to achieve a 40/60 clock duty cycle is -180 mV on CLK. 35 2104A-BDC-09/03 Noise Immunity Information Circuit noise immunity performance begins at the design level. Efforts have been made on the design to make the device as insensitive as possible to chip environment perturbations resulting from the circuit itself or induced by external circuitry (cascade stages isolation, internal damping resistors, clamps, internal (on-chip) decoupling capacitors). Furthermore, the fully differential operation from the analog input up to the digital output provides enhanced noise immunity by common mode noise rejection. Common mode noise voltage induced on the differential analog and clock inputs will be canceled out by these balanced differential amplifiers. Moreover, proper active signals shielding has been provided on the chip to reduce the amount of coupled noise on the active inputs: The analog inputs and clock inputs of the TS8388B chip have been surrounded by ground pads, which must be directly connected to the external ground plane. Digital Outputs The JTS8388B differential output buffers are internally 75 loaded. The 75 resistors are connected to the digital ground pads through a -0.8 V level shift diode (see Figures 34 and 35 on page 38 and Figure 36 on page 39). The JTS8388B output buffers are designed for driving 75 (default) or 50 properly terminated impedance lines or coaxial cables. An 11 mA bias current flowing alternately into one of the 75 resistors when switching, ensures a 0.825 voltage drop across the resistor (unterminated outputs). The VPLUSD positive supply voltage allows the adjustment of the output common mode level from -1.2 V (VPLUSD = 0 V for ECL output compatibility) to 1.2 V (VPLUSD = 2.4 V for LVDS output compatibility). Therefore, the single-ended output voltages vary approximately between -0.8 V and -1.625 V (outputs unterminated), around -1.2 V common mode voltage. Three possible line driving and back termination scenarios are proposed (assuming VPLUSD = 0 V): 1. 75 impedance transmission lines, 75 differentially terminated (Figure 34): each output voltage varies between -1 V and -1.42 V (respectively 1.4 V and 1 V), leading to 0.41 V = 0.825 V in differential, around -1.21 V (respectively 1.21 V) common mode for VPLUSD = 0 V (respectively 2.4 V). 2. 50 impedance transmission lines, 50 differentially termination (Figure 35): each output voltage varies between -1.02 V and -1.35 V (respectively 1.38 V and 1.05 V), leading to 0.33 V = 660 mV in differential, around -1.18 V (respectively 1.21 V) common mode for VPLUSD = 0 V (respectively 2.4 V). 3. 75 impedance open transmission lines (Figure 36): each output voltage varies between -1.6 V and -0.8 V (respectively 0.8 V and 1.6 V), which are true ECL levels, leading to 0.8 V = 1.6 V in differential, around -1.2 V (respectively 1.2 V) common mode for VPLUSD = 0 V (respectively 2.4 V). Therefore, it is possible to drive high input impedance storing registers directly, without terminating the 75 transmission lines. In the time domain, this means the incident wave will reflect at the 75 transmission line output and travel back to the generator (i.e. the 75 data output buffer). As the buffer output impedance is 75 , no back reflection will occur. Note: This is no longer true if a 50 transmission line is used, as the latter is not matching the buffer 75 output impedance. 36 JTS8388B 2104A-BDC-09/03 JTS8388B Each differential output termination length must be kept identical. It is recommended to decouple the midpoint of the differential termination with a 10 nF capacitor to avoid common mode perturbation in case of slight mismatch in the differential output line lengths. Too large mismatches (keep < a few mm) in the differential line lengths will lead to switching currents flowing into the decoupling capacitor, in turn leading to switching ground noise. The differential output voltage levels (75 or 50 termination) are not ECL standard voltage levels. However, it is possible to drive standard logic ECL circuitry like the ECLinPS logic line from Motorola(R). At sampling rates exceeding 1 Gsps, it may be difficult to trigger the HP16500 or any other acquisition system with digital outputs. It becomes necessary to regenerate digital data and Data Ready by means of external amplifiers, in order to be able to test the JTS8388B at its optimum performance conditions. 37 2104A-BDC-09/03 Differential Output Loading Configurations (levels for ECL compatibility) Figure 34. Differential Output: 75 Terminated VPLUSD = 0 V -0.8 V -1 V/-1.41 V Out 75 75 75 Differential output: 0.41 V = 0.825 V 75 + - 75 impedance 10 nF Common mode level: -1.2 V (-1.2 V below VPLUSD level) 75 OutB -1.41 V/-1 V Out -1.02 V/-1.35 V 11 mA DVEE Figure 35. Differential Output: 50 Terminated VPLUSD = 0 V -0.8 V 75 75 50 50 + - 50 impedance 10 nF 50 Differential output: 0.33 V = 0.660 V Common mode level: -1.2 V (-1.2 V below VPLUSD level) OutB -1.35 V/-1.02 V 11 mA DVEE 38 JTS8388B 2104A-BDC-09/03 JTS8388B Figure 36. Differential Output: Open Loaded VPLUSD = 0 V -0.8 V Out 75 75 75 + - 75 impedance -0.8 V/-1.6 V Differential output: 0.8 V = 1.6 V Common mode level: -1.2 V (-1.2 V below VPLUSD level) OutB -1.6 V/-0.8 V 11 mA DVEE 39 2104A-BDC-09/03 Differential Output Loading Configurations (levels for LVDS compatibility) Figure 37. Differential Output: 75 Terminated VPLUSD = 2.4 V 1.6 V 1.4 V/0.99 V Out 75 75 75 Differential output: 0.41 V = 0.825 V 75 + - 75 impedance 10 nF Common mode level: -1.2 V (-1.2 V below VPLUSD level) 75 OutB 0.99 V/1.4 V Out 1.38 V/1.05 V 11 mA DVEE Figure 38. Differential Output: 50 Terminated VPLUSD = 2.4 V 1.6 V 75 75 50 50 + - 50 impedance 10 nF 50 Differential output: 0.33 V = 0.660 V Common mode level: -1.2 V (-1.2 V below VPLUSD level) OutB 1.05 V/1.38 V 11 mA DVEE 40 JTS8388B 2104A-BDC-09/03 JTS8388B Figure 39. Differential Output: Open Loaded VPLUSD = 2.4 V 1.6 V Out 75 75 75 75 impedance + - 1.6 V/0.8 V Differential output: 0.8 V = 1.6 V Common mode level: -1.2 V (-1.2 V below VPLUSD level) OutB 0.8 V/1.6 V 11 mA DVEE Out-of-range Bit An out-of-range (OR, ORB) bit is provided that reaches a logical high state when the input exceeds the positive full-scale or falls below the negative full-scale. When the analog input exceeds the positive full-scale, the digital outputs remain at a logical high state with OR, ORB at a logical 1. When the analog input falls below the negative full-scale, the digital outputs remain at a logical low state with OR, ORB at a logical 1 again. Gray or Binary Output Data Format Select The JTS8388B internal regeneration latches indecision (for inputs very close to the latches' threshold) may produce errors in the logic encoding circuitry and lead to large amplitude output errors. This is due to the fact that the latches regenerate the internal analog residues into logical states with a finite voltage gain value (Av) within a given positive amount of time (t): Av= exp((t)/), with as the positive feedback regeneration time constant. The JTS8388B has been designed for reducing the probability of occurrence of such errors to approximately 10-13 (targeted for the JTS8388B at 1 Gsps). A standard technique for reducing the amplitude of such errors down to 1 LSB consists of setting the digital output data in gray code format. Though the JTS8388B has been designed to feature a Bit Error Rate of 10-13 with a binary output format, it is possible for the user to choose between the binary or gray output data format, in order to reduce the amplitude of such errors when they occur, by storing gray output codes. Digital data format selection: * Binary output format if GORB is floating or VCC * Gray output format if GORB is connected to ground (0 V) 41 2104A-BDC-09/03 JTS8388B Thermal Requirements The JTS8388B is currently mounted on its dedicated Chip Evaluation Board (CEB), which fulfills the device's thermal requirements in still air at room temperature. For operation in the military temperature range, forced convection is required to maintain the device junction temperature below the specified maximum value. The JTS8388B's power dissipation is 3.6 W at a 70C junction temperature, and 3.8 W at a 125C junction temperature. The die dimensions are 2.44 mm x 3 mm = 7.32 mm2. The maximum junction temperature is 145C. To correctly manage the power dissipation of the JTS8388B device, the following thermal fixture profile is used, taking into account the die dimensions and power dissipation: * 7.5C/W typical value for die attach Ag filled Epoxy glue, but depending on glue film thickness * 0.5C/W Copper block * 1C/W isolation foil * 6.5C/W heatsink (still air) The heatsink used is the 3334B pin fin heatsink from Thermalloy (also used for cooling the 604 Power PC P). Its dimensions are 50.70 mm x 50.39 mm x 16.51 mm (1.996 " x 1.984 " x 0.650 "). The measured die junction to ambient thermal resistance (RTHJA) for the Chip Evaluation Board is approximately 15.5C/W in still air. At room temperature (25C), this yields to a device junction temperature of approximately 80C, in thermal steady-state conditions. 42 JTS8388B 2104A-BDC-09/03 JTS8388B Diode Pad 32 The DIODE pad 32 is provided for die junction temperature monitoring. The operating die junction temperature must be kept below 145C, therefore an adequate cooling system has to be set up. The diode mounted transistor measured Vbe value versus the junction temperature is given below: Figure 40. Diode Pad 32 1000 960 920 VBE (mV) 880 840 800 760 720 680 640 600 -55 -35 -15 5 25 45 65 Junction Temperature (C) 85 105 125 ADC Gain Control Pad 38 The ADC gain is adjustable by means of pad 38 (input impedance is 1 M in parallel with 2 pF). The gain adjust transfer function is given below: Figure 41. ADC Gain Control Pad 38 1.20 1.15 ADC Gain 1.10 1.05 1.00 0.95 0.90 0.85 0.80 -500 -400 -300 -200 -100 0 100 200 300 400 500 Vgain (command voltage) (mV) 43 2104A-BDC-09/03 Equivalent Input / Output Schematics Figure 42. Equivalent Analog Input Circuit and ESD Protections VCC = 5 V VCC VCLAMP = 2.4 V -0.8 V -0.8 V GND GND = 0 V -5.8 V -5.8 V 1.65 V 50 50 E21 V E21 V VEE VEE 200 VIN 200 VINB Pad capacitance 340 fF Pad capacitance 340 fF 5.8 V 5.8 V -1.55 V 0.8 V 0.8 V E21G Note: E21G VEE = -5 V The ESD protections are present but not connected for Vin and Vinb. Figure 43. Equivalent Analog Clock Input Circuit and ESD Protections VCC VCC = 5 V 0.8 V -5.8 V -0.8 V -5.8 V -5.8 V GND = 0 V -5.8 V -5.8 V VEE E31V E31V 150 CLK Pad capacitance 340 fF 150 5.8 V VEE CLKB Pad capacitance 340 fF 5.8 V 380 A 0.8 V 0.8 V E21G Note: 44 VEE = -5 V E21G The ESD protections are present but not connected for Clk and Clkb. JTS8388B 2104A-BDC-09/03 JTS8388B Figure 44. Equivalent Data Output Buffer Circuit and ESD Protections VPLUSD = 0 V to 2.4 V -5.8 V VEE -5.8 V E01V E01V VEE OUT OUTB 5.8 V 5.8 V Pad capacitance 180 fF Pad capacitance 180 fF 0.8 V 0.8 V 0.8 V 0.8 V DVEE = -5 V VEE = -5 V VEE = -5 V Figure 45. ADC Gain Adjust Equivalent Input Circuits and ESD Protections VCC = 5 V GND -0.8 V 0.8 V NP1032C2 -5.8 V E22V 1 k GA Pad capacitance 180 fF 0.8 V 2 pF 0.8 V GND 5.8 V VEE E22GA 500 A 500 A VEE = -5 V 45 2104A-BDC-09/03 Figure 46. GORB Equivalent Input Schematic and ESD Protections VCC = 5 V -0.8 V 1 k 1 k -0.8 V 1 k -5.8 V VEE E21VA 5 k GORB Pad capacitance 180 fF 5.8 V 5.8 V 250 A 250 A 5.8 V E31G VEE = -5 V GND = 0 V GORB: gray or binary select input; floating or tied to VCC -> binary Figure 47. DRRB Equivalent Input Schematic and ESD Protections VCC = 5 V GND = 0 V NP1032C2 10 k 200 DRRB -1.3 V Pad capacitance 180 fF -2.6 V 5.8 V 0.8 V VEE E21G VEE = -5 V Actual protection range: 6.6 V above VEE, in fact stresses above GND are clipped by the CB diode used for TJ monitoring 46 JTS8388B 2104A-BDC-09/03 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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