STL45N10F7AG Automotive-grade N-channel 100 V, 20 m typ., 18 A, STripFETTM F7 Power MOSFET in a PowerFLATTM 5x6 package Datasheet - production data Features Order code VDS RDS(on) max ID PTOT STL45N10F7AG 100 V 24 m 18 A 72 W AEC-Q101 qualified Among the lowest RDS(on) on the market Excellent FoM (figure of merit) Low Crss/Ciss ratio for EMI immunity High avalanche ruggedness Wettable flank package Applications Figure 1: Internal schematic diagram Switching applications Description This N-channel Power MOSFET utilizes STripFETTM F7 technology with an enhanced trench gate structure that results in very low onstate resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. Table 1: Device summary Order code Marking Package Packing STL45N10F7AG 45N10F7 PowerFLATTM 5x6 Tape and reel February 2017 DocID030342 Rev 1 This is information on a product in full production. 1/15 www.st.com Contents STL45N10F7AG Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 5 2/15 4.1 PowerFLATTM 5x6 WF type R package information .......................... 9 4.2 PowerFLATTM 5x6 packing information ........................................... 12 Revision history ............................................................................ 14 DocID030342 Rev 1 STL45N10F7AG 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 100 V VGS Gate-source voltage 20 V ID(1) Drain current (continuous) at TC = 25 C 18 A ID (1) Drain current (continuous) at TC = 100 C 18 A IDM(2) Drain current (pulsed) 72 A PTOT Total dissipation at TC = 25 C 72 W EAS(3) Single pulse avalanche energy 150 mJ -55 to 175 C Value Unit Thermal resistance junction-case 2.08 C/W Thermal resistance junction-pcb 31.3 C/W TJ Operating junction temperature range Tstg Storage temperature range Notes: (1)Limited (2)Pulse by package. width limited by safe operating area. (3)Starting Tj = 25 C, ID = 9 A, VDD = 60 V Table 3: Thermal resistance Symbol Rthj-case Rthj-pcb (1) Parameter Notes: (1)When mounted on FR-4 board of 1inch, 2oz Cu, t < 10 s DocID030342 Rev 1 3/15 Electrical characteristics 2 STL45N10F7AG Electrical characteristics (TCASE = 25 C unless otherwise specified) Table 4: On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS= 0 V, ID = 250 A Min. Typ. Max. 100 Unit V VGS = 0 V, VDS = 100 V 1 VGS = 0 V, VDS = 100 V; TC = 125 C(1) 10 Gate body leakage current VDS = 0 V, VGS = 20 V 100 nA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 A 4.5 V RDS(on) Static drain-source onresistance VGS = 10 V, ID = 9 A 20 24 m Min. Typ. Max. Unit - 1450 - pF - 350 - pF - 25 - pF - 19.5 - nC - 9.1 - nC - 4.3 - nC Min. Typ. Max. Unit - 15 - ns - 5.5 - ns - 17 - ns - 5 - ns IDSS Zero gate voltage drain current IGSS 2.5 A Notes: (1)Defined by design, not subject to production test. Table 5: Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Test conditions VDS = 50 V, f = 1 MHz, VGS = 0 V VDD = 50 V, ID = 18 A, VGS = 0 to 10 V (see Figure 14: "Test circuit for gate charge behavior") Table 6: Switching times Symbol td(on) tr td(off) tf 4/15 Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD = 50 V, ID = 9 A, RG = 4.7 , VGS = 10 V (see Figure 13: "Test circuit for resistive load switching times" and Figure 18: "Switching time waveform") DocID030342 Rev 1 STL45N10F7AG Electrical characteristics Table 7: Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD Source-drain current - 18 A ISDM(1) Source-drain current (pulsed) - 72 A VSD(2) Forward on voltage ISD = 9 A, VGS = 0 V - 1.2 V trr Reverse recovery time - 46 ns Qrr Reverse recovery charge - 46 nC IRRM Reverse recovery current ISD = 18 A, di/dt = 100 A/s, VDD = 80 V (see Figure 15: "Test circuit for inductive load switching and diode recovery times") - 2 A Notes: (1)Pulse (2) width limited by safe operating area Pulsed: pulse duration=300 s, duty cycle 1.5% DocID030342 Rev 1 5/15 Electrical characteristics 2.1 STL45N10F7AG Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance 6/15 DocID030342 Rev 1 STL45N10F7AG Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Source-drain diode forward characteristics Figure 12: Normalized V(BR)DSS vs temperature DocID030342 Rev 1 7/15 Test circuits 3 8/15 STL45N10F7AG Test circuits Figure 13: Test circuit for resistive load switching times Figure 14: Test circuit for gate charge behavior Figure 15: Test circuit for inductive load switching and diode recovery times Figure 16: Unclamped inductive load test circuit Figure 17: Unclamped inductive waveform Figure 18: Switching time waveform DocID030342 Rev 1 STL45N10F7AG 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK (R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 4.1 PowerFLATTM 5x6 WF type R package information Figure 19: PowerFLATTM 5x6 WF type R package outline A0Y5_8231817_R_WF_Rev_14 DocID030342 Rev 1 9/15 Package information STL45N10F7AG Table 8: PowerFLATTM 5x6 WF type R mechanical data mm Dim. Min. Max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 C 5.80 6.00 6.10 0.50 5.20 5.40 D 5.00 D2 4.15 D3 4.05 4.20 4.35 D4 4.80 5.00 5.10 D5 0.25 0.4 0.55 D6 0.15 0.3 0.45 e 10/15 Typ. 4.45 1.27 E 6.20 E2 3.50 3.70 E3 2.35 2.55 E4 0.40 0.60 E5 0.08 0.28 E6 0.20 0.325 0.45 E7 0.85 1.00 1.15 E9 4.00 4.20 4.40 E10 3.55 3.70 3.85 K 1.275 L 0.725 0.825 0.925 L1 0.175 0.275 0.375 0 DocID030342 Rev 1 6.40 6.60 1.575 12 STL45N10F7AG Package information Figure 20: PowerFLATTM 5x6 recommended footprint (dimensions are in mm) 8231817_FOOTPRINT_rev14 DocID030342 Rev 1 11/15 Package information 4.2 STL45N10F7AG PowerFLATTM 5x6 packing information Figure 21: PowerFLATTM 5x6 WF tape (dimensions are in mm) Figure 22: PowerFLATTM 5x6 package orientation in carrier tape 12/15 DocID030342 Rev 1 STL45N10F7AG Package information Figure 23: PowerFLATTM 5x6 reel (dimensions are in mm) DocID030342 Rev 1 13/15 Revision history 5 STL45N10F7AG Revision history Table 9: Document revision history 14/15 Date Revision Changes 16-Feb-2017 1 First release. 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All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2017 STMicroelectronics - All rights reserved DocID030342 Rev 1 15/15