8442AYLF - Integrated Device Technology

ICS8442

REFER TO PCN# N1308-01, Effective date 1/31/2014

FOR NEW DESIGNS USE PART NUMBER: ICS8442B DATA SHEET

700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL

LVDS FREQUENCY SYNTHESIZER

GENERAL DESCRIPTION

The ICS8442 is a general purpose, dual output Crystal-to-Dif-

ferential LVDS High Frequency Synthesizer. The ICS8442 has

a selectable TEST_CLK or crystal input. The TEST_CLK in-

put accepts LVCMOS or LVTTL input levels and translates them

to LVDS levels. The VCO operates at a frequency range of

250MHz to 700MHz.The VCO frequency is programmed in

steps equal to the value of the input reference or crystal fre-

quency. The VCO and output frequency can be programmed

using the serial or parallel interface to the configuration logic.

The low phase noise characteristics of the ICS8442 makes it

an ideal clock source for Gigabit Ethernet and Sonet applica-

tions.

BLOCK DIAGRAM PIN ASSIGNMENT

FEATURES

•Dual differential LVDS outputs

•Selectable crystal oscillator interface or

LVCMOS/LVTTL TEST_CLK

•Output frequency range: 31.25MHz to 700MHz

•Crystal input frequency range: 10MHz to 25MHz

•VCO range: 250MHz to 700MHz

•Parallel or serial interface for programming counter

and output dividers

•RMS period jitter: 2.7ps (typical)

•Cycle-to-cycle jitter: 18ps (typical)

•3.3V supply voltage

•0°C to 85°C ambient operating temperature

•Lead-Free package fully RoHS compliant

32-Lead LQFP

7mm x 7mm x 1.4mm package body

Y Package

Top View

OSC

VCO_SEL

XTAL_SEL

TEST_CLK

XTAL_IN

XTAL_OUT

S_LOAD

S_DATA

S_CLOCK

nP_LOAD

M0:M8

N0:N1

VCO

PLL

FOUT0

nFOUT0

FOUT1

nFOUT1

TEST

CONFIGURATION

INTERFACE

LOGIC

÷ M

PHASE DETECTOR ÷ 1

÷ 2

÷ 4

÷ 8

32 31 30 29 28 27 26 25

9 10 11 12 13 14 15 16

XTAL_OUT

TEST_CLK

XTAL_SEL

DDA

S_LOAD

S_DATA

S_CLOCK

GND

nFOUT0

FOUT0

nFOUT1

FOUT1

TEST

XTAL_IN

nP_LOAD

VCO_SEL

ICS8442

ICS8442 Data Sheet 700MHz, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER

put divider to a specific default state that will automatically

occur during power-up. The TEST output is LOW when op-

erating in the parallel input mode. The relationship between

the VCO frequency, the crystal frequency and the M divider

is defined as follows:

The M value and the required values of M0 through M8 are

shown in Table 3B, Programmable VCO Frequency Function

Table. Valid M values for which the PLL will achieve lock for

a 25MHz reference are defined as 10 ≤ M ≤ 28. The fre-

quency out is defined as follows:

Serial operation occurs when nP_LOAD is HIGH and

S_LOAD is LOW. The shift register is loaded by sampling

the S_DATA bits with the rising edge of S_CLOCK. The con-

tents of the shift register are loaded into the M divider and N

output divider when S_LOAD transitions from LOW-to-HIGH.

The M divide and N output divide values are latched on the

HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH,

data at the S_DATA input is passed directly to the M divider

and N output divider on each rising edge of S_CLOCK. The

serial mode can be used to program the M and N bits and

test bits T1 and T0. The internal registers T0 and T1 deter-

mine the state of the TEST output as follows:

NOTE: The functional description that follows describes op-

eration using a 25MHz crystal. Valid PLL loop divider values

for different crystal or input frequencies are defined in the

Input Frequency Characteristics, Table 5, NOTE 1.

The ICS8442 features a fully integrated PLL and therefore

requires no external components for setting the loop band-

width. A fundamental crystal is used as the input to the on-

chip oscillator. The output of the oscillator is fed into the phase

detector. A 25MHz crystal provides a 25MHz phase detector

reference frequency. The VCO of the PLL operates over a

range of 250MHz to 700MHz. The output of the M divider is

also applied to the phase detector.

The phase detector and the M divider force the VCO output fre-

quency to be M times the reference frequency by adjusting the

VCO control voltage. Note that for some values of M (either too

high or too low), the PLL will not achieve lock. The output of the

VCO is scaled by a divider prior to being sent to each of the

LVDS output buffers. The divider provides a 50% output duty cycle.

The programmable features of the ICS8442 support two in-

put modes to program the M divider and N output divider.

The two input operational modes are parallel and serial.

Fig-

ure 1

shows the timing diagram for each mode. In parallel

mode, the nP_LOAD input is initially LOW. The data on in-

puts M0 through M8 and N0 and N1 is passed directly to the

M divider and N output divider. On the LOW-to-HIGH transi-

tion of the nP_LOAD input, the data is latched and the M

divider remains loaded until the next LOW transition on

nP_LOAD or until a serial event occurs. As a result, the M

and N bits can be hardwired to set the M divider and N out-

FUNCTIONAL DESCRIPTION

fVCO = fxtal x M

T1 T0 TEST Output

00 LOW

0 1 S_Data, Shift Register Input

1 0 Output of M divider

1 1 CMOS FOUT

FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS

Time

SERIAL LOADING

PARALLEL LOADING

M, N

S_CLOCK

S_DATA

S_LOAD

nP_LOAD

M0:M8, N0:N1

nP_LOAD

S_LOAD

*NOTE: The NULL timing slot must be observed.

T1 T0

NULL

N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0

FOUT = fVCO = fxtal x M

ICS8442 Data Sheet 700MHz, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER

TABLE 1. PIN DESCRIPTIONS

rebmuNemaNepyTnoitpircseD

15MtupnIpulluP

noitsisnartHGIH-ot-WOLnodehctalataD.stupniredividM

.slevelecafretniLT

TVL/SOMCVL.tupniDAOL_Pnfo

,4,3,2

,92,82

23,13,03

,8M,7M,6M

,1M,0M

4M,3M,2M

tupnInwodlluP

6,51N,0NtupnInwodlluP C3e

lbaTnidenifedsaeulavredividtuptuosenimreteD

.slevelecafretniLTTVL/SOMCVL.elbaTnoitcnuF

7cndesunU.tcennocoN

61,8DNGrewoP.dnuorgylppusrewoP

9TSETtuptuO tuptuO.noitarepofoedomlairesehtniEVITCAsihcihwtuptuotseT

.slevele

cafretniLTTVL/SOMCVL.edomlellarapniWOLnevird

31,01V

rewoP.snipylppuseroC

21,111TUOFn,1TUOFtuptuO .slevelecafretniSDVL.rezisehtnysehtroftuptuolaitnereffiD

51,410

TUOFn,0TUOFtuptuO .slevelecafretniSDVL.rezisehtnysehtroftuptuolaitnereffiD

71RMtupnInwodlluP

sredividlanretn

ieht,HGIHcigolnehW.teseRretsaMhgiHevitcA

detrevniehtdnawologotxTUOFstuptuoeurtehtgnisuacteserera

srediv

idlanretnieht,WOLcigolnehW.hgihogotxTUOFnstuptuo

dedaoltceffetonseodRMfonoitressA.delbaneerastuptuoeht

dna

.slevelecafretniLTTVL/SOMCVL.seulavTdna,N,M

81KCOLC_StupnInwodlluP retsigertfihsehtotnitupniATAD_Statne

serpatadlairesniskcolC

.slevelecafretniLTTVL/SOMCVL.KCOLC_Sfoegdegnisirehtno

91ATAD_StupnInwodlluP egdegnis

irehtnodelpmasataD.tupnilairesretsigertfihS

.slevelecafretniLTTVL/SOMCVL.KCOLC_Sfo

02DAOL_StupnInwodlluP .s

redividehtotniretsigertfihsmorfatadfonoitisnartslortnoC

.slevelecafretniLTTVL/SOMCVL

12V

ADD

rewoP.nipylppusgolanA

22LES_LATXtupnIpulluP

ecnereferLLPehtsastupnitsetrorotallicsolatsyrcneewtebstceleS

neh

wKLC_TSETstceleS.HGIHnehwstupniLATXstceleS.ecruos

.slevelecafretniLTTVL/SOMCVL.WOL

32KLC_TSETtupnInwodlluP.

slevelecafretniLTTVL/SOMCVL.tupnikcolctseT

52,42 ,NI_LATX

TUO_LATX tupnI ,tupniehtsiNI_LATX.ecafretnirotal

licsolatsyrC

.tuptuoehtsiTUO_LATX

62DAOL_PntupnInwodlluP

si0M:8MtatneserpatadnehwsenimreteD.tupnidaollellar

ehtstes0N:1Ntatneserpatadnehwdna,redividMotnidedaol

.slevelecafretniLTTVL/SOMCVL.eulavredividtuptuoN

72LES_OCVtupnIpulluP .edomssapybroLLPnisirezisehtnysrehtehwsenimreteD

.slevelecafretniLTTVL/SOMCVL

:ETON

pulluP

dna

nwodlluP

.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotrefer

TABLE 2. PIN CHARACTERISTICS

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

ecnaticapaCtupnI 4Fp

PULLUP

rotsiseRpulluPtupnI 15kΩ

NWODLLUP

rotsiseRnwodlluPtupnI 15kΩ

ICS8442 Data Sheet 700MHz, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER

TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE

TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE

TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE

stupnI eulaVrediviDN )zHM(ycneuqerFtuptuO

1N0NmuminiMmumixaM

00 1 052007

01 2 521053

10 4 5.26571

11 8 52.135.78

ycneuqerFOCV

)zHM( ediviDM 6528214623618421

8M7M6M5M4M3M2M1M0M

05201 0 0 0 00 10 10

57211 00000 10 11

• • •••••••••

05662 0 0 0 0 1 10 10

57672 000011011

00782 000011100

ycneuqerftupniKLC_TSETrolatsyrcotdnops

errocseicneuqerfgnitluserehtdnaseulavedividMesehT:1ETON

.zHM52fo

stupnI snoitidnoC

RMDAOL_PnMNDAOL_SKCOLC_SATAD_S

HX XXX X X

laitnereffidaotstuptuoehtsecrof,HGIHnehW.teseR

tub,)HGIH=xTUO

FndnaWOL=xTUOF(etatsWOL

.seulavTdna,N,Mdedaoltceffetonseod

LL ataDataDX X X MehtotyltceriddessapstupniNdnaMnoataD

.WOLdecroftuptuoTSET.redividtuptuoNdnaredivid

L↑ataDataDL X X dedaolsniamerdnasretsigertupniotnidehctalsiataD

.sruccotnevelairesalitnuronoitisnartWOLtxenlitnu

LH XXL ↑ataD noatadhtiwdedaolsiretsigertfihS.edomtupnilaireS

.KCOLC_SfoegdegnisirhcaenoATAD_S

LH XX↑LataD ehtotdessaperaretsigertfihsehtfostnetnoC

.redividtuptuoNdnarediv

idM

LH XX↓LataD.dehctaleraseulavredividtuptuoNdnaredividM

LH XXL X X .sretsigertfihstceffatonodtupnilairesrolellaraP

LH XXH ↑at

aD.dekcolcsitisaredividMotyltceriddessapATAD_S

WOL=L:ETON

HGIH=H

eract'noD=X

↑noitisnartegdegnisiR=

↓noitis

nartegdegnillaF=

ICS8442 Data Sheet 700MHz, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 85°C

TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVylppuSeroC 531.33.3564.3V

ADD

egatloVylppuSgolanA 531.33.3564.3V

tnerruCylppuSrewoP 551Am

ADD

tnerruCylppuSgolanA 02Am

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

tupnI

egatloVhgiH

,DAOL_Pn,RM,1N,0N,8M-0M

,DAOL_S,ATAD_S,KCOLC_S

LES_OCV,LES_LATX

3.0+V

KLC_TSET2V

3.0+V

tupnI

egatloVwoL

,DAOL_Pn,RM,1N,0N,8M-0M

,DAOL_S,ATAD_S,KCOLC_S

LES_OCV,LES_LATX

3.0-8.0V

KLC_TSET3.0-3.1V

tupnI

tnerruChgiH

,RM,1N,0N,8M-6M,4M-0M

,ATAD_S,KCOLC_S,DAOL_Pn

,DAOL_S

V564.3=051Aµ

LES_OCV,LES_LATX,5MV

V564.3=5

tupnI

tnerruCwoL

,RM,1N,0N,8M-6M,4M-0M

,ATAD_S,KCOLC_S,DAOL_Pn

,DAOL_S

,V564.3=

V0= 5-Aµ

LES_OCV,LES_LATX,5M V

,V564.3=

V0= 051-

tuptuO

egatloVhgiH 1ETON;TSET6.2V

tuptuO

egatloVwoL 1ETON;TSET 5.0V

05htiwdetanimretstuptuO:1ETON ΩVot

,noitcesnoitamrofnItnemerusaeMretemaraPeeS.2/

."tiucriCtseTdaoLtuptuOV3.3"

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V

DD 4.6V

Inputs, VI-0.5V to VDD + 0.5V

Outputs, IO

Continuous Current 10mA

Surge Current 15mA

Package Thermal Impedance, θJA 47.9°C/W (0 lfpm)

Storage Temperature, T

STG -65°C to 150°C

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device. These ratings are stress specifications only. Func-

tional operation of product at these conditions or any condi-

tions beyond those listed in the

DC Characteristics

Characteristics

is not implied. Exposure to absolute maxi-

mum rating conditions for extended periods may affect prod-

uct reliability.

TABLE 4C. LVDS DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVtuptuOlaitnereffiD 052054006Vm

ΔV

egnahCedutingaM 05Vm

egatloVtesffO 521.14.16.1V

ΔV

egnahCedutingaM 05Vm

ICS8442 Data Sheet 700MHz, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER

TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 85°C

TABLE 6. CRYSTAL CHARACTERISTICS

retemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

noitallicsOfoedoM latnemadnuF

ycneuqerF 0152zHM

)RSE(ecnatsiseR

seireStnelaviuqE 05 Ω

ecnaticapaCtnuhS 7Fp

leveLevirD 1Wm

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

TUO

ycneuqerFtuptuO 52.13007zHM

)cc(tij3,1ETON;rettiJelcyC-ot-elcyC 2,1=N8182sp

4=N7254sp

)rep(tij3,1ETON;SMR,rettiJdoireP 7.27sp

)o(ks3,2ETON;wekStuptuO 51sp

emiTllaF/esiRtuptuO%08ot%02051056sp

emiTputeS

DAOL_PnotN,M5sn

KCOLC_SotATAD_S5sn

DAOL_SotKCOLC_S5sn

emiTdloH

DAOL_PnotN,M5sn

KCOLC_SotATAD_S5sn

DAOL_SotKCOLC_S5sn

cdo4ETON;elcyCytuDtuptuO1>N8425%

htdiWesluPtuptuO1=Nt

doireP

051-2/t

doireP

051+2/sp

KCOL

emiTkcoLLLP 1sm

.noitcesnoitamrofnItnemerusaeMretemaraPeeS

.stupniLATXgnisuecnamrofreprettiJ:1ETON

.snoiti

dnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:2ETON

.stniopssorclaitnereffidtu

ptuoehttaderusaeM

.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:3ETON

".tnemevorpmIelcyCytuDla

itnereffiD",etonnoitacilppaehtotreferesaelp,noitceSsnoitacilppAehtnI:4ETON

TABLE 7. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

ycneuqerFtupnI

1ETON;KLC_TSET0152zHM

;TUO_LATX,NI_LATX

1ETON 0152zHM

KCOLC_S 05zHM

ehtnihtiwetarepootOCVehtroftese

btsumeulavMehtegnarycneuqerfKLC_TSETdnalatsyrctupniehtroF:1ETON

52eraMfoseulavdilavzHM01foycneuqerftup

nimuminimehtgnisU.egnarzHM007otzHM052 ≤M≤ehtgnisU.07

01eraMfoseulavdilavzHM52foycneuqerfmumixam ≤M≤.82

ICS8442 Data Sheet 700MHz, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER

PARAMETER MEASUREMENT INFORMATION

OUTPUT SKEW

OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

Cycle-to-Cycle Jitter Period Jitter

VOH

VREF

VOL

Mean Period

(First edge after trigger)

Reference Point

(Trigger Edge)

1σ contains 68.26% of all measurements

2σ contains 95.4% of all measurements

3σ contains 99.73% of all measurements

4σ contains 99.99366% of all measurements

6σ contains (100-1.973x10-7)% of all measurements

Histogram

OUTPUT RISE/FALL TIME

Clock

Outputs 20%

80% 80%

20%

SWIN G

PERIOD

odc = x 100%

nFOUT0, nFOUT1

FOUT0, FOUT1

➤

nFOUT0,

nFOUT1

FOUT0,

FOUT1

tsk(o)

nFOUTx

FOUTx

nFOUTy

FOUTy

OFFSET VOLTAGE SETUP

DIFFERENTIAL OUTPUT VOLTAGE SETUP

3.3V OUTPUT LOAD TEST CIRCUIT

out

LVDS

DC Input

➤

/Δ V

➤

100

out

LVDS

DC Input V

/Δ V

SCOPE

nQx

LVD S

Power Supply

Float GND

cycle n

cycle n+1

jit(cc) =

cycle n –

cycle n+1

1000 Cycles

VDD

ICS8442 Data Sheet 700MHz, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER

STORAGE AREA NETWORKS

A variety of technologies are used for interconnection of the

elements within a SAN. The tables below lists the common

Table 8. Common SANs Application Frequencies

Table 9. Configuration Details for SANs Applications

APPLICATION INFORMATION

ygolonhceTtcennocretnIetaRkcolC SEDRESotycneuqerFecnerefeR

)zHM(

ycneuqerFlatsyrC

)zHM(

tenrehtEtibagiGzHG52

.152.651,052,52152135.91,52

lennahCerbiF zHG5260.11CF

zHG0521.22CF 5218.231,521.35,52.60152,5265106.61

dnabin

ifnIzHG5.2052,52152

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. The ICS8442 provides sepa-

rate power supplies to isolate any high switching noise from

the outputs to the internal PLL. VDD and VDDA, should

be individually connected to the power supply plane through

vias, and bypass capacitors should be used for each pin. To

achieve optimum jitter performance, better power supply

isolation is required.

Figure 2

illustrates how a 10Ω along

|with a 10μF and a .01μF bypass capacitor should be

connected to each VDDA pin.

POWER SUPPLY FILTERING T ECHNIQUES

FIGURE 2. POWER SUPPLY FILTERING

10Ω

VDDA

10μF

.01μF

3.3V

.01μF

VDD

tcennocretnI

ygolonhceT

ycneuqerFlatsyrC

)zHM(

2448SCI

ycneuqerFtuptuO

SEDRESot

)zHM(

2448SCI

sgnitteSN&M

8M7M6M5M4

M3M2M1M0M1N0N

tenrehtEtibagiG

52521 0000 10100 10

52052 0000 101000 1

5252.651 0000 1100110

52135.9152.651 000 10000010

1lennahCrebiF

52521.35 00001000111

5252.601 0000 1000110

2lennahCrebiF5265106.61521

8.231 000 10000010

dnabinifnI

52521 0000 10100 10

52052 0000 101000 1

frequencies used as well as the settings for the ICS8442 to

generate the appropriate frequency.

ICS8442 Data Sheet 700MHz, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER

CRYSTAL INPUT INTERFACE

A crystal can be characterized for either series or parallel mode

operation. The ICS8442 has a built-in crystal oscillator circuit.

This interface can accept either a series or parallel crystal without

additional components and generate frequencies with accuracy

Figure 3. CRYSTAL INPUt INTERFACE

suitable for most applications. Additional accuracy can be

achieved by adding two small capacitors C1 and C2 as shown

Figure 3

. Typical results using parallel 18pF crystals are shown

in Table 10.

LVDS DRIVER TERMINATION

A general LVDS interface is shown in

Figure 4.

In a 100Ω

differential transmission line environment, LVDS drivers require

a matched load termination of 100Ω across near the receiver

input. For a multiple LVDS outputs buffer, if only partial outputs

are used, it is recommended to terminate the un-used out-

puts.

100ΩΩ

ΩΩ

Ω Differential Transmission Line

FIGURE 4. TYPICAL LVDS DRIVER TERMINATION

DIFFERENTIAL DUTY CYCLE IMPROVEMENT

The schematic below is recommended for applications using the

÷1 output configuration for improving the differential duty cycle.

FIGURE 5. DIFFERENTIAL DUTY CYCLE IMPROVEMENT

3.3V

LVDS_DRIVER

100

HiPerClockS

Zo = 50 Ohm

nCLK

CLK

100

.1uf

Vcc = 3.3V

800

LVDS Driv er

1.3k

Zo = 50

1.3k

.1uf

Receiv er_dif

Zo = 50

800

18p

18pF Parallel Crystal

22p

XTAL_IN

XTAL_OUT

ICS8442 Data Sheet 700MHz, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER

The schematic of the ICS8442 layout example used in this lay-

out guideline is shown in

Figure 6A.

The ICS8442 recommended

PCB board layout for this example is shown in

Figure 6B.

This

layout example is used as a general guideline. The layout in the

LAYOUT GUIDELINE

FIGURE 6A. RECOMMENDED SCHEMATIC LAYOUT

actual system will depend on the selected component types,

the density of the components, the density of the traces, and

the stack up of the P.C. board.

nFOUT1

VDDA

C14

0.1u

FOUT1

VDD

nFOUT0

C16

10u

Z o = 50 Ohm

ICS8442

GND

TEST

VDD

FOUT1

nFOUT1

VDD

FOUT0

nFOUT0

GND

S_CLOCK

S_DATA

S_LOAD

VDDA

nXTAL_SEL

T_CLK

X_OUT

VCO_SEL

nP_LOAD

X_IN

C15

0.1u

VDD

Z o = 50 Ohm

VDD

Z o = 50 Ohm

FOUT0

C11

0.01u

100

ICS8442 Data Sheet 700MHz, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER

The following component footprints are used in this layout

example: All the resistors and capacitors are size 0603.

POWER AND GROUNDING

Place the decoupling capacitors C14 and C15 as close as pos-

sible to the power pins. If space allows, placing the decoupling

capacitor at the component side is preferred. This can reduce

unwanted inductance between the decoupling capacitor and

the power pin generated by the via.

Maximize the pad size of the power (ground) at the decoupling

capacitor. Maximize the number of vias between power (ground)

and the pads. This can reduce the inductance between the power

(ground) plane and the component power (ground) pins.

If VDDA shares the same power supply with VDD, insert the RC

filter R7, C11, and C16 in between. Place this RC filter as close

to the VDDA as possible.

CLOCK TRACES AND TERMINATION

The component placements, locations and orientations should

be arranged to achieve the best clock signal quality. Poor clock

signal quality can degrade the system performance or cause

system failure. In the synchronous high-speed digital system,

the clock signal is less tolerable to poor signal quality than other

signals. Any ringing on the rising or falling edge or excessive

ring back can cause system failure. The trace shape and the

trace delay might be restricted by the available space on the

board and the component location. While routing the traces, the

clock signal traces should be routed first and should be locked

prior to routing other signal traces.

• The traces with 50W transmission lines TL1 and TL2 at

FOUT and nFOUT should have equal delay and run

adjacent to each other. Avoid sharp angles on the clock

trace. Sharp angle turns cause the characteristic

impedance to change on the transmission lines.

• Keep the clock trace on same layer. Whenever possible,

avoid any vias on the clock traces. Any via on the trace

can affect the trace characteristic impedance and hence

degrade signal quality.

• To prevent cross talk, avoid routing other signal traces in

parallel with the clock traces. If running parallel traces is

unavoidable, allow more space between the clock trace and

the other signal trace.

• Make sure no other signal trace is routed between the clock

trace pair.

The matching termination resistors R1 and R2 should be located

as close to the receiver input pins as possible. Other termination

scheme can also be used but is not shown in this example.

CRYSTAL

The crystal X1 should be located as close as possible to the

pins 24 (XTAL_OUT) and 25 (XTAL_IN). The trace length be-

tween the X1 and U1 should be kept to a minimum to avoid

unwanted parasitic inductance and capacitance. Other signal

traces should not be routed near the crystal traces.

FIGURE 6B. PCB BOARD LAYOUT FOR ICS8442

VDD

TL1

C15

C14

Same requirement f

FOUT1/nFOUT1

VDDA

Close to the input

pins of the

receiver

For FOUT0/n FOUT

output TL1, TL1N ar

50 Ohm traces and

equal length

VIA

GND

TL1N

TL1

PIN 1

TL1N

C11 C16

ICS8442 Data Sheet 700MHz, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER

RELIABILITY INFORMATION

TRANSISTOR COUNT

The transistor count for ICS8442 is: 3662

TABLE 10. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP

θθ

θJA by Velocity (Linear Feet per Minute)

0 200 500

Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W

Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

ICS8442 Data Sheet 700MHz, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER

PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP

TABLE 11. PACKAGE DIMENSIONS

Reference Document: JEDEC Publication 95, MS-026

NOITAIRAVCEDEJ

SRETEMILLIMNISNOISNEMIDLLA

LOBMYS

ABB

MUMINIMLANIMONMUMIXAM

N23

A----06.1

1A 50.0--51.0

2A 53.104.154.1

b03.073.054.0

c90.0--02.0

DCISAB00.9

1D CISAB00.7

2D .feR06.5

ECISAB00.9

1E CISAB00.7

2E .feR06.5

eCISAB08.0

L54.006.057.

θθ

θθ 0

-- 7

ccc ----01.0

ICS8442 Data Sheet 700MHz, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER

TABLE 12. ORDERING INFORMATION

Part/Order Number Marking Package Shipping Packaging Temperature

8442A Y LF ICS 8442AY LF 32 lead "Lead Free" LQF P Tray 0°C t o + 85°C

8442A Y LF T ICS 8442AY LF 32 lead "Lead Free" LQF P Tape and Reel 0°C t o + 85°C

ICS8442 Data Sheet 700MHz, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER

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ICS8442 Data Sheet 700MHz, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER