enceienee ( W89C925 PENTIC (Winbond Ok PCMCIA ETHERNET NETWORK TWISTED-PAIR INTERFACE CONTROLLER GENERAL DESCRIPTION The W89C925 PENTIC is a CMOS device designed for easy implementaion of PCMCIA R2.0/JEIDA 4.1 compatible CSMA/CD local area networks. The W89C925 combines a W89C902 Serial LAN Coprocessor for Twisted-pair (SLCT) with a PCMCIA Bus Interface (PBI), thus integrating into a single chip ail the registers and logic necessary to connect the SLCT to buffer SRAMs, flash memories, and the PCMCIA system bus. The W89C925 makes it easy and cost-effective to implement a PCM- CIA LAN card. The SLCT provides a LAN Coprocessor for Ethernet (LCE), a Serial Network Adaptor (SNA) with an AUI interface, and a Twisted-pair transceiver. Applications on 10BASE2, 10BASE5, and 10BASE-T media can be easily implemented, and the PENTIC's 10Base-T transceiver complies with the IEEE UTP standard. The PCMCIA Bus Interface (PBI) is designed to provide a switchless setting architecture that allows the card setting to be accomplished by software. The PBI contains several configuration registers for the selection of operating conditions. The card can be configured quickly and easily by modifying the contents of the configuration registers of the PENTIC. The PENTIC supports shared memory mode and NE2000 compatible I/O mode operations on a 16-bit bus interface. For enhanced performance, an optional enhanced mode (supporting up to 64KB packet buffer) structure is also available. FEATURES Single-chip solution for PCMCIA Ethernet Complies fully with PCMCIA R2.0/JEIDA 4.1 bus interface specification - Conforms to IEEE 802.3 10BASE-T, 10BASE2, and 10BASES5 Ethernet specifications e Integrates PBI, LCE, SNA, and UTP transceiver e Selectable (16KB/64KB) buffer memory size for high performance Supports up to 128KB flash memory (or EEPROM) with the lower half reserved for attribute memory space and the upper half reserved for common memory space Software compatible with NE2000 Shared memory mode and I/O mode operation provided Configuration registers supported for switchless card setting UTP/BNC auto media-switching function provided Supports full set of LEDs Single 5V power supply with low power consumption 144-pin thin package (TQFP) fits into PCMCIA Type II profile Publication Release Date:March 1994 Revision AlW89C925 74 73 | 82 81 BO |.79 78 | 77 76 76 7 2 7 4 7 0 6 9 6 7 6 6 6 4 6 3 6 2 6 1 4 4 4 3 4 2 4 1 PIN CONFIGURATION iy ' lel | : ssessssess ~ iain! | Slee (eclelie leo) 2) ! : . | Lit Lt poet 1 l ow * ' + tite, +, =sNz2Q000 OSES OSS GOSS SER OO RARER SARK YOKXE ZUM WUD > DPORxxLOUreSSsSVOTRHGEESS Foaoxxoo 222aaF FR Kage ang aq << Oakeod a a @eza zo Sn0Wen FWOr sno-- Lao =0OQ-0 woe =nvaAn LON =O0 eza ~KOYON On .~23w wor 2va-9 200 Znaan Ow Z0de0 Law Znden Lon >ou o2za ~cow ~LBO f0de- ~wOuw e2z0 ~o.du ~CLOV] rae Zvon zo =000 LOee =o0w0 oza svo~ raw =znva" TAcn ZvaQn rae zn0+ ro-m =znQ0 >ouo >oo Zon nde eza eza roe- snan ~OWe 2u0dan ro-w Zoae XrIdeo Endo ~OulN ENd0 ~Ow Zuar Idee 2nan ~-Ora ZNdeO rida: ee <"9Ofummade-e@e0e gozogggoggss =Orrr>rrrrr | wleules @ WinbondPIN DESCRIPTION W89C925 Name Number Type Description PCMCIA Bus Interface IREQ 30 O/ODH Interrupt Request: IREQ is asserted by the PENTIC to request host service. WE 32 Write Enable: The /WE input is asserted by the system to strobe memory write data into the card memory. It has an internal 10K ohm pull-high resistor. 40 Output Enable: The /OE line is asserted by the system to obtain memory read data from the card memory. It has an internal 10K ohm pull- high resistor. CE1,2 REG lO1S16 INPACK WAIT 44,41 13 15 17 VTTL O/ODH O/ODE O/ODH Card Enable: CE12 are asserted by the system for data bus width control as shown below. These pins have an internal 10K ohm pull- high resistor. CE2 CE1 HD15-HD8 HD7-HDO Valid 0 Valid 1 Valid 0 1 High-Z Valid High-Z High-Z High-Z Register & I/O selection: REGis asserted by the system to access attribute memory or 1/O space. It remains high inactive for common memory ac- cesses. It has an internal 10K ohm pull-high resistor. 16-bit |/O access: Asserted by the PENTIC to inform the system that current op- eration is a 16-bit i/O access. Input Acknowledge: Asserted by the PENTIC when it has been selected and can respond to an I/O read cycle. Wait State: Asserted by the PENTIC to insert WAIT states into current memory or I/O access cycles. RESET 22 Card Reset: RESET clears the card's Configuration Option Register (COR) and places the PENTIC in an unconfigured state. It also signals the beginning of card initialization. Publication Release Date: March 1994 -3- Revision Al(Winbond W89C925 Pin description, continued Name Number Type Description IORD 38 VTTL (/O Read: IORD is asserted by the system to read data from the card's 1/O space. It has an internal 10K ohm pull-high resistor. IOWR 36 VTTL I/O Write: IOWR is asserted by the system to write data to the card's 1/O space. It has an internal 10K ohm pull-high resistor. HAO-2 11,12,14 TTL Host Address Bus: HA3-4 19,21 Host address lines used to decode accesses to the card's HA5-7 23-25 memory and I/O spaces. HA8-10 35,37,42 HA11-13 39,26,34 HA14-16 33,27,28 HDO-2 10,85 |O/3SH_ | Host Data Bus: HD3-5 56,55,52 Bidirectional host data bus. HD6-8 50,47,9 HD9-11 6,4,54 HD12-13 51,49 HD14-15 45,43 Buffer Memory Interface MSA1 135 O/MOS_ | Memory Support Address: MSA2-8 137-143 Latched address used to decode accesses to the buffer MSAQ-10 118,119 SRAM. MSA11-12 123,120 MSA13-14 144,117 MSA15 1 MSD0-7 133-126 10/3SH | Memory Support Data Bus: MSD8-12 114-110 Bidirectional buffer SRAM data bus. MSD13-15 107-105 RCS12 125,115 O/MOS_ | SRAM Chip Select: RCS12 are asserted by the PENTIC for SRAM chip enable during buffer memory access. ROE 422 O/MOS_ | SRAM Output Enable: ROE is asserted by the PENTIC to strobe read data from the buffer SRAM. RWE 116 O/MOS_ | SRAM Write Enable: RWE is asserted by the PENTIC to strobe write data into the buffer SRAM. Fiash Memory Interface FDO-2 70-68 lO/3SH_ | Flash Memory Data Bus: FD3-4 66,65 Bidirectional flash memory data bus. FD5-7 63-61(Winbond Pin description, continued W89C925 Name Number Type Description FCS 59 O/MOS | Flash Memory Chip Select: FCS is asserted by the PENTIC for flash memory chip en- able during flash memory access. FOE 58 O/MOS_ | Flash Memory Output Enable: FOEis asserted by the PENTIC to strobe read data from the flash memory. EWE 57 O/MOS_ | Flash Memory Write Enable: FWE is asserted by the PENTIC to strobe write data into the flash memory. Network Interface TXOd+,- 102,99 O/MOS_ | Twisted Pair Transmit Outputs: TXO+,- 100,101 These high drive CMOS level outputs should be resistively combined externally to produce differential output signals with pre-equalization to compensate for Inter-Symboi Inter- ference(iSI) on the twisted-pair medium. Refer to W89C902 data sheet for more details. RXI+,- 95,96 I/DIF Twisted Pair Receive Inputs: These inputs are fed into a differential amplifier which passes valid data to the LCE core. TX+,- 85,84 O/DIF AUI Transmit Outputs: Differential transmit outputs. These pins should be con- nected to 270 ohm external pull-down resistors. RX+,- 89,88 DIF AUI Receive Inputs: Differential receive input pair from AUI interface. CD+,- 91,90 /DIF AUI Collision Inputs: Differential collision input pair from AUI interface. X1 81 VTTL Crystal Input 1: Master 20MHz clock input. X2 80 TTL Crystal Input 2: This pin should be connected to ground when a crystal is used and should be left unconnected when an oscillator is used. THIN 79 O/MOS_| Thin Cable Select: This pin is high when the PENTIC is configured for thin cable media. It can-be used as a switch to DC-DC converter for network media selection. TXLED 76 O/MOS | Transmit: This active high output is asserted for approximately 50mS whenever the PENTIC transmits data. RXLED 75 O/MOS_ | Receive: This active low output is asserted for approximately 50mS whenever the PENTIC receives data. Publication Release Date: March 1994 -5- Revision AlMinbond W89C925 Pin description, continued Name Number Type Description COLED 74 O/MOS | Collision: This active low output is asserted for approximately 50mS whenever the PENTIC detects a collision on the network. POLED 77 O/MOS | Polarity: This active low output is asserted whenever the PENTIC detects seven consecutive link pulses or three consecutive received packets with reversed polarity. __ 78 O/MOS_| Good Link: GDLNK This active low output is asserted if the PENTIC is in TPI mode, the link checking is enabled, and the link integrity is good or if the link checking is disabled. Power and Test Pins TEST 71 /MOS Test: When high, this pin is used for testing. Under normal op- eration, it should be left unconnected. [t has an internal 10K ohm pull-low resistor. PLLVcc 93 PLL Power Supply Pin: This pin supplies +5V to the PENTICs PLL inside the EN- DEC block. Analog layout rules and decoupling methods must be applied between this pin and PLLGND. PLLGND 98 PLL GND Pin: The ground to the PLL circuit. AVcc 82,83,92, Analog Power Supply Pins: 94,104 These pins supply +5V to the PENTIC's analog circuitry for the network interface. AGND 73,86 87, Analog GND Pins: 97,103 These pins are the ground to the analog circuitry. Vec 7,20,29, Digital Power Supply Pins: 48,64,108, These pins supply +5V to the PENTIC's digital circuitry. 121,134 GND 3,16,18, Digital Ground Pins: 31,46,53, These pins are the ground to the digital circuitry. 60,67,109, 124,136 NC 72 - Notes: {: input pin; O: output pin; 10: bidirectional input/output pin; TTL: TTL level buffer stage: ODH: open drain buffer stage; MOS: MOS level buffer stage; 3SH: tri-state buffer stage; DIF: differential buffer stage.(Winbond W89C925 SYSTEM DIAGRAM A _ HAn PH 128K X8 3K X8 FLASH SRAM P MEMORY C M Cc A FOn MSDn S MSAn L > O Osc. ii LEDs W89C925 > PENTI wegqAlll__yy CTRL BUS C UTP <> Fitter <<-_- [| THIN yy < Publication Release Date: March 1994 Revision Al| Winbond W89C925 BLOCK DIAGRAM MA CFR SRAM > MSR IF ~<+ VD LOCAL BUS Flash iD lO Core IF Regs Ports Controller <4 POMCIA BUS NETWORK IF COR FUNCTIONAL DESCRIPTION The W89C925 PENTIC is an integrated Ethernet controller which includes a W89C902 SLCT (composed of an LCE, SNA, and UTP Transceiver) and a PBI (PCMCIA Bus Interface) along with other registers necessary for configuration setting. Details concerning the PBI, LCE, SNA, and UTP module are described in the corresponding sections below. PBI The PBI block provides an interface between the LCE core, the buffer SRAMs, the CIS/ID/XIP flash memory, and the PCMCIA system bus. The following sections describe the configuration register files, the memory architecture, and the interface functions and operating modes of the PBI. Configuration Register File The PENTIC has a Configuration Register (CFR) and a Configuration Option Register (COR) for PCMCIA interface control and a Memory Select Register (MSR) for shared memory mode operation. The MSR is used only under shared memory mode and hence will be described in the subsection be- low entitled "Shared Memory Mode Operation."|, Winbond W89C925 CFR (Configuration Register) The CFR register can be read as a register of the LCE with an address at page 0, OAH. The read timing is exactly the same as that for an LCE register. To prevent accidental writes from the system, CFR must be read before being written to. Any write operation without a previous read will be re- garded as a write to the RBCRO register of the LCE. Access Address: |OBASE + OAH (for I/O mode) IOBASE + 1AH (for shared memory mode) Access Type: I/O Read/Write Bit Symbol Description 0-4 PHY01 These two bits determine to which type of medium the PENTIC is attached. The THIN pin will output low in 10BASE5 mode and high in 10BASE2 mode, according to PHY0,1. This can be used to control the DC-DC con- verter for electrical isolation. PHY1 PHYO Attached Medium Type TPI (1OBASE-T Compatible Squeich Level) Thin Ethernet (10BASE2) Thick Ethernet (10BASES5) 0 0 1 1 TP! (Reduced Squeich Level) =O. 0 The PENTIC also provides a UTP/BNC auto media-switching function. The physical interface will jump from UTP to BNC when the PENTIC is configured at UTP, the link checking is enabled, and the UTP path currently in use is broken. It will jump back immediately after the UTP path has been reconnected. When the physical interface is not configured at TP! or the link checking is disabled, the auto media-switching function will be disabled. GDLNK Writing a "1" to this bit will disable the link pulse generation, auto media- switching function, and link integrity check function. Writing a "0" to this bit will enable these functions. When GDLNK is read, it will indicate present link status. It is high if the PENTIC is in TPI mode, the link checking is en- abled, and the link integrity is good or if the link checking is disabled; other- wise, it is low. Reserved. Should be set to zero. ENHANCE When this bit is high, the PENTIC operates in the enhanced mode with up to 64KB packet buffer support; otherwise, the PENTIC supports only a 16KB buffer. PAGE This bit is used for swapping between the upper and lower eight bytes of the ID registers during Node ID setting. PAGE _ Selected ID Bytes 0 Upper eight bytes 1 Lower eight bytes Publication Release Date: March 1994 -9- Revision Al|, Winbond W89C925 CFR, Continued Bit Symbol Description 6-7 WAIT1,2 These two bits determine the wait state duration when a flash memory ac- cess is in progress. WAIT2 WAIT1 WAIT State Selection No WAIT state WAIT duration is longer than 100nS WAIT duration is longer than 150nS WAIT duration is longer than 200nS - =]2 0 0 =O 7-0 COR (Configuration Option Register) COR is located in attribute memory space, 100H. It is used for card initialization in according with PCMCIA R2.0. Access Address: Attribute MEMBASE + 100H Access Type: Read/Write Bit Symbol Description 0-2 IDX0-2 These three bits are used to indicate entry of the card configuration table located in the CIS (Card Information Structure; refer to PCMCIA R2.0) 3 MODE The PENTIC operates in I/O mode when MODE is low and in shared memory mode when MODE is high. 4-6 - Reserved. 7 SRESET A software reset is issued when a 1 is written to this bit. Writing a 0 to this bit will clear the software reset. Memory Architecture and Address Decoding Scheme The memory architecture for the PENTIC is composed of common memory space and attribute mem- ory space. The common memory comprises SRAM and flash memory for data buffers and future XiIP (Execute In Place; refer to PCMCIA R2.0) applications, respectively. The attribute memory consists of flash memory (or EEPROM), which is used for Card Information Structure (CIS) and Node ID stor- age. The system address decoding (system I/O address or system memory address decoding) is divided into base address decoding and offset decoding. The IOBASE (I/O base address) and MEMBASE (memory base address) are determined by the socket enabler and host PCMCIA interface controller; only the offset decoding is served by the PENTIC. This decoding scheme provides more flexible system design and makes LAN cards transparent to the driver. The following operating modes are available (the operating modes are described in detail in the corre- sponding sections below : 16-Bit I/O Mode (NE2000 compatible) 16-Bit [/O Enhanced Mode - 10 -" MMinbond W89C925 1 16-Bit Shared Memory Mode + 16-Bit Shared Memory Enhanced Mode 1/0 Mode Operation The 1/0 mode is selected by setting the third bit of the Configuration Option Register (COR) low. In this mode, the system will use only |/O commands to complete all transmit or receive operations for the network. The 1/O mode includes two submodes, NE2000 compatible mode and enhanced mode. Selection between these modes is performed by setting the fourth bit of the Configuration Register (CFR). The I/O mode provides two DMA channels for system access. The remote DMA moves data between system memory space and local memory space. The local DMA moves data between the FIFO of the SLCT and local memory space. However, since the SLCT can handle local DMA operations without system intervention (refer to the data sheet for the SLCT), the system only has to perform re- mote DMA reads/writes. In a transmit operation, the data should first be moved from the system to local buffer memory. This is simply an "OUT" command on the PC. Then the system orders the SLCT to start transmission, and the local DMA starts to move data from buffer memory to the transmit FIFO for transmission. ln a receive operation, the local DMA moves received data from the receive FIFO to the buffer and asserts /IREQ to the system when the buffer ring needs to be serviced. The system must move data out before the buffer ring overflows. This is done through a remote DMA read operation, which is simply a "IN" command on the PC. |/O Address Mapping for I/O Mode The register mapping of the W89C925 LCE block is register-level compatible with that of the W89C905. The I/O address mapping is as follows. 1/0 Mapping (NE2000 Compatible Mode/Enhanced Mode) System . Offset Name Operation 0000H LCE Core Slave Register O00OFH Registers Read/Write 0010H Remote DMA 0017H | Remote DMA Port Read/Write 0018H 001FH Reset Port Software Reset In 1/O mode, the PENTIC's register files are mapped into the lower 16 1O spaces: IOBASE to lIOBASE + OFH. Any read/write to the PENTIC's registers is an "IN"/"OUT" command to these addresses. The data width is 8 bits within the register region but 16 bits for the DMA port. Addresses IOBASE + 10H to IOBASE + 17H are mapped to the DMA port for the PENTIC. The remote DMA reads/writes refer "IN"/"OUT" commands to these addresses. Reading the address IOBASE + 18H~ + 1FH will result in a software reset being issued to the core coprocessor; the next write command will release the software reset. Publication Release Date: March 1994 i Revision Al| Winbond W89C925 Memory Address Mapping for 1/O Mode Although the I/O address mapping is the same for both compatibie and enhanced modes, the buffer memory space maps are slightly different. The memory space is 16K bytes for NE2000 compatible mode and 64K bytes for enhanced mode. For !/O mode, the lowest 32 bytes are allocated to ID registers. Although the ID registers occupy 32 address spaces, only 16 bytes of ID are used by the PENTIC, which performs only partial decoding. The memory map is summarized in the following table: Buffer Memory Mapping NIC Core . Memory Map Memory Type NE2000 Compatible NE2000 Enhanced 0000H . . O01FH Common/SRAM ID Registers ID Registers 0020H Aliased OOFFH Common/ Aliased ID Registers 0100H SRAM ID Registers 3FFFH 4000H Buffer SRAM Buffer SRAM 7FFFH Common/SRAM (16K x 8) (64K x 8) 8000H FFEFH Common/SRAM Unused Flash Memory Mapping (NE2000 Compatible/Enhanced Mode) over Memory Type Name 00000H Attribute/ CIS/ID/COR OFFFFH Flash (64K x 8) 10000H Common/ XIP (optional) 1FFFFH Flash (64K x 8) Note: Attribute offset 00100H is occupied by COR, which is actually resident in the PBI. Shared Memory Mode Operation The shared memory mode is selected by setting the third bit of the Configuration Option Register (COR) high. In this mode, the local memory is mapped as part of the system memory. The host fills the transmit buffer SRAM by a memory move operation when it requires data transmission and then issues a transmit command to the PENTIC. When it receives data, the PENTIC will generate an interrupt to the host by asserting IREQ when one or more packets have been received. The PENTIC will then place the packets into the shared memory. The host should check the shared memory and move the data back before the buffer ring overflows. Bus arbitration is performed between the host and LCE core for shared memory usage. When memory accesses are issued, the arbiter will grant the bus master an acknowledge signal, which is a BACK to the LCE or a WAIT signal to the host. There is no predefined priority in the PENTIC; bus arbitration is performed on a first-come, first-served basis. -1]2-A W89C925 There are two sub-modes from which to select: normal shared memory mode and enhanced mode. Selection between these modes is performed by setting the fourth bit of the Configuration Register (CFR). To implement the shared memory mode, the PENTIC has a memory select register (MSR) for memory mapping control. The MSR can be accessed through I/O commands. The contents of the MSR are described below. MSR (Memory Select Register) MSR is used for memory enable and software reset. It is located in I/O space, 00H, and can be ac- cessed only under shared memory mode. Access Address: lIOBASE + 00H Access Type: write-only Bit Symbol Description 0-5 - Reserved. 6 MEN If this bit is high, the buffer memory may be accessed by the system: if it is low, the buffer memory access is disabled. A shared memory mode software reset is issued when a 1 is written to this bit. Writing a 0 to this bit will clear the software reset. 7 SRESET 1/O Address Mapping for Shared Memory Mode The register mapping of the W89C925 LCE block is register-level compatible with that of the W89C905. The I/O address map for shared memory mode is summarized below: I/O Mapping (Shared Memory Mode/Enhanced Mode) System . Offset Name Operation 0000H MSR Register I/O Write 0008H . . OOOFH ID Registers I/O Read/Write 0010H LCE Core Slave Register 001FH Registers Read/Write in shared memory mode, the PENTIC's register files are mapped into the higher 16 |O spaces: IOBASE + 10 to IOBASE + 1FH. Any read/write to the PENTIC's registers is an "IN"/*OUT" command to these addresses. Addresses IOBASE + 08H to IOBASE + OFH are mapped to the ID registers for the PENTIC. MSR is located at |OBASE + 00H, which is used for shared memory mode control. All registers within the I/O map are 8 bits wide. Writing a "1" to the MSB of MSR will cause a software reset to be issued to the core coprocessor; writing a "0" to the same bit will release the software reset. Publication Release Date: March 1994 -13- Revision AlW89C925 Memory Mapping for Shared Memory Mode If the MEN bit in MSR is high, the PENTIC allows the system to access the local memory; if MEN is low, the PENTIC will disable all memory access. In 16-bit normal shared memory mode, the system can access the full 16K bytes of local memory. In 16-bit enhanced mode, the PENTIC allows the system to access 64K bytes of local memory. The PENTIC decodes only the offset address; base ad- dress decoding is under the socket enabler's control. Buffer Memory Mapping (Shared Memory Mode/Enhanced Mode) System Memory Type Shared Memory Shared Memory Offset ry "yp Mode Enhanced Mode 00000H Common/SRAM | Buffer SRAM(16K X 8) O3FFFH Buffer SRAM 04000H (64K X 8) OFFFFH Common/SRAM Unused Flash Memory Mapping (Shared Memory Mode/Enhanced Mode) System Offset Memory Type Name 00000H . CIS/ID/COR OFFFFH Attribute/Flash (64K x 8) 10000H XIP (optional) 1EFFFH Comman/Flash (64K x 8) Note: Attribute offset 00100H is occupied by COR, which is actually resident in the PBI. Power-On Reset Operation and Initialization The PENTIC clears all the registers for PBI and leaves the LCE core in an uninitialized state after a RESET signal is applied. The system must then configure the PENTIC's register files with appropri- ate settings before initializing the device. This is simply a software setting procedure which can easily be handled by drivers. To be recognized as a valid power-on reset, the RESET signal from the system slot must be active for at least 10uS. Attribute Memory Access and Node ID Setting Attribute Memory Access The contents of the attribute memory include the Card Information Structure (CIS) and Node ID. The contents of the attribute memory should be placed on the even addresses. A 150nS access time flash memory (or EEPROM) should be used. The programmable power supply to the flash memory is controlled by the host PCMCIA controller, which facilitates PC card circuit design. Up to 64K offset decoding range is provided to the attribute memory. Node ID Setting Each node in an Ethernet network has a unique six-byte ID. The ID of the PENTIC must be stored in the attribute memory. The ID may be placed anywhere in the attribute memory. If I/O mode is selected, the procedure for writing to the ID registers is as follows: -14-fou 4 , Winbond W89C925 Step 1. Change to shared memory mode. Step 2. Read ID contents from attribute memory. Step 3. Select page 0 by setting the PAGE bit of CFR to 0 and then writing the fotlowing positions: ID Register Address High Byte Low Byte IOBASE + 08H - ID-1st byte IOBASE + 09H - ID-2nd byte IOBASE + 0AH - ID-3rd byte IOBASE + 0BH - ID-4th byte IOBASE + 0CH - ID-5th byte IOBASE + ODH - ID-6th byte Step 4. Switch to page 1 and write the following positions. ID Register Address High Byte Low Byte IOBASE + 0EH - 57H IOBASE + OFH - 57H Step 5. Switch back to I/O Mode. If shared memory mode is selected, the procedure for writing to the ID registers is as follows: Step 1. Read ID contents from attribute memory. Step 2. Select page 0 by setting PAGE bit of CFR to 0 and then writing the following positions: ID Register Address High Byte Low Byte IOBASE + 08H - ID-1st byte IOBASE + 09H - ID-2nd byte IOBASE + OAH - ID-3rd byte IOBASE + 0BH - ID-4th byte IOBASE + OCH - ID-5th byte IOBASE + ODH - ID-6th byte jOBASE + 0EH - Board Type (05H) IOBASE + OFH - Check Sum XIP Architecture The PENTIC supports an optional XIP (Execute In Place) architecture for diskless applications. Card makers can build XIP procedures in the flash memory in the following range. For more details about XIP procedures, refer to PCMCIA R2.0. System Offset Memory Type Name 10000H - 1FFFFH Common/Flash XIP (optional)(64K x 8) Publication Release Date: March 1994 -15- Revision Al4 Winbond W89C925 Auto Media-Switching Function The PENTIC also provides a user-friendly auto media-switching function. If the PENTIC is configured at the TPI, the link checking is enabled, and the UTP link is broken, the PENTIC will detect the link status and switch to the BNC port immediately. After the UTP link is repaired, the PENTIC will detect the good link and switch back to the TPI again. If, however, the PENTIC is not configured at the TPI or the link checking is disabled, the auto media- switching function will be disabled. Bus Arbitration and State Diagram The PENTIC handles bus arbitration automatically. it can operate in four modes: idle state, slave read/write mode, DMA mode, and shared memory mode. The PENTIC controls the on-board devices by decoding these modes. At power-on, the PENTIC is in idle mode. If a register read/write command is issued, the PENTIC enters the slave read/write mode. If a local DMA or remote DMA (I/O mode only) is initiated by the PENTIC core coprocessor, the PENTIC enters DMA mode. A memory command will put the PENTIC into memory mode. At any given time, the PENTIC can be in only one state. The PENTIC handles state changes automatically. However, two events, such as a DMA command and a memory com- mand, may be requested at the same time; in this case, the PENTIC allocates the bus on a first- come, first-served basis. No predefined priority is set within the PENTIC. Register access Slave read/ write - Core Power-on Idle access ~ DMA operation Memory Memory operation access ry Op In cases where the system has no authority on the requested bus, the PENTIC will drive the WAIT pin low so that the system can insert wait states. After the PENTIC has released the bus authority, WAIT is deasserted to inform the system to stop inserting wait states. When flash memory accesses are in progress, the wait state duration can be selected by setting the WAIT1,2 bits of CFR (see the definition of CFR). This function is usually used to ensure compatiblity with different PCs. SLCT CORE FUNCTION The SLCT core coprocessor has five major logic blocks that control Ethernet operations: the register files, transmit logic, receive logic, FIFO logic, and DMA logic. The relationship between these blocks is depicted in the following block diagram. -16-, Winbond W89C925 Transmit PCMCIA Logic DMA SNA rice | incrace | | 18 I ex Logic afi nt Receive Logic Logic Be) Register fT ile Core Register Files The register files of the SLCT can be accessed in the same way as the configuration register CFR. The PENTIC should be in slave mode when the system accesses the register files. The command register (CR) determines the page number of the register file, while the system address HA<0:3> se- lects one register address from 01H to OFH (I/O mode) or from 10H to 1FH (shared memory mode). The PCMCIA IORD and IOWR are the read/write commands used to activate the I/O opera- tions. Refer to the W89C90 data sheet for more detailed information on the registers. DMA Interface Logic In 1/O mapping mode, the SLCT has two types of DMA operations, local DMA and remote DMA. In shared memory mode, only local DMA is available. Local DMA The local DMA transfers data from/to the on-board buffers. To perform data reception or transmission from/to remote nodes in the network, data must be moved from/to the FIFO. To enhance the effi- ciency of the transmission, the local DMA transfers data in batches: data is first collected and then moved in a batch. Each transfer can move up to 12 bytes of data at once. This scheme reduces time wasted in requesting the bus. A local DMA begins by requesting the local bus. If the local bus is available to the SLCT core, the bus arbiter inside the PENTIC responds at once by asserting the bus acknowledge (BACK, refer to LCE); if, on the other hand, the bus is currently authorized to another device, the arbiter will not assert the bus acknowledge and the SLCT must wait. Note that this sequence will not affect the host system or system bus signals. After each batch of data is transferred, the SLCT checks the FIFO threshold levels to determine if another batch transfer should be requested. Remote DMA A remote DMA can be performed only in I{O mode. The remote DMA moves data between the host and the local buffers. Unlike a local DMA, the remote DMA is word-wide: the remote DMA operation transfers one word each time. Since the remote DMA is simply a system I/O operation, the system bus is sometimes affected by a remote DMA. If the remote DMA is interleaved with other devices, WAIT is asserted to force the system to insert wait states. The PENTIC will automatically handle any arbitration necessary. Publication Release Date: March 1994 -17- Revision Al|, Winbond W89C925 FIFO Logic The SLCT has a 16-byte FIFO, which acts as an internal buffer to adjust transmission/reception speed differences between DMAs. The FIFO has FIFO threshold pointers to determine the level at which it should initiate a local DMA. The threshold levels are different for reception and transmission. The FIFO threshold levels are defined in the DCR register. The FIFO logic also provides a FIFO overrun and underrun signal for network management purposes. In a case where the receive packets are flooding into the FIFO but the SLCT still does not have bus authority, the FIFO may be overrun. On the other hand, if a transmission begins before data are fed into the FIFO, it may be underrun. Either case results in a network error. These types of cases can be prevented by changing the values of the FIFO thresholds. Normally, the data in the FIFO cannot be read; reading FIFO data during normal operation may cause WAIT to be asserted and the system to hang. In loopback mode, however, the SLCT allows FIFO data to be read by byte in order to check the correctness of the loopback operation. Receive Logic The receive logic is responsible for receiving the serial network data and packing the data in byte/word sequence. The receive logic thus has serial-to-parallel logic in addition to network detection capability. The PENTIC accepts both physical addresses and group addresses (multicast and broadcast ad- dresses). The SLCT extracts the address field from the serial input data. It then determines if the address is acceptable according to the configurations defined in the Receive Configuration Register (RCR). If the address is not acceptable, the packet reception is aborted. If the address is acceptable, the data packet is sent to the serial-to-parallel logic before being fed into the FIFO. After receiving a data packet, the SLCT automatically adds four bytes of data receive status, next packet pointer, and two bytes of receive byte count into the FIFO for network management purposes. The receive status contains the status of the incoming packet, so that the system can determine if the packet is desired. The next packet pointer points to the starting address of the next packet in the local receive ring. The receive byte count is the length of the packet received by the SLCT. Note that the receive byte count may be different from the "length" field specified in the Ethernet packet format. These four bytes of data will be transferred to the local buffer with the last batch of the local DMA. However, these four bytes are stored at the first four addresses of the packet. Transmit Logic The SLCT must be filled before transmission may begin. That is, the local DMA read must begin before the SLCT starts transmission. The SLCT first transmits 62 bits of preamble, then two bits of SFD, and then the data packet. The parallel-to-serial logic serializes the data from the FIFO into a data packet. After the data packet, the SLCT optionally adds four bytes of cyclic redundancy code (CRC) to the tail of the packet. A protocol PLA determines the network operations of the PENTIC. Collision detection, random back- off, and auto retransmit are implemented in the transmit logic. The protocol PLA ensures that the PENTIC follows IEEE 802.3 protocol. SNA Module The PENTIC also contains a serial network adaptor (SNA), which adapts the non-return-to-zero (NRZ) used in the core processor and host system to Manchester coded network symbols. Two kinds of in- terfacing signals are provided in the PENTIC: an AUI interface for Ethernet and a coaxial interface for Cheapernet. The SNA contains three blocks: a phase locked loop (PLL), a Manchester en- coder/decoder, and a collision decoder as well as crystal/oscillator logic. -18-', Winbond W89C925 TP OF gg tp) AUL fg} fee} | Transmit Coax Interface Logic 4 y Osc/ |g pp! Receive Crystal Logic The Manchester encoder/decoder handles code interpretation between NRZ signals and Manchester coded signals. The PLL locks the receiving signals with an internal voltage control oscillator (VCO) so that network noise can be eliminated before the signals enter the core coprocessor. The collision de- coder detects whether the network is in acollision status. The oscillator logic supplies the PENTIC with the required 20MHz clock. This clock also supplies the SNA clocking system. TWISTED PAIR INTERFACE MODULE Transmit Driver There are four signals for data transmission: the true and complement Manchester differential data (TXO+/-), and these signals delayed by 50 nS (TXOd+/-). These four signals are resistively combined, TXOd+ with TXO- and TXOd- with TXO+, to form two pre-equalized signals, which are then passed to the twisted-pair cable via a transmitter filter and an optional common mode choke. Smart Squeich The main function of this block is to determine when valid data are present on the differential receiving inputs (RXI+/-). To ensure that impulse noise on the medium will not be taken as valid data, this circuit adopts a combination of amplitude and timing measurements to determine the validity of the input signals. To qualify incoming data, the smart squelch circuitry monitors the signals for three peaks of alternating polarity that occur within a 400 nS window. Once this condition has been satisfied, the squelch level is reduced to minimize the noise effect and the chances of causing premature Start Of Idle (SOl) pulse detection. If the receiver detects activity on the receive line while packets are being transmitted, incoming data are qualified on five peaks of alternating polarity so as to prevent false collisions caused by impulse noise. The squelch function returns to its squelch state under any of the following conditions: A normal Start Of Idle (SO!) signal An inverted SOI signal A missing SOI! signal A missing SO} signal is assumed when neo transitions have occurred on the receiver for 175nS after a packet has arrived. In this case, a normal SOI! signal is generated and appended to the data. Publication Release Date: March 1994 - 19- Revision Al|, Winbond W89C925 Collision Detection The collision detection logic determines when transmit and receive signals occur simultaneously on the twisted pair cable. Collisions will not be reported when the device is in a link-fail state. The collision signal is also generated when the transceiver has detected a jabber condition or when the SQE test is being performed. SQE Test The Signal Quality Error (SQE) test is used to test the collision signaling circuitry in the twisted-pair transceiver module. Aftereach packet transmission, an SQE signal is sent to the SLCT. The SLCT expects this signal and will flag an error if it does not exist. Jabber The jabber timer monitors the transmitter and disables the transmission if the transmitter is active for greater than 26.2 mS. The jabber will re-enable the transmitter after the SLCT has been idle for at least 420 mS. Link Integrity During periods of inactivity, link pulses are generated and received by both MAUs at either end of the twisted pair to ensure that the cable has not been broken or shorted. A positive, 100 nS link integrity signal is generated by the twisted-pair transceiver and transmitted on the twisted pair cable every 13 mS during periods of no transmission activity. The PENTIC assumes a link-good state if it sees valid link pulse activity on the twisted-pair transceiver receive circuit. If neither receive data nor a link pulse (positive or negative) is seen within 105 mS, the PENTIC enters a link-fail state. When a link-fail condition occurs, four consecutive positive link pulses (or eight negative link pulses) must be received before a link-good condition is assumed. LCE CORE REGISTERS This section lists the access addresses and access types of the LCE core registers. Refer to the W89C90 or W89C901 data sheets for more detailed information. Page 0 Address Assignments (PS1= 0, PSO= 0) RAO-3 Read Write 00 Command (CR) Command (CR) 01 Current Local DMA Address 0 (CLDAO) Page Start Register (PSTART) 02 Current Local DMA Address 1 (CLDA1) Page Stop Register (PSTOP) 03 Boundary Pointer (BNRY) Boundary Pointer (BNRY) 04 Transmit Status Register (TSR) Transmit Page Start Address (TPSR) 05 Number of Collisions Register (NCR) Transmit Byte Count Register 0 (TBCRO) 06 FIFO (FIFO) Transmit Byte Count Register 1 (TBCR1) 07 Interrupt Status Register (ISR) Interrupt Status Register (ISR) 08 Current Remote DMA Address 0 (CRDAO) | Remote Start Address Register 0 (RSARO) 09 Current Remote DMA Address 1 (CRDA1) | Remote Start Address Register 1 (RSAR1) -20-{, Winbond Page 0 Address assignments, continued W89C925 (CNRT2) RAO-3 Read Write 0A Reserved Remote Byte Count Register 0 (RBCRO) 0B Reserved _ Remote Byte Count Register 1 (RBCR1) 0c Received Status Register (RSR) Receive Configuration Register (RCR) 0D (CNTRO) nter 0 (Frame Alignment Errors) Transmit Configuration Register (TCR) OE Tally Counter 1 (CRC Errors)(CNTR1) Data Configuration Register (DCR) OF Tally Counter 2 (Missed Packet Errors) Interrupt Mask Register (IMR) Page 1 Address Assignments (PS1= 0, PSO= 1) RAO-3 Read Write 00 Command (CR) Command (CR) 01 Physical Address Register 0 (PAR 0) Physical Address Register 0 (PAR 0) 02 Physical Address Register 1 (PAR 1) Physical Address Register 1 (PAR 1) 03 Physical Address Register 2 (PAR 2) Physical Address Register 2 (PAR 2) 04 Physical Address Register 3 (PAR 3) Physical Address Register 3 (PAR 3) 05 Physical Address Register 4 (PAR 4) Physical Address Register 4 (PAR 4) 06 Physical Address Register 5 (PAR 5) Physical Address Register 5 (PAR 5) 07 Current Page Register (CURR) Current Page Register (CURR) 08 Multicast Address 0 (MAR 0) Multicast Address 1 (MAR 0) 09 Multicast Address 1 (MAR 1) Multicast Address 1 (MAR 1) OA Multicast Address 2 (MAR 2) Multicast Address 2 (MAR 2) 0B Multicast Address 3 (MAR 3) Multicast Address 3 (MAR 3) oc Multicast Address 4 (MAR 4) Multicast Address 4 (MAR 4) oD Multicast Address 5 (MAR 5) Multicast Address 5 (MAR 5) OE Multicast Address 6 (MAR 6) Multicast Address 6 (MAR 6) OF Multicast Address 7 (MAR 7) Multicast Address 7 (MAR 7) -2)- Publication Release Date: March 1994 Revision Al(Winbond Page 2 Address Assignments (PS1= 1, PSO= 0) W89C925 RAO-3 Read Write 00 Command (CR) Command (CR) 01 Page Start Register (PSTART) Current Local DMA Address 0 (CLDAO) 02 Page Stop Register (PSTOP) Current Local DMA Address 1 (CLDA1) 03 Remote Next Packet Pointer Remote Next Package Pointer 04 Transmit Page Start Address (TPSR) Reserved 05 Local Next Packet Pointer Local Next Packet Pointer 06 Address Counter (Upper) Address Counter (Upper) 07 Address Counter (Lower) Address Counter (Lower) 08 Reserved Reserved 09 Reserved Reserved 0A Reserved Reserved 0B Reserved Reserved 0c Receive Configuration Register (RCR) Reserved oD Transmit Configuration Register (TCR) Transmit Configuration OE Data Configuration Register (DCR) Reserved OF Interrupt Mask Register (IMR) Reserved Note: Page 2 registers should be accessed only for diagnostic purposes. They should not be modified during operation. Page 3 should never be modified. -22-, Winbond W89C925 MECHANICAL SPECIFICATIONS The PENTIC is packaged in a 144-pin TQFP for PCMCIA Type II PC Card applications. Detailed dimensions are attached as follows. ie HHH Et ot W89C925F HYUHREEE C | E ee HEHEHE b JRA | | 5 Ny Pad Details T _ I= : aa ccc Pad Details Symbol mm D 22.0+0.4 D1 20.0 Typ. E 22.0+0.4 E1 20.0 Typ. L 0.5+0.1 L1 1.0+0.2 e 0.5 A 1.7 Max. Al 0.12+0.4 c 0.17 b 0.2 Typ. ccc 0.1 Publication Release Date: March 1994 - 23- Revision Al(Winbond ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings W89C925 Symbol Parameter Minimum Maximum Unit TA Operating Temperature 0 70 C TS Storage Temperature -55 150 sO Vop Supply Voltage -0.5 7.0 V VIN Input Voltage Vgg-0.5 Voptd.5 Vv Vout Output Voltage Vgg-0.5 Vppt0.5 Vv TL Lead Temperature (soldering . 250 C 10 seconds maximum) ESD ESD Tolerance 2K - V DC CHARACTERISTICS Power Supply: (Vop= 4.75 V, Vgg= 0 V, TA 0C to 70 C) Symbol Parameter Minimum | Maximum Unit IAVI Average Idle Supply Current _ 150 mA (Note 1) Average Transmit Supply . IAVT Current (Note 2) 250 mA Note 1: X1= 20MHz, ViIN= Vec or GND. Note 2:X1= 20MHz, normal transmitting operation. Note 2: X1= 20MHz, Digital: (Vpp= 4.75 V to 5.25 V, Vgg= 0 V, TA=0C to 70 C) Symbol Parameter Minimum | Maximum Unit Vin Low Input Voltage Vgg-0.5 08 mA Vin High Input Voltage 2.0 Vpp+0.5 V VoL Low Output Voltage (Vpp=4.5V) . 04 Vv Von High Output Voltage (Vpp=4.5V) 24 . V 4 Input Leakage Current (Note 1) . 40 WA li2 Input Leakage Current (Note 2) . 150 WA Output Leakage Current (V,_= lot 5.5V) 9 oo - 10 pA -~24-|, Winbond Note 1: All input pins except those stated in Note 2. Note 2: RXI+, RXI-, CD+, CD-, RX+, RX-, TEST. AUI: (Vpp= 4.75 V to 5.25 V, Vgg= 0 V, TA= 0 C to 70 C) W89C925 Symbol Parameter Minimum Maximum Unit Voo Differential Output Voltage (TX+/-) +/-550 +/-1200 mV Differential Output Voltage Imbalance Vos (TX+4/-) - 40 mV Vy Undershoot Voltage (TX+/-) - 100 mV Differential Squelch Threshold (CD+/-, Vos RX+/-) -175 -300 mV Differential Input Common Mode Volt- Vom | age (CD+/-, RX+/-) 0 5.8 mv Twisted Pair: (Vpp=4.75 V to 5.25 V, Vgg=0 V, TA=0 C to 70 C) Symbol Parameter Minimum Maximum Unit Ry, RxXI+/- Differential Input Resistance 3 - K Voip RXI+/- Open Circuit Input Voltage (bias) -2.75 Vpp-1.0 Vv RXI+/- Differential Input Voltage Range Vv -3.1 3.1 V TIV (Vpp= 5V) Vips RXI+/- Positive Squelched Threshold 300 585 mV Vins RXI+/- Negative Squelched Threshold -585 -300 mV Vopy RXI+/- Positive Unsquelched Threshold 200 350 mV ViInu RXI+/- Negative Unsqueiched Threshold -350 -200 mV VtoH TXO+/-, TXOD+/-High Output Voltage VppTP-0.44 VppTP V TXO+/-, TXOD+/- Low Output Voltage VroL (I= 32mA) VggTP Vogg I P+.44 Vv Ito TXO+/-, TXOD+/- Output Current - 32 mV Rio TXO+/-, TXOD+/- Output Resistance - 13.5 K -~25- Publication Release Date: March 1994 Revision Al(Winbond SWITCHING CHARACTERISTICS Memory Support Bus Access W89C925 T9 MSAn ifn > potty Rs 72 (eas LLL x 17 T lena = Valid , MSOn (Wt) ee * 8 Valid Symbol Description Min. Max Unit T1 MSA1 - 15 valid to RCS1,2 asserted. 0 - ns T2 MSA1 - 15 valid to ROE, RWE asserted. 10 - ns T3 MSA1 - 15 held valid after ROE, RWE 15 . ns deasserted. T4 RCS12 held valid after ROE, RWE 10 - ns deasserted. T5 ROE asserted to read data valid. - 55 ns T6 Read data hold from ROE deasserted. 0 - ns T7 Write data setup to RWE deasserted. 40 - ns T8 Write data hold from RWE deasserted. 5 - ns T9 Inter-transfer interval 350 - ns -26-{Winbond Flash Memory Access W89C925 HAn REG HDn (Read) HDn (Write) FCS FOE FDn (Read) FDn WAIT. csi = (Write) Valid Symbol Description Min. Max. Unit T1 HAO -16 valid to OE, WE asserted. 30 - ns T2 OE asserted to WAIT asserted (Note 1). . 35 ns T3 CE12 asserted to OE, WE asserted. 0 - ns T4 OE asserted to HDO - 7 read data valid (Note . 150 ns 3). TS Read data setup before WAIT deasserted 0 - ns (Note 1). _27- Publication Release Date: March 1994 Revision Al(Winbond Flash memory access, Continued W89C925 Symbol Description Min. Max. Unit T6 HDO - 7 read data hold from OE deasserted. 5 - ns 17 HDO - 7 write data setup before WE 80 . nS deasserted. T8 HDO - 7 write data hold from WE deasserted. 30 - ns T9 CE12 asserted to /FCS asserted. 30 ns T10 OE, WE asserted to FOE, FWE asserted. - 20 ns T11 FCS hold from CE1,2 deasserted. - 32 ns T12 FOE, FWE hold from OE, WE deasserted. - 27 ns 113 FOO - 7 read data valid to HDO - 7 read data ; 35 nS valid. T14 FDO - 7 read data hold from FOE deasserted. 0 - ns T15 HDO - 7 write data valid to FDO - 7 write data ; 60 ns valid. T16 FDO - 7 write data hold from FWE deasserted. 10 - ns T17 HAO - 16 hold valid from OE, WE deasserted. 20 - ns T18 CE12 hold valid from OE, WE deasserted. 20 - ns Ti9 OE, WE deasserted to next OE, WE 50 . ns asserted. T20 REG valid to OE, WE asserted (Note 4). 30 - ns T21 REG hold valid from OE, WE deasserted 20 . ns (Note 4). Note 1: This is the timing for insert wait states. WAIT is asserted if the core cannot service the access immediately; it will hold asserted until the core is ready, causing the system to insert wait states. Note 2: When wait states are inserted, read data valid is referenced to WAIT. Note 3: Read data is referenced to OE if no wait states are inserted. Note 4: REG is asserted for attribute memory access and I/O access; it is deasserted for common memory access. - 28 -W89C925 PCMCIA Bus Slave Access HAn y = = REG T2 #--- T13 _-+ T30 BE, WE TORD, TOWR 13 TW14 TiS 7 le ~ Torsi6 T4 \ TS * je T16 T6 Ta T9 ea LL. | T10 TH HD (Write) 7 Af Valid 5 Tir MSAN, Valid T28 T21 Tia} } RCSn T29 T19 722 723 720 T24 T26 Valid Le MSDn (Read) 125 127 Valid MSOn Pf 17 (Write) N Publication Release Date: March 1994 - 29- Revision AlPCMCIA Bus Slave Access W89C925 Symbol Description Min. Max. Unit Tia | HAO- 16 & REG valid to OE, WE asserted (Note 2). 20 . ns T1b HAO - 16 & REG valid to IORD,IOWR asserted (Note 3). 5 . ns T2a CE12 asserted to OE, WE asserted. 0 - ns T2b | CE12 asserted to ORD, IOWR asserted. 5 - ns T3a__| HAO- 16 valid to OE, WE asserted. 20 - ns T3b | HAO - 16 valid to IORD, IOWR asserted. 70 . ns 14 HAO - 16 valid to |O1S16 asserted (Note 4). - 30 ns T5 OE, IORD asserted to WAIT asserted (Note 1). - 35 ns T6 {ORD asserted to INPACK asserted (Note 8). - 30 ns T7a IORD asserted to HDO - 15 read data valid (Note 6). - 100 ns T7b OE asserted to HDO - 15 read data valid (Note 9). - 150 ns T8a WAIT deasserted to HDO - 15 memory read data valid . 0 ns (Note 1, 5). T8b an deasserted to HDO - 15 I/O read data valid (Note 1, - 35 ns T9 HDO - 15 read data hold after OE, IORD deasserted. 0 - ns T10 HDO - 15 write data setup before WE deasserted. 60 - ns T11a | HDO- 15 write data hold after WE deasserted. 30 - ns T11b HDO - 15 write data hold after IOWR deasserted. 30 - ns T12a | OE, WE deasserted to REG deasserted (Note 7). 20 - ns T12b | IORD, IOWR deasserted to REG deasserted (Note 7). 0 - ns T13a OE, WE deasserted to CE1,2 deasserted. 20 - ns T13b | JORD, IOWR deasserted to CE1,2 deasserted. 20 - ns T14a | OE, WE deasserted to HAO - 16 deasserted. 20 - ns -30-|, Winbond W89C925 PCMCIA Bus Slave Access, continued Symbol Description Min. Max. Unit T14b | IORD, IOWR deasserted to HAO - 16 deasserted. 20 - ns T15 HAO - 16 to IOIS16 deasserted (Note 4). - 35 ns T16 IORD deasserted to INPACK deasserted. - 45 ns T17 HAO - 16 valid to MSAO - 16 valid (Note 1, 2). - 35 ns T18 CE12 asserted to RCS1,2 asserted. - 30 ns T19 OE, WE asserted to ROE, RWE asserted (Note 2). - 30 ns T20 MSA1 - 15 valid to ROE, RWE asserted. 10 - ns 721 RCS1,2 asserted before WAIT deasserted (Notes 1,2). - 185 ns 122 ROE, RWE asserted before WAIT deasserted (Notes . 120 ns 1,2). T23 OE, WE deasserted to ROE, RWE deasserted. - 20 ns T24 MSD0 - 15 read data valid to HDO - 15 read data valid. - 60 ns T25 HDO - 15 write data valid to MSDO - 15 write data valid. - 90 ns T26 MSDO - 15 read data hold after ROE deasserted. 0 - ns T27 MSD0 - 15 write data hold after RWE deasserted. 10 - ns T28 HAO - 16 invalid to MSA1 - 15 invalid. - 20 ns T29 CE1,2 deasserted to RCS12 deasserted. - 10 ns T30 Command deasserted to next command asserted. 150 - ns Note 1: This is the timing for insert wait states. WAIT is asserted if the core cannot service the access immediately; it will hoid asserted until the core is ready, causing the system to insert wait states. Note 2. This is the timing for shared memory access. Note 3. This is the timing for I/O access. Note 4: |O!1S16 is asserted for 16-bit I/O transfers. Note 5: Read data valid is referenced to WAIT when wait states are inserted. Note 6: if no wait states are inserted, read data valid can be referenced from OE, IORD. Note 7: REG is asserted for !/O access and it is deasserted for common memory access. Publication Release Date: March 1994 -3]- Revision AlWinbond Note 8: INPACK is asserted only for I/O read operation. Note 9: This is a shared memory access without bus contention. Reset Timing Symbol Description Min. Max. Unit Tw Reset Pulse Width 10 - ps AUI Transmit Timing (End of Packet) W89C925 -32- Symbol Description Min. Max. Unit tou Transmit Output High before Idle 200 - ns ror Transmit Output Idle Time - 8000 ns|, Winbond AUI/TPI Receive Timing (End of Packet) W89C925 RX ove | | - Or \ - tEOP1 RX- or RXI- 0 0 | | ! RX+ or xe NZ NN tEOPO RX- or RXTI- / \ / \ / teop? | after Logic "0" (Note 1) Symbol Description Min. Max. Unit t 1 End of Packet Received Hold Time 200 . nS EOP after Logic "1" (Note 1) End of Packet Received Hold Time 200 - ns Note 1: This parameter is specified by design and is not tested. Link Pulse Timing __tLpw { tLPI | oe TO TXOd+ TXO TXOd _33- Publication Release Date: March 1994 Revision AlW89C925 Symbol Description Min. Max. Unit Let | Link Output Pulse Interval 8 24 ms lew | Link Output Pulse Width 80 120 ns TPI Transmit Timing (End of Packet) et TXOd Symbol Description Min. Max. | eae | tPOD FE ration ipa Delay (TXO+/- to s - - tETH1 aX oF Packet T ransmitted Hold Time 1 750 tETH2 ax (of Packet Transmitted Hold Time 2 00 Note 1: This parameter is specified by design and is not tested. ~34-4, Winbond W89C925 AC TIMING TEST CONDITIONS Input Test Pattern Levels (TTL/CMOS) GND to 3.0V Input Rise and Fall Times (TTL/CMOS) 5nsS Input and Output Pattern Reference Level (TTL/CMOS) 1.3V Input Waveform Level (Diff) -350 to -1315 mV Input and Output Waveform Reference Levels (Diff) 50% Point of the Differential 3-State Reference Levels Float (V) + 0.5V The above specifications are valid only if the mandatory isolations are properly employed and all dif- ferential signals are taken to the AUI of the pulse transformer. Output Load Veco SW1 (Note 3) [ OL T 0.1uF RL = 2.2K a Input | Output T CL (Note 1,2) Note 1: Load Capacitance employed depends on output type: For 3SL, MOS, TPI, AUL:CL= 50 pF For 3SH, OCH:CL= 240 pF Note 2: Specifications which measure delays from an active state to a High-Z state are not guaranteed by production testing, but are characterized using 240 pF and are correlated to determine true driver turn-off time by eliminating inherent R-C delay times in measurements. Publication Release Date: March 1994 -35- we Revision Al, Winbond W89C925 Note 3: SW1= Open for push-pull outputs during timing test. SW1= Veg for Vo, test. SW1= GND for Vo, test. SW1= Veg for High-Z to active low and active low to High-2 measurements. SW1= GND for High-Z to active high and active high to High-Z measurements. Pin Capacitance TA=25C f= 1 MHz Symbol Parameter Type Unit Cin Input Capacitance 7 pF Cout Output Capacitance 10 pF Derating Factor Output timing is measured with a purely capacitive load of 50pF or 240pF. The following correction factor can be used for other loads (note: this factor is preliminary): Derating for 3SL, MOS = -0.05 nS/pF Derating for 3SH, OCL, TP! = -0.03 nS/pF AUI Transmit Test Load TX+ 27uH TX- Note: In the above diagram, the TX+ and TX- signals are taken from the AUI side of the isolation (pulse transformer). The pulse transformer used for all testing is a 100uH +/- 0.1% Pulse Engineering PE64103. - 36-|, Winbond PS _ Winbond TTI ly . ~=6Electronics Corp. Bnei I CORPORATE HEADQUARTERS: Winbond Electronics (H.K.) Ltd. Winbond Electronics No. 4, Creation Rd. Ill Rm. 803, World Trade Square, Tower Il, (North America) Corp. Science-Based Industrial Park 423 Hoi Bun Road, Kwun Tong, 90 Wes! Plumeria Drive Hsinchu, Taiwan, R.O.C. Kowloon, Hong Kong San Jose, CA 95134 USA, TEL: 886-35-770066 TEL: 852-7516023-7 TEL: 1-408-943-6666 FAX: 886-35-789467 FAX: 852-7552064 FAX: 1-408-943-6668 TAIPE! SALES OFFICE: 44Fl, No. 115, Sec, 3, Min Sheng E. Rd. Taipei, Taiwan, R.O.C. TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 46485 WINTPE Note Alt data and specificahons are subject to change without notice