LP8552 www.ti.com SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 LP8552 High-Efficiency LED Backlight Driver for Notebooks Check for Samples: LP8552 FEATURES DESCRIPTION * The LP8552 is a white LED driver with integrated boost converter. It has six adjustable current sinks which can be controlled by PWM input or with I2Ccompatible serial interface. 1 2 * * * * * * * * * * High-Voltage DC/DC Boost Converter with Integrated FET with Four Switching Frequency Options: 156/312/625/1250 kHz 2.7V to 22V Input Voltage Range to Support 1x...5x cell Li-Ion Batteries Programmable PWM Resolution - 8 to 13 True Bit (Steady State) - Additional 1 to 3 Bits Using Dithering During Brightness Changes I2C-Compatible and PWM Brightness Control Automatic PWM & Current Dimming for Improved Efficiency PWM Output Frequency and LED Current set Through Resistors Optional Synchronization to Display VSYNC Signal 6 LED Outputs with LED Fault (Short/Open) Detection Low Input Voltage, Over-temperature, Overcurrent Detection and Shutdown Minimum Number of External Components DSBGA 25-bump Package, 2.466 x 2.466 x 0.6 mm APPLICATIONS * * Notebook and Netbook LCD Display LED Backlight LED Lighting The boost converter has adaptive output voltage control based on the LED driver voltages. This feature minimizes the power consumption by adjusting the voltage to lowest sufficient level in all conditions. LED outputs have 8-bit current resolution and up to 13-bit PWM resolution with additional 1-3 bit dithering to achieve smooth and precise brightness control. Proprietary Phase Shift PWM control is used for LED outputs to reduce peak current from the boost converter, thus making the boost capacitors smaller. The Phase Shifting scheme also eliminates audible noise. Automatic PWM dimming at lower brightness values and current dimming at higher brightness values can be used to improve the optical efficiency. Internal EEPROM is used for storing the configuration data. This makes it possible to have minimum external component count and make the solution very small. LP8552 has safety features which make it possible to detect LED outputs with open or short fault. As well low input voltage and boost over-current conditions are monitored and chip is turned off in case of these events. Thermal de-rating function prevents overheating of the device by reducing backlight brightness when set temperature has been reached. LP8552 is available in a DSBGA 25-bump package. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2011-2014, Texas Instruments Incorporated LP8552 SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 www.ti.com Typical Application VBATT L1 5.5V 22V CVLDO D1 CIN 15 eH 5V 10V 40V 210 mA 400 mA 39 pF 10 eF COUT 4.7 eF 1 eF VDDIO reference voltage VSYNC signal 100 nF VDDIO VLDO SW VIN FB VSYNC OUT1 FILTER 1 eF 120 k5 RISET OUT2 OUT3 LP8552 ISET RFSET OUT4 FSET OUT5 SCLK SDA OUT6 MCU PWM EN Can be left floating if not used FAULT GNDs Figure 1. Typical Application 2.7V 22V VBATT 5.5V 22V L1 D1 CIN 15 eH +5V input rail 10 25V, 180 mA 10 40V, 180 400 mA 39 pF 10 eF 1 eF VDDIO reference voltage VSYNC signal 100 nF VDDIO VLDO SW VIN COUT 4.7 eF CVLDO FB VSYNC OUT1 FILTER 1 eF 120 k5 RISET OUT2 ISET LP8552 OUT3 OUT4 RFSET FSET OUT5 SCLK SDA OUT6 MCU PWM EN Can be left floating if not used FAULT GNDs Figure 2. Typical Application for Low Input Voltage 2 Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 LP8552 www.ti.com SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 2.7V 22V VBATT 5.5V 22V L1 D1 CIN 15 eH +5V input rail 39 pF 10 eF 1 eF VDDIO reference voltage VSYNC signal 100 nF VLDO SW VIN COUT 4.7 eF CVLDO VDDIO 10 25V, 180 mA 10 40V, 180 400 mA FB VSYNC OUT1 FILTER 1 eF 120 k5 RISET OUT2 ISET LP8552 OUT3 OUT4 RFSET FSET OUT5 SCLK SDA OUT6 MCU PWM EN Can be left floating if not used FAULT GNDs Figure 3. Typical Application for Three Channels and Low Input Voltage NOTE Separate 5V rail to VLDO can be also used to improve efficiency for applications with higher battery voltage. No power sequencing requirements between VIN/VLDO and VBATT. Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 3 LP8552 SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 www.ti.com Connection Diagrams DSBGA 25-Bump Package 2.466 x 2.466 x 0.6mm, 0.5 mm pitch Package Number YZR002511A 1 2 3 4 5 5 A GND SW GND SW EN PWM FB FB B SW SW ISET FSET GND_S C VIN FILTER FAULT VDDIO D VLDO VSYNC SCLK E OUT6 OUT5 OUT4 3 2 1 PWM EN GND SW GND SW A GND_S FSET ISET SW SW B OUT3 OUT3 VDDIO FAULT FILTER VIN C SDA OUT2 OUT2 SDA SCLK VSYNC VLDO D GND_L OUT1 OUT1 GND_L OUT4 OUT5 OUT6 E Figure 4. Top View 4 Figure 5. Bottom View Pin Descriptions (1) (1) 4 Pin # Name A1 GND_SW Type G Description Boost switch ground A2 GND_SW G Boost switch ground A3 EN I Enable input pin A4 PWM A PWM dimming input. This pin must be connected to GND if not used. A5 FB A Boost feedback input B1 SW A Boost switch B2 SW A Boost switch B3 ISET A Set resistor for LED current. This pin can be left floating if not used. B4 FSET A PWM frequency set resistor. This pin can be left floating if not used. B5 GND_S G Signal ground C1 VIN P Input power supply up to 22V. If 2.7V VBATT < 5.5V (Figure 2) then external 5V rail must be used for VLDO and VIN. C2 FILTER A Low pass filter for PLL. This pin can be left floating if not used. C3 FAULT OD C4 VDDIO P Digital IO reference voltage (1.65V...5V) for I2C interface and PWM input. C5 OUT3 A Current sink output D1 VLDO P LDO output voltage. External 5V rail can be connected to this pin in low voltage application. D2 VSYNC I VSYNC input. This pin must be connected to GND if not used. D3 SCLK I Serial clock. This pin must be connected to GND if not used. D4 SDA I/O Serial data. This pin must be connected to GND if not used. D5 OUT2 A Current sink output E1 OUT6 A Current sink output E2 OUT5 A Current sink output E3 OUT4 A Current sink output E4 GND_L G LED ground E5 OUT1 A Current sink output Fault indication output. If not used, can be left floating. A: Analog Pin, G: Ground Pin, P: Power Pin, I: Input Pin, I/O: Input/Output Pin, O: Output Pin, OD: Open Drain Pin Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 LP8552 www.ti.com SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) -0.3V to +24.0V VIN VLDO -0.3V to +6.0V Voltage on Logic Pins (VSYNC, PWM, EN, SCLK, SDA) -0.3V to +6.0V -0.3V to VDDIO + 0.3V Voltage on Logic Pin (FAULT) Voltage on Analog Pins (FILTER, VDDIO, ISET, FSET) -0.3V to +6.0V -0.3V to +44.0V V (OUT1...OUT6, SW, FB) Continuous Power Dissipation (3) Internally Limited Junction Temperature (TJ-MAX) 125C Storage Temperature Range -65C to +150C Maximum Lead Temperature (Soldering) (4) Human Body Model ESD Rating (5) 2 kV Machine Model 200V Charged Device Model (1) (2) (3) (4) (5) 1 kV Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to the potential at the GND pins. Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 150C (typ.) and disengages at TJ = 130C (typ.). For detailed soldering specifications and information, please refer to Texas Instruments AN1112: DSBGA Wafer Level Chip Scale Package. Human Body Model, applicable standard JESD22-A114C. Machine Model, applicable standard JESD22- A115-A. Charged Device Model, applicable standard JESD22A-C101. Operating Ratings (1) (2) Input Voltage Range (VIN) Figure 1 5.5V to 22V Input Voltage Range (VIN + VLDO) Figure 2 4.5V to 5.5V VDDIO 1.65V to 5V V(OUT1...OUT6, SW, FB) 0V to 40V -30C to +125C Junction Temperature (TJ) Range Ambient Temperature (TA) Range (3) (1) (2) (3) -30C to +85C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to the potential at the GND pins. In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (JA), as given by the following equation: TA-MAX = TJ-MAX-OP - (JA x PD-MAX). Thermal Properties Junction-to-Ambient Thermal Resistance (JA), YZR002511A Package (1) (1) 40 to 73C/W Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 5 LP8552 SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 www.ti.com Electrical Characteristics (1) (2) Limits in standard typeface are for TA = 25C. Limits in boldface type apply over the full operating ambient temperature range (-30C TA +85C). Unless otherwise specified: VIN = 12.0V, VDDIO = 2.8V, CVLDO = 1 F, L1 = 15 H, CIN = 10 F, COUT = 10 F. RISET = 16 k (3) Symbol Parameter Standby Supply Current IIN Normal Mode Supply Current Condition Min Typ Internal LDO disabled EN=L and PWM=L LDO enabled, boost enabled, no current going through LED outputs 5 MHz PLL Clock 3.0 10 MHz PLL Clock 3.7 20 MHz PLL Clock 4.7 40 MHz PLL Clock Internal Oscillator Frequency Accuracy -4 -7 VLDO Internal LDO Voltage 4.5 ILDO Internal LDO External Loading (3) Units 1 A mA 6.7 fOSC (1) (2) Max +4 +7 5.0 % 5.5 V 5.0 mA All voltages are with respect to the potential at the GND pins. Min and Max limits are specified by design, test, or statistical analysis. Typical numbers are not verified, but do represent the most likely norm. Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics. Boost Converter Electrical Characteristics Symbol Parameter RDSON Switch ON Resistance VMAX Boost Maximum Output Voltage ILOAD Maximum Continuous Load Current VOUT/VIN Conversion Ratio fSW Switching Frequency VOV Over-voltage Protection Voltage tPULSE Switch Pulse Minimum Width tSTARTUP Startup Time (1) IMAX SW Pin Current Limit (1) 6 Condition Min Typ Max Units ISW = 0.5A 0.12 40 V 9.0V VBATT, VOUT = 35V 450 6.0V VBATT, VOUT = 35V 300 3.0V VBATT, VOUT = 25V 180 fSW = 1.25 MHz fSW = 625 kHz BOOST_FREQ BOOST_FREQ BOOST_FREQ BOOST_FREQ mA 10 15 = 00 = 01 = 10 = 11 no load BOOST_IMAX = 0 BOOST_IMAX = 1 156 312 625 1250 kHz VBOOST + 1.6V V 50 ns 6 ms 1.4 2.5 A Startup time is measured from the moment boost is activated until the VOUT crosses 90% of its target value. Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 LP8552 www.ti.com SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 LED Driver Electrical Characteristics Symbol Typ Max Units Leakage Current Outputs OUT1...OUT6, VOUT = 40V 0.1 1 A IMAX Maximum Source Current OUT1...OUT6 EN_I_RES = 0, CURRENT[7:0] = FFh 30 EN_I_RES = 1, CURRENT[7:0] = FFh 50 IOUT Output Current Accuracy (1) Output current set to 23 mA, EN_I_RES = 1 IMATCH Matching (1) Output current set to 23 mA, EN_I_RES = 1 0.5 fLED = 5 kHz, fPLL = 5 MHz 10 fLED = 10 kHz, fPLL = 5 MHz 9 fLED = 20 kHz, fPLL = 5 MHz 8 fLED = 5 kHz, fPLL = 40 MHz 13 fLED = 10 kHz, fPLL = 40 MHz 12 fLED = 20 kHz, fPLL = 40 MHz 11 PWM_FREQ[4:0] = 00000b PLL clock 5 MHz 600 PWM_FREQ[4:0] = 11111b PLL clock 5 MHz 19.2k Output current set to 20 mA 105 220 Output current set to 30 mA 160 290 ILEAKAGE PWMRES VSAT (2) (3) PWM Output Resolution (2) LED Switching Frequency (2) fLED (1) Parameter Saturation Voltage (3) Condition Min -3 -4 mA +3 +4 % % bits Hz mV Output Current Accuracy is the difference between the actual value of the output current and programmed value of this current. Matching is the maximum difference from the average. For the constant current sinks on the part (OUT1 to OUT6), the following are determined: the maximum output current (MAX), the minimum output current (MIN), and the average output current of all outputs (AVG). Two matching numbers are calculated: (MAX-AVG)/AVG and (AVG-MIN/AVG). The largest number of the two (worst case) is considered the matching figure. The typical specification provided is the most likely norm of the matching figure for all parts. Note that some manufacturers have different definitions in use. PWM output resolution and frequency depend on the PLL settings. Please see section "PWM Frequency Settings" for full description Saturation voltage is defined as the voltage when the LED current has dropped 10% from the value measured at 1V. PWM Interface Characteristics Symbol Parameter Condition Min Typ 0.1 Max Units 25 kHz fPWM PWM Frequency Range tMIN_ON Minimum Pulse ON time 1 tMIN_OFF Minimum Pulse OFF time 1 tSTARTUP Turn on delay from standby to backlight on PWM input active, EN pin rise from low to high 6 ms TSTBY Turn Off Delay PWM input low time for turn off, slope disabled 50 ms PWMRES PWM Input Resolution fIN fIN fIN fIN 10 11 12 13 bits < 9.0 kHz < 4.5 kHz < 2.2 kHz < 1.1 kHz Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 s 7 LP8552 SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 www.ti.com Under-Voltage Protection Symbol Parameter Condition Min UVLO[1:0] = 00 VUVLO VIN UVLO Threshold Voltage Typ Max Units Disabled UVLO[1:0] = 01, falling 2.55 2.70 2.94 UVLO[1:0] = 01, rising 2.62 2.76 3.00 UVLO[1:0] = 10, falling 5.11 5.40 5.68 UVLO[1:0] = 10, rising 5.38 5.70 5.98 UVLO[1:0] = 11, falling 7.75 8.10 8.45 UVLO[1:0] = 11, rising 8.36 8.73 9.20 V Logic Interface Characteristics Symbol Parameter Condition Min Typ Max Units 0.4 V 1.0 A 0.4 V 1.0 A 55000 Hz 0.2xVDDIO V Logic Input EN VIL Input Low Level VIH Input High Level 1.2 II Input Current -1.0 V Logic Input VSYNC VIL Input Low Level VIH Input High Level 2.2 II Input Current -1.0 fVSYNC Frequency Range 58 V 60 Logic Input PWM VIL Input Low Level VIH Input High Level II Input Current 0.8xVDDIO V -1.0 1.0 A 0.2xVDDIO V Logic Inputs SCL, SDA VIL Input Low Level VIH Input High Level II Input Current 0.8xVDDIO V -1.0 1.0 A 0.5 V 1.0 A Logic Outputs SDA, FAULT VOL Output Low Level IOUT = 3 mA (pull-up current) IL Output Leakage Current VOUT = 2.8V 8 Submit Documentation Feedback 0.3 -1.0 Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 LP8552 www.ti.com SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 I2C Serial Bus Timing Parameters (SDA, SCLK) (1) Symbol Limit Parameter Min fSCLK Clock Frequency 1 Hold Time (repeated) START Condition 2 3 Max 400 Units kHz 0.6 s Clock Low Time 1.3 s Clock High Time 600 ns 4 Setup Time for a Repeated START Condition 600 ns 5 Data Hold Time 50 ns 6 Data Setup Time 100 7 Rise Time of SDA and SCL 20+0.1Cb 300 ns 8 Fall Time of SDA and SCL 15+0.1Cb 300 ns 9 Set-up Time for STOP condition 600 ns 10 Bus Free Time between a STOP and a START Condition 1.3 s Cb (1) Capacitive Load Parameter for Each Bus Line Load of 1 pF corresponds to 1 ns. 10 ns 200 ns Verified by design. VDDIO = 1.65V to 5.5V. Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 9 LP8552 SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 www.ti.com Typical Performance Characteristics Unless otherwise specified: VBATT = 12.0V, CVLDO = 1 F, L1 = 33 H, CIN = 10 F, COUT = 10 F LED Drive Efficiency, fLED = 9.6 kHz LED Drive Efficiency, fLED = 9.6 kHz, L1 = 15 H 100 100 95 VIN = 12V 90 85 EFFICIENCY (%) EFFICIENCY (%) 95 VIN = 9V 80 75 85 VIN = 12V 80 75 70 70 65 65 60 VIN = 9V 90 60 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 DUTY CYCLE (%) DUTY CYCLE (%) Figure 6. Figure 7. Boost Converter Efficiency Battery Current 100 1,200 98 1,000 VBOOST = 35V 94 92 VBOOST = 40V 90 88 IBATT (mA) EFFICIENCY (%) 96 800 VBOOST = 40V VBOOST = 35V 600 400 86 VBOOST = 30V 84 200 82 VBOOST = 30V 80 LOAD = 150 mA 0 0 50 100 150 200 250 300 6 IOUT (mA) 8 10 12 14 16 18 20 VBATT (V) Figure 8. Figure 9. ILED vs. RISET Typical Waveforms, fLED = 9.6 kHz 50 ILED (mA) 40 30 CURRENT[7:0] = FFh 20 10 0 CURRENT[7:0] = 7Fh 0 10 20 30 40 50 60 70 80 90 100 RISET (k ) Figure 10. 10 Figure 11. Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 LP8552 www.ti.com SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 Typical Performance Characteristics (continued) Unless otherwise specified: VBATT = 12.0V, CVLDO = 1 F, L1 = 33 H, CIN = 10 F, COUT = 10 F Typical Waveforms, fLED = 9.6 kHz Boost Line Transient Response Figure 12. Figure 13. Optical Efficiency with 15" panel Input Power vs. Luminance 130 120 6 5 PWM AND CURR 50% MODE 110 100 90 80 15 inch panel, 23 mA current PWM AND CURR 25% MODE INPUT POWER (W) OPTICAL EFFICIENCY (Nits/W) 140 PWM 3 PWM 2 1 70 60 4 PWM AND CURRENT 50% MODE 15 inch panel, 23 mA current PWM AND CURRENT 25% MODE 0 0 10 20 30 40 50 60 70 80 90 100 0 PWM INPUT (%) 100 200 500 Figure 15. Luminance vs. PWM Input Power saved with PWM & current mode compared to PWM mode 35 30 PWM AND CURR 50% MODE 300 PWM 200 POWER SAVED (%) LUMINANCE (Nits) 400 Figure 14. 500 400 300 LUMINANCE (Nits) 100 25% MODE 25 20 15 50% MODE 10 5 0 PWM AND CURR 25% MODE 0 -5 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 PWM INPUT (%) PWM INPUT (%) Figure 16. Figure 17. Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 11 LP8552 SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 www.ti.com Modes of Operation RESET EN = H (pin) VLDO ok EN = L (VLDO low) or POR = H STANDBY EN = H (pin) and BL_CTL = 1 or PWM = H (pin) BL_CTL = 0 and PWM = L INTERNAL STARTUP SEQUENCE TSD = H VREF = 95% OK* ~2 ms Delay EN_BOOST = 1* EN_BOOST = 0* BOOST STARTUP EN_BOOST rising edge* ~4 ms Delay NORMAL MODE *) TSD = L RESET: In the RESET mode all the internal registers are reset to the default values. Reset is entered always when VLDO voltage is low. EN pin is enable for the internal LDO. Power On Reset (POR) will activate during the chip startup or when the supply voltage VLDO fall below POR level. Once VLDO rises above POR level, POR will inactivate and the chip will continue to the STANDBY mode. STANDBY: The STANDBY mode is entered if the register bit BL_CTL is LOW and external PWM input is not active and POR is not active. This is the low power consumption mode, when only internal 5V LDO is enabled. Registers can be written in this mode and the control bits are effective immediately after start up. STARTUP: When BL_CTL bit is written high or PWM signal is high, the INTERNAL STARTUP SEQUENCE powers up all the needed internal blocks (VREF, Bias, Oscillator etc.). Internal EPROM and EEPROM are read in this mode. To ensure the correct oscillator initialization etc., a 2 ms delay is generated by the internal-state machine. If the chip temperature rises too high, the Thermal Shutdown (TSD) disables the chip operation and STARTUP mode is entered until no thermal shutdown event is present. BOOST STARTUP: Soft start for boost output is generated in the BOOST STARTUP mode. The boost output is raised in low current PWM mode during the 4 ms delay generated by the state-machine. All LED outputs are off during the 4 ms delay to ensure smooth startup. The Boost startup is entered from Internal Startup Sequence if EN_BOOST is HIGH. NORMAL: During NORMAL mode the user controls the chip using the external PWM input or with Control Registers through I2C. The registers can be written in any sequence and any number of bits can be altered in a register in one write. 12 Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 LP8552 www.ti.com SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 Functional Overview Device Description LP8552 is a high-voltage LED driver for medium sized LCD backlight applications. It includes high-voltage boost converter. Boost voltage automatically sets to the correct level needed to drive the LED strings. This is done by monitoring LED output voltage drop in real time. Six LED outputs are driven either with constant current sinks with PWM control or by controlling both PWM and current. Constant current value is set with EEPROM bits and with RISET resistor. Brightness (PWM) is controlled either with I2C register or with PWM input. PWM frequencies are set with EEPROM bits and with RFSET resistor. Special Phase-Shift PWM mode can be used to reduce boost output current peak, thus reducing output ripple, capacitor size and audible noise. With LP8552 it is possible to synchronize the PWM output frequency to VSYNC signal received from video processor. Internal PLL ensures that the PWM output clock is always synchronized to the VSYNC signal. Special dithering mode makes it possible to increase output resolution during fading between two brightness values and by this making the transition look very smooth with virtually no stepping. Transition slope time can be adjusted with EEPROM bits. Safety features include LED fault detection with open and short detection. LED fault detection will prevent system overheating in case of open in some of the LED strings. Chip internal temperature is constantly monitored and based on this LP8552 can reduce the brightness of the backlight to reduce thermal loading once certain trip point is reached. Threshold is programmable in EEPROM. If chip internal temperature reaches too high, the boost converter and LED outputs are completely turned off until the internal temperature has reached acceptable level. Boost converter is protected against too high load current and over-voltage. LP8552 notifies the system about the fault through I2C register and with FAULT pin. EEPROM programmable functions include: * PWM frequencies * Phase shift PWM mode * LED constant current * Boost output frequency * Temperature thresholds * Slope for brightness changes * Dithering options * PWM output resolution * Boost control bits External components RISET and RFSET can also be used for selecting the output current and PWM frequencies. Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 13 LP8552 SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 www.ti.com BLOCK DIAGRAM VIN VLDO VIN SW LDO OSC TSD VSYNC TEMP SENSOR FB BOOST GND_SW OUT1 VSYNC FILTER PLL OUT2 OUT3 VDDIO PWM PWM DETECTOR OUT4 LED DRIVERS OUT5 OUT6 MCU SCLK SDA LOGIC 2 I C/ INTERFACE ISET RISET FSET GND_LED FAULT RFSET EN EEPROM GND Clock Generation LP8552 has an internal 5 MHz oscillator which is used for clocking the boost converter, state machine, PWM input duty cycle measurement, internal timings such as slope time for output brightness changes. The internal clock can be used for generating the PWM output frequency. In this case the 5 MHz clock can be multiplied with the internal PLL to achieve higher resolution. The higher the clock frequency for PWM generation block, the higher the resolution; however, the tradeoff is higher IQ of the part. Clock multiplication is set with <PWM_RESOLUTION[1:0]> EEPROM Bits. The PLL can also be used for generating the required PWM generation clock from the VSYNC signal. This makes sure that the LED output PWM is always synchronized to the VSYNC signal and there is no clock variation between LCD display video update and the LED backlight output frequency. Also HSYNC signal up to 55 kHz can be used. PLL has an internal counter which has 13-bit control <PLL[12:0]> to achieve correct output clock frequency based on the VSYNC frequency. For the PLL it can take couple of seconds to synchronize to 60 Hz VSYNC signal in startup before this correct PWM clock frequency is generated from internal oscillator. FILTER pin component selection affects the time it takes from the PLL to lock to VSYNC signal. Special logic is implemented for allowing steady clock frequency even if there are missing VSYNC pulses. In case pulses are randomly left out, the LP8552 can generate the pulses internally while keeping the same PWM output frequency. When VSYNC pulses are available again, the internal logic will automatically switch to the external VSYNC clock without glitch. 14 Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 LP8552 www.ti.com SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 PWM_FREQ[4:0] or External VSYNC 60 Hz EN_VSYNC VBOOST set resistor RFSET PSPWM 0/1 PLL Phase Detector 5MHz internal oscillator 5 MHz...40 MHz Filter VCO PWM generation LED Drivers 1-6 PLL[12:0] BOOST_FREQ N = 4, 8, 16, 32 Divider 1/N Counter 1/N State machine, PWM input, internal timings, Slope etc. Boost PWM_RESOLUTION[1:0] Figure 18. Principle of the Clock Generation Brightness Control Methods LP8552 controls the brightness of the backlight with PWM. PWM control is received either from PWM input pin or from I2C register bits. The PWM source selection is done with <BRT_MODE[1:0]> bits as follows: BRT_MODE[1] BRT_MODE[0] PWM source 0 0 PWM input pin duty cycle control. Default. 0 1 PWM input pin duty cycle control. 1 0 Brightness register 1 1 PWM direct control (PWM in = PWM out) PWM INPUT DUTY CYCLE With PWM input pin duty cycle control the output PWM is controlled by PWM input duty cycle. PWM detector block measures the duty cycle in the PWM pin and uses this 13-bit value to generate the output PWM. Output PWM can have different frequency than input in this mode, and also phase shift PWM mode can be used. Slope and dither are effective in this mode. PWM input resolution is defined by the input PWM clock frequency. BRIGHTNESS REGISTER CONTROL With brightness register control the output PWM is controlled with 8-bit resolution <BRT7:0> register bits. Phase shift scheme can be used with this, and the output PWM frequency can be freely selected. Slope and dither are effective in this mode. PWM DIRECT CONTROL With PWM direct control the output PWM will directly follow the input PWM. Due to the internal logic structure the input is anyway clocked with the 5 MHz clock or the PLL clock. PSPWM mode is not possible in this mode. Slope and dither are not effective in this mode. PWM CALCULATION DATA FLOW Below is a flow chart of the PWM calculation data flow. In PWM direct control mode most of the blocks are bypassed and this flow chart does not apply. Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 15 LP8552 SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 HYSTERESIS 5 MHz [1:0] clock PWM input signal PWM detector BRT_MODE [1:0] 13-bit Temperature sensor Brightness register Brightness control www.ti.com PWM_FREQ[4:0] 13-bit Resolution selector SLOPE[3:0] 8...13-bit 12-bit I_SLOPE[1:0] 16-bit Sloper PWM & Current Control DITHER[1:0] 8...16-bit 16-bit Dither 13-bit EN_PWM_&_I_CTRL PWM_RESOLUTION [1:0] 0/1 ... LED Drivers 1-6 PWM Counter MODE_25/50%_SEL 8-bit PWM comparator PLL clock 5...40 MHz Figure 19. PWM Calculation Data Flow PWM DETECTOR PWM detector block measures the duty cycle of the input PWM signal. Resolution depends on the input signal frequency. Hysteresis selection sets the minimum allowable change to the input. If smaller change is detected, it is ignored. With hysteresis the constant changing between two brightness values is avoided if there is small jitter in the input signal. BRIGHTNESS CONTROL Brightness control block gets 13-bit value from the PWM detector, 12-bit value from the temperature sensor as well as 8-bit value from the brightness register. <BRT_MODE[1:0]> selects whether to use PWM input duty cycle value or the brightness register value as described earlier. Based on the temperature sensor value the duty cycle is reduced if the temperature has reached the temperature limit set to the <TEMP_LIM[1:0]> EEPROM bits. RESOLUTION SELECTOR Resolution selector takes the necessary MSB bits from the input data to match the output resolution. For example, if 11-bit resolution is used for output, then 11 MSB bits are selected from the input. Dither bits are not taken into account for the output resolution. This is to make sure that in steady state condition, there is no dithering used for the output. SLOPER Sloper makes the smooth transition from one brightness value to another. Slope time can be adjusted from 0 to 500 ms with <SLOPE[3:0]> EEPROM bits. The sloper output is 16-bit value. PWM & CURRENT CONTROL Automatic PWM & current control improves the optical efficiency of the LEDs by using PWM control with small brightness values and current control with bigger values. <EN_PWM_&_I_CTRL > EEPROM bit selects whether the PWM & current control is used instead of PWM control or not. PWM to current dimming switch point can be set to 25% or 50% of the brightness range with <MODE_25/50_SEL> EEPROM bit. Current slope can be adjusted by using the <I_SLOPE[1:0]> EEPROM bits. DITHER With dithering the output resolution can be "artificially" increased during sloping from one brightness value to another. This way the brightness change steps are not visible to eye. Dithering can be from 0 to 3 bits, and is selected with <DITHER[1:0]> EEPROM bits. PWM COMPARATOR The PWM counter clocks the PWM comparator based on the duty-cycle value received from Dither block. Output of the PWM comparator controls directly the LED drivers. If PSPWM mode is used, then the signal to each LED output is delayed certain amount. CURRENT SETTING Maximum current of the LED outputs is controlled with CURRENT[7:0] EEPROM register bits linearly from 0 to 30 mA. If <EN_I_RES> = 1 the maximum LED output current can be scaled also with external resistor, RISET. RISET controls the LED current as follows: 16 Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 LP8552 www.ti.com SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 (1) Default value for CURRENT[7:0] = 7Fh (127d). Therefore, the output current can be calculated as follows: (2) E.g., If 16 k RISET resistor is used, then the LED maximum current is 23 mA. Note: formula is only approximation for the actual current. PWM FREQUENCY SETTING PWM frequency is selected with PWM_FREQ[4:0] EEPROM register. If PLL clock frequency multiplication is used, it will affect the output PWM frequency as well. <PWM_RESOLUTION[1:0]> EEPROM bits will select the PLL output frequency and hence the PWM frequency and resolution. Below are listed PWM frequencies with <EN_VSYNC]> = 0. PWM resolution setting affects the PLL clock frequency (5 MHz...40 MHz). Highlighted frequencies with boldface can be selected also with external resistor RFSET. To activate RFSET frequency selection the <EN_F_RES> EEPROM bit must be 1. PWM_RES[1:0] 00 01 10 11 PWM_FREQ[4:0] 5 MHz 10 MHz 20 MHz 40 MHz Resolution (bits) 11111 19232 - - - 8 11110 16828 - - - 8 11101 14424 - - - 8 11100 12020 - - - 8 11011 9616 19232 - - 9 11010 7963 15927 - - 9 11001 6386 12771 - - 9 11000 4808 9616 19232 - 10 10111 4658 9316 18631 - 10 10110 4508 9015 18030 - 10 10101 4357 8715 17429 - 10 10100 4207 8414 16828 - 10 10011 4057 8114 16227 - 10 10010 3907 7813 15626 - 10 10001 3756 7513 15025 - 10 10000 3606 7212 14424 - 10 01111 3456 6912 13823 - 10 01110 3306 6611 13222 - 10 01101 3155 6311 12621 - 10 01100 3005 6010 12020 - 10 01011 2855 5710 11419 - 10 01010 2705 5409 10818 - 10 01001 2554 5109 10217 - 10 01000 2404 4808 9616 19232 11 00111 2179 4357 8715 17429 11 00110 1953 3907 7813 15626 11 00101 1728 3456 6912 13823 11 00100 1503 3005 6010 12020 11 00011 1202 2404 4808 9616 12 00010 1052 2104 4207 8414 12 00001 826 1653 3306 6611 12 00000 601 1202 2404 4808 13 Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 17 LP8552 SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 www.ti.com RFSET resistance values with corresponding PWM frequencies: PWM_RES[1 :0] 00 01 10 11 RFSET (k) 5 MHz Clock Resolution 10 MHz Clock Resolution 20 MHz Clock Resolution 40 MHz Clock Resolution 10...15 19232 8 19232 9 19232 10 19232 11 26...29 16828 8 15927 9 16227 10 17429 11 36...41 14424 8 12771 9 14424 10 15626 11 50...60 12020 8 9616 10 12020 10 12020 11 85...100 9616 9 8715 10 9616 11 9616 12 135...150 7963 9 7813 10 7813 11 8414 12 200...300 6386 9 6311 10 6010 11 6811 12 450... 4808 10 4808 11 4808 12 4808 13 PHASE SHIFT PWM SCHEME Phase shift PWM scheme allows delaying the time when each LED output is active. When the LED output are not activated simultaneously, the peak load current from the boost output is greatly decreased. This reduces the ripple seen on the boost output and allows smaller output capacitors. Reduced ripple also reduces the output ceramic capacitor audible ringing. PSPWM scheme also increases the load frequency seen on boost output by x6 and thus transfers the possible audible noise to so high frequency that human ear cannot hear it. Description of the PSPWM mode is seen on the following diagram. PSPWM mode is enabled by setting <EN_PSPWM> EEPROM bit to 1. Shift time is the delay between outputs and it is defined as 1 / (fPWM x 6). If the <EN_PSPWM> bit is 0, then the delay is 0 and all outputs are active simultaneously. Shift time tSHIFT = 1/(FPWM x 6) Cycle time 1/(FPWM) OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 Figure 20. Phase Shift PWM Mode 18 Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 LP8552 www.ti.com SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 SLOPE AND DITHERING During transition between two brightness (PWM) values special dithering scheme is used if the slope is enabled. It allows increased resolution and smaller average steps size. Dithering is not used in steady-state condition. Slope time can be programmed with EEPROM bits <SLOPE[3:0]> from 0 to 500 ms. Same slope time is used for sloping up and down. Advanced slope makes brightness changes smooth for the eye. Dithering can be programmed with EEPROM bits <DITHER[1:0]> from 0 to 3 bits. Example below is for 1-bit dithering; e.g. for 3bit dithering, every 8th pulse is made 1 LSB longer to increase the average value by 1/8 of LSB. Brightness (PWM) Sloper Input Brightness (PWM) PWM Output Time Steady state without dithering Normal slope If dither is enabled it will be used during transition to enable smooth effect Advanced slope Time Slope Time Figure 21. Sloper Operation PWM value 510 (10-bit) +1 LSB PWM value 510 1/2 (10-bit) PWM value 511 (10-bit) Figure 22. Example of the Dithering, 1-bit dither, 10-bit resolution DRIVER HEADROOM CONTROL Driver headroom can be controlled with <DRV_HEADR[2:0]> EEPROM bits. Driver headroom control sets the minimum threshold for the voltage over the LED output which has the smallest driver headroom and controls the boost output voltage accordingly. Boost output voltage step size is 125 mV. The LED output which has the smallest forward voltage is the one which has highest VF across the LEDs. The strings with highest forward voltage is detected automatically. To achieve best possible efficiency smallest possible headroom voltage should be selected. If there is high variation between LED strings, the headroom can be raised slightly to prevent any visual artifacts. Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 19 LP8552 SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 www.ti.com EEPROM EEPROM memory stores various parameters for chip control. The 64-bit EEPROM memory is organized as 8 x 8 bits. The EEPROM structure consists of a register front-end and the non-volatile memory (NVM). Register data can be read and written through the serial interface, and data will be effective immediately. To read and program NVM, separate commands need to be sent. Erase and program voltages are generated on-chip charge pump; no other voltages than normal input voltage are required. A complete EEPROM memory map is shown in the chapter LP8552 EEPROM Memory Map. NOTE EEPROM NVM can be programmed or read by customer for bench validation. Programming for production devices should be done in TI production test, where appropriate checks will be performed to confirm EEPROM validity. Writing to EEPROM Control register of production devices (for burning or reading EEPROM) is not recommended. If special EEPROM configuration is required, please contact the TI Sales Office for availability. EE_PROG = 1 EEPROM NVM EEPROM REGISTERS Address A0h...A7h 2 I C 8 x 8 bits Startup or EE_READ=1 User Device Control REGISTERS ADDRESS 00h...72h Device Control Boost Converter OPERATION The LP8552 boost DC/DC converter generates a 10...40V supply voltage for the LEDs from 2.7...22V input voltage. The output voltage can be controlled either with EEPROM register bits <VBOOST[4:0]>, or automatic adaptive voltage control can be used. The converter is a magnetic-switching PWM mode DC/DC converter with a current limit. The topology of the magnetic boost converter is called CPM (current programmed mode) control, where the inductor current is measured and controlled with the feedback. Switching frequency is selectable between 156 kHz and 1.25 MHz with EEPROM bit <BOOST_FREQ[1:0]>. When <EN_BOOST> EEPROM register bit is set to 1, then boost will activate automatically when backlight is enabled. In adaptive mode the boost output voltage is adjusted automatically based on LED driver headroom voltage. Boost output voltage control step size is in this case 125 mV to ensure as small as possible driver headroom and high efficiency. Enabling the adaptive mode is done with <EN_ADAPT> EEPROM bit. If boost is started with adaptive mode enabled, then the initial boost output voltage value is defined with the <VBOOST[4:0]> EEPROM register bits in order to eliminate long output voltage iteration time when boost is started for the first time. The following figure shows the boost topology with the protection circuitry: 20 Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 LP8552 www.ti.com SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 FB SW Startup VREF Light Load OVP R R + gm Boost output voltage adjustment Active Load + R S Osc/ ramp R Switch Driver OCP 6 + - Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 21 LP8552 SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 www.ti.com PROTECTION Three different protection schemes are implemented: 1. Over-voltage protection, limits the maximum output voltage. - Over-voltage protection limit changes dynamically based on output voltage setting. - Keeps the output below breakdown voltage - Prevents boost operation if battery voltage is much higher than desired output. 2. Over-current protection, limits the maximum inductor current. 3. Duty cycle limiting. MANUAL OUTPUT VOLTAGE CONTROL User can control the boost output voltage with <VBOOST[4:0]> EEPROM register bits when adaptive mode is disabled. VBOOST[4:0] Voltage (typical) Bin Dec Volts 00000 0 10 00001 1 11 00010 2 12 00011 3 13 00100 4 14 ... ... ... 11101 29 39 11110 30 40 11111 31 40 ADAPTIVE BOOST CONTROL Adaptive boost control function adjusts the boost output voltage to the minimum sufficient voltage for proper LED driver operation. The output with highest VF LED string is detected and boost output voltage adjusted accordingly. Driver headroom can be adjusted with <DRIVER_HEADR[2:0]> EEPROM bits from ~300 mV to 1200 mV. Boost adaptive control voltage step size is 125 mV. Boost adaptive control operates similarly with and without PSPWM. VBOOST Driver headroom OUT1 string VF OUT6 string VF OUT5 string VF OUT4 string VF OUT3 string VF OUT2 string VF OUT1 string VF VBOOST Time Figure 23. Boost Adaptive Control Principle with PSPWM 22 Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 LP8552 www.ti.com SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 Fault Detection LP8552 has fault detection for LED fault, low-battery voltage, over-current and thermal shutdown. The open drain output pin (FAULT) can be used to indicate occurred fault. The cause for the fault can be read from status register. Reading the fault register will also reset the fault. Setting the EN pin low will also reset the faults, even if an external 5V line is used to power VLDO pin. LED FAULT DETECTION With LED fault detection, the voltages across the LED drivers are constantly monitored. Shorted or open LED string is detected. If LED fault is detected: * The corresponding LED string is taken out of boost adaptive control loop; * Fault bits are set in the fault register to identify whether the fault has been open/short and how many strings are faulty; and * Fault open-drain pin is pulled down. LED fault sensitivity can be adjusted with <LED_FAULT_THR> EEPROM bit which sets the allowable variation between LED output voltage to 3.3V or 5.3V. Depending on application, and how much variation there can be in normal operation between LED string forward voltages, this setting can be adjusted. Fault is cleared by setting EN pin low or by reading the fault register. By default the LED fault detection is active only in automatic PWM & current dimming mode. If LED fault detection is needed in PWM dimming mode, please contact a Texas Instruments representative for guidance. UNDER-VOLTAGE DETECTION LP8552 has detection for too-low VIN voltage. Threshold level for the voltage is set with EEPROM register bits as seen in the following table: UVLO[1:0] Threshold (V) 00 OFF 01 2.7V 10 5.4V 11 8.1V When under-voltage is detected the LED outputs and boost will shutdown, FAULT pin is pulled down and corresponding fault bit is set in fault register. LEDs and boost will start again when the voltage has increased above the threshold level. Hysteresis is implemented to threshold level to avoid continuous triggering of fault when threshold is reached. Fault is cleared by setting EN pin low or by reading the fault register. OVER-CURRENT PROTECTION LP8552 has detection for too-high loading on the boost converter. When over-current fault is detected, the LP8552 will shut down. Fault is cleared by setting EN pin low or by reading the fault register. Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 23 LP8552 SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 www.ti.com DEVICE THERMAL REGULATION LP8552 has an internal temperature sensor which can be used to measure the junction temperature of the device and protect the device from overheating. During thermal regulation, LED PWM is reduced by 2% of full scale per C whenever the temperature threshold is reached. Temperature regulation is enabled automatically when chip is enabled. 11-bit temperature value can be read from Temp MSB and Temp LSB registers; MSB should be read first. Temperature limit can be programmed in EEPROM as shown in the following table. Thermal regulation function does not generate fault signal. TEMP_LIM[1:0] Over-Temp Limit (C) 00 OFF 01 110 10 120 11 130 THERMAL SHUTDOWN If the LP8552 reaches thermal shutdown temperature (150C ) the LED outputs and boost will shut down to protect it from damage. Also, the fault pin will be pulled down to indicate the fault state. Device will activate again when temperature drops below 130C degrees. Fault is cleared by setting EN pin low or by reading the fault register. I2C-Compatible Serial Bus Interface INTERFACE BUS OVERVIEW The I2C-compatible synchronous serial interface provides access to the programmable functions and registers on the device. This protocol uses a two-wire interface for bidirectional communications between the IC's connected to the bus. The two interface lines are the Serial Data Line (SDA) and the Serial Clock Line (SCLK). These lines should be connected to a positive supply, via a pull-up resistor and remain HIGH even when the bus is idle. Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending on whether it generates or receives the SCLK. The LP8552 is always a slave device. DATA TRANSACTIONS One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock SCLK. Consequently, throughout the clock's high period, the data should remain stable. Any changes on the SDA line during the high state of the SCLK and in the middle of a transaction, aborts the current transaction. New data should be sent during the low SCLK state. This protocol permits a single data line to transfer both command/control information and data using the synchronous serial clock. SDA SCL Data Line Stable: Data Valid Change of Data Allowed Figure 24. Bit Transfer Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and a Stop Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is transferred with the most significant bit first. After each byte, an Acknowledge signal must follow. The following sections provide further details of this process. 24 Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 LP8552 www.ti.com SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 Data Output by Transmitter Transmitter Stays Off the Bus During the Acknowledgment Clock Data Output by Receiver Acknowledgment Signal From Receiver SCL 1 2 3-6 7 8 9 S Start Condition Figure 25. Start and Stop The Master device on the bus always generates the Start and Stop Conditions (control codes). After a Start Condition is generated, the bus is considered busy, and it retains this status until a certain time after a Stop Condition is generated. A high-to-low transition of the data line (SDA) while the clock (SCLK) is high indicates a Start Condition. A low-to-high transition of the SDA line while the SCLK is high indicates a Stop Condition. SDA SCL S P Start Condition Stop Condition Figure 26. Start and Stop Conditions In addition to the first Start Condition, a repeated Start Condition can be generated in the middle of a transaction. This allows another device to be accessed, or a register read cycle. ACKNOWLEDGE CYCLE The Acknowledge Cycle consists of two signals: the acknowledge clock pulse the master sends with each byte transferred, and the acknowledge signal sent by the receiving device. The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver must pull down the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to receive the next byte. "ACKNOWLEDGE AFTER EVERY BYTE" RULE The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge signal after every byte received. There is one exception to the "acknowledge after every byte" rule. When the master is the receiver, it must indicate to the transmitter an end of data by not-acknowledging ("negative acknowledge") the last byte clocked out of the slave. This "negative acknowledge" still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down. Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 25 LP8552 SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 www.ti.com ADDRESSING TRANSFER FORMATS Each device on the bus has a unique slave address. The LP8552 operates as a slave device with 7-bit address combined with data direction bit. Slave address is 2Ch as 7-bit or 58h for write and 59h for read in 8-bit format. Before any data is transmitted, the master transmits the address of the slave being addressed. The slave device should send an acknowledge signal on the SDA line, once it recognizes its address. The slave address is the first seven bits after a Start Condition. The direction of the data transfer (R/W) depends on the bit sent after the slave address -- the eighth bit. When the slave address is sent, each device in the system compares this slave address with its own. If there is a match, the device considers itself addressed and sends an acknowledge signal. Depending upon the state of the R/W bit (1:read, 0:write), the device acts as a transmitter or a receiver. Figure 27. I2C Chip Address MSB LSB ADR6 Bit7 ADR5 bit6 ADR4 bit5 ADR3 bit4 ADR2 bit3 ADR1 bit2 ADR0 bit1 x x x x x x x R/W bit0 2 I C SLAVE address (chip address) Control Register Write Cycle * Master device generates start condition. * Master device sends slave address (7 bits) and the data direction bit (r/w = 0). * Slave device sends acknowledge signal if the slave address is correct. * Master sends control register address (8 bits). * Slave sends acknowledge signal. * Master sends data byte to be written to the addressed register. * Slave sends acknowledge signal. * If master will send further data bytes the control register address will be incremented by one after acknowledge signal. * Write cycle ends when the master creates stop condition. Control Register Read Cycle * Master device generates a start condition. * Master device sends slave address (7 bits) and the data direction bit (r/w = 0). * Slave device sends acknowledge signal if the slave address is correct. * Master sends control register address (8 bits). * Slave sends acknowledge signal. * Master device generates repeated start condition. * Master sends the slave address (7 bits) and the data direction bit (r/w = 1). * Slave sends acknowledge signal if the slave address is correct. * Slave sends data byte from addressed register. * If the master device sends acknowledge signal, the control register address will be incremented by one. Slave device sends data byte from addressed register. * Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop condition. 26 Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 LP8552 www.ti.com SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 Table 1. Data Read and Write Cycles Address Mode Data Read <Start Condition> <Slave Address><r/w = 0>[Ack] <Register Addr.>[Ack] <Repeated Start Condition> <Slave Address><r/w = 1>[Ack] [Register Data]<Ack or NAck> ... additional reads from subsequent register address possible <Stop Condition> Data Write <Start Condition> <Slave Address><r/w='0'>[Ack] <Register Addr.>[Ack] <Register Data>[Ack] ... additional writes to subsequent register address possible <Stop Condition> <>Data from master [ ] Data from slave Register Read and Write Detail S Slave Address (7 bits) '0' A Control Register Add. A (8 bits) Register Data (8 bits) A P Data transfered, byte + Ack R/W From Slave to Master A - ACKNOWLEDGE (SDA Low) S - START CONDITION From Master to Slave P - STOP CONDITION Register Write Format S Slave Address (7 bits) '0' A Control Register Add. A Sr (8 bits) Slave Address (7 bits) R/W '1' A Data- Data (8 bits) A/ P NA Data transfered, byte + Ack/NAck R/W Direction of the transfer will change at this point From Slave to Master From Master to Slave A - ACKNOWLEDGE (SDA Low) NA - ACKNOWLEDGE (SDA High) S - START CONDITION Sr - REPEATED START CONDITION P - STOP CONDITION Register Read Format Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 27 LP8552 SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 www.ti.com APPLICATIONS INFORMATION Recommended External Components INDUCTOR SELECTION There are two main considerations when choosing an inductor; the inductor should not saturate, and the inductor current ripple should be small enough to achieve the desired output voltage ripple. Different saturation current rating specifications are followed by different manufacturers so attention must be given to details. Saturation current ratings are typically specified at 25C. However, ratings at the maximum ambient temperature of application should be requested from the manufacturer. Shielded inductors radiate less noise and should be preferred. The saturation current should be greater than the sum of the maximum load current and the worst case average to peak inductor current. The equation below shows the worst case conditions. ISAT > IOUTMAX ' Where IRIPPLE = Where D = * * * * * * * + IRIPPLE (VOUT VIN) (2 x L x f) (VOUT VIN) (VOUT) x VIN VOUT DQG'= (1 - D) IRIPPLE: Average to peak inductor current IOUTMAX: Maximum load current VIN: Maximum input voltage in application L: Min inductor value including worst case tolerances f: Minimum switching frequency D: Duty cycle for CCM Operation VOUT: Output voltage (3) Example using above equations: * VIN = 12V * VOUT = 38V * IOUT = 400 mA * L = 15 H - 20% = 12 H * f = 1.25 MHz * ISAT = 1.6A As a result the inductor should be selected according to the ISAT. A more conservative and recommended approach is to choose an inductor that has a saturation current rating greater than the maximum current limit of 2.5A. A 15 H inductor with a saturation current rating of 2.5A is recommended for most applications. The inductor's resistance should be less than 300 m for good efficiency. For high efficiency choose an inductor with high frequency core material such as ferrite to reduce core losses. To minimize radiated noise, use shielded core inductor. Inductor should be placed as close to the SW pin and the IC as possible. Special care should be used when designing the PCB layout to minimize radiated noise and to get good performance from the boost converter. For more information on the PCB layout recommendations, please refer to LP8552TL layout guide. OUTPUT CAPACITOR A ceramic capacitor with 50V voltage rating or higher is recommended for the output capacitor. The DC-bias effect can reduce the effective capacitance by up to 80%, which needs to be considered in capacitance value selection. For light loads a 4.7 F capacitor is sufficient. Effectively the capacitance should be 4 F for < 150 mA loads. For maximum output voltage/current 10 F capacitor (or two 4.7 F capacitors) is recommended to minimize the output ripple. 28 Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 LP8552 www.ti.com SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 LDO CAPACITOR A 1F ceramic capacitor with 10V voltage rating is recommended for the LDO capacitor. OUTPUT DIODE A Schottky diode should be used for the output diode. Peak repetitive current should be greater than inductor peak current (2.5A) to ensure reliable operation. Average current rating should be greater than the maximum output current. Schottky diodes with a low forward drop and fast switching speeds are ideal for increasing efficiency in portable applications. Choose a reverse breakdown voltage of the Schottky diode significantly larger (~60V) than the output voltage. Do not use ordinary rectifier diodes, since slow switching speeds and long recovery times cause the efficiency and the load regulation to suffer. RESISTORS FOR SETTING THE LED CURRENT AND PWM FREQUENCY See CURRENT SETTING and PWM FREQUENCY SETTING sections on how to select values for these resistors FILTER COMPONENT VALUES Optimal components for 60 Hz VSYNC frequency and 4 Hz cut-off frequency of the low-pass filter are shown in the typical application diagrams and in the figure below. If 2 Hz cut-off frequency i.e., slower response time is desired, filter components are: C1 = 1 F, C2 = 10 F and R = 47 k. If different VSYNC frequency or response time is desired, please contact Texas Instruments' representative for guidance. Register Maps Table 2. Register Map ADD R REGISTER D7 00H Brightness Control 01H Device Control 02H Fault OPEN 03H ID PANEL 04H Direct Control 05H Temp MSB 06H Temp LSB 72H EEPROM_cont rol D6 D5 D4 D3 D2 D1 D0 DEFAU LT BRT[7:0] 0000 0000 BRT_MODE[1:0] SHORT 2_CHANN ELS 1_CHANN EL BL_FAULT OCP MFG[3:0] TSD BL_CTL 0000 0000 UVLO 0000 0000 REV[2:0] 1111 1100 OUT[6:1] 0000 0000 TEMP[10:3] 0000 0000 TEMP[2:0] 0000 0000 EE_READ Y EE_INIT EE_PROG EE_READ Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 0000 0000 29 LP8552 SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 www.ti.com Table 3. EEPROM Memory Map ADDR REGISTER A0H eeprom addr 0 D7 D6 D5 A1H eeprom addr 1 A2H eeprom addr 2 A3H eeprom addr 3 UVLO[1:0] EN_PSP WM A4H eeprom addr 4 PWM_RESOLUTION[1: 0] EN_I_RE S A5H eeprom addr 5 EN_VSY NC A6H eeprom addr 6 A7H eeprom addr 7 D4 D3 D2 D1 D0 CURRENT[7:0] BOOST_FREQ[1:0] EN_PWM _&_I_CTR L ADAPTIVE_SPEED[1:0] ADV_SLO PE TEMP_LIM[1:0] MODE_25/ 50%_SEL SLOPE[2:0] EN_ADAPT EN_BOOS T BOOST_IM AX I_SLOPE[ 1] PWM_FREQ[4:0] LED_FAUL T_THR I_SLOPE[0] DITHER[1:0] DRV_HEADR[2:0] VBOOST[4:0] PLL[12:5] PLL[4:0] EN_F_RES HYSTERESIS[1:0] Register Bit Explanations BRIGHTNESS CONTROL Address 00h Reset value 0000 0000b Brightness Control register 7 6 5 4 3 2 1 2 1 0 BRT[7:0] Name Bit Access BRT 7:0 R/W Description Backlight PWM 8-bit linear control. DEVICE CONTROL Address 01h Reset value 0000 0000b Device Control register 7 6 5 4 3 BRT_MODE[1:0] Name Bit Access BRT_MODE 2:1 R/W 0 BL_CTL Description PWM source mode 00b = PWM input pin duty cycle control (default) 01b = PWM input pin duty cycle control 10b = Brightness register 11b = Direct PWM control from PWM input pin BL_CTL 0 R/W Enable backlight 0 = Backlight disabled and chip turned off if BRT_MODE[1:0] = 10. In external PWM pin control the state of the chip is defined with the PWM pin and this bit has no effect. 1 = Backlight enabled and chip turned on if BRT_MODE[1:0] = 10. In external PWM pin control the state of the chip is defined with the PWM pin and this bit has no effect. 30 Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 LP8552 www.ti.com SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 FAULT Address 02h Reset value 0000 0000b Fault register 7 6 5 4 3 2 1 0 OPEN SHORT 2_CHANNELS 1_CHANNEL BL_FAULT OCP TSD UVLO Name Bit Access OPEN 7 R Description LED open fault detection 0 = No fault 1 = LED open fault detected. Fault pin is pulled to GND. Fault is cleared by reading the register 02h or setting EN pin low. SHORT 6 R LED short fault detection 0 = No fault 1 = LED short fault detected. Fault pin is pulled to GND. Fault is cleared by reading the register 02h or setting EN pin low. 2_CHANNELS 5 R LED fault detection 0 = No fault 1 = 2 or more channels have generated either short or open fault. Fault pin is pulled to GND. Fault is cleared by reading the register 02h or setting EN pin low. 1_CHANNEL 4 R LED fault detection 0 = No fault 1 = 1 channel has generated either short or open fault. Fault pin is pulled to GND. Fault is cleared by reading the register 02h or setting EN pin low. BL_FAULT 3 R LED fault detection 0 = No fault 1 = LED fault detected. Generated with OR function of all LED faults. Fault pin is pulled to GND. Fault is cleared by reading the register 02h or setting EN pin low. OCP 2 R Over current protection 0 = No fault 1 = Over current detected in boost output. OCP detection block monitors the boost output and if the boost output has been too low for more than 50 ms it will generate OCP fault and disable the boost. Fault pin is pulled to GND. Fault is cleared by reading the register 02h or setting EN pin low. After clearing the fault boost will startup again. TSD 1 R Thermal shutdown 0 = No fault 1 = Thermal fault generated, 150C reached. Boost converted and LED outputs will be disabled until the temperature has dropped down to 130C. Fault pin is pulled to GND. Fault is cleared by reading the register 02h or setting EN pin low. UVLO 0 R Under-voltage detection 0 = No fault 1 = Under-voltage detected in VIN pin. Boost converted and LED outputs will be disabled until VIN voltage is above the threshold voltage. Threshold voltage is set with EEPROM bits from 3V...9V. Fault pin is pulled to GND. Fault is cleared by reading the register 02h or setting EN pin low. Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 31 LP8552 SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 www.ti.com IDENTIFICATION Address 03h Reset value 1111 1100b Identification register 7 6 5 PANEL 4 3 2 MFG[3:0] 1 0 REV[2:0] Name Bit Access PANEL 7 R Description Panel ID code MFG 6:3 R Manufacturer ID code REV 2:0 R Revision ID code 5 4 DIRECT CONTROL Address 04h Reset value 0000 0000b Direct Control register 7 6 3 2 1 0 OUT[6:1] Name Bit Access OUT 5:0 R/W Description Direct control of the LED outputs 0 = Normal operation. LED output are controlled with PWM. 1 = LED output is forced to 100% PWM. TEMP MSB Address 05h Reset value 0000 0000b Temp MSB register 7 6 5 4 3 2 1 0 TEMP[10:3] Name Bit Access TEMP 7:0 R Description Device internal temperature sensor reading first 8 MSB. MSB must be read before LSB, because reading of MSB register latches the data. TEMP LSB Address 06h Reset value 0000 0000b Temp LSB register 7 6 5 4 3 2 1 0 TEMP[2:0] 32 Name Bit Access TEMP 7:5 R Description Device internal temperature sensor reading last 3 LSB. MSB must be read before LSB, because reading of MSB register latches the data. Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 LP8552 www.ti.com SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 EEPROM CONTROL Address 72h Reset value 0000 0000b EEPROM Control register 7 6 5 4 3 EE_READY Name Bit Access EE_READY 7 R 2 1 0 EE_INIT EE_PROG EE_READ Description EEPROM ready 0 = EEPROM programming or read in progress 1 = EEPROM ready, not busy EE_INIT 2 R/W EEPROM initialization bit. This bit must be written 1 before EEPROM read or programming. EE_PROG 1 R/W EEPROM programming. 0 = Normal operation 1 = Start the EEPROM programming sequence. EE_INIT must be written 1 before EEPROM programming can be started. Programs data currently in the EEPROM registers to non volatile memory (NVM). Programming sequence takes about 200 ms. Programming voltage is generated inside the chip. EE_READ 0 R/W EEPROM read 0 = Normal operation 1 = Reads the data from NVM to the EEPROM registers. Can be used to restore default values if EEPROM registers are changed during testing. Programming sequence (program data permanently from registers to NVM): 1. Turn on the chip by writing BL_CTL bit to 1 and BRT_MODE[1:0] to 10b (05h to address 01h) 2. Write data to EEPROM registers (address A0h...A7h). 3. Write EE_INIT to 1 in address 72h. (04h to address 72h). 4. Write EE_PROG to 1 and EE_INIT to 0 in address 72h. (02h to address 72h). 5. Wait 200 ms. 6. Write EE_PROG to 0 in address 72h. (00h to address 72h). Read sequence (load data from NVM to registers): 1. Turn on the chip by writing BL_CTL bit to 1 and BRT_MODE[1:0] to 10b (05h to address 01h). 2. Write EE_INIT to 1 in address 72h. (04h to address 72h). 3. Write EE_READ to 1 and EE_INIT to 0 in address 72h. (01h to address 72h). 4. Wait 200 ms. 5. Write EE_READ to 0 in address 72h. (00h to address 72h). Data written to EEPROM registers is effective immediately even if the EEPROM programming sequence has not been done. When power is turned off, the device will however lose the data if it is not programmed to the NVM. During startup device automatically loads the data from NVM to registers. NOTE EEPROM NVM can be programmed or read by customer for bench validation. Programming for production devices should be done in TI production test, where appropriate checks will be performed to confirm EEPROM validity. Writing to EEPROM Control register of production devices (for burning or reading EEPROM) is not recommended. If special EEPROM configuration is required, please contact the TI Sales Office for availability. Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 33 LP8552 SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 www.ti.com EEPROM Bit Explanations EEPROM Default Values ADDR LP8552 LP8552-E00 LP8552-E01 LP8552-E04 LP8552-E05 LP8552-E06 A0h 0111 1111 0111 1111 0110 0001 0111 1111 0110 0001 0111 1111 A1h 1111 0101 1011 0101 1010 1001 1111 0101 1010 1001 0111 0000 A2h 1011 1111 1011 1111 1011 1101 1011 1111 1001 1101 1001 1111 A3h 0111 1011 0111 1011 0111 1111 0111 1011 0111 1111 0111 1011 A4h 0010 1000 0010 1000 0010 1000 0010 1000 0010 1000 0010 1000 A5h 1100 1111 1100 1111 0110 1110 0100 0101 0110 1110 0100 0101 A6h 0110 0100 0110 0100 0110 0100 0110 0100 0110 0100 0110 0100 A7h 0010 1101 0010 1101 0010 1110 0010 1110 0010 1110 0010 1110 EEPROM ADDRESS 0 Address A0h EEPROM ADDRESS 0 register 7 6 5 4 3 2 1 0 CURRENT[7:0] Name Bit Access CURRENT 7:0 R/W Description Backlight current adjustment. If EN_I_RES = 0 the maximum backlight current is defined only with these bits as described below. If EN_I_RES = 1, then the external resistor connected to ISET pin also scales the LED current. With 16 k resistor and CURRENT set to 7Fh the output current is then 23 mA. EN_I_RES = 0 EN_I_RES = 1 0000 0000 0 mA 0 mA 0000 0001 0.12 mA (1/255) x 600 x 1.23V/RISET 0000 0010 0.24 mA (2/255) x 600 x 1.23V/RISET ... ... ... 0111 1111 (default) 15.00 mA (127/255) x 600 x 1.23V/RISET ... ... ... 1111 1101 29.76 mA (253/255) x 600 x 1.23V/RISET 1111 1110 29.88 mA (254/255) x 600 x 1.23V/RISET 1111 1111 30.00 mA (255/255) x 600 x 1.23V/RISET EEPROM ADDRESS 1 Address A1h EEPROM ADDRESS 1 register 7 6 BOOST_FREQ[1:0] 5 4 EN_PWM_&_I_CTRL Name Bit Access BOOST_FREQ 7:6 R/W 3 2 TEMP_LIM[1:0] 1 0 SLOPE[2:0] Description Boost Converter Switch Frequency 00 = 156 kHz 01 = 312 kHz 10 = 625 kHz 11 = 1250 kHz EN_PWM_&_I_CTRL 5 R/W Enable PWM & current control 0 = PWM control used with constant current 1 = Automatic PWM & current control enabled 34 Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 LP8552 www.ti.com SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 EEPROM ADDRESS 1 register TEMP_LIM 4:3 R/W Thermal deration function temperature threshold 00 = thermal deration function disabled 01 = 110C 10 = 120C 11 = 130C SLOPE 2:0 R/W Slope time for brightness change 000 = Slope function disabled, immediate brightness change 001 = 50 ms 010 = 75 ms 011 = 100 ms 100 = 150 ms 101 = 200 ms 110 = 300 ms 111 = 500 ms EEPROM ADDRESS 2 Address A2h EEPROM ADDRESS 2 register 7 6 ADAPTIVE_SPEED[1:0] 5 4 3 2 1 0 ADV_SLOPE MODE_25/50_S EL EN_ADAPT EN_BOOST BOOST_IMAX I_SLOPE[1] Name Bit Access ADAPTIVE SPEED[1] 7 R/W Description Boost converter adaptive control speed adjustment 0 = Normal mode 1 = Adaptive mode optimized for light loads. Activating this helps the voltage droop with light loads during boost / backlight startup. ADAPTIVE SPEED[0] 6 R/W Boost converter adaptive control speed adjustment 0 = Adjust boost once for each phase shift cycle or normal PWM cycle 1 = Adjust boost every 16th phase shift cycle or normal PWM cycle ADV_SLOPE 5 R/W Advanced slope 0 = Advanced slope is disabled 1 = Use advanced slope for brightness change to make brightness changes smooth for eye MODE_25/50_SEL 4 R/W 25% or 50% mode selection for PWM & current control 0 = 50% mode selected 1 = 25% mode selected EN_ADAPT 3 R/W Enable boost converter adaptive mode 0 = adaptive mode disabled, boost converter output voltage is set with VBOOST EEPROM register bits 1 = adaptive mode enabled. Boost converter startup voltage is set with VBOOST EEPROM register bits, and after startup voltage is reached the boost converter will adapt to the highest LED string VF. LED driver output headroom is set with DRV_HEADR EEPROM control bits. EN_BOOST 2 R/W Enable boost converter 0 = boost is disabled 1 = boost is enabled and will turn on automatically when backlight is enabled BOOST_IMAX 1 R/W Boost converter inductor maximum current 0 = 1.4A 1 = 2.5A (recommended) Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 35 LP8552 SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 www.ti.com EEPROM ADDRESS 2 register I_SLOPE[1] 0 R/W Current slope I_SLOPE[1:0] trim bits adjust the constant current level of the PWM control range in the PWM & current control mode. I_SLOPE[1:0] 25% MODE 50% MODE 00 -2.5% -1.25% 01 -5.0% -2.50% 10 -7.5% -3.75% 11 -10.0% -5.00% EEPROM ADDRESS 3 Address A3h EEPROM ADDRESS 3 register 7 6 5 UVLO[1:0] 4 3 EN_PSPWM Name Bit Access UVLO 7:6 R/W 2 1 0 PWM_FREQ[4:0] Description 00 = Disabled 01 = 2.7V 10 = 5.4V 11 = 8.1V EN_PSPWM 5 R/W Enable phase shift PWM scheme 0 = phase shift PWM disabled, normal PWM mode used 1 = phase shift PWM enabled PWM_FREQ 4:0 R/W PWM output frequency setting. See PWM FREQUENCY SETTING for full description of selectable PWM frequencies. EEPROM ADDRESS 4 Address A4h EEPROM ADDRESS 4 register 7 6 PWM_RESOLUTION[1:0] 5 4 3 EN_I_RES LED_FAULT_THR I_SLOPE[0] Name Bit Access PWM RESOLUTION 7:6 R/W 2 1 0 DRV_HEADR[2:0] Description PWM output resolution selection. Actual resolution depends also on the output frequency. See table in PWM FREQUENCY SETTING for full description. 00 = 8...10 bits (19.2 kHz...4.8 kHz) 01 = 9...11 bits (19.2 kHz... 4.8 kHz) 10 = 10...12 bits (19.2 kHz...4.8 kHz) 11 = 11...13 bits (19.2 kHz...4.8 kHz) EN_I_RES 5 R/W Enable LED current set resistor 0 = Resistor is disabled and current is set only with CURRENT EEPROM register bits 1 = Enable LED current set resistor. LED current is defined by the RISET resistor and the CURRENT EEPROM register bits. LED_FAULT_T HR 4 R/W LED fault detector thresholds. VSAT is the saturation voltage of the driver, typically 200 mV. 0 = 3.3V 1 = 5.3V I_SLOPE[0] 36 3 R/W Current slope I_SLOPE[1:0] trim bits adjust the constant current level of the PWM control range in the PWM & current control mode. See I_SLOPE[1] bit descriptions in EEPROM ADDRESS 2 above. Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 LP8552 www.ti.com SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 EEPROM ADDRESS 4 register DRV_HEADR 2:0 R/W LED output driver headroom control. VSAT is the saturation voltage of the driver, typically 200 mV. 000 = VSAT + 125 mV 001 = VSAT + 250 mV 010 = VSAT + 375 mV 011 = VSAT + 500 mV 100 = VSAT + 625 mV 101 = VSAT + 750 mV 110 = VSAT + 875 mV 111 = VSAT + 1000 mV EEPROM ADDRESS 5 Address A5h EEPROM ADDRESS 5 register 7 6 EN_VSYNC 5 4 3 2 DITHER[1:0] 1 0 VBOOST[4:0] Name Bit Access EN_VSYNC 7 R/W Description Enable VSYNC function 0 = VSYNC input disabled 1 = VSYNC input enabled. VSYNC signal is used by the internal PLL to generate PWM output and boost frequency. DITHER 6:5 R/W Dither function controls 00 = Dither function disabled 01 = 1-bit dither used for output PWM transitions 10 = 2-bit dither used for output PWM transitions 11 = 3-bit dither used for output PWM transitions VBOOST 4:0 R/W Boost voltage control from 10V to 40V with 1V step. If adaptive boost control is enabled, this sets the initial start voltage for the boost converter. If adaptive mode is disabled, this will directly set the output voltage of the boost converter. 0 0000 = 10V 0 0001 = 11V 0 0010 = 12V ... 1 1101 = 39V 1 1110 = 40V 1 1111 = 40V EEPROM ADDRESS 6 Address A6h EEPROM ADDRESS 6 register 7 6 5 4 3 2 1 0 PLL[12:5] Name Bit Access PLL 7:0 R/W Description 13-bit counter value for PLL, 8 MSB bits. PLL[12:0] bits are used when en_vsync = 1. See EEPROM ADDRESS 7 below for PLL value calculation. Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 37 LP8552 SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 www.ti.com EEPROM ADDRESS 7 Address A7h EEPROM ADDRESS 7 register 7 6 5 4 3 PLL[4:0] 2 1 EN_F_RES 0 HYSTERESIS[1:0] Name Bit Access PLL 7:3 R/W Description 13-bit counter value for PLL, 5 LSB bits. PLL[12:0] bits are used when en_vsync = 1. See Table 4 below for PLL value calculation. EN_F_RES 2 R/W Enable PWM output frequency set resistor 0 = Resistor is disabled and PWM output frequency is set with PWM_FREQ EEPROM register bits 1 = PWM frequency set resistor is enabled. RFSET defines the output PWM frequency. See table in PWM FREQUENCY SETTING for full description of the PWM frequencies. HYSTERESIS 1:0 R/W PWM input hysteresis function. Will define how small changes in the PWM input are ignored to remove constant switching between two values. 00 = OFF 01 = 1-bit hysteresis with 11-bit resolution 10 = 1-bit hysteresis with 10-bit resolution 11 = 1-bit hysteresis with 8-bit resolution Table 4. PLL Value Calculation en_vsync PLL frequency [MHz] 0 5, 10, 20, 40 not used 5 5 MHz / (26 x fVSYNC) 10 10 MHz / (50 x fVSYNC) 1 PLL[12:0] 20 20 MHz / (98 x fVSYNC) 40 40 MHz / (196 x fVSYNC) PLL frequency is set by PWM_RESOLUTION[1:0] bits. For Example: If fPLL = 5 MHz and fVSYNC = 60 Hz, then PLL[12:0] = 5000000 Hz / (26 * 60 Hz) = 3205d = C85h. If fPLL = 10 MHz and fVSYNC = 75 Hz, then PLL[12:0] = 10000000 Hz / (50 * 75 Hz) = 2667d = A6Bh. 38 Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 LP8552 www.ti.com SNVS693D - SEPTEMBER 2011 - REVISED JANUARY 2014 REVISION HISTORY Changes from Revision C (March 2013) to Revision D Page * Added add note re: EEPROM configuration ....................................................................................................................... 20 * Added add note re: EEPROM configuration ....................................................................................................................... 33 Submit Documentation Feedback Copyright (c) 2011-2014, Texas Instruments Incorporated Product Folder Links: LP8552 39 PACKAGE OPTION ADDENDUM www.ti.com 25-Apr-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty LP8552TLE-E04/NOPB PREVIEW DSBGA YZR 25 LP8552TLE-E06/NOPB PREVIEW DSBGA YZR 25 LP8552TLX-E04/NOPB PREVIEW DSBGA YZR 25 LP8552TLX-E06/NOPB PREVIEW DSBGA YZR 25 250 3000 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 52E4 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 52E6 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 52E4 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 52E6 (4/5) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Apr-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) LP8552TLE-E04/NOPB DSBGA YZR 25 250 178.0 8.4 LP8552TLX-E04/NOPB DSBGA YZR 25 3000 178.0 LP8552TLX-E06/NOPB DSBGA YZR 25 0 178.0 2.69 2.69 0.76 4.0 8.0 Q1 8.4 2.69 2.69 0.76 4.0 8.0 Q1 8.4 2.69 2.69 0.76 4.0 8.0 Q1 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 26-Apr-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP8552TLE-E04/NOPB DSBGA YZR LP8552TLX-E04/NOPB DSBGA YZR 25 250 210.0 185.0 35.0 25 3000 210.0 185.0 35.0 LP8552TLX-E06/NOPB DSBGA YZR 25 0 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA YZR0025xxx 0.6000.075 D E TLA25XXX (Rev D) D: Max = 2.49 mm, Min = 2.43 mm E: Max = 2.49 mm, Min = 2.43 mm 4215055/A NOTES: A. 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