M2Y25664TUH4B0F / M2Y51264TU88B0B / M2Y1G64TU8HB0B 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM 240pin Unbuffered DDR2 SDRAM MODULE Based on 64Mx8 & 32Mx16 DDR2 SDRAM B Die Features * Performance: PC2-4200 PC2-5300 PC2-6400 PC2-6400 -37B -3C -25C -25D 4 5 5 6 f CK Clock Frequency 266 333 400 400 t CK Clock Cycle 3.75 3 2.5 2.5 ns f DQ DQ Burst Frequency 533 667 800 800 MHz Speed Sort DIMM Latency* * JEDEC Standard 240-pin Dual In-Line Memory Module * 32Mx64 DDR2 Unbuffered DIMM based on 32Mx16 DDR2 SDRAM B die * 64Mx64 and 128Mx64 DDR2 Unbuffered DIMM based on 64Mx8 DDR2 SDRAM B die * Intended for 266MHz, 333MHz, and 400MHz applications * Inputs and outputs are SSTL-18 compatible * VDD = VDDQ = 1.8Volt 0.1 * SDRAMs have 4 internal banks for concurrent operation * Differential clock inputs * Data is read or written on both clock edges * Bi-directional data strobe with one clock cycle preamble and one-half clock post-amble * Address and control signals are fully synchronous to positive clock edge * Programmable Operation: Unit MHz - Device Latency: 3, 4, 5 - Burst Type: Sequential or Interleave - Burst Length: 4, 8 - Operation: Burst Read and Write * Auto Refresh (CBR) and Self Refresh Modes * Automatic and controlled precharge commands * 13/10/1 Addressing (row/column/rank) - 256MB * 14/10/1 Addressing (row/column/rank) - 512MB * 14/10/2 Addressing (row/column/rank) - 1GB * 7.8 s Max. Average Periodic Refresh Interval * Serial Presence Detect * Gold contacts * SDRAMs in 60 and 84 ball BGA Package * RoHS compliance Description M2Y25664TUH4B0F, M2Y51264TU88B0B, and M2Y1G64TU8HB0B are 240-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Unbuffered Dual In-Line Memory Module (UDIMM), organized as one-rank 32Mx64 and 64Mx64 and two ranks 128Mx64 high-speed memory array. NT256T64UH4B0FY use four 32Mx16 DDR2 SDRAMs. NT512T64U88B0BY use eight 64Mx8 DDR2 SDRAMs. NT1GT64U8HB0BY use sixteen 64Mx8 DDR2 SDRAMs. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All Elixir DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint. The DIMM is intended for use in applications operating up to 233 MHz (333MHz and 400MHz) clock speeds and achieves high-speed data transfer rates of up to 533MHz (667MHz and 800MHz). Prior to any access operation, the device latency and burst / length / operation type must be programmed into the DIMM by address inputs A0-A14 and I/O inputs BA0 and BA1 using the mode register set cycle. The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer. REV 1.0 08/2006 1 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y25664TUH4B0F / M2Y51264TU88B0B / M2Y1G64TU8HB0B 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Ordering Information Part Number Speed Organization M2Y25664TUH4B0F -37B 266MHz (3.75ns@ CL = 4) DDR2-533 PC2-4200 M2Y25664TUH4B0F -3C 333MHz (3.00ns@ CL = 5) DDR2-667 PC2-5300 M2Y25664TUH4B0F -25C 400MHz (2.50ns@ CL = 5) DDR2-800 PC2-6400 M2Y25664TUH4B0F -25D 400MHz (2.50ns@ CL = 6) DDR2-800 PC2-6400 M2Y51264TU88B0B -37B 266MHz (3.75ns@ CL = 4) DDR2-533 PC2-4200 M2Y51264TU88B0B -3C 333MHz (3.00ns@ CL = 5) DDR2-667 PC2-5300 M2Y51264TU88B0B -25C 400MHz (2.50ns@ CL = 5) DDR2-800 PC2-6400 M2Y51264TU88B0B -25D 400MHz (2.50ns@ CL = 6) DDR2-800 PC2-6400 M2Y1G64TU8HB0B -37B 266MHz (3.75ns@ CL = 4) DDR2-533 PC2-4200 M2Y1G64TU8HB0B -3C 333MHz (3.00ns@ CL = 5) DDR2-667 PC2-5300 M2Y1G64TU8HB0B -25C 400MHz (2.50ns@ CL = 5) DDR2-800 PC2-6400 M2Y1G64TU8HB0B -25D 400MHz (2.50ns@ CL = 6) DDR2-800 PC2-6400 Leads Power Gold 1.8V Note 32Mx64 64Mx64 128Mx64 Pin Description CK0-CK2, CKE0, CKE1 Differential Clock Inputs DQ0-DQ63 Clock Enable DQS0-DQS8 Row Address Strobe DM0-DM8 Column Address Strobe - Write Enable , A0-A9, A11-A13 A10/AP BA0, BA1 Chip Selects Address Inputs NC REV 1.0 08/2006 Bidirectional data strobes Input Data Mask/High Data Strobes Differential data strobes VDD Power (1.8V) VREF Ref. Voltage for SSTL_18 inputs VDDSPD Serial EEPROM positive power supply Column Address Input/Auto-precharge VSS Ground SDRAM Bank Address Inputs SCL Serial Presence Detect Clock Input Reset pin ODT0, ODT1 Data input/output SDA Active termination control lines SA0-2 Serial Presence Detect Data input/output Serial Presence Detect Address Inputs No Connect 2 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y25664TUH4B0F / M2Y51264TU88B0B / M2Y1G64TU8HB0B 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Pinout Pin Front Pin Front Pin Front Pin 1 VREF 42 NC 82 VSS 121 VSS 2 VSS 43 NC 83 122 DQ4 3 DQ0 44 VSS 84 DQS4 123 DQ5 4 DQ1 45 NC 85 VSS 124 5 VSS 46 NC 86 DQ34 47 VSS 87 DQ35 DQS0 48 NC 88 8 VSS 49 NC 9 DQ2 50 VSS 10 DQ3 51 VDDQ 91 11 VSS 52 CKE0 92 12 DQ8 53 VDD 93 13 DQ9 54 NC 94 14 VSS 55 NC 56 VDDQ A11 6 7 15 Back Pin Back Pin Back 162 NC 202 DM4 163 VSS 203 NC 164 NC 204 VSS VSS 165 NC 205 DQ38 125 DM0 166 VSS 206 DQ39 126 NC 167 NC 207 VSS VSS 127 VSS 168 NC 208 DQ44 89 DQ40 128 DQ6 169 VSS 209 DQ45 90 DQ41 129 DQ7 170 VDDQ 210 VSS VSS 130 VSS 171 CKE1 211 DM5 131 DQ12 172 VDD 212 NC DQS5 132 DQ13 173 NC 213 VSS VSS 133 VSS 174 NC 214 DQ46 95 DQ42 134 DM1 175 VDDQ 215 DQ47 96 DQ43 135 NC 176 A12 216 VSS 97 VSS 136 VSS 177 A9 217 DQ52 CK1 178 VDD 218 DQ53 179 A8 219 VSS CK2 16 DQS1 57 17 VSS 58 A7 98 DQ48 137 18 NC 59 VDD 99 DQ49 138 19 NC 60 A5 100 VSS 139 VSS 180 A6 220 20 VSS 61 A4 101 SA2 140 DQ14 181 VDDQ 221 21 DQ10 62 VDDQ 102 NC 141 DQ15 182 A3 222 VSS 22 DQ11 63 A2 103 VSS 142 VSS 183 A1 223 DM6 23 VSS 64 VDD 104 143 DQ20 184 VDD 224 NC 24 DQ16 25 DQ17 65 26 VSS 27 KEY 105 DQS6 144 DQ21 VSS 106 VSS 145 VSS 185 KEY 66 VSS 107 DQ50 146 DM2 186 67 VDD 108 DQ51 147 NC 187 CK0 225 VSS 226 DQ54 227 DQ55 VDD 228 VSS 28 DQS2 68 NC 109 VSS 148 VSS 188 A0 229 DQ60 29 VSS 69 VDD 110 DQ56 149 DQ22 189 VDD 230 DQ61 30 DQ18 70 A10/AP 111 DQ57 150 DQ23 190 BA1 231 VSS 31 DQ19 71 BA0 112 VSS 151 VSS 191 VDDQ 232 DM7 32 VSS 72 VDDQ 113 152 DQ28 192 233 NC 33 DQ24 73 153 DQ29 193 234 VSS 34 DQ25 74 35 VSS 75 36 114 VDDQ 76 DQS7 115 VSS 154 VSS 194 VDDQ 235 DQ62 116 DQ58 155 DM3 195 ODT0 236 DQ63 117 DQ59 156 NC 196 A13 237 VSS 37 DQS3 77 ODT1 118 VSS 157 VSS 197 VDD 238 VDDSPD 38 VSS 78 VDDQ 119 SDA 158 DQ30 198 VSS 239 SA0 39 DQ26 79 VSS 120 SCL 159 DQ31 199 DQ36 240 SA1 40 DQ27 80 DQ32 160 VSS 200 DQ37 41 VSS 81 DQ33 161 NC 201 VSS REV 1.0 08/2006 3 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y25664TUH4B0F / M2Y51264TU88B0B / M2Y1G64TU8HB0B 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Input/Output Functional Description Symbol CK0, CK1, CK2 , , Type Polarity Function (SSTL) The positive line of the differential pair of system clock inputs which drives the input to Positive the on-DIMM PLL. All the DDR2 SDRAM address and control inputs are sampled on the Edge rising edge of their associated clocks. (SSTL) Negative The negative line of the differential pair of system clock inputs which drives the input to Edge the on-DIMM PLL. CKE0, CKE1 (SSTL) Active High Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode. , (SSTL) Active Low Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. (SSTL) Active Low When sampled at the positive rising edge of the clock, operation to be executed by the SDRAM. , , , , define the VREF Supply Reference voltage for SSTL-18 inputs VDDQ Supply Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity ODT0, ODT1 Input Active High BA0, BA1 (SSTL) - Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-A14 defines the row address (RA0-RA13) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) when sampled at the rising clock edge. In addition to the column address, AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge. A0 - A9 A10/AP A11 - A13 (SSTL) - DQ0 - DQ63 (SSTL) Active High VDD, VSS Supply DQS0 - DQS8 - (SSTL) DM0 - DM8 Input On-Die Termination control signals Data and Check Bit Input/Output pins. Power and ground for the DDR SDRAM input buffers and core logic Negative and Data strobe for input and output data Positive Edge Active High The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. SA0 - SA2 - Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. SDA - This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V DD to act as a pull-up. SCL - This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DD to act as a pull-up. VDDSPD REV 1.0 08/2006 Supply Serial EEPROM positive power supply. 4 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y25664TUH4B0F / M2Y51264TU88B0B / M2Y1G64TU8HB0B 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Functional Block Diagram (256MB, 1 Rank, 32Mx16 DDR2 SDRAMs) # ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! " " ! ! ! ! ! ! ! ! " " ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! " " ! ! ! ! ! ! ! ! " " ! ! ! ! ! ! ! ! # # # & ' & & & & $ ! % ()* '& REV 1.0 08/2006 ' ' ' ' $ & ' ! %& ' + *) ! , -./ 0 1 23 -. 4, *3- 10* + + $ *)-'35' / -* - 4 ''3),-+ + ''*) ' !3/' 6 7 + # 89 89 9 9 ''*) ' + !3/ '6 7 + 44 '' -42)-*) ''*) ' !3/' 6 7 5 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y25664TUH4B0F / M2Y51264TU88B0B / M2Y1G64TU8HB0B 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Functional Block Diagram (512MB, 1 Rank, 64Mx8 DDR2 SDRAMs) # # ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! # # & ' & & $ ! % ()* ' & REV 1.0 08/2006 ' ' ' ' $ & ! %& + *) ! , -./ 01 23 -. 4, *3- 10* + + $ *)-'35' / -* - 4 ' '3),-+ + ''*) ' !3/ '6 7 + # 89 89 9 9 ''*) ' + !3/' 6 7 + 44 '' -42)-*) ''*) ' !3/ '6 7 6 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y25664TUH4B0F / M2Y51264TU88B0B / M2Y1G64TU8HB0B 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Functional Block Diagram (1GB, 2 Rank, 64Mx8 DDR2 SDRAMs) # # ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! # # & ' & & & $ $ ! % ! % ()* '& REV 1.0 08/2006 & $ & $ & ! %& ! %& ' ' ' ' ' ' ' ' + *) ! , -. / 01 23 -. 4, *3- 10* + + $ *)-'35' / -* - 4 ''3),-+ + ''*) ' !3/'6 7 + # 89 89 9 9 ''*) ' + !3/' 6 7 + 44 '' -42)-*) ''*) ' !3/'6 7 7 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y25664TUH4B0F / M2Y51264TU88B0B / M2Y1G64TU8HB0B 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect -- Part 1 of 2 (256MB) 32Mx64 1 RANK UNBUFFERED DDR2 SDRAM DIMM based on 32Mx16, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte SPD Entry Value Description -37B -3C -25C Serial PD Data Entry (Hexadecimal) -37B -3C 0 Number of Serial PD Bytes Written during Production 128 80 1 Total Number of Bytes in Serial PD device 256 08 2 Fundamental Memory Type 3 Number of Row Addresses on Assembly 4 5 6 Data Width of this Assembly 7 8 9 DDR2 SDRAM Device Cycle Time at CL=5 3.75ns 3ns 2.5ns 3D 30 25 10 DDR2 SDRAM Device Access Time from Clock at CL=5 0.5ns 0.45ns 0.4ns 50 45 40 11 DIMM Configuration Type 12 Refresh Rate/Type 13 14 15 Reserved 16 17 18 DDR2 SDRAM Device Attributes: 19 Reserved 20 DDR2 SDRAM DIMM Type Information 21 DDR2 SDRAM Module Attributes: DDR2 08 13 0D Number of Column Addresses on Assembly 10 0A Number of DIMM Bank, Package, and Height 1 rank, Height=30mm 60 64 40 Reserved Undefined 00 Voltage Interface Level of this Assembly SSTL_1.8V 05 Non parity/ECC 00 7.8:s/self 82 Primary DDR2 SDRAM Width x16 10 Error Checking DDR2 SDRAM Device Width N/A 00 Undefined 00 DDR2 SDRAM Device Attributes: Burst Length Supported 4,8 0C DDR2 SDRAM Device Attributes: Number of Device Banks 4 04 Latencies Supported 3,4,5 38 <4.1mm 01 Regular UDIMM (133.35mm) 02 Normal DIMM 00 Support weak Driver, 50; ODT, and PASR 07 22 DDR2 SDRAM Device Attributes: General 23 Minimum Clock Cycle at CL=4 3.75ns 3D 24 Maximum Data Access Time (tac) from Clock at CL=4 0.5ns 50 25 Minimum Clock Cycle Time at CL=3 5.0ns 50 26 Maximum Data Access Time (tac) from Clock at CL=3 0.6ns 60 27 Minimum Row Precharge Time (tRP) 28 Minimum Row Active to Row Active delay (tRRD) 15.0ns 12.0ns 3C 12.0ns 3C 10ns 15.0ns 32 28 32 29 Minimum RAS to CAS delay (tRCD) 30 Minimum RAS Pulse Width (tRAS) 31 Module Bank Density 32 Address and Command Setup Time Before Clock (tIS) 0.25ns 0.20ns 0.175ns 25 20 17 33 Address and Command Hold Time After Clock (tIH) 0.375ns 0.275ns 0.25ns 37 27 25 34 Data Input Setup Time Before Clock (tDS) 0.10ns 0.10ns 0.05ns 10 10 05 35 Data Input Hold Time After Clock (tDH) 0.225ns 0.175ns 0.125ns 22 17 12 36 Write Recovery Time (tWR) 15.0ns 3C 37 Internal Write to Read Command delay (tWTR) 7.5ns 1E 38 Internal Read to Precharge delay (tRTP) 7.5ns 1E 39 Memory Analysis Probe Characteristics Undefined 00 REV 1.0 08/2006 Note -25C 45.0 2D 256MB 40 8 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y25664TUH4B0F / M2Y51264TU88B0B / M2Y1G64TU8HB0B 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect -- Part 2 of 2 (256MB) 32Mx64 1 RANK UNBUFFERED DDR2 SDRAM DIMM based on 32Mx16, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte SPD Entry Value Description -37B -3C -25C Serial PD Data Entry (Hexadecimal) -37B 00: The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns. 30: The number below a decimal point of tRC is 5, tRFC is less than 256ns -3C 40 Extension of Byte 41 tRC and Byte 42 tRFC 41 Minimum Core Cycle Time (tRC) 42 Min. Auto Refresh Command Cycle Time (tRFC) 43 Maximum Clock Cycle Time (tCK) 44 Max. DQS-DQ Skew Factor (tDQS) 0.30ns 0.24ns 0.20ns 1E 18 14 45 Read Data Hold Skew Factor (tQHS) 0.40ns 0.34ns 0.30ns 28 22 1E 46 PLL Relock Time 47 Tcasemax DT4R4W Delta 48 Thermal Resistance of DRAM Package from Top (Case) to Ambient (Psi-T-A DRAM) 49 DRAM Case Temperature Rise from Ambient due to Activate-Precharge/Mode Bits (DT0/Mode Bits) 7.85C 8.41C 9.42C 47 4F 5F 50 DRAM Case Temperature Rise from Ambient due to Precharge/Quiet Standby (DT2N/DT2Q) 4.48C 5.61C 5.72C 2D 39 3A 51 DRAM Case Temperature Rise from Ambient due to Precharge Power-Down (DT2P) 52 DRAM Case Temperature Rise from Ambient due to Active Standby (DT3N) 4.82C 5.61C 6.73C 21 26 2D 53 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Fast PDN Exit (DT3Pfast) 3.14C 3.7C 4.37C 3F 4A 58 54 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Slow PDN Exit (DT3Pslow) 1.01C 55 DRAM Case Temperature Rise from Ambient due to Page Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit) 12.33C 14.57C 17.38C 3E 4A 58 56 DRAM Case Temperature Rise from Ambient due to Burst Refresh (ST5B) 16.82C 17.94C 19.62C 22 24 28 57 DRAM Case Temperature Rise from Ambient due to Bank interleave Reads with Auto-Precharge (DT7) 17.94C 19.06C 19.06C 24 27 27 58 Thermal Resistance of PLL Package from Top (Case) to Ambient (Psi T-A PLL) 00 00 59 Thermal Resistance of Register Package from Top (Case) to Ambient (Psi T-A Register) 00 00 60 PLL Case Temperature Rise from Ambient due to PLL Active (DT PLL Active) 00 00 61 Register Case Temperature Rise from Ambient due to Register Active/Mode Bit (DT Register Active/Mode Bit) 00 00 62 SPD Reversion 1.2 12 63 Checksum for byte 0-62 60.0ns 105ns 39 50 53 50 76 35 Checksum data 92-255 Reserved 08/2006 95C 0C 0.78C 73-91 Module Part number 3C 00 59C/W Module Manufacturing Location REV 1.0 95C 1.2C 30 80 N/A 95C 0C 00 69 8.0ns 64-71 Manufacture's JEDEC ID Code 72 57.5ns Note -25C 29 06 FA 15 NANYA 7F7F7F0B00000000 Manufacturing Code -- Module Part Number in ASCII -- Undefined -- 9 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y25664TUH4B0F / M2Y51264TU88B0B / M2Y1G64TU8HB0B 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect - Part 1 of 2 (512MB) 64Mx64 1 RANK UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte SPD Entry Value Description -37B -3C -25C Serial PD Data Entry (Hexadecimal) -37B -3C 0 Number of Serial PD Bytes Written during Production 128 80 1 Total Number of Bytes in Serial PD device 256 08 2 Fundamental Memory Type 3 Number of Row Addresses on Assembly 4 5 6 Data Width of this Assembly 64 40 7 Reserved Undefined 00 8 Voltage Interface Level of this Assembly SSTL_1.8V 05 9 DDR2 SDRAM Cycle Time at CL=5 (ns) 3.75 10 DDR2 SDRAM Access Time from Clock at CL=5 (ns) 0.50 11 DIMM Configuration Type 12 Refresh Rate/Type 13 14 15 Reserved 16 DDR2 SDRAM Device Attributes: Burst Length Supported 17 DDR2 SDRAM Device Attributes: Number of Device Banks 18 DDR2 SDRAM Device Attributes: 19 Reserved 20 DDR2 SDRAM DIMM Type Information 21 DDR2 SDRAM Module Attributes: DDR2 08 14 0E Number of Column Addresses on Assembly 10 0A Number of DIMM Bank, Package, and Height 1 rank, Height=30mm 60 3 2.5 3D 30 25 0.45 0.40 50 45 40 Non parity/ECC 00 7.8:s/self 82 Primary DDR2 SDRAM Width X8 08 Error Checking DDR2 SDRAM Device Width N/A 00 Undefined 00 4,8 0C 4 04 3,4,5 38 Latencies Supported <4.1mm 01 Regular UDIMM (133.35mm) 02 Normal DIMM 00 Support weak Driver, 50; ODT, and PASR 07 3.75ns 3D 22 DDR2 SDRAM Device Attributes: General 23 Minimum Clock Cycle at CL=4 24 Maximum Data Access Time (tac) from Clock at CL=4 (ns) 0.5 50 25 Minimum Clock Cycle Time at CL=3 (ns) 5.0 50 26 Maximum Data Access Time (tac) from Clock at CL=3 (ns) 0.6 60 27 Minimum Row Precharge Time (tRP) (ns) 28 Minimum Row Active to Row Active delay (tRRD) 29 Minimum RAS to CAS delay (tRCD) (ns) 30 Minimum RAS Pulse Width (tRAS) 31 Module Bank Density 32 Address and Command Setup Time Before Clock (tIS) (ns) 0.25 0.20 0.175 25 20 17 33 Address and Command Hold Time After Clock (tIH) (ns) 0.375 0.275 0.25 37 27 25 34 Data Input Setup Time Before Clock (tDS) 35 Data Input Hold Time After Clock (tDH) (ns) 36 Write Recovery Time (tWR) 15.0ns 3C 37 Internal Write to Read Command delay (tWTR) 7.5ns 1E 38 Internal Read to Precharge delay (tRTP) 7.5ns 1E 39 Memory Analysis Probe Characteristics Undefined 00 REV 1.0 08/2006 15.0 12.5 3C 12.5 3C 7.5ns 15.0 0.225 32 1E 32 45.0 2D 512MB 80 0.10ns 0.175 Note -25C 0.05ns 0.125 10 22 05 17 12 10 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y25664TUH4B0F / M2Y51264TU88B0B / M2Y1G64TU8HB0B 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect -- Part 2 of 2 (512MB) 64Mx64 1RANK UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte SPD Entry Value Description -37B -3C -25C Serial PD Data Entry (Hexadecimal) -37B 00: The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns. 30: The number below a decimal point of tRC is 5, tRFC is less than 256ns -3C 40 Extension of Byte 41 tRC and Byte 42 tRFC 41 Minimum Core Cycle Time (tRC) (ns) 42 Min. Auto Refresh Command Cycle Time (tRFC) 105ns 69 43 Maximum Clock Cycle Time (tCK) 8.0ns 80 44 Max. DQS-DQ Skew Factor (tDQS) (ns) 0.3 0.24 0.2 1E 18 14 45 Read Data Hold Skew Factor (tQHS) (ns) 0.40 0.34 0.30ns 28 22 1E 46 PLL Relock Time 47 Tcasemax DT4R4W Delta 95C 0C 95C 1.2C 48 Thermal Resistance of DRAM Package from Top (Case) to Ambient (Psi-T-A DRAM) 49 DRAM Case Temperature Rise from Ambient due to Activate-Precharge/Mode Bits (DT0/Mode Bits) 8.11C 8.69C 9.74C 4B 53 63 50 DRAM Case Temperature Rise from Ambient due to Precharge/Quiet Standby (DT2N/DT2Q) 4.64C 5.8C 5.91C 2F 3A 3C 51 DRAM Case Temperature Rise from Ambient due to Precharge Power-Down (DT2P) 52 DRAM Case Temperature Rise from Ambient due to Active Standby (DT3N) 4.98C 5.8C 6.95C 22 27 2F 53 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Fast PDN Exit (DT3Pfast) 3.25C 3.82C 4.52C 41 4D 5B 54 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Slow PDN Exit (DT3Pslow) 1.04C 55 DRAM Case Temperature Rise from Ambient due to Page Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit) 12.75C 15.07C 17.96C 56 DRAM Case Temperature Rise from Ambient due to Burst Refresh (ST5B) 17.39 C 57 DRAM Case Temperature Rise from Ambient due to Bank interleave Reads with Auto-Precharge (DT7) 18.54C 58 Thermal Resistance of PLL Package from Top (Case) to Ambient (Psi T-A PLL) 00 00 59 Thermal Resistance of Register Package from Top (Case) to Ambient (Psi T-A Register) 00 00 60 PLL Case Temperature Rise from Ambient due to PLL Active (DT PLL Active) 00 00 61 Register Case Temperature Rise from Ambient due to Register Active/Mode Bit (DT Register Active/Mode Bit) 00 00 62 SPD Reversion 1.2 12 63 Checksum for byte 0-62 60.0 N/A 73-91 Module Part number 92-255 Reserved 08/2006 30 3C 39 53 50 7A 37 2A 20.28C 19.7C Checksum data Module Manufacturing Location REV 1.0 50 0.81C 18.54 C 00 00 95C 0C 61C/W 64-71 Manufacture's JEDEC ID Code 72 57.5 Note -25C 40 4C 5C 23 26 29 26 4A 28 3E 5C NANYA 7F7F7F0B00000000 Manufacturing Code -- Module Part Number in ASCII -- Undefined -- 11 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y25664TUH4B0F / M2Y51264TU88B0B / M2Y1G64TU8HB0B 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect - Part 1 of 2 (1GB) 128Mx64 2 RANKs UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte SPD Entry Value Description -37B -3C -25C Serial PD Data Entry (Hexadecimal) -37B -3C 0 Number of Serial PD Bytes Written during Production 128 80 1 Total Number of Bytes in Serial PD device 256 08 2 Fundamental Memory Type 3 Number of Row Addresses on Assembly 4 5 6 Data Width of this Assembly 7 DDR2 08 14 0E Number of Column Addresses on Assembly 10 0A Number of DIMM Bank, Package, and Height 2 rank, Height=30mm 61 64 40 Reserved Undefined 00 8 Voltage Interface Level of this Assembly SSTL_1.8V 05 9 DDR2 SDRAM Cycle Time at CL=5 (ns) 3.75 3 2.5 3D 30 25 10 DDR2 SDRAM Access Time from Clock at CL=5 (ns) 0.5 0.45 0.4 50 45 40 11 DIMM Configuration Type 12 Refresh Rate/Type 13 14 15 Reserved 16 DDR2 SDRAM Device Attributes: Burst Length Supported 17 DDR2 SDRAM Device Attributes: Number of Device Banks 18 DDR2 SDRAM Device Attributes: 19 Reserved 20 DDR2 SDRAM DIMM Type Information 21 DDR2 SDRAM Module Attributes: Non parity/ECC 00 7.8:s/self 82 Primary DDR2 SDRAM Width X8 08 Error Checking DDR2 SDRAM Device Width N/A 00 Undefined 00 4,8 0C 4 04 3,4,5 38 Latencies Supported <4.1mm 01 Regular UDIMM (133.35mm) 02 Normal DIMM 00 Support weak Driver, 50; ODT, and PASR 07 22 DDR2 SDRAM Device Attributes: General 23 Minimum Clock Cycle at CL=4 3.75ns 3D 24 Maximum Data Access Time (tac) from Clock at CL=4 0.5ns 50 25 Minimum Clock Cycle Time at CL=3 5.0ns 50 26 Maximum Data Access Time (tac) from Clock at CL=3 0.6ns 60 27 Minimum Row Precharge Time (tRP) (ns) 28 Minimum Row Active to Row Active delay (tRRD) 29 Minimum RAS to CAS delay (tRCD) (ns) 30 Minimum RAS Pulse Width (tRAS) 31 Module Bank Density 32 Address and Command Setup Time Before Clock (tIS) (ns) 0.25 0.20 0.175 25 20 17 33 Address and Command Hold Time After Clock (tIH) (ns) 0.375 0.275 0.25 37 27 25 34 Data Input Setup Time Before Clock (tDS) (ns) 0.10 0.10 0.05 10 10 05 35 Data Input Hold Time After Clock (tDH) (ns) 0.225 0.175 0.125 22 17 12 36 Write Recovery Time (tWR) 15.0ns 3C 37 Internal Write to Read Command delay (tWTR) 7.5ns 1E 38 Internal Read to Precharge delay (tRTP) 7.5ns 1E 39 Memory Analysis Probe Characteristics Undefined 00 REV 1.0 08/2006 15.0 12.5 3C 12.5 3C 7.5ns 15.0 Note -25C 32 1E 32 45.0 2D 512MB 80 12 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y25664TUH4B0F / M2Y51264TU88B0B / M2Y1G64TU8HB0B 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect -- Part 2 of 2 (1GB) 128Mx64 2 RANKs UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte SPD Entry Value Description -37B -3C -25C Serial PD Data Entry (Hexadecimal) -37B 00: The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns. 30: The number below a decimal point of tRC is 5, tRFC is less than 256ns -3C 40 Extension of Byte 41 tRC and Byte 42 tRFC 41 Minimum Core Cycle Time (tRC) (ns) 42 Min. Auto Refresh Command Cycle Time (tRFC) 43 Maximum Clock Cycle Time (tCK) 44 Max. DQS-DQ Skew Factor (tDQS) (ns) 0.3 0.24 0.2 1E 18 14 45 Read Data Hold Skew Factor (tQHS) (ns) 0.40 0.34 0.30 28 22 1E 46 PLL Relock Time 47 Tcasemax DT4R4W Delta 48 Thermal Resistance of DRAM Package from Top (Case) to Ambient (Psi-T-A DRAM) 49 DRAM Case Temperature Rise from Ambient due to Activate-Precharge/Mode Bits (DT0/Mode Bits) 8.11C 8.69C 9.74C 4B 53 63 50 DRAM Case Temperature Rise from Ambient due to Precharge/Quiet Standby (DT2N/DT2Q) 4.64C 5.8C 5.91C 2F 3A 3C 51 DRAM Case Temperature Rise from Ambient due to Precharge Power-Down (DT2P) 52 DRAM Case Temperature Rise from Ambient due to Active Standby (DT3N) 4.98C 5.8C 6.95C 22 27 2F 53 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Fast PDN Exit (DT3Pfast) 3.25C 3.82C 4.52C 41 4D 5B 54 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Slow PDN Exit (DT3Pslow) 1.04C 55 DRAM Case Temperature Rise from Ambient due to Page Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit) 12.75C 15.07C 17.96C 40 4C 5C 56 DRAM Case Temperature Rise from Ambient due to Burst Refresh (ST5B) 17.39C 18.54C 20.28C 23 26 29 57 DRAM Case Temperature Rise from Ambient due to Bank interleave Reads with Auto-Precharge (DT7) 18.54C 26 58 Thermal Resistance of PLL Package from Top (Case) to Ambient (Psi T-A PLL) 00 00 59 Thermal Resistance of Register Package from Top (Case) to Ambient (Psi T-A Register) 00 00 60 PLL Case Temperature Rise from Ambient due to PLL Active (DT PLL Active) 00 00 61 Register Case Temperature Rise from Ambient due to Register Active/Mode Bit (DT Register Active/Mode Bit) 00 00 62 SPD Reversion 1.2 12 63 Checksum for byte 0-62 60.0 105ns 39 50 53 50 7A 37 19.7C Checksum data 92-255 Reserved 08/2006 95C 0C 0.81C 73-91 Module Part number 3C 00 61C/W Module Manufacturing Location REV 1.0 95C 1.2C 30 80 N/A 95C 0C 00 69 8.0ns 64-71 Manufacture's JEDEC ID Code 72 57.5 Note -25C 2A 4B 28 3F 5D NANYA 7F7F7F0B00000000 Manufacturing Code -- Module Part Number in ASCII -- Undefined -- 13 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y25664TUH4B0F / M2Y51264TU88B0B / M2Y1G64TU8HB0B 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Absolute Maximum Ratings Symbol VIN, VOUT VDD VDDQ Parameter Rating Units Voltage on I/O pins relative to Vss -0.5 to 2.3 V Voltage on VDD supply relative to Vss -1.0 to +2.3 V Voltage on VDDQ supply relative to Vss -0.5 to +2.3 V Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC operating Conditions Symbol Parameter TCASE Operating Temperature (Ambient) TSTG Storage Temperature (Plastic) Short Circuit Output Current IL Note: 1. 2. 3. Rating Units Note 0 to 95 C 1,2,3 -55 to 100 C -5 to 5 :A Case temperature is measured at top and center side of any DRAMs. tCASE > 85C tREFI = 3.9 :s All DRAM specification only support 0C < tCASE < 85C DC Electrical Characteristics and Operating Conditions (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) Symbol Parameter VDD VDDQ VSS, VSSQ VREF Min Max Units Notes Supply Voltage 1.7 1.9 V 1 I/O Supply Voltage 1.7 1.9 V 1 0 0 V 0.49VDDQ 0.51VDDQ V 1, 2 Supply Voltage, I/O Supply Voltage I/O Reference Voltage VIH (DC) Input High (Logic1) Voltage VREF + 0.125 VDDQ + 0.3 V 1 VIL (DC) Input Low (Logic0) Voltage -0.3 VREF - 0.125 V 1 Note: 1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. Environmental Parameters Symbol Rating Units Note TOPR Module Operating Temperature Range (ambient) Parameter 0 to 55 C 3 HOPR Operating Humidity (relative) 10 to 90 % TSTG Storage Temperature (Plastic) -55 to 100 C 1 5 to 95 % 1 105 to 69 K Pascal 1,2 HSTG Storage Humidity (without condensation) PBAR Barometric Pressure (operating & storage) Note: 1. 2. 3. Stresses greater than those listed may cause permanent damage to the device. This is a tress rating only, and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Up to 9850 ft. The component maximum case temperature shall not exceed the value specified in the component spec. REV 1.0 08/2006 14 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y25664TUH4B0F / M2Y51264TU88B0B / M2Y1G64TU8HB0B 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.8V 0.1V (256MB, 1 Rank, 32Mx16 DDR2 SDRAMs) Symbol PC2-4200 PC2-5300 PC2-6400 (-37B) (-3C) (-25C) Parameter/Condition Unit I DD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 420 440 480 mA I DD1 Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle 420 460 500 mA I DD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) 60 60 60 mA I DD2N Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle 160 180 200 mA I DD2Q Precharge standby current; All banks idle; tCK = tCK (IDD); CKE is high; CS is high; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. 180 220 220 mA I DD3PF Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Fast PDN Exit MRS(12) = 0mA 120 160 180 mA I DD3PS Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Slow PDN Exit MRS(12) = 1mA 60 60 60 mA I DD3N Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 200 240 280 mA I DD4W Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) 580 700 740 mA I DD4R Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA 620 720 740 mA I DD5 Auto-Refresh Current: tRC = tRFC (MIN) 660 700 760 mA I DD6 Self-Refresh Current: CKE 0.2V 60 60 60 mA I DD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 1100 1140 1140 mA Note: REV 1.0 08/2006 Module IDD was calculated from component IDD. It may different from the actual measurement. 15 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y25664TUH4B0F / M2Y51264TU88B0B / M2Y1G64TU8HB0B 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.8V 0.1V (512MB, 1 Rank, 64Mx8 DDR2 SDRAMs) Symbol PC2-4200 PC2-5300 PC2-6400 (-37B) (-3C) (-25C) Parameter/Condition Unit I DD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 720 760 840 mA I DD1 Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle 720 800 880 mA I DD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) 120 120 120 mA I DD2N Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle 320 360 400 mA I DD2Q Precharge Quiet Standby Current: All banks idle; is HIGH; CKE is HIGH; tCK = tCK (MIN); Other control and address inputs are stable, Data bus inputs are floating. 360 440 440 mA I DD3PF Active Power-Down Current: All banks open; tCK = tCK (MIN), CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are floating. MRS A12 bit is set to low (Fast Power-down Exit). 240 320 360 mA I DD3PS Active Power-Down Current: All banks open; tCK = tCK (MIN), CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are floating. MRS A12 bit is set to high (Slow Power-down Exit). 120 120 120 mA I DD3N Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 400 480 560 mA I DD4W Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) 1000 1240 1320 mA I DD4R Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA 1040 1240 1280 mA I DD5 Auto-Refresh Current: tRC = tRFC (MIN) 1320 1400 1520 mA I DD6 Self-Refresh Current: CKE 0.2V 120 120 120 mA I DD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 1400 1480 1480 mA Note: Module IDD was calculated from component IDD. It may different from the actual measurement. REV 1.0 08/2006 16 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y25664TUH4B0F / M2Y51264TU88B0B / M2Y1G64TU8HB0B 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.8V 0.1V (1GB, 2 Ranks, 64Mx8 DDR2 SDRAMs) Symbol PC2-4200 PC2-5300 PC2-6400 (-37B) (-3C) (-25C) Parameter/Condition Unit I DD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 1040 1120 1240 mA I DD1 Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle 1040 1160 1280 mA I DD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) 240 240 240 mA I DD2N Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle 640 720 800 mA I DD2Q Precharge Quiet Standby Current: All banks idle; is HIGH; CKE is HIGH; tCK = tCK (MIN); Other control and address inputs are stable, Data bus inputs are floating. 720 880 880 mA I DD3PF Active Power-Down Current: All banks open; tCK = tCK (MIN), CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are floating. MRS A12 bit is set to low (Fast Power-down Exit). 480 640 720 mA I DD3PS Active Power-Down Current: All banks open; tCK = tCK (MIN), CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are floating. MRS A12 bit is set to high (Slow Power-down Exit). 240 240 240 mA I DD3N Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 720 840 960 mA I DD4W Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) 1320 1600 1720 mA I DD4R Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA 1360 1600 1680 mA I DD5 Auto-Refresh Current: tRC = tRFC (MIN) 1640 1760 1920 mA I DD6 Self-Refresh Current: CKE 0.2V 240 240 240 mA I DD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 1720 1840 1880 mA Note: Module IDD was calculated from component IDD. It may different from the actual measurement. REV 1.0 08/2006 17 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y25664TUH4B0F / M2Y51264TU88B0B / M2Y1G64TU8HB0B 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 1 of 2) Symbol Parameter PC2-4200 PC2-5300 PC2-6400 Unit Min. Max. Min. Max. Min. Max. DQ output access time from CK/ -0.50 0.50 -0.45 +0.45 -0.40 +0.40 DQS output access time from CK/ -0.45 0.45 -0.40 +0.40 -0.35 +0.35 ns tCH CK high-level width 0.45 0.55 0.45 0.55 0.45 0.55 tCK tCL CK low-level width 0.45 0.55 0.45 0.55 0.45 0.55 tCK tHP Minimum half clk period for any given cycle; defined by clk high (tCH) or clk low (tCL) time tCH or tCL - tCH or tCL - tCH or tCL - tCK tCK Clock Cycle Time 3.75 8 3 8 2.5 8 ns tDS DQ and DM input setup time(differential data strobe) 0.1 - 0.1 - 0.05 - ns tDH DQ and DM input hold time(differential data strobe) 0.225 - 0.175 - 0.125 - ns tIPW Input pulse width 0.6 - 0.6 - 0.6 - tCK DQ and DM input pulse width (each input) 0.35 - 0.35 - 0.35 - tCK - tAC max - tACmax - tACmax ns tAC max tACmin tACmax tACmin tACmax ns tAC tDQSCK tDIPW tHZ Data-out high-impedance time from CK/ tLZ(DQS) DQS low-impedance time from CK/ tAC min tLZ(DQ) DQ low-impedance time from CK/ 2tAC min tAC max 2tAC min tAC max 2tAC min tAC max tDQSQ ns ns DQS-DQ skew (DQS & associated DQ signals) - 0.3 - 0.24 - 0.20 ns tQHS Data hold Skew Factor - 0.4 - 0.34 - 0.3 ns tQH Data output hold time from DQS tHP tQHS - tHP tQHS - tHP tQHS - ns tDQSS Write command to 1st DQS latching transition -0.25 0.25 -0.25 +0.25 -0.25 +0.25 tCK DQS input low (high) pulse width (write cycle) 0.35 - 0.35 - 0.35 - tCK tDSS DQS falling edge to CK setup time (write cycle) 0.2 - 0.2 - 0.2 - tCK tDSH DQS falling edge hold time from CK (write cycle) 0.2 - 0.2 - 0.2 - tCK tDQSL,(H) tMRD Mode register set command cycle time 2 - 2 - 2 - tCK tWPST Write postamble 0.4 0.6 0.40 0.60 0.40 0.60 tCK tWPRE Write preamble 0.35 - 0.35 - 0.35 - tCK 375 - 275 - 250 - ps tIH tIS Address and control input hold time Address and control input setup time 250 - 200 - 175 - ps tRPRE Read preamble 0.9 1.1 0.90 1.10 0.90 1.10 tCK tRPST Read postamble 0.4 0.6 0.40 0.60 0.40 0.60 tCK tRRD Active bank A to Active bank B command 10 - 7.5 - 7.5 - ns tDelay Minimum time clocks remains ON after CKE asynchronously drops Low tIS + tCK + tIH - tIS + tCK + tIH - ns tREFI tOIT tCCD REV 1.0 08/2006 tIS+tCK+ tIH Average Periodic Refresh Interval (85C < TCASE < 95C) 3.9 3.9 3.9 :s Average Periodic Refresh Interval (0C < TCASE < 85C) 7.8 7.8 7.8 :s OCD drive mode output delay 0 to 2 12 0 2 12 0 2 12 ns tCK 18 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y25664TUH4B0F / M2Y51264TU88B0B / M2Y1G64TU8HB0B 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 2 of 2) Symbol PC2-4200 Parameter Min. Max. PC2-5300 Min. Max. PC2-6400 Min. Max. Unit tWR Write recovery time without Auto-Precharge 15 - 15 - 15 - ns WR Write recovery time with Auto-Precharge tWR/tCK - tWR/tCK - tWR/tCK - tCK tDAL Auto precharge write recovery + precharge time WR+tRP - WR+tRP - WR+tRP - tCK tWTR Internal write to read command delay 7.5 - 7.5 - tRTP Internal read to precharge command delay 7.5 tXSNR Exit self refresh to a Non-read command tXSRD Exit self refresh to a Read command tXP 7.5 ns 7.5 7.5 ns tRFC+10 - tRFC+10 tRFC+10 ns 200 - 200 200 tCK 2 - 2 - - 2 - Exit precharge power down to any Non- read command 2 - tCK 2 - tCK tXARD Exit active power down to read command 2 tXARDS Exit active power down to read command 6-AL 7-AL 8-AL tCK 3 3 3 tCK tCKE CKE minimum pulse width ODT tAOND ODT turn-on delay 2 2 2 2 2 2 tCK ODT turn-on tAC (min) tAC (max) tAC (min) tAC (max) tAC (min) tAC (max) ODT turn-on (Power down mode) tAC (min) +2 2tCK + tAC(max) +1 tAC (min) +2 2tCK + tAC(max) +1 tAC (min) +2 2tCK + tAC(max) +1 ns 2.5 2.5 2.5 2.5 2.5 2.5 tCK ODT turn-off tAC(min) tAC(max) +0.6 tAC(min) tAC(max) +0.6 tAC(min) tAC(max) +0.6 ns tAOFPD ODT turn-off (Power down mode) tAC (min)+2 2.5tCK + tAC(max) +1 tAC (min)+2 2.5tCK + tAC(max) +1 tAC (min)+2 2.5tCK + tAC(max) +1 ns tANPD ODT to power down entry latency 3 3 3 tCK tAXPD ODT power down exit latency 8 8 8 tCK tAON tAONPD tAOFD tAOF +1 ODT turn-off delay +0.7 +0.7 ns Speed Grade Definition Symbol Parameter -37B -25C -3C Min Max Min Max Min Max Unit tRAS Row Active Time 45 70,000 45 70,000 45 70,000 ns tRC Row Cycle Time 60 - 60 - 57.5 - ns tRCD RAS to CAS delay 15 - 15 - 12.5 - ns Row Precharge Time 15 - 15 - 12.5 - ns tRP REV 1.0 08/2006 19 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y25664TUH4B0F / M2Y51264TU88B0B / M2Y1G64TU8HB0B 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Package Dimensions (256MB, 1 Rank, 32Mx16 DDR2 SDRAMs) !(% + + + + + + + = >? + + + + + + + + + * # + + # + + + + * # + + + + + + "-*'& 6 + 6 + $ * ()* & + + * + + 4/ -')-' *052 , *3*) -2 ')@6 + 4*3 *23 = + ? A- '')*3 , ' '* * 4+ / * '= -23 '? Note: Device position is only for reference. REV 1.0 08/2006 20 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y25664TUH4B0F / M2Y51264TU88B0B / M2Y1G64TU8HB0B 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Package Dimensions (512MB, 1 Rank, 64Mx8 DDR2 SDRAMs) !(% + + + + + = >? + + + + + + + + + + + * # + + * + + # + + + + * # + + + + + + "-*'& 6 + 6 + $ * ()* & + + 4/ -')-' *052 , *3*) -2 ')@6 + 4*3 *23 = + ? A- '')*3 , ' '* * 4+ / * '= -23 '? Note: Device position is only for reference. REV 1.0 08/2006 21 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y25664TUH4B0F / M2Y51264TU88B0B / M2Y1G64TU8HB0B 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Package Dimensions + + + + + + + + + + + + = >? + + (1GB, 2 Rank, 64Mx8 DDR2 SDRAMs) Note: Device position is only for reference. REV 1.0 08/2006 22 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2Y25664TUH4B0F / M2Y51264TU88B0B / M2Y1G64TU8HB0B 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Revision Log Rev Date 0.1 07/2006 Preliminary Release 1.0 08/2006 Official Release -37B/-3C/-25C products. REV 1.0 08/2006 Modification 23 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.