EVB-LAN9252-3PORT EtherCAT(R) ESC PHY Connection Mode Evaluation Board User's Guide 2015 Microchip Technology Inc. DS50002403A Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. 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Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. 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(c) 2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63277-752-2 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == DS50002403A-page 2 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2015 Microchip Technology Inc. Object of Declaration: EVB-LAN9252-3PORT 2015 Microchip Technology Inc. DS50002403A-page 3 EVB-LAN9252-3PORT EtherCAT(R) ESC PHY Connection Mode User's Guide NOTES: DS50002403A-page 4 2015 Microchip Technology Inc. EVB-LAN9252-3PORT ETHERCAT(R) ESC PHY CONNECTION MODE USER'S GUIDE Table of Contents Preface ........................................................................................................................... 7 Introduction............................................................................................................ 7 Document Layout .................................................................................................. 7 Conventions Used in this Guide ............................................................................ 8 The Microchip Web Site ........................................................................................ 9 Development Systems Customer Change Notification Service ............................ 9 Customer Support ................................................................................................. 9 Document Revision History ................................................................................. 10 Chapter 1. Overview 1.1 Introduction ................................................................................................... 11 1.2 References ................................................................................................... 12 1.3 Terms and Abbreviations ............................................................................. 12 Chapter 2. Board Details 2.1 Power ........................................................................................................... 13 2.2 Resets .......................................................................................................... 13 2.2.1 Power-on Reset ......................................................................................... 13 2.2.2 Reset Out .................................................................................................. 13 2.3 Clock ............................................................................................................ 13 Chapter 3. Board Configuration 3.1 External PHY connection mode ................................................................... 15 3.2 Jumper Settings ........................................................................................... 15 3.2.1 Strap Options ............................................................................................ 16 3.2.2 LED Indicators ........................................................................................... 19 3.2.3 EEPROM Switch ....................................................................................... 19 3.2.4 SPI + 3 Port Mode Selection ..................................................................... 20 3.2.5 SoC ........................................................................................................... 22 3.3 Mechanicals ................................................................................................. 24 Appendix A. EVB-LAN9252-3PORT Evaluation Board A.1 Introduction .................................................................................................. 25 Appendix B. EVB-LAN9252-3PORT Evaluation Board Schematics B.1 Introduction .................................................................................................. 27 Appendix C. Bill of Materials (BOM) C.1 Introduction .................................................................................................. 39 Worldwide Sales and Service .................................................................................... 44 2015 Microchip Technology Inc. DS50002403A-page 5 EVB-LAN9252-3PORT EtherCAT(R) ESC PHY Connection Mode User's Guide NOTES: DS50002403A-page 6 2015 Microchip Technology Inc. EVB-LAN9252-3PORT ETHERCAT(R) ESC PHY CONNECTION MODE USER'S GUIDE Preface NOTICE TO CUSTOMERS All documentation becomes dated, and this manual is no exception. Microchip tools and documentation are constantly evolving to meet customer needs, so some actual dialogs and/or tool descriptions may differ from those in this document. Please refer to our web site (www.microchip.com) to obtain the latest documentation available. Documents are identified with a "DS" number. This number is located on the bottom of each page, in front of the page number. The numbering convention for the DS number is "DSXXXXXA", where "XXXXX" is the document number and "A" is the revision level of the document. For the most up-to-date information on development tools, see the MPLAB(R) IDE online help. Select the Help menu, and then Topics to open a list of available online help files. INTRODUCTION This chapter contains general information that will be useful to know before using the EVB-LAN9252-3PORT. Items discussed in this chapter include: * * * * * * Document Layout Conventions Used in this Guide The Microchip Web Site Development Systems Customer Change Notification Service Customer Support Document Revision History DOCUMENT LAYOUT This document describes how to use the EVB-LAN9252-3PORT as a development tool for the Microchip LAN9252 EtherCAT(R) slave controller. The manual layout is as follows: * Chapter 1. "Overview" - Shows a brief description of the EVB-LAN9252-3PORT. * Chapter 2. "Board Details" - Includes details and instructions for using the EVB-LAN9252-3PORT. * Chapter 3. "Board Configuration" - Describes the various EVB-LAN9252-3PORT board features, including jumpers, LEDs, test points, system connections, and switches. * Appendix A. "EVB-LAN9252-3PORT Evaluation Board" - This appendix shows the EVB-LAN9252-3PORT. * Appendix B. "EVB-LAN9252-3PORT Evaluation Board Schematics" - This appendix shows the EVB-LAN9252-3PORT schematics. * Appendix C. "Bill of Materials (BOM)" - This appendix includes the EVB-LAN9252-3PORT Bill of Materials (BOM). 2015 Microchip Technology Inc. DS50002403A-page 7 EVB-LAN9252-3PORT EtherCAT(R) ESC PHY Connection Mode User's Guide CONVENTIONS USED IN THIS GUIDE This manual uses the following documentation conventions: DOCUMENTATION CONVENTIONS Description Arial font: Italic characters Represents Referenced books Emphasized text A window A dialog A menu selection A field name in a window or dialog A menu path MPLAB(R) IDE User's Guide ...is the only compiler... the Output window the Settings dialog select Enable Programmer "Save project before build" A dialog button A tab A number in verilog format, where N is the total number of digits, R is the radix and n is a digit. A key on the keyboard Click OK Click the Power tab 4`b0010, 2`hF1 Italic Courier New Sample source code Filenames File paths Keywords Command-line options Bit values Constants A variable argument Square brackets [ ] Optional arguments Curly brackets and pipe character: { | } Ellipses... Choice of mutually exclusive arguments; an OR selection Replaces repeated text #define START autoexec.bat c:\mcc18\h _asm, _endasm, static -Opa+, -Opa0, 1 0xFF, `A' file.o, where file can be any valid filename mcc18 [options] file [options] errorlevel {0|1} Initial caps Quotes Underlined, italic text with right angle bracket Bold characters N`Rnnnn Text in angle brackets < > Courier New font: Plain Courier New Represents code supplied by user DS50002403A-page 8 Examples File>Save Press <Enter>, <F1> var_name [, var_name...] void main (void) { ... } 2015 Microchip Technology Inc. Preface THE MICROCHIP WEB SITE Microchip provides online support via our web site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQs), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives DEVELOPMENT SYSTEMS CUSTOMER CHANGE NOTIFICATION SERVICE Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. The Development Systems product group categories are: * Compilers - The latest information on Microchip C compilers, assemblers, linkers and other language tools. These include all MPLAB C compilers; all MPLAB assemblers (including MPASM assembler); all MPLAB linkers (including MPLINK object linker); and all MPLAB librarians (including MPLIB object librarian). * Emulators - The latest information on Microchip in-circuit emulators.This includes the MPLAB REAL ICE and MPLAB ICE 2000 in-circuit emulators. * In-Circuit Debuggers - The latest information on the Microchip in-circuit debuggers. This includes MPLAB ICD 3 in-circuit debuggers and PICkit 3 debug express. * MPLAB IDE - The latest information on Microchip MPLAB IDE, the Windows Integrated Development Environment for development systems tools. This list is focused on the MPLAB IDE, MPLAB IDE Project Manager, MPLAB Editor and MPLAB SIM simulator, as well as general editing and debugging features. * Programmers - The latest information on Microchip programmers. These include production programmers such as MPLAB REAL ICE in-circuit emulator, MPLAB ICD 3 in-circuit debugger and MPLAB PM3 device programmers. Also included are nonproduction development programmers such as PICSTART Plus and PIC-kit 2 and 3. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support 2015 Microchip Technology Inc. DS50002403A-page 9 EVB-LAN9252-3PORT EtherCAT(R) ESC PHY Connection Mode User's Guide Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://www.microchip.com/support DOCUMENT REVISION HISTORY Revision A (August 2015) * Initial Release of this Document. Revision B (August 2015) * Updated Appendix C. "Bill of Materials (BOM)". DS50002403A-page 10 2015 Microchip Technology Inc. EVB-LAN9252-3PORT ETHERCAT(R) ESC PHY CONNECTION MODE USER'S GUIDE Chapter 1. Overview 1.1 INTRODUCTION The LAN9252 is an 2/3 port EtherCAT(R) slave controller with dual integrated Ethernet PHYs which each contain a full-duplex 100BASE-TX transceiver and support 100Mbps (100BASE-TX) operation. 100BASE-FX is supported via an external fiber transceiver. Each port receives an EtherCAT frame, performs frame checking and forwards it to the next port. Time stamps of received frames are generated when they are received. The Loop-back function of each port forwards the frames to the next logical port, if there is either no link at a port, or if the port is not available, or if the loop is closed for that port. The Loop-back function of port 0 forwards the frames to the EtherCAT Processing Unit. The loop settings can be controlled by the EtherCAT master. Packets are forwarded in the following order: Port 0 -> EtherCAT Processing Unit -> Port 1 -> Port 2 The EtherCAT Processing Unit (EPU) receives, analyses and processes the EtherCAT data stream. The main purpose of the EtherCAT Processing unit is to enable and coordinate access to the internal registers and the memory space of the ESC, which can be addressed both from the EtherCAT master and from the local application. Data exchange between master and slave application is comparable to a dual-ported memory (process memory), enhanced by special functions e.g. for consistency checking (SyncManager) and data mapping (FMMU). Each FMMU performs the task of bitwise mapping of logical EtherCAT system addresses to physical addresses of the device. The scope of this document is to describe the EVB set-up for LAN9252 which supports 3-port mode and its jumper configurations. The LAN9252 is connected to an RJ45 Ethernet jack with integrated magnetics for 100BASE-T connectivity. A simplified block diagram of the LAN9252 can be seen Figure 1-1. 2015 Microchip Technology Inc. DS50002403A-page 11 EVB-LAN9252-3PORT EtherCAT(R) ESC PHY Connection Mode User's Guide FIGURE 1-1: EVB-LAN9252-3PORT BLOCK DIAGRAM Board to Board Connector SOC ON Board SOC PIC32MX795F512L EtherCAT ID Select Switches MII Connector Power Supply Module 5V Board to Board Connector SOC SPI/SQI/I2C AARDVARK EEPROM Microchip LAN9252 Straps 1.2 Port 1 Port 2 100BASETX Ethernet Magnetics & RJ45 100BASETX Ethernet Magnetics & RJ45 Ethernet Ethernet Crystal REFERENCES Concepts and material available in the following documents may be helpful when reading this document. Visit www.microchip.com for the latest documentation. * LAN9252 Datasheet * AN 8.13 Suggested Magnetics * EVB-LAN9252-3PORT Schematics 1.3 TERMS AND ABBREVIATIONS * * * * * * * DS50002403A-page 12 ESC - EtherCAT(R) Slave Controller EVB - Evaluation Board SPI - Serial Protocol Interface 100BASE-TX- 100 Mbps Fast Ethernet, IEEE802.3u Compliant GPIO - General Purpose I/O MII - Media Independent Interface RMII - Reduced Media Independent Interface 2015 Microchip Technology Inc. EVB-LAN9252-3PORT ETHERCAT(R) ESC PHY CONNECTION MODE USER'S GUIDE Chapter 2. Board Details 2.1 POWER DC 5V is applied through (J1) DC Socket, powered by a +5V external wall adapter. Switch (SW1) needs to be ON position for the 5V to reach the 3.3V regulator. Glowing of Green LED (D1) indicates successful generation of 3.3V o/p. This Power is supplied to the LAN9252 and it has internal 1.2 V regulator which supplies power to the internal core logic. 2.2 RESETS 2.2.1 Power-on Reset A power-on reset occurs whenever power is initially applied to the LAN9252 or if the power is removed and reapplied to the LAN9252. This event resets all circuitry within the LAN9252. After initial power-on, the LAN9252 can be reset by pressing the reset switch (SW2). The reset LED D2 will assert (red) when the LAN9252 is in reset condition. For stability, a delay of approximately 180ms is added from the +3.3V o/p to reset release. 2.2.2 Reset Out The LAN9252 reset pin can be configured as an output to reset the SoC. The RST# pin becomes an open-drain output and is asserted for the minimum required time of 80ms 2.3 CLOCK LAN9252 requires an external 25Mhz crystal or clock. By default, Short 1-2 of J14 header to connect the 25 MHz crystal Y1 to the internal oscillator of the LAN9252. 2015 Microchip Technology Inc. DS50002403A-page 13 EVB-LAN9252-3PORT ETHERCAT(R) ESC PHY CONNECTION MODE USER'S GUIDE Chapter 3. Board Configuration The following sections describe the various board features, including jumpers, LEDs, test points, system connections, and switches. A top view of the LAN9252 in 3-port mode is shown in Figure 3-1. FIGURE 3-1: LAN9252 - 3 PORT MODE Port 0 (External) (with integrated magnetics & LEDs) EVB-LAN8740 MII PHY Board Port 0 - MII Link Port 0 (Female) MII Connector Port 0 - MII Reset Power On Board SoC ADD on SoC Header TX Shift EEPROM Strap Microchip LAN9252 Port 1 (with integrated magnetics & LEDs) Note: 2015 Microchip Technology Inc. Port 2 (with integrated magnetics & LEDs) 3-port Mode: Port 1 and Port 2 both are Internal, Port 0 is External. DS50002403A-page 14 Board Configuration 3.1 EXTERNAL PHY CONNECTION MODE Figure 3-2 shows the principle connection between ESC and PHY. The clock source of Ethernet PHYs and ESC has to be the same quartz or quartz oscillator. TX_CLK is usually not connected unless automatic TX Shift compensation is used, because the ESCs do not incorporate a TX FIFO. The TX signals can be delayed inside the ESC for TX_CLK phase shift compensation. LINK_STATUS is an LED output indicating a 100 Mbit/s (Full Duplex) link. FIGURE 3-2: 3.2 EXTERNAL PHY CONNECTION JUMPER SETTINGS The default jumper settings for the LAN9252 are given below in Table 3-1. TABLE 3-1: 2015 Microchip Technology Inc. DEFAULT JUMPER SETTINGS Jumper Pin Settings J4 & J7 2-3 J5 & J8 1-2 J6 & J9 1-2 J15 & J16 2-3 J19,J20,J21,J22 & J23 OPEN DS50002403A-page 15 EVB-LAN9252-3PORT EtherCAT(R) ESC PHY Connection Mode User's Guide 3.2.1 Strap Options The following tables describe the default settings and jumper descriptions for the EVB-LAN9252-3PORT. These defaults are the recommended configurations for evaluation of the LAN9252. These settings may be changed as needed, however, any deviation from the defaults settings should be approached with care and knowledge of the schematics and datasheet. An incorrect jumper setting may disable the board. 3.2.1.1 JUMPERS J4:J9 AND J15:J16 Jumpers J4 through J9 and J15 through J16 set various functions of the LAN9252. They can also be used as GPIOs, LED drivers. When used as LED drivers, as they are on the EVB-LAN9252-3PORT, they are connected a specific way to set the strap value to a "1", and another way to set the strap value to a "0". Figure 4 illustrates the schematics connections with the D3 circuit as a pull-up, and the D4 circuit as a pull-down. To illuminate D3, the LAN9252 will drive the cathode of the D3 low. To illuminate D4, the LAN9252 will drive the cathode of the D4 high. The J4 - J15 jumpers must be configured in pairs to identical settings in order to realize the D3 circuit or the D4 circuit. The pairings are as follows: - J4 & J7 J6 & J9 J5 & J8 J15& J16 The following subsections detail the jumper pair settings, their associated strap settings, and the functional effects of setting the straps. All strap values are read during power-up and on the rising edge of nRST signal. Once the strap value is set, the LAN9252 will drive the LED's high or low for illumination according the strap value. For other designs which may use these pins as GPIOs refer to LAN9252 datasheet for additional information. In those cases, internal default straps must be changed by an I2C or SMI master or through EEPROM fields. FIGURE 3-3: DS50002403A-page 16 LED STRAP CIRCUIT 2015 Microchip Technology Inc. Board Configuration 3.2.1.2 EEPROM CONFIGURATION EEPROM_size_strap (J6 & J9): This strap determines the EEPROM size range. A low selects 1K bits (128 x 8) through 16K bits (2K x 8)_24C16. A high selects 32K bits (4K x 8) through 512K bits (64K x 8) or 4Mbits (512K x 8)_24C512. TABLE 3-2: EEPROM SIZE CONFIGURATION Header Pin Settings eeprom_size_strap Value J6 & J9 1-2 (Default) 1 EEPROM size = 32K bits (4K x 8) through 4Mbits (512K x 8). J6 & J9 2-3 0 EEPROM size = 1K bits (128 x 8) through 16K bits (2K x 8). 3.2.1.3 Description TX SHIFT STRAP EtherCAT MII Port TX Timing Shift Strap is used to configure default value of EtherCAT MII Port TX Timing Shift Strap "TX_SHIFT[1:0]". These straps determine the value of the MII TX Timing Shift for the MII. TABLE 3-3: ETHERCAT MII PORT TX TIMING SHIFT STRAP OPTIONS TX_SHIFT 1 TX_SHIFT 0 0 0 20 0 1 30 (Default) 1 0 0 1 1 10 TABLE 3-4: TX Timing Shift (ns) MII TX TIMING SHIFT CONFIGURATIONS Switch Short Pins TX_SHIFT[1:0] Switch KNOB Position SW9 1-2 01 DOWN SW10 1-3 Note: 3.2.1.4 UP For switch P/N: 450301014042, pin 1 is at the middle of the switch. To short 1-2, knob position must be in the 1-3 position, and vice versa. COPPER AND FIBER STRAPS The LAN9252 supports 100BASE-TX (Copper) and 100BASE-FX (Fiber) modes. In 100BASE-FX operation, the presence of the receive signal is indicated by the external transceiver as either an open-drain, CMOS level, Loss of Signal (SFP) or a LVPECL Signal Detect (SFF). This EVB supports 100BASE-TX (Copper) and SFP 100BASE-FX (Fiber) modes. By default Copper Mode is active. Fiber Mode is supported as an assembly option. To select the Copper or Fiber Mode, the respective strap and signal routing resister assembly options must to be configured. Note: 2015 Microchip Technology Inc. Vendor part number for SFP: Finisar/FTLF1217P2 DS50002403A-page 17 EVB-LAN9252-3PORT EtherCAT(R) ESC PHY Connection Mode User's Guide 3.2.1.4.1 Copper Mode Strap The EVB-LAN9252-3PORT is set to Copper Mode by default. Table 3-5 details the required strap resistor settings for Copper Mode operation. TABLE 3-5: COPPER MODE STRAP RESISTORS Resistors Signal Names Description R79 (10K) FXLOSEN Copper twisted pair for ports A and B further determined by FXSDENA and FXSDENB R76, R80 (10K) FXSDA/FXSDB Note: Configures Port 0 and Port 1 to Copper Mode R75, R77, and R78 must not be populated (DNP). Additionally, the signal routing resistors detailed in Table 3-6 must be assembled for Copper mode operation. TABLE 3-6: COPPER MODE SIGNAL ROUTING RESISTORS Resistors Description R17, R19,R21, R23 Port 0 Copper mode is Enabled R31, R33, R35, R37 Port 1 Copper mode is Enabled Note: R16, R18, R20, R22, R30, R32, R34, and R36 (0402 package) must not be populated (DNP). 3.2.1.4.2 Fiber Mode Strap The EVB-LAN9252 supports SFP type 100BASE-FX mode. To enable Fiber Mode, the respective strap and signal routing resisters must be configured. Note: Copper Mode related resistors must be DNP while Fiber Mode is active (See Section 3.2.1.4.1 "Copper Mode Strap"). Table 3-7 details the required strap resistor settings for Fiber Mode operation. TABLE 3-7: FIBER MODE STRAP RESISTORS Resistors R77 (10K) R75, R78 (10K) Note: Description Configures Port 0 & 1 to FX_LOS Mode Configures Port 0 & 1 to Fiber mode, respectively R76, R79, and R80 must not be populated (DNP). Additionally, the signal routing resistors detailed in Table 3-8 must be assembled for Fiber Mode operation. TABLE 3-8: FIBER MODE SIGNAL ROUTING RESISTORS Resistors Note: DS50002403A-page 18 Description R16, R18, R20, R22 Port 0 Fiber mode Enabled R30, R32, R34, R36 Port 1 Fiber mode Enabled R17, R19, R21, R23, R31, R33, R35, and R37 (0402 package) must not be populated (DNP). 2015 Microchip Technology Inc. Board Configuration 3.2.1.4.3 FX-LOS Fiber Mode Strap The EVB-LAN9252-3PORT is set to Copper Mode by default. Table 3-9 details the required strap resistor settings for FX-LOS Fiber Mode operation. TABLE 3-9: FX-LOS FIBER MODE STRAP RESISTOR SETTINGS R77 (10K) R79 (10K) Reference Voltage (V) Populate DNP 3.3 A level above 2V selects FX-LOS for Port 0 and Port1 Populate Populate 1.5 A level greater than 1.5V and below 2V selects FX-LOS for Port 0 and FX-SD / copper twisted pair for Port 1, further determined by FXSDB DNP Populate Note: 3.2.2 Function 0 (DEFAULT) A level of 0V selects FX-SD / copper twisted pair for Ports 0 and 1, further determined by FXSDA and FXSDB The above strap details describe the LAN9252 function. This EVB does not support SFF Fiber Mode. Therefore, FX-SD related straps are not applicable. LED Indicators The D3, D4 and D7 LEDs are used to indicate the Link/Activity status on the corresponding EVB ports, as detailed in Table 3-10. The Link/Act LED should be ON at each port when the cable is present. If the Link/Act LED is not ON, it indicates there is an issue with the connection or cable. TABLE 3-10: D3, D4 AND D7 LINK/ACTIVITY LED STATUS INDICATORS State Description Off Link is down Flashing Green Link is up, with activity Steady Green Link is up, no activity Additionally, the D5 LED is used as a RUN indicator (green) to show the AL status of the EtherCAT State Machine (ESM), as detailed in Table 3-11. TABLE 3-11: ESM AL STATUS State Description Off The device is in INITIALIZATON state Blinking (on 200ms, off 200ms) The device is in PRE-OPERATIONAL state Single Flash (on 200ms, off 1000ms) The device is in SAFE-OPERATIONAL state On The device is in OPERATIONAL state Flickering (on 50ms, off 50ms) The device is booting and has not yet entered the INITIALIZATION state, or the device is in the BOOTSTRAP state and firmware download is in progress. (Optional. Off when not implemented.) Additionally, LED D10 is used as Error LED and the LED D9 is DNP. 3.2.3 EEPROM Switch The EVB-LAN9252-3PORT utilizes 0x50 (7-bit) I2C slave addressing. The SW3 switch can be used to select the A0, A1, and A2 address bits, as shown in Figure 3-4 and Table 3-12. The eighth bit of the slave address determines if the master device wants to read or write to the EEPROM (24FC512). 2015 Microchip Technology Inc. DS50002403A-page 19 EVB-LAN9252-3PORT EtherCAT(R) ESC PHY Connection Mode User's Guide FIGURE 3-4: SLAVE ADDRESS ALLOCATION TABLE 3-12: EEPROM SWITCH Ref. Des Description 2C I EEPROM Address selection (A0,A1,A2) see Figure 3-4 SW3 3.2.4 SPI + 3 Port Mode Selection 3.2.4.1 SPI Settings ON for logic 0 (default) OFF for logic 1 The SPI lines are directly connected to the SOC. No jumper settings are required for SPI. 3.2.4.2 SPI/SQI/I2C AARDVARK(R) J11 & J12 connectors are used for Aardvark/SPI headers. Respective pin details are given below in Table 3-13. Resisters R61, R62 & R122 are need to be populated to use this option. By default, R61, R62 & R122 are DNP. TABLE 3-13: 3.2.4.3 SPI/SQI/I2C AARDVARK(R) PIN DETAILS Signal Pin No SCL J11.1 SDA J11.3 SCK J11.7 SCS# J11.9 SI(SIO0) J11.8 SO(SIO1) J11.5 SIO2 J12.3 SIO3 J12.4 3 PORT MODE The following Assembly/jumper settings are used to configure LAN9252 in to 3-Port mode. 3.2.4.3.1 Assembly of the Boards The MII Female Connector (J27) is used to connect External PHY Board. EVB-LAN8740 MII PHY Board have been used as External PHY Board as shown in Figure 3-2. DS50002403A-page 20 2015 Microchip Technology Inc. Board Configuration 3.2.4.3.2 External PHY - Power The Jumper (J26) is used to supply "on-board 5V or delayed 5V" to external PHY Board. TABLE 3-14: EXTERNAL PHY BOARD PIN SETTINGS Header Pin Settings J26 1-2 Connects on-board 5V to an external PHY Board (Default) J26 2-3 Connects Delayed 5V to an external PHY Board in Enhanced Link detection 3.2.4.3.3 Description External PHY - MII Link Connect MII Link from an external PHY board (EVB-LAN8740) to the 1st pin of J24 through jumpers as shown in Figure 3-2. 3.2.4.3.4 External PHY - MII Reset Connect reset from an external PHY board (EVB-LAN8740) to the 3rd pin of J24 through jumpers as shown in Figure 3-2. 3.2.4.3.5 External PHY - CLK The MII_CLK25 from LAN9252 is available on J24-12th pin and this signal has to be routed to Master Clock of the External PHY. Note: The EVB-LAN8740 is used for an External PHY. Refer to link http://ww1.microchip.com/downloads/en/DeviceDoc/evb8740_user.pdf for more details on EVB-LAN8740. Remove on board crystal and connect MII-CLK25 from MII connector to the LAN8740 OSCO pin as shown below in Figure 3-5 (through Green wire). FIGURE 3-5: 2015 Microchip Technology Inc. LAN8740 DS50002403A-page 21 EVB-LAN9252-3PORT EtherCAT(R) ESC PHY Connection Mode User's Guide 3.2.4.3.6 Chip Mode Selection Chip Mode Straps (J4,J7 &J5,J8) are used configure default value of EtherCAT Chip Mode Strap "chip_mode_strap[1:0]". This strap determines the number of active ports and port types. TABLE 3-15: CHIP MODE CONFIGURATION Header Pin Settings chip_mode_strap[1:0] Description J4,J7 1-2 01 J5,J8 2-3 3 port downstream mode. Ports 1 and 2 are connected to internal PHYs A and B. Port 0 is connected to the external MII pins Note: 3.2.5 Default setting LAN9252 EVB -- Chip mode 10 (3port downstream mode). Chip mode 00 and 11 are not supported by this EVB. SoC The EVB-LAN9252 supports both an on-board SoC and add-on SoC. By default, the on-board SoC is enabled. However, an external add-on SoC can be connected via the add-on SoC headers P8 and P9. The SoC selection is configured via the SW5 switch, as detailed in the following subsections. 3.2.5.1 SOC SELECTION Whenever the ADD ON PCB is used for SoC, then the Switch knob position must be UP. The SW5 switch selects the enabled SoC. The SW5 switch knob position must be down (Text = "PIC") to select the on-board PIC. If the switch knob position is up (Text = "PIM"), then the add-on board/SoC is selected and the on-board PIC is always in the reset state. Whenever an add-on board/SoC is used, the switch knob must be in the up position. TABLE 3-16: 3.2.5.2 SOC SWITCH CONFIGURATION Switch Position SW5 DOWN SW5 UP Settings PIC enabled ADD ON BOARD enabled ON-BOARD PIC By default, the on-board Microchip PIC32MX795F512L (U7) is used as the default SoC. The LAN9252 can be connected to the PIC using SPI interface. No jumper settings are required to establish SPI communications between PIC and LAN9252. 3.2.5.3 RESET SW5 is used to reset the on-board PIC. The LAN9252 can also reset the SoC if the reset pin is configured to output mode. For stability, a delay of approximately 180ms is added from the 3.3V o/p to reset release. 3.2.5.4 ICSP HEADER The programing is done using the ICSP header - J13. Table 3-17 shows the PIN details of J13. TABLE 3-17: DS50002403A-page 22 J13 PIN DETAILS J13 PIN No Signals Detail 1 MLCR 2015 Microchip Technology Inc. Board Configuration TABLE 3-17: J13 PIN DETAILS (CONTINUED) J13 PIN No 3.2.5.5 Signals Detail 2 3V3 3 GND 4 PGD2 5 PGC2 6 NC SOC EEPROM The EVB-LAN9252 provides an optional SoC EEPROM. Some SoCs may require an EEPROM. However, the PIC on-board SoC and PIC based add-on SoC boards do not require this EEPROM. 3.2.5.6 ADD-ON SOC An add-on board can be attached to the EVB-LAN9252 to use an add-on SoC. The add-on board must be mounted to the P8 and P9 connectors (2x23, 100mil normal gold plated berg stick). The SW5 switch must be in the up position when using an add-on SoC. Additionally, the J10 2-pin jumper must be shorted to route power to the add-on board from the EVB-LAN9252. An ADD on BOARD can be used for SoC. At the connectors P8 & P9 (2X23, 100mil normal gold platted berg stick) the ADD on BOARD need to be mounted. SW5 - switch NOB position must be UP to use this option. Also J10 - 2 pin jumper must be short to get the power for the ADD on BOARD. 3.2.5.7 ESC ID SELECT The signals shown in Table 3-18 are provided as EtherCAT ID selection for complex ESCs. Switches SW7, SW8 and respective pull-up resistors are used to configure the ID select signals high or low. By default, the EtherCAT ID values is set to 5. To achieve this, ID0 and ID2 are high via pull-up resistors, while the remainder of the ID select signals are low (ID1, ID3-ID15). When required, setting the respective switch knob to the on position will change the ID select signal to low. TABLE 3-18: ID SELECT SIGNALS ID Selection Signal PIC PIN No SW PIN No Res Ref. Des ID_SELECT_RB0 25 SW7.1 R123 ID_SELECT_RB1 24 SW7.2 R124 ID_SELECT_RB2 23 SW7.3 R126 ID_SELECT_RB3 22 SW7.4 R125 ID_SELECT_RB4 21 SW7.5 R127 ID_SELECT_RB5 20 SW7.6 R128 ID_SELECT_RB8 32 SW7.7 R129 ID_SELECT_RB9 33 SW7.8 R130 ID_SELECT_RB10 34 SW8.1 R131 ID_SELECT_RB11 35 SW8.2 R133 ID_SELECT_RB12 41 SW8.3 R134 ID_SELECT_RB13 42 SW8.4 R132 ID_SELECT_RC1 6 SW8.5 R135 ID_SELECT_RC2 7 SW8.6 R136 ID_SELECT_RC3 8 SW8.7 R137 ID_SELECT_RC4 9 SW8.8 R138 2015 Microchip Technology Inc. DS50002403A-page 23 EVB-LAN9252-3PORT EtherCAT(R) ESC PHY Connection Mode User's Guide 3.3 MECHANICALS Figure 3-6 details EVB-LAN9252(SPI + 3 Port) mechanical dimensions. Dimensions are in mm. FIGURE 3-6: DS50002403A-page 24 EVB-LAN9252 MECHANICAL DIMENSIONS 2015 Microchip Technology Inc. EVB-LAN9252-3PORT ETHERCAT(R) ESC PHY CONNECTION MODE USER'S GUIDE Appendix A. EVB-LAN9252-3PORT Evaluation Board A.1 INTRODUCTION This appendix shows the EVB-LAN9252-3PORT Evaluation Board. FIGURE A-1: EVB-LAN9252-3PORT EVALUATION BOARD 2015 Microchip Technology Inc. DS50002403A-page 25 EVB-LAN9252-3PORT EtherCAT(R) ESC PHY Connection Mode User's Guide NOTES: DS50002403A-page 26 2015 Microchip Technology Inc. EVB-LAN9252-3PORT ETHERCAT(R) ESC PHY CONNECTION MODE USER'S GUIDE Appendix B. EVB-LAN9252-3PORT Evaluation Board Schematics B.1 INTRODUCTION This appendix shows the EVB-LAN9252-3PORT Evaluation Board Schematics. 2015 Microchip Technology Inc. DS50002403A-page 27 DS50002403A-page 28 BLOCK DIAGRAM :-"/ EVB 2015 Microchip Technology Inc. EVB-LAN9252-3PORT EtherCAT(R) ESC PHY Connection Mode User's Guide BLOCK DIAGRAM FIGURE B-1: POWER SUPPLY & RST POWER SUPPLY FB1 2 3 5V_SW 3 R1 0 2A/0.05DCR 2 Switch, SPDT, Slide P/N:1101M2S3CQE2 J1 C2 10uF 25V EN12_1 2 1 VIN ENABLE C3 0.1uF 3_Amp VOUT TRIM GND C1 OKR-T/3-W12-C R3 3.30K 1% (Ra) R4 470E 1% (Rb) 3V3 C5 4.7uF DNP 0.1uF D1 GRN Note: 1.POR -> Reset to ASIC & SOC (Default) 2.RESET O/P from ASIC -> Reset to EX-PHY (PORT2) & SOC :Only Ethercat sku 3.RESET from SOC (GPIO/RST-O/P) -> Reset to ASIC 4.RESET from Push Botton -> Reset to ASIC & SOC RESET NDS355AN_NMOS 1 3 R8 1K D RST# Q1 1 G 5 RESET# 3 MR# 2 3V3 VDD 4 C4 10uF 5 U2 2 1/10W 1% 2 sw_pb_2P 1 R7 100 R5 4.75K 1% 0.1uF GND 1 C6 2 SW2 R4A 33E 1% RESET Options 3V3 R6 10.0K 1/10W 1% TP9 BLACK R2 1K 4 5 3 3V3 Reset Generator TP8 BLACK 1 1 A 5V_EXT 3V3 3V3 C 1 TP2 ORANGE 3 V REGULATOR, 3A ( 3V3 fixed when Rb=503e) U1 2 SW1 "3V3 Present" TP1 RED 5V S SOT23_5 Threshold = 2.64V Delay = 180ms Br_Red-RA U3 2 4 TPS3125 74LVC1G14 1 3 2015 Microchip Technology Inc. FIGURE B-2: R9 2.2K 1 A C 2 D2 "Reset" Schematics DS50002403A-page 29 LAN9252 3V3 Power Supply Filtering VDD33TXRX1 FB2 3V3 2A/0.05DCR VDDCR VDD12TX1 VDD12TX2 0.1uF FB5 2A/0.05DCR (*short 1&2) OSCI OSCO 1 3V3 3 1 2 4 C27 REG_EN 18pF R10 12.1K 1% RBIAS RST# IRQ ATEST/FXLOSEN 7 57 11 44 8 41 I2C2_SCL I2C2_SDA GPIO0 GPIO1 GPIO2 43 42 48 46 45 RBIAS RST# ATEST/FXLOSEN TESTMODE I2CSCL/EESCL/TCK I2CSDA/EESDA/TMS VDDCR1 VDDCR2 VDDCR3 FXSDENA/FXSDA/FXLOSA REG_EN IRQ 6 24 38 14 20 32 37 47 58 5 OSCVDD12 OSCI OSCO OSCVSS INT PORT0 J14 25.000MHz 25ppm Y1 VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 5 3 1 INT PORT1 (Only for Lan9252) R167 100K DNP 18pF VDD33BIAS VDD33 C26 I2C GND 6 4 2 OSCI_Combined OTHER SIGNALS VCC 2 POWER 4 2 1 OSC HEADER 3X2 25MHz Y4 OSCILLATOR DNP 3 OE OUT VDD33TXRX1 VDD33TXRX2 U4A 51 64 Note: OSCVSS need to connect to Chip gnd. 56 59 VDD12TX1 VDD12TX2 0.1uF 3V3 R166 100K DNP C85 0.1uF DNP VDDCR VDD33TXRX1 VDD33TXRX2 BLM18EG221SN1D C25 3V3 TXNA TXPA RXNA RXPA TXNB TXPB RXNB RXPB FXSDENB/FXSDB/FXLOSB LINKACTLED0/TDO/LEDPOL0/CHIP_MODE0 LINKACTLED1/TDI/LEDPOL1/CHIP_MODE1 RUNLED/LEDPOL2/E2PSIZE 2015 Microchip Technology Inc. LAN9252 65 GND GPIO 9 52 53 54 55 63 62 61 60 10 FXSDA/FXLOSA TXNA TXPA RXNA RXPA TXNB TXPB RXNB RXPB FXSDB/FXLOSB C20 C21 C22 0.1uF 0.1uF 1uF C18 0.1uF C16 C17 0.1uF 0.1uF C14 C15 0.1uF 0.1uF 0.1uF C13 C12 DNP 1.0uF C11 470pF 3V3 2A/0.05DCR C24 Low ESR C19 3V3 FB4 C23 1.0uF DNP 0.1uF 3V3 0.1uF C9 2A/0.05DCR DNP 1.0uF 0.1uF VDD33TXRX2 VDD12TX1 VDD12TX2 FB3 C8 C10 C7 1.0uF DNP EVB-LAN9252-3PORT EtherCAT(R) ESC PHY Connection Mode User's Guide DS50002403A-page 30 FIGURE B-3: COPPER MODE INTERFACE VDD33TXRX1 DNP R16 R17 0 0 FX_SFP-TXPA TXNA DNP R18 R19 0 0 FX_SFP-TXNA RXPA DNP R20 R21 0 0 FX_SFP-RXPA RXNA DNP R22 R23 TXPA R12 49.9 1/10W 1% R13 49.9 1/10W 1% R14 49.9 1/10W 1% A C 9 10 T1 Pulse J0011D01BNL R11 49.9 1/10W 1% R15 0 GRN 1 COP-TXPA 4 2 COP-TXNA RJ45 XMIT TD+ 75 75 1 TXCT 4&5 TD- 2 LED1 (Green) = LINK/ACT CHS GND Note: Capacitors C10 through C13 are optional for EMI purposes and are not populated on the LAN8740/41 evaluation board. These capacitors are required for operation in an EMI constrained environment. YEL R24 A1 12 NC C1 8 50V 10% 2 kV 11 C31 10pF 50V 5% DNP MTG1 C30 10pF 50V 5% DNP 6 1000 pF MTG C29 10pF 50V 5% DNP 7 3 7&8 RD- 13 C28 10pF 50V 5% DNP C32 0.022uF 75 RXCT 16 6 75 15 COP-RXNA LED2 (Yellow) = SPEED RD+ GND1 5 FX_SFP-RXNA RCV GND 0 0 3 COP-RXPA 14 2015 Microchip Technology Inc. FIGURE B-4: 0 RES1210 VDD33TXRX2 DNP R30 R31 0 0 FX_SFP-TXPB TXNB DNP R32 R33 0 0 FX_SFP-TXNB RXPB DNP R34 R35 0 0 FX_SFP-RXPB RXNB DNP R36 R37 TXPB R26 49.9 1/10W 1% R27 49.9 1/10W 1% R28 49.9 1/10W 1% A C 9 10 T2 Pulse J0011D01BNL R25 49.9 1/10W 1% R29 0 GRN 1 COP-TXPB 4 COP-TXNB 2 COP-RXPB 3 RJ45 XMIT TD+ 75 75 1 TXCT 4&5 TD- 2 LED1 (Green) = LINK/ACT CHS GND DS50002403A-page 31 Note: Capacitors C10 through C13 are optional for EMI purposes and are not populated on the LAN8740/41 evaluation board. These capacitors are required for operation in an EMI constrained environment. R38 C1 0 RES1210 A1 YEL 12 NC 2 kV 11 8 MTG1 50V 10% MTG C36 10pF 50V 5% DNP 6 1000 pF 16 C35 10pF 50V 5% DNP 7&8 RD- 13 C34 10pF 50V 5% DNP 7 3 Schematics C33 10pF 50V 5% DNP C37 0.022uF 75 RXCT 15 6 GND1 COP-RXNB 75 GND 5 FX_SFP-RXNB LED2 (Yellow) = SPEED RD+ 14 0 0 RCV SFP INTERFACE 3V3 R39 82 R40 82 R41 49.9 R42 49.9 Note:Place capacitors, and resistors close to FOT C38 0.1uF C40 0.1uF 3V3 Fiber Port 0 :SFP Interface R43 82 FX_SFP-RXNA R44 82 R45 49.9 R46 49.9 Note:Place capacitors, and resistors close to FOT C39 0.1uF C41 0.1uF C43 0.1uF Fiber Port 1 :SFP Interface FX_SFP-RXNB FX_SFP-RXPA FX_SFP-RXPB C42 FX_SFP-TXPA 0.1uF FX_SFP-TXPB 3V3 R47 100 3V3 R48 100 SFP_VCCT C44 L2 SFP_VCCR FX_SFP-TXNA 1uH C45 C48 + 10uF 16V C47 0.1uF C49 0.1uF R51 130 R52 130 L1 C50 + 10uF 16V DNP 20 19 18 17 16 15 14 13 12 11 1uH R53 4.7K R54 4.7K C55 0.1uF Note:Place resistors close to ASIC J3 FTLF1217P2 R55 4.7K 2015 Microchip Technology Inc. FXSDA/FXLOSA R56 4.7K VeeT TXFault TX Disable MOD-DEF(2) MOD-DEF (1) MOD-DEF (0) Rate Select LOS VeeR VeeR1 C54 + 10uF 16V SFP_VCCT2 1 2 3 4 5 6 7 8 9 10 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 SFP_VCCT 31 30 29 28 27 26 25 24 23 22 21 VeeT1 TDTD+ VeeT2 VccT VccR VeeR2 RD+ RDVeeR3 20 19 18 17 16 15 14 13 12 11 VeeT1 TDTD+ VeeT2 VccT VccR VeeR2 RD+ RDVeeR3 J2 FTLF1217P2 VeeT TXFault TX Disable MOD-DEF(2) MOD-DEF (1) MOD-DEF (0) Rate Select LOS VeeR VeeR1 Note:Place resistors close to ASIC R57 4.7K R58 4.7K R59 4.7K FXSDB/FXLOSB R60 4.7K 31 30 29 28 27 26 25 24 23 22 21 C56 + 31 10uF 30 16V 29 28 27 26 25 24 23 22 21 C52 + 10uF 16V C51 0.1uF L3 L4 1uH SFP_VCCR2 SFP_RD2+ SFP_RD2- C46 + 10uF 16V DNP SFP_TD2SFP_TD2+ SFP_RD+ SFP_RD- SFP_TDSFP_TD+ R50 130 0.1uF FX_SFP-TXNB 0.1uF R49 130 SFP_VCCT2 C57 0.1uF 1uH C53 0.1uF EVB-LAN9252-3PORT EtherCAT(R) ESC PHY Connection Mode User's Guide DS50002403A-page 32 FIGURE B-5: GPIO [0:2] & LED_POL_Strap I2C EEPROM R73 1K R140 332 1/10W 1% R74 1K 8 VCC 2K I2C2_SCL TH IC. Different sizes can be mounted GPIO1 I2C EEPROM Lower size Below 16K(2K X 8) 3 1 J16 3 1 GPIO2 WP I2C2_SDA 6 SCL 24FC04 J8 3 1 GPIO0 5 SDA 2 2 2 2 J9 3 1 J7 A0 A1 A2 SW DIP-4/SM 2 R72 1K R68 R67 1 7 2K R65 R66 1 2 3 I2C2_1 I2C2_2 I2C2_3 I2C2_7 GND 1 2 3 4 0.1uF 4 8 7 6 5 2 2 R64 R63 SW3 LED1_CATHODE LEDPOL6_CATHODE 2 LED0_CATHODE LED2_CATHODE U5 R139 10.0K 4.7K R71 10.0K 4.7K 1 3 GPIO2 2 2 1 1 1 R70 10.0K 3V3 C58 GPIO1 LED1_ANODE LEDPOL6_ANODE 3V3 GPIO0 J15 2 J5 LED0_ANODE LED2_ANODE 3V3 MII_LINKPOL 3 1 3 1 3 1 J6 2 J4 R69 10.0K 3V3 GPIO1 4.7K 3V3 GPIO2 4.7K 3V3 GPIO0 1 3V3 2 2015 Microchip Technology Inc. STRAP, GPIO, I2C & FXLOS FIGURE B-6: MII_LINKPOL I2C EEPROM Higher size Above 16K(2K X 8) LINK/ACT LED2 LED0_ANODE LED0_CATHODE LED1_ANODE LED1_CATHODE D3 1 GRN A LINK/ACT 2 C D4 1 GRN A LINK/ACT 2 C LEDPOL6_ANODE LEDPOL6_CATHODE LEDPOL6_ANODE LED0_CATHODE D7 1 LED A C 2 DNP D9 1 LED A C FX_Los_Strap_1 & 2 2 3V3 RUNLED LED2_ANODE LED2_CATHODE D5 1 GRN A 2 R77 10K DNP C GPIO0 =LED0,LEDPOL0,MNGT0 ATEST/FXLOSEN GPIO1 = LED1,LEDPOL1,MNGT1 Management/LED Polarity Strap Signal Name Logic 0 Connector J4,J7 (2&3) R79 10K GPIO2 = LED2,LEDPOL2,E2PSIZE FX_Mode_Strap_1 & 2 'HIDXOW &RSSRUPRGH 5 '13 5 $VVHPEOH 6HOHFWV);6'FRSSHUWZLVWHGSDLUIRUSRUWV$DQG%IXUWKHUGHWHUPLQHG E\);6'(1$DQG);6'(1% J4,J7 (1&2) The LED is set as active low, The LED is set as active high. 3V3 MNGT1 1 J5,J8 (1&2) The LED is set as active low, 0 J6,J9(2&3) The LED is set as active high. EEPROM Size=1K bits (128 x 8) through 16K bits (2K x 8) 1 J6,J9 (1&2) The LED is set as active low, EEPROM Size=32K bits (4K x 8) through 512K bits (64K x 8) or 4Mbits (512K x 8) (LAN9252 only) SW9 R141 E2ESIZE 10K R78 DNP 10K FXSDB/FXLOSB R80 10K TX_SHIFT0 10K 3V3 SW10 2 1 3 JS102011CQN R142 10K TX_SHIFT1 )LEHU0RGH 55$VVHPEOH 5 5 '13 2 1 JS102011CQN 3 MII TX Shift Timing TX_SHIFT0 TX_SHIFT1 MII TX Timing Shift 0 0 0 ns 0 1 10 ns 1 0 20 ns 1 1 30 ns Schematics DS50002403A-page 33 Note: --To use GPIOs as LED * Short 2-3 of both jumpers (ex. for GPIO0 short 2-3 of J4 & J7) R76 'HIDXOW &RSSRUPRGH 55$VVHPEOH 5 5 '13 LED Polarity Strap J5,J8 (2&3) DNP 10K 3V3 5 . 5 . /HYHORI9VHOHFWV);/26IRUSRUW$DQG );6'&RSSHUWZLVWHGSDLUIRUSRUW%IXUWKHUGHWHUPLQHGE\);6'(1% The LED is set as active high. 1 FXSDA/FXLOSA 5 $VVHPEOH 5 '13 $ERYH9VHOHFWV);/26IRUSRUWV$DQG% MNGT0 0 3V3 R75 B2B INTERFACE 1 2 3 7 SW DIP-4/SM SDA SCL WP 5 I2C1_SDA 6 I2C1_SCL I2C EEPROM Only for Host SOC 4 24FC512 A0 A1 A2 R86 U6 VCC I2C3_1 I2C3_2 I2C3_3 I2C3_7 GND 1 2 3 4 R83 R82 SW4 8 7 6 5 2K R85 4.7K C59 0.1uF 2K R84 4.7K 3V3 8 R81 4.7K Host SOC EEPROM 4.7K 3V3 P8 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 PME_LATCH1 FIFOSEL_LATCH0 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 TP10 ORANGE HEADER 23x2 P9 VDD3V3EXP VDD_5V SYS_RESETN I2C1_SDA STORM_SIO3 SPI_CE# SPI_MISO 2015 Microchip Technology Inc. IRQ 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 5V VDD3V3EXP 1 VDD_5V 2 J10 C60 DNP 0.1uF 5V power to HOST SOC board from EVB Board I2C1_SCL RST_GPIO SYS_RESETN STORM_SIO2 SPI_MOSI SPI_CLK RST_GPIO HEADER 23x2 I2C1_SDA I2C1_SCL PME_LATCH1 FIFOSEL_LATCH0 STORM_SIO3 SPI_CE# SPI_MISO STORM_SIO2 SPI_MOSI SPI_CLK IRQ 2 RST_GPIO SYS_RESETN 1 D6 2 3 SW11 1 RST# JS102011CQN DIODE Board to Board Connectors for SoC Short 1 -2 = To Reset ASIC from SoC-GPIO Short 2-3 = To Reset SoC from ASIC EVB-LAN9252-3PORT EtherCAT(R) ESC PHY Connection Mode User's Guide DS50002403A-page 34 FIGURE B-7: PIM+ON-BOARD-PIC32MX D10 RST_GPIO STORM_SIO3 STORM_SIO2 R90 No C61 0.1uF C62 10uF 1K 1 A C 2 GRN No U7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 ID_SELECT_RC1 ID_SELECT_RC2 ID_SELECT_RC3 ID_SELECT_RC4 PIC_MCLR PIM_MCLR FIFOSEL_LATCH0 PME_LATCH1 AERXERR VDD PMD5 PMD6 PMD7 RC1 RC2 RC3 RC4 PMA5 PMA4 AERXDV MCLR AERXCLK/AEREFCLK VSS VDD1 TMS/RA0 AERXD0 AERXD1 AN5/C1IN+/VBUSON/CN7/RB5 RB4 RB3 RB2 RB1 RB0 VSS4 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 INT0 EMDC PMCS2 SS1/IC2/RD9 EMDIO AETXEN AETXCLK VSS3 OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD4 PIM CONN TDO/RA5 PIC32MX795F512L-80I/PT TDI/RA4 SDA2 SCL2 D+/RG2 D-/RG3 VUSB VBUS SCL3/SDO3/U1TX/RF8 SDA3/SDI3/U1RX/RF2 USBID/RF3 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 C63 IRQ 11pF 32Khz Y2 C64 Aardvark / SPI Storm- Connector 11pF J11 C65 20pF I2C2_SCL I2C2_SDA SPI_MISO SPI_CLK SPI_CE# Y3 8 Mhz I2C1_SDA I2C1_SCL C66 R62 R122 0 0 1 3 5 7 9 2 4 6 8 10 0 SPI_MOSI R61 20pF J12 R168 STORM_SIO2 STORM_SIO3 0 3 4 1 2 J73 - SPI AARDVAR HEADER J73+J74 - SPI STROM HEADER 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 ID_SELECT_RB5 ID_SELECT_RB4 ID_SELECT_RB3 ID_SELECT_RB2 ID_SELECT_RB1 ID_SELECT_RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PMD4 PMD3 PMD2 RG13 RG12 TRD2/RG14 PMD1 PMD0 RA7 RA6 PMD8 PMD9 PMD10 PMD11 VDD5 VCAP/VDDCORE PMD15 PMD14 PMRD PMWR PMD13 PMD12 OC4/RD3 OC3/RD2 OC2/RD1 PIM1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 3V3 PGEC2/AN6/RB6 PGED2/AN7/RB7 AERXD2 AERXD3 AVDD AVSS RB8 RB9 RB10 AETXERR VSS1 VDD2 TCK/RA1 SCK4 SS4 AECRS MII2_COL PMA1/AETXD3/PMALH PMALL/PMA0/AETXD2 VSS2 VDD3 AETXD0 AETXD1 SDI4 SDO4 2015 Microchip Technology Inc. FIGURE B-8: 3V3 3V3 DBG ICSP Header 3V3 PIC_MCLR R88 4.7K SW5 JS202011CQN 1 4 2 5 PIM_MCLR 3 6 ID_SELECT_RB0 ID_SELECT_RB1 ID_SELECT_RB2 ID_SELECT_RB3 ID_SELECT_RB4 ID_SELECT_RB5 ID_SELECT_RB8 ID_SELECT_RB9 SW DIP-8 C67 C68 C69 C70 C71 C72 C73 C74 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF MCLR SW Position 1-2 & 4-5 = PIM ON SW Position 2-3 & 5-6 = PIC ON 0.1uF C75 DS50002403A-page 35 0.1uF 1K 16 15 14 13 12 11 10 9 ID_SELECT_RB10 ID_SELECT_RB11 ID_SELECT_RB12 ID_SELECT_RB13 ID_SELECT_RC1 ID_SELECT_RC2 ID_SELECT_RC3 ID_SELECT_RC4 SW8 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SW DIP-8 SYS_RESETN Decap for U3 Schematics R89 SW7 1 2 3 4 5 6 7 8 3V3 SW6 sw_pb_2P RESET 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K SPI_MISO SPI_MOSI DNP SPI_CLK SPI_CE# PGD2 PGC2 R87 OE ID_SELECT_RB12 ID_SELECT_RB13 MCLR ID_SELECT_RB8 ID_SELECT_RB9 ID_SELECT_RB10 ID_SELECT_RB11 1 2 3 4 5 6 R123 R124 R126 R125 R127 R128 R129 R130 J13 R131 R133 R134 R132 R135 R136 R137 R138 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 3V3 EXPANSION MODE INTERFACE U4B A4/DIGIO12/GPI12/GPO12/MII_RXD0 A3/DIGIO11/GPI11/GPO11/MII_RXDV A2/ALEHI/DIGIO10/GPI10/GPO10/LINKACTLED2/MII_LINKPOL/LEDPOL6 A1/ALELO/OE_EXT/MII_CLK25 MII_RXD3 MII_RXD2 MII_RXD1 PME_LATCH1 FIFOSEL_LATCH0 31 30 28 18 34 27 26 29 25 MII_RXD0 MII_RXDV MII_CLK25 MII_LINKPOL RD/RD_WR/DIGIO15/GPI15/GPO15/MII_RXD3 WR/ENB/DIGIO14/GPI14/GPO14/MII_RXD2 CS/DIGIO13/GPI13/GPO13/MII_RXD1 A0/D15/AD15/DIGIO9/GPI9/GPO9/MII_RXER D14/AD14/DIGIO8/GPI8/GPO8/MII_TXD3/TX_SHIFT1 D13/AD13/DIGIO7/GPI7/GPO7/MII_TXD2/TX_SHIFT0 D12/AD12/DIGIO6/GPI6/GPO6/MII_TXD1 D11/AD11/DIGIO5/GPI5/GPO5/MII_TXD0 D10/AD10/DIGIO4/GPI4/GPO4/MII_TXEN D9/AD9/LATCH_IN/SCK D8/AD8/DIGIO2/GPI2/GPO2/MII_MDIO D7/AD7/DIGIO1/GPI1/GPO1/MII_MDC D6/AD6/DIGIO0/GPI0/GPO0/MII_RXCLK D5/AD5/OUTVALID/SCS# D4/AD4/DIGIO3/GPI3/GPO3/MII_LINK D3/AD3/WD_TRIG/SIO3 D2/AD2/SOF/SIO2 D1/AD1/EOF/SO/SIO1 D0/AD0/WD_STATE/SI/SIO0 SYNC/LATCH1 SYNC/LATCH0 33 15 16 21 22 23 19 40 39 36 50 49 35 12 13 17 MII_RXER MII_TXD3 MII_TXD2 MII_TXD1 MII_TXD0 MII_TXEN MII_MDIO MII_MDC MII_RXCLK SPI_CLK SPI_CE# MII_LINK STORM_SIO3 STORM_SIO2 SPI_MISO SPI_MOSI LAN9252 Ethercat Expansion Mode MII_MDIO MII_MDC MII_TXD0 MII_TXD1 MII_TXD2 MII_TXD3 MII_TXEN MII_CLK25 MII_RXD0 MII_RXD1 MII_RXD2 MII_RXD3 MII_RXDV MII_RXCLK MII_RXER MII_TXD3 MII_TXD2 5V J19 2 1 Brd2_OSC OSCI_Combined TX_SHIFT1 TX_SHIFT0 RST# Supply selection for Combined and Separate Connector Number COMBINED MODESEPARATE MODE 5V - J63 (1&2) Short Open RST# - J64 (1&2) Short Open MII_RXD3 MII_RXD2 MII_RXD1 MII_RXD0 MII_RXDV MII_RXCLK Brd2_5V Brd2_RST J21 1 2 Brd2_RST Brd2_5V MII_CLK25 MII_TXEN MII_TXD0 MII_TXD1 MII_TXD2 MII_TXD3 J17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 (4 Port Mode) J18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 MII_RXD3 MII_RXD2 MII_RXD1 MII_RXD0 MII_RXDV MII_RXCLK Brd2_5V Brd2_RST Brd2_OSC Brd2_RST Brd2_5V MII_CLK25 MII_TXEN MII_TXD0 MII_TXD1 MII_TXD2 MII_TXD3 3V3 TP3 TP4 R143 4.7K J70 = Open for 3 Port mode J20 MII_MDIO 1 2 (*short) MII_MDC 10K R144 DNP J22 MII_RXER 1 MII_LINK 1 2 (*open) J23 2 Note: Ethercat Expansion mode short J72- 1&2 Place to near MII conn,to connect fly wires. 2015 Microchip Technology Inc. EVB-LAN9252-3PORT EtherCAT(R) ESC PHY Connection Mode User's Guide DS50002403A-page 36 FIGURE B-9: ENHANCED LINK DETECTION 3V3 R145 1K R150 10.0K R149 ZERO VDD RESET SENSE GND CT MR 1 2 3 5V RST_Delay 0.001uF U9 6 5 4 R151 ZERO C79 C81 0.001uF 180mS=176.17nF 800mS=180.1nF DNP 180mS=176.17nF 800mS=180.1nF External Port 2 Interface RC2 RC3 RC5 3V3 C83 200 mS 300 mS 500 mS 1 3 5 7 R155 MII_LINK J25 3V3 5V_Delay DNP Enhanced Link Detection RST# R156 100K 1 2 3 PHY Power sequencing with transceiver power Down/Reset PHY reset release delay with transceiver power Down/Reset 5V VDD RESET SENSE GND CT MR NCP308SNADJT1G C80 R153 374E NCP308SNADJT1G R154 374E R147 10.0K R146 ZERO U8 6 5 4 R152 ZERO C78 Standard Link Detection 0.1uF 0.1uF R148 1K RST# C76 2 4 6 8 DNP J24 ZERO RST# 2 RST_Delay RC4 VCC_EXT0 0.1uF D8 5V VCC_EXT0 10uF 0.1uF sw_pb_2P ICSPDAT ICSPCLK RC4 MII_MDC MII_MDIO RC2 PIC16F1824-I/ST MCLR ICSPDAT ICSPCLK R164 ZERO 3 U11 1 J30 2 5V_Delay DNP 1K 1 (1-2*) DBG ICSP Header R162 R163 100K 2 3 4 S1 D1 S2 D2 S3 D3 G D4 8 1 VCC_EXT0 J29 2 Note: Default open. When used J79 DNP J28 1K 1 Q2 BC547 TP5 TP6 TP7 WHITE WHITE WHITE 5V 3V3 R159 7 6 5 R165 10.0K DNP MCP87130 Link Detection Selection J27 MII_MDIO MII_MDC MII_RXD3 MII_RXD2 MII_RXD1 MII_RXD0 MII_RXDV MII_RXCLK R160 MII_RXER TXER MII_CLK25 R161 MII_TXEN MII_TXD0 MII_TXD1 MII_TXD2 MII_TXD3 COL CRS 33E 33E 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 +5V1 MDIO MDC RXD3 RXD2 RXD1 RXD0 RX_DV RX_CLK RX_ER TX_ER TX_CLK TX_EN TXD0 TXD1 TXD2 TXD3 COL CRS +5V2 +5V4 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18 +5V3 42 41 RC5 RC4 RC3 SW12 14 13 12 11 10 9 8 42 41 MCLR VDD VSS RA5 RA0/ICSPDAT RA4 RA1/ICSPCLK MCLR/VPP/RA3 RA2 RC5 RC0 RC4 RC1 RC3 RC2 3 1 2 3 4 5 6 7 RA4 1 2 3 4 5 6 C84 U10 R158 4.7K 2 R157 100K C82 J26 2 RA4 1 IN4148 1 2 3 4 5 6 7 8 3 C77 5V 3V3 Standard Link Detection 3V3 1 2015 Microchip Technology Inc. FIGURE B-10: 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 MII_MDIO MII_MDC MII_TXD0 MII_TXD1 MII_TXD2 MII_TXD3 MII_TXEN MII_CLK25 MII_RXD0 MII_RXD1 MII_RXD2 MII_RXD3 MII_RXDV MII_RXCLK MII_RXER 5173277-2 MII Female for External PHY Board Note: Ethercat external board (Port2_TXER,COL,CRS signals not used) Link Detection selection J79 Standard Short 1&2 Enhanced Short 2&3 uC detects auto-negotiation restart command and power down PHY and transceiver / resets PHY and transceiver Schematics DS50002403A-page 37 EVB-LAN9252-3PORT EtherCAT(R) ESC PHY Connection Mode User's Guide NOTES: DS50002403A-page 38 2015 Microchip Technology Inc. EVB-LAN9252-3PORT ETHERCAT(R) ESC PHY CONNECTION MODE USER'S GUIDE Appendix C. Bill of Materials (BOM) C.1 INTRODUCTION This appendix includes the EVB-LAN9252-3PORT Evaluation Board Bill of Materials (BOM). 2015 Microchip Technology Inc. DS50002403A-page 39 EVB-LAN9252-3PORT EVALUATION BOARD BILL OF MATERIALS Reference Part PCB Footprint DNP Manufacturer Manufacturer Part Number Item Qty 2 2 C2,C4 10uF CAP0805 No Murata GRM21BR61E106KA73L 3 29 C3,C5,C6,C8,C10,C11,C13,C14,C15, C16,C17,C18,C21,C22,C24,C25,C58, C59,C61,C67,C68,C69,C70,C71,C72, C73,C74,C75,C84 0.1uF CAP0603 No Murata GRM188R71E104KA01D 5 1 C19 1uF CAP0603 No Murata GRM188R61C105KA93D 6 1 C20 470pF CAP0603 No Murata GRM033R71E471KA01D 7 2 C26,C27 18pF CAP0603 No Murata GRM1885C1H180JA01D 9 2 C32,C37 0.022uF CAP0603 No Kemet C0603C223K5RACTU 12 2 C62,C82 10uF CAP0603 No TDK C1608X5R0J106K080AB 13 2 C63,C64 11pF CAP0603 No Murata GRM1885C1H110JA01D 14 2 C65,C66 20pF CAP0603 No Murata GRM1885C1H200JA01D 17 5 D1,D3,D4,D5,D10 GRN LED0603 No Stanley Electric BG1111C-TR 18 1 D2 Br_Red-RA LED0603 No Stanley Electric FR1113F 19 1 D6 DIODE SOD123 No Micro Commercial Co 1N4148W-TP 20 1 D7 LED LED0603 No Stanley Electric BG1111C-TR 22 5 FB1,FB2,FB3,FB4,FB5 2A/0.05DCR RES0603 No Murata BLM18EG221SN1D 23 1 J1 SKT_PWR_2R0mm_4A_THRU_RA th_conn_pwrjack_dc-210_rt No Cui Stack PJ-002AH 25 9 J4,J5,J6,J7,J8,J9,J15,J16,J26 HDR_1x3 TH_CONN_1X3P No FCI 68000-103HLF 26 1 J11 HEADER 5X2 TH_CONN_2X5P No FCI 67997-210HLF 27 1 J12 HEADER 2X2 TH_CONN_2X2P No FCI 67997-204HLF 28 1 J13 DBG ICSP Header TH_CONN_1x6P No FCI 68000-106HLF 2015 Microchip Technology Inc. 29 1 J14 HEADER 3X2 TH_CONN_2X2P No FCI 67997-206HLF 31 1 J10 HDR_1x2 TH_CONN_1X2P No FCI 68000-102HLF 33 1 J24 CONN_8P TH_CONN_1X8P No FCI 68000-108HLF 35 1 J27 5173277-2 TH_CONN_TE-5173277_40P No TE 5173277-2-ND 38 2 P8,P9 HEADER 23x2 TH_CONN_2X23P No FCI 67997-246HLF 39 1 Q1 NDS355AN_NMOS sot23-NDS No Fairchild NDS355AN 41 7 R1,R15,R29,R61,R62,R122,R155 0E RES0603 No Panasonic ERJ-3GEY0R00V 42 7 R2,R8,R72,R73,R74,R89,r90 1K RES0603 No Panasonic ERJ-3GEYJ102V 43 1 R3 3.30K RES0603 No Yageo America 9C06031A3301FKHFT 44 1 R4 470E RES0603 No BOURNS CR0603-FX-4700ELF EVB-LAN9252-3PORT EtherCAT(R) ESC PHY Connection Mode User's Guide DS50002403A-page 40 TABLE C-1: 2015 Microchip Technology Inc. TABLE C-1: Item Qty 45 3 EVB-LAN9252-3PORT EVALUATION BOARD BILL OF MATERIALS (CONTINUED) Reference Part PCB Footprint DNP Manufacturer R4A,R160,R161 33E RES0603 No BOURNS Manufacturer Part Number CR0603-FX-33R0ELF 46 1 R5 4.75K RES0603 No Panasonic ERJ-3EKF4751V 47 5 R6,R69,R70,R71,R139 10.0K RES0603 No Panasonic ERJ-3EKF1002V 48 1 R7 100E RES0603 No Panasonic ERJ-3EKF1000V 49 1 R9 2.2K RES0603 No Panasonic ERJ-3GEYJ222V 50 1 R10 12.1K RES0603 No Rohm CR03ERTF1212 51 8 R11,R12,R13,R14,R25,R26,R27,R28 49.9 RES0603 No Yageo America 9C06031A49R9FKHFT 54 8 R17,R19,R21,R23,R31,R33,R35,R37 0E RES0402 No Panasonic ERJ-2GE0R00X 55 2 R24,R38 0E RES1210 No Vishay CRCW12100000Z0EA 61 10 R63,R64,R65,R66,R81,R82,R84,R85, R88,R143 4.7K RES0603 No Panasonic ERJ-3EKF4701V 62 4 R67,R68,R83,R86 2K RES0603 No Panasonic ERJ-3GEYJ202V 64 21 R76,R79,R80,R123,R124,R125,R126, R127,R128,R129,R130,R131,R132, R133,R134,R135,R136,R137,R138, R141,R142 10K RES0603 No Panasonic ERJ-3GEYJ103V 66 1 R140 332 RES0603 No Panasonic ERJ-3EKF3320V 73 1 SW1 SW-SPDT-SLIDE sw_ck_1101m2s3cqe2 No C&K 1101M2S3CQE2 74 2 SW2,SW6 sw_pb_2P sw_pb_2P No Panasonic EVQ-PJU04K 2 SW3,SW4 SW DIP-4/SM TH_SW_DIP4 No Wurth electronics 418117270904 76 1 SW5 JS202011CQN TH_SW_DPDT_6P No C&K 401-2001-ND 77 2 SW7,SW8 SW DIP-8 SW_DIP_SMT_8P-ADE08S04 No TE 1-1825058-9/ade08s04 78 3 SW9,SW10,SW11 450301014042 TH_SW_SPST_3P_10x2p5 No Wurth electronics 450301014042 79 1 TP1 RED TH_TP_60D40 No Keystone 5005 80 1 TP2 ORANGE TH_TP_60D40 No Keystone 5003 2 TP8,TP9 TEST POINT TH_TP_60D40 No Keystone 5001 83 2 T1,T2 Pulse - J0011D01BNL th_conn_pulse_rj45_j0026 No Pulse Electronics 553-1483-ND 84 1 U1 3_Amp TH_DC-DC_VERT_5PIN_P67 No Murata OKR-T/3-W12-C 85 1 U2 TPS3125 SOT23_5 No TI TPS3125L30DBVR 86 1 U3 74LVC1G14 SOT23_5 No TI SN74LVC1G14DCKR 87 1 U4 LAN9252 IC_QFN64 No Microchip LAN9252 88 1 U5 24FC04 IC_DIP8_300 No Microchip 24AA04 89 1 U6 24FC512 IC_DIP8_300 No Microchip 24FC512-IP Bill of Materials (BOM) DS50002403A-page 41 75 EVB-LAN9252-3PORT EVALUATION BOARD BILL OF MATERIALS (CONTINUED) Reference Qty 90 1 U7 PIC32MX795F512L-80I/PT IC_TQFP100_12x12x1-0p4mm No Microchip PIC32MX795F512L-80I/PT-ND 94 1 Y1 Citizen America XTAL_HCM49 No Cardinal Components Inc. CSM1Z-A5B2C5-40-25.0D 18-F 95 1 Y2 32Khz TH_XTAL_ECS-31X_32KHZ No ECS INC XC1392-ND 96 1 Y3 8 Mhz th_hc49us_2p No Citizen Finetech 300-6017-ND TABLE C-2: Part PCB Footprint DNP Manufacturer Manufacturer Part Number Item DNP COMPONENTS Reference Part PCB Footprint DNP Manufacturer Manufacturer Part Number Item Qty 15 2 C78,C79 0.001uF CAP0603 DNP Murata GRM188R71H102KA01D 3 3 C76,C77,C83 0.1uF CAP0603 DNP Murata GRM188R71E104KA01D 71 3 R156,R157,R163 100K RES0603 DNP Panasonic ERJ-3EKF1003V 42 4 R145,R148,R159,R162 1K RES0603 DNP Panasonic ERJ-3GEYJ102V 34 1 J25 2x4 Th_CONN_2X4P DNP 69 2 R153,R154 374E RES0603 DNP Panasonic ERJ-3EKF3740V 61 1 R158 4.7K RES0603 DNP Panasonic ERJ-3EKF4701V 40 1 Q2 BC547 SOT23 DNP Diodes Incorporated MMBT4401-7-F 31 4 J29,J19,J21,J23 CONN_2P TH_CONN_1X2P DNP 30 2 J17,J18 1x22 TH_CONN_1X22P No 28 1 J28 DBG ICSP Header TH_CONN_1x6P DNP 25 1 J30 HDR_1x3 TH_CONN_1X3P DNP FCI 68000-122HLF 21 1 D8 IN4148 SOD123 DNP Micro Commercial Co 1N4148W-TP 93 1 U11 MCP87130 IC_PDFN8_5x6mm_MCP8713 DNP Microchip MCP87130T-U/LCTR-ND 2015 Microchip Technology Inc. 91 2 U8,U9 NCP308SNADJT1G SOT23_6 DNP ON Semiconductor NCP308SNADJT1G-ND 92 1 U10 PIC16F1824-I/ST IC_TSSOP14-4P5X5MM DNP Microchip PIC16F1824-I/ST-ND 82 3 TP5,TP6,TP7 WHITE TH_TP_60D40 DNP Keystone 5002 31 1 J20 CONN_2P TH_CONN_1X2P DNP 32 1 J22 CONN_2P th_conn_1x2p DNP 74 1 SW12 sw_pb_2P sw_pb_2P DNP Panasonic EVQ-PJU04K 1 1 C1 4.7uF CAP0603 DNP Murata GRM188R60J475KE19D 4 4 C7,C9,C12,C23 1.0uF CAP0603 DNP Murata GRM188R61C105KA93D 8 8 C28,C29,C30,C31,C33,C34,C35,C36 10pF CAP0402 DNP Murata GRM188R61C105KA93D EVB-LAN9252-3PORT EtherCAT(R) ESC PHY Connection Mode User's Guide DS50002403A-page 42 TABLE C-1: 2015 Microchip Technology Inc. TABLE C-2: DNP COMPONENTS (CONTINUED) Item Qty Reference 10 14 C38,C39,C40,C41,C42,C43,C44,C45, C47,C49,C51,C53,C55,C57 Part 0.1uF PCB Footprint DNP Manufacturer Manufacturer Part Number CAP0603 DNP Murata GRM188R71E104KA01D B45190E3106K209 11 6 C46,C48,C50,C52,C54,C56 10uF CAP_B_3528 DNP Kemet 16 2 C80,C81 TBD CAP0603 DNP 24 2 J2,J3 FTLF1217P2 CONN_FX_SFP_FTLF1217P2 DNP Finisar 36 4 L1,L2,L3,L4 1uH L0805 DNP Panasonic ERJ-3GEY0R00V 53 8 R16,R18,R20,R22,R30,R32,R34,R36 0 RES0402 DNP Panasonic ERJ-2GE0R00X 56 4 R39,R40,R43,R44 82 RES0603 DNP BOURNS CR0603-FX-82R0ELF 57 4 R41,R42,R45,R46 49.9 RES0603 DNP Yageo America 9C06031A49R9FKHFT 58 2 R47,R48 100 RES0603 DNP Panasonic ERJ-3EKF1000V 775-1011-ND 59 4 R49,R50,R51,R52 130 RES0603 DNP Panasonic ERJ-3EKF1300V 60 8 R53,R54,R55,R56,R57,R58,R59,R60 4.7K RES0603 DNP Panasonic ERJ-3EKF4701V ERJ-3GEYJ103V 63 4 R75,R77,R78,R144 10K RES0603 DNP Panasonic 70 6 R146,R149,R151,R152,R164,R168 ZERO RES0603 DNP 72 1 R165,R147,R150 10.0K RES0603 DNP Panasonic 37 1 PIM1 PIM CONN TH_CONN_PIM100 DNP 81 2 TP3,TP4 TEST POINT TH_TP_60D40 DNP FCI ERJ-3EKF1002V 68000-201HLF Bill of Materials (BOM) DS50002403A-page 43 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Germany - Dusseldorf Tel: 49-2129-3766400 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Hong Kong Tel: 852-2943-5100 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8569-7000 Fax: 86-10-8528-2104 Austin, TX Tel: 512-257-3370 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Novi, MI Tel: 248-848-4000 Houston, TX Tel: 281-894-5983 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 New York, NY Tel: 631-435-6000 San Jose, CA Tel: 408-735-9110 Canada - Toronto Tel: 905-673-0699 Fax: 905-673-6509 China - Dongguan Tel: 86-769-8702-9880 China - Hangzhou Tel: 86-571-8792-8115 Fax: 86-571-8792-8116 India - Pune Tel: 91-20-3019-1500 Japan - Osaka Tel: 81-6-6152-7160 Fax: 81-6-6152-9310 Japan - Tokyo Tel: 81-3-6880- 3770 Fax: 81-3-6880-3771 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 China - Hong Kong SAR Tel: 852-2943-5100 Fax: 852-2401-3431 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 China - Shenzhen Tel: 86-755-8864-2200 Fax: 86-755-8203-1760 Taiwan - Hsin Chu Tel: 886-3-5778-366 Fax: 886-3-5770-955 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Taiwan - Kaohsiung Tel: 886-7-213-7828 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 Germany - Karlsruhe Tel: 49-721-625370 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Italy - Venice Tel: 39-049-7625286 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Poland - Warsaw Tel: 48-22-3325737 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Sweden - Stockholm Tel: 46-8-5090-4654 UK - Wokingham Tel: 44-118-921-5800 Fax: 44-118-921-5820 Taiwan - Taipei Tel: 886-2-2508-8600 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 07/14/15 DS50002403A-page 44 2015 Microchip Technology Inc.