©2004 Integrated Device Technology, Inc.
1
OCTOBER 2004
DSC 2943/6
I/O
Control
Address
Decoder MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
Address
Decoder
I/O
Control
R/W
L
CE
L
OE
L
BUSY
L
A
14L
A
0L
2943 drw 01
I/O
0L
-I/O
7L
CE
L
OE
L
R/W
L
SEM
L
INT
L
M/S
BUSY
R
I/O
0R
-I/O
7R
A
14R
A
0R
SEM
R
INT
R
CE
R
OE
R
(2)
(1,2) (1,2)
(2)
R/W
R
CE
R
OE
R
15
15
R/W
R
,
IDT70V07S/L
HIGH-SPEED 3.3V
32K x 8 DUAL-PORT
STATIC RAM
Features
◆◆
◆◆
◆True Dual-Ported memory cells which allow simultaneous
access of the same memory location
◆◆
◆◆
◆High-speed access
– Commercial: 25/35/55ns (max.)
– Industral: 25ns (max.)
◆◆
◆◆
◆Low-power operation
– IDT70V07S
Active: 300mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V07L
Active: 300mW (typ.)
Standby: 660
µ
W (typ.)
◆◆
◆◆
◆Interrupt Flag
◆◆
◆◆
◆IDT70V07 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
◆◆
◆◆
◆M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
◆◆
◆◆
◆On-chip port arbitration logic
◆◆
◆◆
◆Full on-chip hardware support of semaphore signaling
between ports
◆◆
◆◆
◆Fully asynchronous operation from either port
◆◆
◆◆
◆TTL-compatible, single 3.3V (±0.3V) power supply
◆◆
◆◆
◆Available in 68-pin PGA and PLCC, and a 80-pin TQFP
◆Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Functional Block Diagram
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY and INT outputs are non-tri-stated push-pull.
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
2
2943 drw 02
12
13
14
15
16
17
18
INDEX
19
20
21
22
98765432168676665
27 28 29 30 31 32 33 34 35 36 37 38 39
V
CC
VCC
I/O1R
I/O2R
I/O3R
I/O4R
INTL
GND
A4L
A3L
A2L
A1L
A0L
A3R
A0R
A1R
A2R
I/O2L A5L
11
10
M/S
23
24
25
26
40 41 42 43
58
57
56
55
54
53
52
51
50
49
48
59
60
47
46
45
44
64 63 62 61
I/O3L
GND
I/O0R
VCC
A4R
BUSYL
GND
BUSYR
INTR
A
12R
I/O
7R
N/C
GND
OE
R
R/W
R
CE
R
CE
L
N/C
I/O
0L
I/O
1L
IDT70V07J
J68-1
(4)
68-Pin PLCC
Top View
(5)
I/O4L
I/O5L
I/O6L
I/O7L
I/O5R
I/O6R
A
12L
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
A
13R
A
13L
A
14L
A
14R
R/W
L
OE
L
SEM
L
SEM
R
10/25/01
Description
The IDT70V07 is a high-speed 32K x 8 Dual-Port Static RAM. The
IDT70V07 is designed to be used as a stand-alone 256K-bit Dual-Port
RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-
or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM
approach in 16-bit or wider memory system applications results in full-
speed, error-free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by CE permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 300mW of power.
The IDT70V07 is packaged in a ceramic 68-pin PGA and PLCC and
a 80-pin thin quad flatpack (TQFP).
Pin Configurations(1,2,3)
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. J68-1 package body is approximately .95 in x .95 in x .17 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
3
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
INDEX
I/O
2L
V
CC
GND
GND
A
4R
BUSY
L
BUSY
R
GND
M/S
OE
L
I/O
1L
R/W
L
CE
L
SEM
L
V
CC
OE
R
CE
R
R/W
R
SEM
R
A
12R
GND
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
7R
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
A
3R
A
2R
A
1R
A
0R
A
0L
A
1L
A
2L
A
3L
A
4L
A
6L
A
7L
A
8L
A
9L
A
10L
A
11L
A
12L
I/O
0L
2943 drw 03
A
13R
A
13L
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
46
45
44
43
42
41
56
55
54
53
52
51
50
47
48
49
3231
302928
272625
2423
2221
63 62 61
64
33 34 35 36 37 38 39 40
656667686970
71
72
73
7475767778
79
80
N/C
N/C
A
14L
N/C
N/C
N/C
N/C
A
14R
N/C
N/C
17
18
19
20
57
58
59
60
A
5L
N/C
INT
L
INT
R
N/C
N/C
N/C
I/O
6R
N/C
N/C
IDT70V07PF
PN80-1
(4)
80-Pin TQFP
Top View
(5)
10/25/01
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. PN80-1 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Pin Configurations(1,2,3) (con't.)
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
4
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. Package body is approximately 1.18 in x 1.18 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking. Pin Names
Pin Configurations(1,2,3) (con't.)
Left Port Right Port Names
CE
L
CE
R
Chip Enable
R/W
L
R/W
R
Re ad /Write Enable
OE
L
OE
R
Output Enable
A
0L
- A
14L
A
0R
- A
14R
Address
I/O
0L
- I/O
7L
I/O
0R
- I/O
7R
Data Inp ut/ Outp ut
SEM
L
SEM
R
Semaphore Enable
INT
L
INT
R
Inte rrupt Flag
BUSY
L
BUSY
R
Busy Flag
M/SMaster or Slave Select
V
CC
Powe r (3.3V)
GND G ro und (0V)
2943 tb l 01
2943 drw 04
51 50 48 46 44 42 40 38 36
53
55
57
59
61
63
65
67
68
66
1357911 13 15
20
22
24
26
28
30
32
35
IDT70V07G
G68-1
(4)
68-Pin PGA
Top View
(5)
ABCDEFGH J
K
L
47 45 43 41 34
21
23
25
27
29
31
33
246810121416
18 19
17
56
58
60
62
64
11
10
09
08
07
06
05
04
03
02
01
52
54
49 39 37
A
5L
INT
L
SEM
L
CE
L
V
CC
OE
L
R/W
L
I/O
0L
N/C
GND GND
I/O
0R
V
CC
N/C
OE
R
R/W
R
SEM
R
CE
R
GND BUSY
R
BUSY
L
M/SINT
R
GND
A
1R
INDEX
A
4L
A
2L
A
0L
A
3R
A
2R
A
4R
A
5R
A
7R
A
6R
A
9R
A
8R
A
11R
A
10R
A
12R
A
0R
A
7L
A
6L
A
3L
A
1L
A
9L
A
8L
A
11L
A
10L
A
12L
V
CC
I/O
2R
I/O
3R
I/O
5R
I/O
6R
I/O
1R
I/O
4R
I/O
7R
I/O
1L
I/O
2L
I/O
4L
I/O
7L
I/O
3L
I/O
5L
I/O
6L
A
13R
A
13L
A
14R
A
14L
,
10/25/01
5
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Truth Table I: Non-Contention Read/Write Control
Truth Table II: Semaphore Read/Write Control
Maximum Operating Temperature
and Supply Voltage(1)
Absolute Maximum Ratings(1)
Capacitance(1)
(TA = +25°C, f = 1.0MHz) TQFP Only
Recommended DC Operating
Conditions(2)
NOTE:
1. A0L — A14L ≠ A0R — A14R
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 0.3V.
3. Ambient Temperature Under Bias. No AC Conditions. Chip Deselected.
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 0.3V.
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. COUT also references CI/O.
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0-A2
Inputs
(1)
Outputs
Mode
CE R/WOE SEM I/O
0-7
H X X H High-Z Des ele cte d: Power-Down
LLXHDATA
IN
Write to Me mory
LHLHDATA
OUT
Read Me mory
X X H X High-Z Outputs Disabled
2943 tbl 02
Inputs(1) Outputs
Mode
CE R/WOE SEM I/O
0-7
HHLLDATA
OUT
Re ad Data in Se mapho re Flag
H↑XLDATA
IN
Write I/O
0
into Semaphore Flag
LXXL
____
Not Allowe d
2943 tbl 03
Symbol Rating Commercial
& Industrial Unit
V
TERM
(2)
Ter mina l V olt a ge
with Re s p e c t to GND -0.5 to +4.6 V
T
BIAS
(3)
Te mp erature Under Bias -55 to +125
o
C
T
STG
StorageTemperature -65 to +150
o
C
T
JN
J unc ti o n Te m perature + 150
o
C
I
OUT
DC Outp ut Curre nt 50 mA
2943 tbl 04
Grade Ambient Temperature GND Vcc
Commercial 0
O
C to +70
O
C0V3.3V
+
0.3
Industrial -40
O
C to + 85
O
C0V3.3V
+
0.3
2943 tbl 05
Symbol Parameter Min. Typ. Max. Unit
V
CC
Supp ly Vol tag e 3. 0 3.3 3.6 V
GND Ground 0 0 0 V
V
IH
Input High Voltage 2.0
____
V
CC
+0.3
(2)
V
V
IL
Input Lo w Vo ltag e -0.3
(1)
____
0.8 V
2943 tbl 06
Symbol Parameter Conditions Max. Unit
C
IN
Inp ut Cap a citanc e V
IN
= 0V 9 p F
C
OUT
(2)
Outp ut Capacitance V
OUT
= 0V 10 p F
2943 tb l 07
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
6
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VCC = 3.3V ± 0.3V)
NOTES:
1. 'X' in part number indicates power rating (S or L).
2. VCC = 3.3V, TA = +25°C, and are not production tested. ICCDC = 80mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions" of input levels
of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V)
NOTE:
1. At VCC < 2.0V, input leakages are undefined.
Symbol Parameter Test Conditio ns
70V07S 70V07L
UnitMin. Max. Min. Max.
|I
LI
| Inp ut Le akag e Curre nt
(1)
V
CC
= 3.6V, V
IN
= 0V to V
CC
___
10
___
5µA
|I
LO
| Outp ut Le ak age Curre nt CE = V
IH
, V
OUT
= 0V to V
CC
___
10
___
5µA
V
OL
Output Low Vo ltage I
OL
= +4mA
___
0.4
___
0.4 V
V
OH
Output High Voltage I
OH
= -4mA 2.4
___
2.4
___
V
2943 t bl 08
70V07X25
Com'l
& In d
70V07X35
Com 'l Only 70V07X55
Com'l Only
S ym bol P ar ame ter Test Co ndi tio n Ver si on Typ.
(2)
Max. Typ.
(2)
Max. Typ.
(2)
Max. Unit
I
CC
Dyn ami c Ope rating
Current
(Both Ports Active)
CE = V
IL
, Outp uts Disabled
SEM = V
IL
f = f
MAX
(3)
COM'L S
L100
100 170
140 90
90 140
120 90
90 140
120 mA
IND S
L
____
100
____
185
____
____
____
____
____
____
____
____
I
SB1
Standby Curre nt
(Both Ports - TTL
Lev el Inp u ts )
CE
R
= CE
L
= V
IH
SEM
R
= SEM
L
= V
IH
f = f
MAX
(3)
COM'L S
L14
12 30
24 12
10 30
24 12
10 30
24 mA
IND S
L
____
12
____
50
____
____
____
____
____
____
____
____
I
SB2
Standby Curre nt
(One P o rt - TTL
Lev el Inp u ts )
CE
"A"
= V
IL
and CE
"B"
= V
IH
(5)
Active Po rt Outputs Disabled,
f=f
MAX
(3)
SEM
R
= SEM
L
= V
IH
COM'L S
L50
50 95
85 45
45 87
75 45
45 87
75 mA
IND S
L
____
50
____
105
____
____
____
____
____
____
____
____
I
SB3
Full Standb y Current
(B o th P or ts -
CM OS Le v e l In p uts )
Both Ports CE
L
and
CE
R
> V
CC
- 0. 2V,
V
IN
> V
CC
- 0. 2V o r
V
IN
< 0. 2V, f = 0
(4)
SEM
R
= SEM
L
> V
CC
- 0.2V
COM'L S
L1.0
0.2 6
31.0
0.2 6
31.0
0.2 6
3mA
IND S
L
____
0.2
____
3
____
____
____
____
____
____
____
____
I
SB4
Full Standb y Current
(One P o rt -
CM OS Le v e l In p uts )
CE
"A"
< 0. 2V and
CE
"B"
> V
CC
- 0. 2V
(5)
SEM
R
= SEM
L
> V
CC
- 0.2V
V
IN
> V
CC
- 0. 2V o r V
IN
< 0.2V
Active Po rt Outputs Disabled,
f = f
MAX
(3)
COM'L S
L60
60 90
80 55
55 85
74 55
55 85
74 mA
IND S
L
____
60
____
90
____
____
____
____
____
____
____
____
2943 tb l 09
7
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
AC Test Conditions
Figure 1. AC Output Test Load
Timing of Power-Up Power-Down
NOTES:
1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.
4. 'X' in part number indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(4)
CE
2943 drw 07
t
PU
I
CC
I
SB
t
PD
,
Inp ut Puls e Le ve ls
Inp ut Ris e /Fall Time s
Inp ut Timing Refere nce Le ve ls
Outp ut Re fe re nc e Le ve l s
Outp ut Load
GND to 3 . 0V
3ns
1.5V
1.5V
Fi g ure s 1 and 2
2943 tbl 10
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
* Including scope and jig.
2943 drw 06
590Ω
30pF
435Ω
3.3V
DATA
OUT
BUSY
INT
590Ω
5pF*
435Ω
3.3V
DATA
OUT
2943 drw 05
70V07X25
Com'l
& Ind
70V07X35
Com'l Only 70V07X55
Com'l Only
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.
READ CYCLE
t
RC
Re ad Cyc le Time 25
____
35
____
55
____
ns
t
AA
Address Access Time
____
25
____
35
____
55 ns
t
ACE
Chip Enable Access Time
(3)
____
25
____
35
____
55 ns
t
AOE
Outp ut Enable Acce ss Time
____
15
____
20
____
30 ns
t
OH
Output Hold from Address Change 3
____
3
____
3
____
ns
t
LZ
O u t pu t L ow - Z Ti me
(1,2)
3
____
3
____
3
____
ns
t
HZ
Outp ut Hig h-Z Ti me
(1,2)
____
15
____
20
____
25 ns
t
PU
Chip E nab le to P o we r Up Time
(2)
0
____
0
____
0
____
ns
t
PD
Chip Disab le to Po we r Down Ti me
(2)
____
25
____
35
____
50 ns
t
SOP
Semaphore Flag Update Pulse (OE or SEM)15
____
15
____
15
____
ns
t
SAA
Se map hore Add ress Acce ss Time
____
35
____
45
____
65 ns
2943 tb l 1
1
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
8
Waveform of Read Cycles(5)
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no
relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
NOTES:
1. Transition is measured 0mV from Low or High impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part number indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(5)
t
RC
R/W
CE
ADDR
t
AA
OE
2943 drw 08
(4)
t
ACE
(4)
t
AOE
(4)
(1)
t
LZ
t
OH
(2)
t
HZ
(3,4)
t
BDD
DATA
OUT
BUSY
OUT
VALID DATA
(4)
Symbol Parameter
70V07X25
Com'l
& I nd
70V07X35
Com'l Only 70V07X55
Com'l Only
UnitMin. Max. Min. Max. Min. Max.
WRI TE CYCLE
t
WC
Wri te C y c l e Ti me 2 5
____
35
____
55
____
ns
t
EW
Chip Enable to End -of-Write
(3)
20
____
30
____
45
____
ns
t
AW
Address Valid to End-of-Write 20
____
30
____
45
____
ns
t
AS
Address Set-up Time
(3)
0
____
0
____
0
____
ns
t
WP
Wri te P u lse Wi d th 2 0
____
25
____
40
____
ns
t
WR
Write Reco ve ry Time 0
____
0
____
0
____
ns
t
DW
Da ta Va l id to En d- of- Wr i te 1 5
____
20
____
30
____
ns
t
HZ
Output High-Z Time
(1,2)
____
15
____
20
____
25 ns
t
DH
Da ta Hol d Ti m e
(4)
0
____
0
____
0
____
ns
t
WZ
Wri te E nable to Output i n High-Z
(1,2)
____
15
____
20
____
25 ns
t
OW
Outp ut Activ e fro m End -o f-Write
(1,2,4)
0
____
0
____
0
____
ns
t
SWRD
SEM Flag Write to Read Time 5
____
5
____
5
____
ns
t
SPS
SEM Fl ag Co nte ntio n Wi nd ow 5
____
5
____
5
____
ns
2943 tb l 12
9
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5)
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/ W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the
bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
9. To access SRAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
R/W
t
WC
t
HZ
t
AW
t
WR
t
AS
t
WP
DATA
OUT
(2)
t
WZ
t
DW
t
DH
t
OW
OE
ADDRESS
DATA
IN
CE or SEM
(6)
(4) (4)
(3)
2943 drw 09
(7)
(9)
(7)
t
LZ
,
t
HZ
(7)
2943 drw 10
t
WC
t
AS
t
WR
t
DW
t
DH
ADDRESS
DATA
IN
R/W
t
AW
t
EW
(3)
(2)
(6)
CE or SEM
(9)
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
10
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH.
2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/WB or SEM"B" going HIGH.
4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
NOTES:
1. CE = VIH for the duration of the above timing (both write and read cycle).
2. “DATAOUT VALID” represents all I/O's (I/O0-I/O7) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
SEM
2943 drw 11
t
AW
t
EW
t
SOP
DATA
0
VALID ADDRESS
t
SAA
R/W
t
WR
t
OH
t
ACE
VALID ADDRESS
DATA VALID
IN
DATA
OUT
t
DW
t
WP
t
DH
t
AS
t
SWRD
t
AOE
t
SOP
Read Cycle
Write Cycle
A
0
-A
2
OE
VALID
(2)
SEM
"A"
2943 drw 12
t
SPS
MATCH
R/W
"A"
MATCH
A
0"A"
-A
2"A"
SIDE "A"
(2)
SEM
"B"
R/W
"B"
A
0"B"
-A
2"B"
SIDE "B"
(2)
11
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
2943 drw 13
t
DW
t
APS
ADDR
"A"
t
WC
DATA
OUT "B"
MATCH
t
WP
R/W
"A"
DATA
IN "A"
ADDR
"B"
t
DH
VALID
(1)
MATCH
BUSY
"B"
t
BDA
VALID
t
BDD
t
DDD
(3)
t
WDD
t
BAA
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6)
Timing Waveform of Write with Port-to-Port Read and BUSY(2,4,5)
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. If M/S = VIL (SLAVE), then BUSY is an input (BUSY"A" = VIH and BUSY"B" = "don't care", for this example).
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
70V07X25
Com'l
& In d
70V07X35
Com'l Only 70V07X55
Com'l Onl y
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
BUSY TI MING (M/S = V
IH
)
t
BAA
BUSY Access Time from Address
____
25
____
35
____
45 ns
t
BDA
BUSY Disable Time from Address
____
25
____
35
____
45 ns
t
BAC
BUSY Access Time from Chip Enable
____
25
____
35
____
45 ns
t
BDC
BUSY Disable Time from Chip Enable
____
25
____
35
____
45 ns
t
APS
Arbitration Priority Set-up Time
(2)
5
____
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(3)
____
35
____
40
____
50 ns
BUSY TI MING (M/S - V
IL
)
t
WB
BUSY Inp ut to Write
(4)
0
____
0
____
0
____
ns
t
WH
Write Hold After BUSY
(5)
20
____
25
____
25
____
ns
P ORT-TO -PORT DE LAY T I MI NG
t
WDD
Write Puls e to Data Delay
(1)
____
55
____
65
____
85 ns
t
DDD
Wr i te D a ta Valid to R ea d D a ta Del a y
(1)
____
50
____
60
____
80 ns
2943 tb l 13
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
12
Waveform of BUSY Arbitration Controlled by CE Timing(1)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from Port “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or the other, but there is no guarantee on which side busy will be asserted.
Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing
(1)
Timing Waveform of Write with BUSY
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on Port "B" blocking R/W"B", until BUSY"B" goes HIGH.
2943 drw 14
R/W
"A"
BUSY
"B"
t
WP
t
WB
R/W
"B"
t
WH
(1)
(2)
2943 drw 15
ADDR
"A"
and
"B"
ADDRESSES MATCH
CE
"A"
CE
"B"
BUSY
"B"
t
APS
t
BAC
t
BDC
(2)
2943 drw 16
ADDR"A" ADDRESS "N"
ADDR"B"
BUSY"B"
tAPS
tBAA tBDA
(2)
MATCHING ADDRESS "N"
13
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
NOTE:
1. 'X' in part number indicates power rating (S or L).
Waveform of Interrupt Timing(1)
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See Interrupt Truth Table III.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
70V07X25
Com'l
& In d
70V07X35
Com'l Only 70V07X55
Com'l Onl y
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
INTERRUPT TIMI NG
t
AS
Address Set-up Time 0
____
0
____
0
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
ns
t
INS
In te rrup t S e t Ti me
____
25
____
30
____
40 ns
t
INR
In te rrup t R e s e t Time
____
30
____
35
____
45 ns
2043 tb l 14
2943 drw 17
ADDR
"A"
INTERRUPT SET ADDRESS
CE
"A"
R/W
"A"
t
AS
t
WC
t
WR
(3) (4)
t
INS
(3)
INT
"B"
(2)
2943 drw 18
ADDR
"B"
INTERRUPT CLEAR ADDRESS
CE
"B"
OE
"B"
t
AS
t
RC
(3)
t
INR
(3)
INT
"B"
(2)
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
14
Truth Table IV — Address BUSY
Arbitration
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70V07 are push-
pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and
enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when
BUSYR outputs are driving LOW regardless of actual logic level on the pin.
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V07.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0 - I/O7). These eight semaphores are addressed by A0 -A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
Truth Table III — Interrupt Flag(1)
NOTES:
1. Assumes BUSYL = BUSYR =VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
Left P ort Ri ght P ort
FunctionR/W
L
CE
L
OE
L
A
14L
-A
0L
INT
L
R/W
R
CE
R
OE
R
A
14R
-A
0R
INT
R
LLX7FFFXXXX X L
(2)
S e t Ri g h t INT
R
Flag
XXX X XX L L7FFF H
(3)
Re s e t Ri g ht INT
R
Flag
XXX X L
(3)
L L X 7FFE X Se t Le ft INT
L
Flag
XLL7FFE H
(2)
XXXXXReset Left INT
L
Flag
2943 tb l 15
Inputs Outputs
Function
CE
L
CE
R
A
0L
-A
14L
A
0R
-A
14R
BUSY
L
(1)
BUSY
R
(1)
XXNO MATCHHHNormal
HXMATCHHHNormal
XHMATCHHHNormal
L L MATCH (2) (2) Write Inhib it
(3)
29 43 tbl 16
Functions D
0
- D
7
Left D
0
- D
7
Right Status
No Action 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token
Left Po rt Write s "0" to Semapho re 1 0 No chang e. Left port has no write ac ce ss to semap ho re
Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token
Right Port Writes "1" to Semaphore 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
2943 tbl 17
15
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Functional Description
The IDT70V07 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70V07 has an automatic power down
feature controlled by CE. The CE controls on-chip power down circuitry
that permits the respective port to go into a standby mode when not
selected (CE HIGH). When a port is enabled, access to the entire
memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail
box or message center) is assigned to each port. The left port interrupt
flag (INTL) is asserted when the right port writes to memory location
7FFE (HEX), where a write is defined as CER = R/WR = VIL per Truth
Table III. The left port clears the interrupt through access of address
location 7FFE when CEL = OEL = VIL, R/W is a "don't care". Likewise,
the right port interrupt flag (INTR) is asserted when the left port writes
to memory location 7FFF (HEX) and to clear the interrupt flag (INTR),
the right port must read the memory 7FFF location 7FFF. The
message (8 bits) at 7FFE or 7FFF is user-defined since it is an
addressable SRAM location. If the interrupt function is not used,
address locations 7FFE and 7FFF are not used as mail boxes, but as
part of the random access memory. Refer to Truth Table III for the
interrupt operation.
programmed by tying the BUSY pins HIGH. If desired, unintended
write operations can be prevented to a port by tying the BUSY pin for
that port LOW .
The BUSY outputs on the IDT 70V07 RAM in master mode, are
push-pull type outputs and do not require pull up resistors to operate.
If these RAMs are being expanded in depth, then the BUSY indication
for the resulting array requires the use of an external AND gate.
Width Expansion with BUSY Logic
Master/Slave Arrays
When expanding an IDT70V07 RAM array in width while using
BUSY logic, one master part is used to decide which side of the RAM
array will receive a BUSY indication, and to output that indication. Any
number of slaves to be addressed in the same address range as the
master, use the BUSY signal as a write inhibit signal. Thus on the
IDT70V07 RAM the BUSY pin is an output if the part is used as a
master (M/S pin = VIH), and the BUSY pin is an input if the part used
as a slave (M/S pin = VIL) as shown in Figure 3.
If two or more master parts were used when expanding in width, a
split decision could result with one master indicating BUSY on one side
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.
The BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with the R/W signal. Failure to
observe this timing can result in a glitched internal write inhibit signal
and corrupted data in the slave.
Semaphores
The IDT70V07 is an extremely fast Dual-Port 32K x 8 CMOS Static
RAM with an additional 8 address locations dedicated to binary
semaphore flags. These flags allow either processor on the left or right
side of the Dual-Port SRAM to claim a privilege over the other
processor for functions defined by the system designer’s software. As
an example, the semaphore can be used by one processor to inhibit
the other from accessing a portion of the Dual-Port SRAM or any other
shared resource.
The Dual-Port SRAM features a fast access time, and both ports
are completely independent of each other. This means that the activity
on the left port in no way slows the access time of the right port. Both
ports are identical in function to standard CMOS Static RAM and can
be read from, or written to, at the same time with the only possible
conflict arising from the simultaneous writing of, or a simultaneous
READ/WRITE of, a non-semaphore location. Semaphores are pro-
tected against such ambiguous situations and may be used by the
system program to avoid any conflicts in the non-semaphore portion
of the Dual-Port SRAM. These devices have an automatic power-
down feature controlled by CE, the Dual-Port SRAM enable, and SEM,
the semaphore enable. The CE and SEM pins control on-chip power
down circuitry that permits the respective port to go into standby mode
when not selected. This is the condition which is shown in Truth Table
Busy Logic
Busy Logic provides a hardware indication that both ports of the
SRAM have accessed the same location at the same time. It also
allows one of the two accesses to proceed and signals the other side
that the SRAM is “busy”. The busy pin can then be used to stall the
access until the operation on the other side is completed. If a write
operation has been attempted from the side that receives a BUSY
indication, the write signal is gated internally to prevent the write from
proceeding.
The use of BUSY logic is not required or desirable for all applica-
tions. In some cases it may be useful to logically OR the BUSY outputs
together and use any BUSY indication as an interrupt source to flag the
event of an illegal or illogical operation. If the write inhibit function of
BUSY logic is not desirable, the BUSY logic can be disabled by placing
the part in slave mode with the M/S pin. Once in slave mode the BUSY
pin operates solely as a write inhibit input pin. Normal operation can be
Figure 3. Busy and chip enable routing for both width and depth expansion
with IDT70V07 RAMs.
2943 drw 19
MASTER
Dual Port
RAM
BUSY
L
BUSY
R
CE
MASTER
Dual Port
RAM
BUSY
L
BUSY
R
SLAVE
Dual Port
RAM
BUSY
L
BUSY
R
SLAVE
Dual Port
RAM
BUSY
L
BUSY
R
BUSY
L
BUSY
R
DECODER
CE
CE
CE
,
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
16
D
2943 drw 20
0DQ
WRITE
D0
D
Q
WRITE
SEMAPHORE
REQUEST FLIP FLOP SEMAPHORE
REQUEST FLIP FLOP
LPORT RPORT
SEMAPHORE
READ SEMAPHORE
READ
,
I where CE and SEM are both HIGH.
Systems which can best use the IDT70V07 contain multiple
processors or controllers and are typically very high-speed systems
which are software controlled or software intensive. These systems
can benefit from a performance increase offered by the IDT70V07's
hardware semaphores, which provide a lockout mechanism without
requiring complex programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in
varying configurations. The IDT70V07 does not use its semaphore
flags to control any resources through hardware, thus allowing the
system designer total flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred
in either processor. This can prove to be a major advantage in very
high-speed systems.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are indepen-
dent of the Dual-Port SRAM. These latches can be used to pass a flag,
or token, from one port to the other to indicate that a shared resource
is in use. The semaphores provide a hardware assist for a use
assignment method called “Token Passing Allocation.” In this method,
the state of a semaphore latch is used as a token indicating that shared
resource is in use. If the left processor wants to use this resource, it
requests the token by setting the latch. This processor then verifies its
success in setting the latch by reading it. If it was successful, it
proceeds to assume control over the shared resource. If it was not
successful in setting the latch, it determines that the right side
processor has set the latch first, has the token and is using the shared
resource. The left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore to
perform another task and occasionally attempt again to gain control of
the token via the set and test sequence. Once the right side has
relinquished the token, the left side should succeed in gaining control.
The semaphore flags are active LOW. A token is requested by
writing a zero into a semaphore latch and is released when the same
side writes a one to that latch.
The eight semaphore flags reside within the IDT70V07 in a
separate memory space from the Dual-Port SRAM. This address
space is accessed by placing a LOW input on the SEM pin (which acts
as a chip select for the semaphore flags) and using the other control
pins (Address, OE, and R/W) as they would be used in accessing a
standard Static RAM. Each of the flags has a unique address which
can be accessed by either side through address pins A0 – A2. When
accessing the semaphores, none of the other address pins has any
effect.
When writing to a semaphore, only data pin D0 is used. If a LOW
level is written into an unused semaphore location, that flag will be set
to a zero on that side and a one on the other side (see Truth Table V).
That semaphore can now only be modified by the side showing the
zero. When a one is written into the same location from the same side,
the flag will be set to a one for both sides (unless a semaphore request
from the other side is pending) and then can be written to by both sides.
The fact that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what makes
semaphore flags useful in interprocessor communications. (A thor-
ough discussion on the use of this feature follows shortly.) A zero
written into the same location from the other side will be stored in the
Figure 4. IDT70V07 Semaphore Logic
semaphore request latch for that side until the semaphore is freed by
the first side.
When a semaphore flag is read, its value is spread into all data bits
so that a flag that is a one reads as a one in all data bits and a flag
containing a zero reads as all zeros. The read value is latched into one
side’s output register when that side's semaphore select (SEM) and
output enable (OE) signals go active. This serves to disallow the
semaphore from changing state in the middle of a read cycle due to a
write cycle from the other side. Because of this latch, a repeated read
of a semaphore in a test loop must cause either signal (SEM or OE) to
go inactive or the output will never change.
A sequence WRITE/READ must be used by the semaphore in
order to guarantee that no system level contention will occur. A
processor requests access to shared resources by attempting to write
a zero into a semaphore location. If the semaphore is already in use,
the semaphore request latch will contain a zero, yet the semaphore
flag will appear as one, a fact which the processor will verify by the
subsequent read (see Truth Table V). As an example, assume a
processor writes a zero to the left port at a free semaphore location. On
a subsequent read, the processor will verify that it has written success-
fully to that location and will assume control over the resource in
question. Meanwhile, if a processor on the right side attempts to write
a zero to the same semaphore flag it will fail, as will be verified by the
fact that a one will be read from that semaphore on the right side during
subsequent read. Had a sequence of READ/WRITE been used
instead, system contention problems could have occurred during the
gap between the read and write cycles.
It is important to note that a failed semaphore request must be
followed by either repeated reads or by writing a one into the same
location. The reason for this is easily understood by looking at the
simple logic diagram of the semaphore flag in Figure 4. Two sema-
phore request latches feed into a semaphore flag. Whichever latch is
first to present a zero to the semaphore flag will force its side of the
semaphore flag LOW and the other side HIGH. This condition will
continue until a one is written to the same semaphore request latch.
Should the other side’s semaphore request latch have been written to
a zero in the meantime, the semaphore flag will flip over to the other
side as soon as a one is written into the first side’s request latch. The
second side’s flag will now stay LOW until its semaphore request latch
17
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
is written to a one. From this it is easy to understand that, if a
semaphore is requested and the processor which requested it no
longer needs the resource, the entire system can hang up until a one
is written into that semaphore request latch.
The critical case of semaphore timing is when both sides request
a single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem. If
simultaneous requests are made, the logic guarantees that only one
side receives the token. If one side is earlier than the other in making
the request, the first side to make the request will receive the token. If
both requests arrive at the same time, the assignment will be arbitrarily
made to one port or the other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is
secure. As with any powerful programming technique, if semaphores
are misused or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be
handled via the initialization program at power-up. Since any sema-
phore request flag which contains a zero must be reset to a one, all
semaphores on both sides should have a one written into them at
initialization from both sides to assure that they will be free when
needed.
Using Semaphores—Some Examples
Perhaps the simplest application of semaphores is their applica-
tion as resource markers for the IDT70V07’s Dual-Port SRAM. Say the
32K x 8 SRAM was to be divided into two 16K x 8 blocks which were
to be dedicated at any one time to servicing either the left or right port.
Semaphore 0 could be used to indicate the side which would control
the lower section of memory, and Semaphore 1 could be defined as the
indicator for the upper section of memory.
To take a resource, in this example the lower 16K of Dual-Port
SRAM, the processor on the left port could write and then read a zero
in to Semaphore 0. If this task were successfully completed (a zero
was read back rather than a one), the left processor would assume
control of the lower 16K. Meanwhile the right processor was attempting
to gain control of the resource after the left processor, it would read
back a one in response to the zero it had attempted to write into
Semaphore 0. At this point, the software could choose to try and gain
control of the second 16K section by writing, then reading a zero into
Semaphore 1. If it succeeded in gaining control, it would lock out the
left side.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore 1 was still occupied by the right side, the left side could
undo its semaphore request and perform other tasks until it was able
to write, then read a zero into Semaphore 1. If the right processor
performs a similar task with Semaphore 0, this protocol would allow the
two processors to swap 16K blocks of Dual-Port SRAM with each
other.
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
semaphore flags. All eight semaphores could be used to divide the
Dual-Port SRAM or other shared resources into eight parts. Sema-
phores can even be assigned different meanings on different sides
rather than being given a common meaning as was shown in the
example above.
Semaphores are a useful form of arbitration in systems like disk
interfaces where the CPU must be locked out of a section of memory
during a transfer and the I/O device cannot tolerate any wait states.
With the use of semaphores, once the two devices has determined
which memory area was “off-limits” to the CPU, both the CPU and the
I/O devices could access their assigned portions of memory continu-
ously without any wait states.
Semaphores are also useful in applications where no memory
“WAIT” state is available on one or both sides. Once a semaphore
handshake has been performed, both processors can access their
assigned SRAM segments at full speed.
Another application is in the area of complex data structures. In this
case, block arbitration is very important. For this application one
processor may be responsible for building and updating a data
structure. The other processor then reads and interprets that data
structure. If the interpreting processor reads an incomplete data
structure, a major error condition may exist. Therefore, some sort of
arbitration must be used between the two different processors. The
building processor arbitrates for the block, locks it and then is able to
go in and update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting processor
to come back and read the complete data structure, thereby guaran-
teeing a consistent data structure.
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
18
Ordering Information
NOTE:
1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office.
2943 drw 21
A
Power
999
Speed
A
Package
A
Process/
Temperature
Range
Blank
I
(1)
Commercial (0°Cto+70°C)
Industrial (-40°Cto+85°C)
PF
G
J
80-pin TQFP (PN80-1)
68-pin PGA (G68-1)
68-pin PLCC (J68-1)
25
35
55
S
LStandard Power
Low Power
XXXXX
Device
Type
256K (32K x 8) 3.3V Dual-Port RAM70V07
IDT
Speed in nanoseconds
Commercial & Industrial
Commercial Only
Commercial Only
,
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History:
3/24/99: Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Page 2 and 3 Added additional notes to pin configurations
6/9/99: Changed drawing formatt
10/14/04: Removed Preliminary status
Page 1 Added I-temp offering
Page 4 Updated Capacitance table
Increased Storage Temp parameter in Absolute Maximum Rating table
Added Junction Temp to Absolute Maximum Rating table
Page 4, 5, 6, 7 & 10 Removed I-temp footnote from tables
Page 5 Added I-temp 25ns power numbers to the DC Electrical Characteristics table
DC Electrical parameters–changed wording from "open" to "disabled"
Page 5 & 6 Changed transition measurement from ±200mV to 0mV in footnotes
Page 6, 7, 10, & 12 Added I-temp to all AC Electrical Characteristics table
Page 8 Updated Timing Waveform of Write Cycle No. 1, R/W Controlled Timing
Page 1 & 17 Replaced old IDTTM logo with new IDTTM logo
Page 17 Added I-temp to 25ns speed grade in ordering information
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794
San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com
www.idt.com
