CRD4299-1 - Cirrus Logic, Inc.



Cirrus Logic, Inc. 1998

CS4614

Preliminary Product Bulletin

CrystalClear™

SoundFusion™ PCI Audio

Accelerator

FEATURES

■255 MIPs SLIMD™ DSP Architecture

■DirectX™ 5.0 3D Positional Audio

■Fat Labs Approved 64-V oice Wavetable Synthesis

with Effects

■NetMeeting™ AEC Hardware Acceleration

■High Quality Hardware Sample Rate Conversion

(90+ dB Dynamic Range)

■PC/PCI Legacy Support

■DDMA Legacy Support

■CrystalClear Legacy Support (CCLS™)

■PCI 2.1 Compliant PCI Interface

■96 Stream DMA Interface with Hardware Scat-

ter/Gather Support

■PCI Power Management (D0 through D3 Hot),

APM 1.2, and ACPI 1.0 Support

■AC ‘97 2.0 Link Codec Interface

■DirectInput™ Joystick Interface

■MPU-401 MIDI Input/Output Interface

■3.3 V Power Supply (5 V tolerant I/O)

DESCRIPTION

The CS4614 is a high performance pin-compatible

upgrade to the 100-pin CS4610/11 PCI audio ac-

celerator. With the added legacy compatibility

modes, the CS4614 enables real mode DOS com-

patible PCI-only audio subsystems. This device,

combined with application and driver software,

provides a complete system solution for hardware

acceleration of Windows 95® DirectSound®,

DirectSound3D®, DirectInput, and Wavetable Syn-

thesis. WDM drivers provide support for both

Windows 98 and Windows NT 5.0.

The CS4614 is based on the Cirrus Logic Crystal-

Clear Stream Processor (SP) DSP core. The SP

core is optimized for digital audio processing, and

is powerful enough to handle complex signal pro-

cessing tasks with ease. The SP core is supported

by a bus mastering PCI interface and a built-in

dedicated DMA engine with hardware scatter-

gather support. These support functions ensure

extremely efficient transfer of audio data streams

to and from host-based memory buffers, providing

a system soluti on with maximum pe rformanc e and

minimal host CPU loading.

The all-digital CS4614 supports a variety of audio

I/O configurations including direct connection to

the CrystalClear CS4297 AC ‘97 Codec.

PC/PCI, DDMA, and CrystalClear Legacy support

provide PCI-only legacy games compatibility.

ORDERING INFORMATION

CS4614-CM 100-pin MQFP 20x14x3. 07 mm

DS292PP3 JUN ‘98

CIRRUS LOGIC PRELIMINARY PRODUCT BULLETIN JUNE 30, 5:03 PM

2CIRRUS LOGIC PRELIMINARY PRODUCT BULLETIN JUNE 30, 5:03 PM DS292PP3

CS4614

CrystalC le ar™ SoundFusion™ PCI Audio Acce le rat or

ABSOLUTE MAXIMUM RATINGS

(PCIGND = CGND = CRYGND = 0 V, all voltages with respec t to 0 V)

Notes: 1. Includes all power generated by AC an d/or DC output loading.

2. The power supply p ins are at reco mmende d maximum valu es. XTALI & XTALO are at 3.6 V maximum.

3. At ambient temperatures above 70° C, total power dissipation must be limited to less than 0.4 Watts.

WARNING: Operation beyond these limits may result in permanent damage to the device.

Normal operation is no t guaranteed at these extremes.

RECOMMENDED OPERATING CONDITION S

(PCIGND = CGND = CRYGND = 0 V, all voltages with respec t to 0 V)

Specifications are subject to change without notice.

Parameter Symbol Min Typ Max Unit

Power Supplies PCIVDD

CVDD

CRYVDD

VDD5REF

4.6

5.5

Total Power Dissip ation (Note 1) - - 1.5 W

Input Current per Pin, DC (Except supply pins) - - 10 mA

Output current per pin, DC - - 10 mA

Input voltage (Note 2) -0.3 - 5.75 V

Ambient temp erature (power appli ed) (Note 3) -45 - 85 °C

Storage temperature -55 - 150 °C

Parameter Symbol Min Typ Max Unit

Power Supplies PCIVDD

CVDD

CRYVDD

VDD5REF

4.75

3.3

3.6

5.25

Internal DSP Frequency - - 85 MHz

Operati ng Ambient Temperatur e TA02570°C

Windows, Windows 95, DirectSound, and DirectSound3D are registered trademarks of Microsoft Corporation.

DirectInput, DirectX and NetMeeting are trademarks of Microsoft Corporation.

Sound Blaster and Sound Blaster Pro are trademarks of Creative Technology, Ltd.

Crystal, CrystalClear, CCLS, SLIMD and SoundFusion are trademarks of Cirrus Logic, Inc.

All other names are trademarks, registered trademarks, or service marks of their respective companies.

DS292PP3 CIRRUS LOGIC PRELIMINARY PRODUCT BULLETIN JUNE 30, 5:03 PM 3

CS4614

CrystalClear™ SoundFusion™ PCI Audio Accelerator

AC CHARACTERISTI CS (PCI SIGNAL PINS ONLY) (TA = 70° C;

PCIVDD = CVDD = CRYVDD = 3.3 V; VDD5REF = 5 V; PCIGND = CGND = CRYGND = 0 V;

Logic 0 = 0 V, Logic 1 = 3.3 V; Reference levels = 1.4 V; unless othe rwise noted; (Note 4))

Notes: 4. Specifications guaranteed by characterization and not production testing.

5. Refer to V/I curves in Figure 1. Specification does not apply to PCICLK and RST# signals. Switching

Current High specification does not apply to SERR# and INTA# which are open drain outputs.

6. Cumulati ve edge rate across specified range. Rise slew rates do not apply to open drain outputs.

7. Equation A: IOH = 11.9 * (Vou t - 5.25) * (Vout + 2.45) for 3.3 V > Vout > 3.1 V

8. Equation B: IOL = 78.5 * Vout * (4. 4 - Vout) for 0 V < Vo ut < 0. 71 V

Parameter Symbol Min Max Unit

Switch ing Current High (Note 5)

0 < Vout < 1.4

1.4 < Vout < 2.4

3.1 < Vout < 3.3

IOH -44

Note 7

Switch ing Current Low (Note 5)

Vout > 2.2

2.2 > Vout > 0.55

0.71 > Vout > 0

IOL 95

Vout/0.023

Note 8

Low Clamp Current -5 < Vin < -1 ICL -mA

Output r ise slew rate 0.4 V - 2.4 V load (Note 6) slewr 1 5 V/ns

Output f all slew rate 2. 4 V - 0.4 V load (Note 6) slewf 1 5 V/ns

44–

Vout

1.4–

0.024

---------------------------+

25–

Vin

0.015

-------------------+

Pu ll Up Pull Down

Equation B:Equation A:

3.3

2.2

0.55

2.4

voltage voltage

1.4

drive point

DC drive

point

AC d rive

point

I = 11.9*(Vout-5.25)*(Vout+2.45)

for 3.3V > Vout > 3.1V

I = 78.5*Vout*(4.4-Vout)

for 0V < Vout < 0.71V

AC drive

point

test

point

test

point

-2

3, 6 95 380

Curr en t (m A) Current (m A)

176

Figure 1. AC Characteristics

4CIRRUS LOGIC PRELIMINARY PRODUCT BULLETIN JUNE 30, 5:03 PM DS292PP3

CS4614

CrystalC le ar™ SoundFusion™ PCI Audio Acce le rat or

DC CHARACTERISTICS (TA = 70° C; PCIVDD = CVDD = CRYVDD = 3.3 V; VDD5REF = 5 V;

PCIGND = CGND = CRYGND = 0 V; all voltages with respect to 0 V unless otherwise noted)

Notes: 9. The following signals are tested to 6 mA: FRAME#, TRDY#, IRDY#, DEVSEL#, STOP#, SERR# ,

PERR#, and INTA#. All other PCI interface signals are tested to 3 mA.

10. Input leakage current s include hi -Z output leakage for all bi-direct ional buffers with three-state out puts.

11. For open drain pins, high level output voltage is dependent on external pull-up used and number of

attached gates.

12. Typic al values a re given as average cu rrent with t ypical SP t ask executi on and data st reaming. Cur rent

values vary dramatically based on the softwar e running on the SP.

Parameter Symbol Min Typ Max Unit

PCI In terface Si g n a l P in s

High level i nput volta ge VIH 2-5.75V

Low level input voltage VIL -0.5 - 0.8 V

High level output voltage Iout = -2 mA VOH 2.4 - - V

Low level output voltage Iout = 3 mA, 6 mA (Note 9) VOL --0.55V

High level l eakage current Vin = 2.7 V (Note 10) IIH --70µA

Low level leakage current Vin = 0.5 V(Note 10) IIL ---70µA

Non-PCI Int erface Signal Pins (Except XTALO)

High level i nput volta ge XTALI

Other Pins VIH 2.3

23.3

-4.0

5.75 V

Low level input voltage XTALI

Other Pins VIL -0.5

-0.5 0

-0.8

0.8 V

High level output voltage Iout = -4 mA (Note 11) VOH 2.4 - - V

Low level output voltage Iout = 4 mA VOL --0.4V

High level l eakage current Vin = 5.25 V IIH --10µA

Low level leakage current Vin = 0 IIL ---10µA

Parameter Min Typ Max Unit

Power Supply Pins (Outputs Unloaded)

Power Supply Current: VDD5REF

PCIVDD/CVDD/CRYVDD Total (Notes 4,12) -

-0.6

164 -

TBD mA

Low Power Mode Supply Curr ent - 10 - mA

DS292PP3 CIRRUS LOGIC PRELIMINARY PRODUCT BULLETIN JUNE 30, 5:03 PM 5

CS4614

CrystalClear™ SoundFusion™ PCI Audio Accelerator

PCI INTERFACE PINS (TA = 0 to 70° C; PCIVDD = CVDD = CRYVDD = 3.3 V; VDD5REF = 5 V;

PCIGND = CGND = CRYGND = 0 V; Logic 0 = 0 V, Logic 1 = 3.3 V; Timing refer ence levels = 1.4 V)

Notes: 13. For Ac tive/ Float me asurements, the Hi- Z or “ off” stat e i s when t he tot al curren t delivered is less tha n or

equal t o the leakage current . Specific ation is guaranteed by design, n ot production tested.

14. RST# is asser ted and de-asserte d asynchronously with respect to PCICLK.

15. All output drivers are asynchronously floated when RST# is active.

Parameter Symbol Min Max Unit

PCICLK cycle time tcyc 30 - ns

PCICLK high time thigh 11 - ns

PCICLK lo w time tlow 11 - ns

PCICLK to signal valid delay - bused signals tval 211ns

PCICLK to signal valid delay - point to point tval(p+p) 212ns

Float to active delay (Note 13) t on 2-ns

Acti ve to Float delay (Note 13) t off -28ns

Input Set up Time to PCICLK - bused signals tsu 7-ns

Input Set up Time to PCICLK - point to point tsu(p+p) 10 , 12 - ns

Input hold time for PCICLK th0-ns

Reset active time after PCICLK stable (Note 14) trst-clk 100 - µs

Reset active to output float delay (Notes 13, 14, 15) trst-off -40ns

PCICLK

rst-clk

RST#

OUTPUTS

Hi-Z

INPUTS

Valid

Input

off

OUTPUTS

Valid

val

rst-off

Figure 2. PCI Timing Measurement Conditions

6CIRRUS LOGIC PRELIMINARY PRODUCT BULLETIN JUNE 30, 5:03 PM DS292PP3

CS4614

CrystalC le ar™ SoundFusion™ PCI Audio Acce le rat or

AC ’97 SERIAL INTERFACE TIMING (TA = 0 to 70° C; PCIVDD = CVDD = CRYVDD = 3.3 V;

VDD5REF = 5 V; VDD5REF = 5 V; PCIGND = CGND = CRYGND = 0 V; Logic 0 = 0 V, Logic 1 = 3.3 V;

Timin g referenc e level s = 1.4 V; unless otherwise noted)

Parameter Symbol Min Typ Max Unit

ABITCLK cycle time taclk 78 81.4 - ns

ABITCLK rising to ASDOUT valid tpd5 -1725ns

ASDIN valid to ABITCLK falling ts5 15 - - ns

ASDIN hold after ABITCLK falling t h5 5--ns

PCICLK rising to ARST# vali d tpd6 -10- ns

PCICLK

aclk

pd5

pd6

Figure 3. AC ’97 Configuration Timing Diagram

ABITCLK

ASYNC

ASDOUT

ASDIN

ARST#

DS292PP3 CIRRUS LOGIC PRELIMINARY PRODUCT BULLETIN JUNE 30, 5:03 PM 7

CS4614

CrystalClear™ SoundFusion™ PCI Audio Accelerator

INDEPENDENT TIMING ENVIRONMENT (TA = 0 to 70° C; PCIVDD = CVDD = CRYVDD = 3.3 V;

VDD5REF = 5 V; VDD5REF = 5 V; PCIGND = CGND = CRYGND = 0 V; L ogic 0 = 0 V, Logi c 1 = 3.3 V;

Timing reference levels = 1.4 V; XTALI = 12.288 MHz; unless otherwise noted)

Parameter Symbol Min Typ Max Units

SCLK output cycle time tsclk 312 326 - ns

FSYNC output cycle time (@SCLK falli ng edge) tfsync 20000 20833 - ns

SCLK falling to FSYNC transition tpd7 -45 2 45 ns

LRCLK output cyc le time (@ SCLK rising edge) t lrclk 20000 20833 - ns

SCLK rising to LRCLK transition tpd8 -45 2 45 ns

SCLK falling to SDOUT/SDO2/SDO3 valid tpd9 -245ns

SDIN/SDIN2 valid to SCLK rising (SI1F2-0: 010, SI2F1-0: 00) ts6 30 - - ns

SDIN/SDIN2 hold after SCLK rising

(SI1F2-0: 010, SI2F1-0: 00) th6 30 - - ns

SDIN/SDIN2 valid to SCLK falling

(SI1F2-0: 011, SI2F1-0: 01) ts7 30 - - ns

SDIN/SDIN2 hold after SCLK falling

(SI1F2-0: 011, SI2F1-0: 01) th7 30 - - ns

XTAL frequency 12.287 12.288 12.289 MHz

XTALI high time (Note 4) 35 - - ns

XTALI low time (Note 4) 35 - - ns

MCLK output fr equency (Note 4) 12.287 12.288 12.289 MHz

SCLK

FSYNC

LRCLK

SDOUT/SD02/SD03

SDIN/SDIN2

sclk

pd7

fsync

lrclk

pd9

pd8

15 015 0

17 16 0 17 16 0

19 18 0 19 18 0

Figure 4. Independent Timing Configuration

8CIRRUS LOGIC PRELIMINARY PRODUCT BULLETIN JUNE 30, 5:03 PM DS292PP3

CS4614

CrystalC le ar™ SoundFusion™ PCI Audio Acce le rat or

EEPROM TIMING CHARACTERISTICS Note 4. (T A = 0 to 70 °C, PCI VDD = CVDD = CRYVDD =

3.3 V; VDD5REF = 5 V; VDD5REF = 5 V; PCIGND = CGND = CRYGND = 0 V; Logic 0 = 0 V, Logic 1 = 3.3 V;

Timing reference levels = 1.4 V; PCI clock frequency = 33 MHz; unless otherwise noted)

Notes: 16. Rise t ime on EEDAT is deter mined by the capaci tance on the EEDAT line wi th all connected gat es and

the required exte rnal pull- up resistor.

Parameter Symbol Min Max Units

EECLK Low to EEDAT Data Out Valid tAA 07.0

µs

Start Condition Hold Time tHD:STA 5.0 - µs

EECLK Low tLEECLK 10 - µs

EECLK High tHEECLK 10 - µs

Start Condition Setup Time (for a Re peated Start Condition ) tSU:STA 5.0 - µs

EEDAT In Hold Time tHD:DAT 0-

µs

EEDAT In Setup Time tSU:DAT 250 - ns

EEDAT/EECLK Rise Time (Note 16) tR-1

µs

EEDAT/EECLK Fall Time tF-300ns

Stop Condition Setup Time tSU:STO 5.0 - µs

EEDAT Out Hold Time tDH 0-

µs

EECLK

EEDAT (IN)

EEDAT (OUT)

SU:STA

HD:STA

HD:DAT

SU:DAT

SU:STO

HEECLK

LEECLK

EEDAT (OUT)

Figure 5. EEPROM Timing

DS292PP3 CIRRUS LOGIC PRELIMINARY PRODUCT BULLETIN JUNE 30, 5:03 PM 9

CS4614

CrystalClear™ SoundFusion™ PCI Audio Accelerator

OVERVIEW

The CS4614 is a high performance audio accelera-

tor DSP for the PCI bus. This device, combined

with application and driver software, provides a

complete system solution for cost effective acceler-

ation of Windows DirectSound, Direct-Sound3D,

DirectInput, MIDI playback via Wavetable Syn-

thesis with reverberation and chorus effects pro-

cessing, and more. The CS4614 is compatible with

the CS4610/11 with the following added fea tures:

• AC ‘97 In terface now 2. 0 compatible

• CrystalClea r L eg acy Support

• PC/PCI Le ga cy Support

• DDMA Legacy Suppo rt

There are three main functional blocks within the

CS4614: the Stream Processor, the PCI Interface,

and the DMA Engine. A block diagram of the

CS4614 devi c e is shown in Figure 6.

The Stream Proc essor (SP) is a high sp eed c ustom

Digital Signal Processor (DSP) core specifically

designed for audio signal processing. The Stream

Processor is capable of running a number of differ-

ent signal processing algorithms simultaneously.

This high concurrency capability is valuable for ap-

plications such as immersive 3D games, which may

play a number of DirectSound streams, a number of

DirectSound3D streams, and a MIDI music se-

quence simulta neously .

Separate RAM memorie s are included on-chip for

the SP p rogram c ode (PROGRAM RAM), param -

eter data ( PARAMETER RAM), an d audi o sam ple

data (SAMPLE RAM). Two ROM memories store

coefficients for sample rate conversion and audio

decompression algorithms (COEFFICIENT ROM)

and common algorithm code (PROGRAM ROM).

The RAM-based DSP architecture of the CS4614

ensures maximum system flexibility. The software

function/feature mix can be adapted to meet the re-

quirements of a variety of different applications,

such as DirectX™ games or DOS applications.

This RAM-based architecture also provides a

means for future system upgrades, allowing the ad-

dition of new or upgraded functionality through

softwar e up dates.

The CS4614 provides an extremely efficient bus

mast ering in terfa ce to the PC I bus. The P CI Inte r-

face functi on allo ws econom i ca l burst mode trans-

fers of audio data between host system memory

buffer s and the CS46 14 device. Program cod e and

parameter data are also transferred to the CS4614

over the PCI interface.

The DM A Engine prov ides dedicated h ardwar e to

manage transfer of up to 96 concurrent audio/da ta

streams to and from host memory buffers. The

DMA Engine provides hardware scatter-gather

support, allowing simple buffer allocation and

96-Stream

DMA Controller

with Hardware

Scatter/Gather

MPU-401

MIDI Interface

Program

ROM

Parameter

RAM

PCI

Interface

Joystick

Interface

SLIMD

SP Core

PC/PCI &

CCLS Legacy

AC ’97 2.0

Interface

GPIO

PLL Clock

Sample

RAM

Program

RAM

Coefficient

ROM

Figure 6. CS4614 Block Diagram

10 CIRRUS LOGIC PRELIMINARY PRODUCT BULLETIN JUNE 30, 5:03 PM DS292PP3

CS4614

CrystalC le ar™ SoundFusion™ PCI Audio Acce le rat or

management. This implementation improves sys-

tem efficiency by minimizing the number of host

interrupts.

The CS4614 supports a variety of audio I/O config-

urations including a CS4297 CrystalClear AC ’97

Codec. The system’s flexibility is further enhanced

by the inclusion of a bi-directional serial MIDI

port, a joystick port, a hardware volume control in-

terface, and a serial data port which allows connec-

tion of an opt ional externa l EEPROM de vi ce.

Stream Processor DSP Core

The CS4614 Stream Processor (SP) is a custom

DSP core design which is optimiz ed for processing

and synthesizing digital audio data streams. The SP

features a Somewhat Long Instruction Multiple

Data (SLIMD) modified dual Harvard architecture.

The device uses a 40-bit instruction word and oper-

ates on 32-bit data words. The SP includes two

Multiply-Accumulate (MAC) blocks and one 16-

bit Ari thmetic and Logic Uni t (AL U ). The SP core

is conservatively rated at 255 Million Instructions

per second (2 55 MIPS) when runni ng at a 85 MHz

inte rnal cl ock speed. The MAC units pe rform dual

20-bit by 16-bit multiplies and have 40-bit accumu-

lators, providing higher quality than typ ical 16-bit

DSP architectures.

A programmable Phase Locked Loop (PLL) circuit

generates the high frequency internal SP clock

from a lower frequency input clock. The input to

the PL L m ay be fr om a cr ystal oscill ator ci rcui t or

the se ri al port c lo ck ABITC LK/ SCL K . C loc k con-

trol ci rcu itry al lows gat ing o f cloc ks to v ariou s in-

ternal functional blocks to conserve power during

power conservation modes, as well as during nor-

mal modes of operation when no tasks are being

executed.

Legacy Support

Lega cy games are supported by Cryst alClear L eg-

acy Support (CCLS), DDMA, or by the PC/PCI in-

terface.

In both motherboard and add-in card designs,

CCLS and DDMA provide support for legacy

gam es by providing a ha rdware interfa ce that sup-

ports a Soun d Blaster Pro comp atible interface, as

well as support for FM, MPU-401, and joystick in-

terfaces. These hardware interfaces provide PCI-

only games compatibility for real-mode DOS and

Windows DOS-b ox support.

For motherboard designs, PC/PCI can be used by

connecting the PCGNT# and PCREQ# pins to the

appropriate pins on the south bridge motherboard

chip. The PC/PCI interface is compliant with In-

tel’s PC/PCI spec. (version 1.2). The BIOS must

enable the PC/PCI mechanism at boot time on both

the CS4614 and the south bridge.

SYSTEM ARCHITECTURES

A typical system diagram depictin g connection of

the CS4614 to the CrystalClear CS4297 AC ’97

Codec is given in Figure 7. All analog audio inputs

and outputs are connected to the CS4297. Audio

data is passed between the CS4297 and the CS4614

over the serial AC-Link. The CS4614 provides a

hardware interface for connection of a joystick and

MIDI devices.

HOST INTERFACE

The CS4614 host interface is comprised of two sep-

arate interface blocks which are memory mapped

into host address space. The interface blocks can be

located anywhere in the host 32-bit physical ad-

dress space. The interface block locations are de-

fined by the addresses programmed into the two

Base Address Registers in the PCI Configuration

Space. These base addresses are normally set up by

the system’s Plug and Play BIOS. The first inter-

face block (located by Base Address 0) is a 4 kByte

regist er blo ck conta inin g gene ra l purpo se conf igu -

ration, control, and status registers for the device.

The second interface block (located by Base Ad-

dress 1 ) is a 1 MByt e block which m ap s all of t he

internal RAM memories (SP Program RAM, Pa-

DS292PP3 CIRRUS LOGIC PRELIMINARY PRODUCT BULLETIN JUNE 30, 5:03 PM 11

CS4614

CrystalClear™ SoundFusion™ PCI Audio Accelerator

rameter RAM, and Sample RAM) into host memo-

ry spa ce. Th is all ows th e host to directl y peek and

poke RAM locations on the device. The relation-

ship between the Base Address Registers in the

CS4614 PCI Configuration Space and the host

memory map is depict ed in Figure 8.

The bus mastering PCI bus interface complies with

the PCI Local Bus Specification (version 2.1).

PCI bus transactions

As a target of a PCI bus transaction, the CS4614

supports the Memory Read (from internal registers

or memory), Memory Write (to internal registers

or memory), Configuration Read (from CS4614

configuration registers), Configuration Write (to

CS4614 configuration registers), Memory Read

Mult iple (ali ased to Memor y Read ), Memo ry Read

Line (aliased to Memory Read), and the Memory

Write and Invalidate (aliased to Memory Write)

transf er cycl es. The I/O Read , I/O Write, Inter rupt

Acknowledge, Special Cycles, and Dual Address

Cycle transa c tions ar e not supported.

As Bus Master, the CS4614 generates the Memory

Read Multiple and Memory Write transactions.

The Memory Read , Configuration Read, Configu-

ration Write, Memory Read Line, Memory Write

Host

Memory

North

Bridge

CPU

South

Bridge CS4297

PCI Bus

PC/PCI (if used)

Audio Out

Audio In

Figure 7. AC ‘97 Codec Interface

CS4614

Accelerator

00h Device ID / Vendor ID

Status / Command

Class Code / Rev isi on

Base Address Register 0

Base Address Register 1

Mi sc. Contr o l

Direct I/O Registers

(Memory Mapped, 4 kByte)

Dir ec t Me mo r y Inter fac e

(Memory Mapped, 1 MByte)

Device PCI Config. Space

04h

08h

0Ch

10h

14h

Figure 8. Host Interface Base Address Registers

12 CIRRUS LOGIC PRELIMINARY PRODUCT BULLETIN JUNE 30, 5:03 PM DS292PP3

CS4614

CrystalC le ar™ SoundFusion™ PCI Audio Acce le rat or

and Inv alidate, I/O Read, I/O Write, Int errupt Ac-

know ledge, Sp ecial Cycles, a n d Dua l Address Cy -

cle t ransacti ons are no t generat ed.

The PCI bus transactions supported by the CS4614

device are summarized in Table 1. Note that no

Target Abort conditions are signalled by the de-

vice. Byte, Word, and Doubleword transfers are

supported for Configuration Space accesses. Only

Doubleword transfers are supported for Register or

Memory area accesses. Bursting is not supported

for ho st-initiated transfers to/from the CS4614 in-

ternal register space, RAM memory space, or PCI

confi guration space (di sconnect after first pha se of

transaction is completed).

Configuration Space

The content and format of the PCI Configuration

Space is given in Table 2.

Initiator Target Type PCI Dir

Host Registers (BA0) Mem Write In

Host Registers (BA0) Mem Read Out

Host Memories (BA1) Mem Write In

Host Memories (BA1) Mem Read Out

Host Config Sp ace 1 Config W ri te In

Host Config Sp ace 1 Config Read Out

DMA Host System Mem Write Out

DMA Host System Mem Read In

Table 1. PCI Interface Transaction Summary

Byte 3Byte 2Byte 1Byte 0Offset

Device ID: R/O, 6003h Vendor ID: R/O, 1013h 00h

Status Regis ter, bits 15-0:

Bit 15 Detected Parity Error: Error Bit

Bit 14 Signal led SERR: Error Bit

Bit 13 Received Master Abort: Error Bit

Bit 12 Received Tar get Abort: Error Bit

Bit 11 Signal led Target Abort : Error Bit

Bit 10-9 DEVSEL Timing: R/O, 01b (medium)

Bit 8 Data Parity Error Detected: Error Bit

Bit 7 Fast Back to Back Capabl e: R/O 0

Bit 6 User Definable Features: R/O 0

Bit 5 66MHz Bus: R/O 0

Bit 4 New C a pabi lit ie s : R /O 1

Bit 3-0Res erved: R/O 0000

Reset Status State: 0210h

Write of 1 to any error bit position clears it.

Command Register, bits 15-0:

Bit 15-10: Reserved, R/O 0

Bit 9 Fast B2B Enable: R/O 0

Bit 8 SERR Enable: R/W, default 0

Bit 7 Wait Control: R/O 0

Bit 6 Parity Erro r Response: R/W, default 0

Bit 5 VGA Palette Snoop: R/O 0

Bit 4 MWI Enable: R/O 0

Bit 3 Special Cycles: R/O 0

Bit 2 Bus Master Enable: R/W, default 0

Bit 1 Memory Space Enable: R/W, default 0

Bit 0 IO Space Enable: R/O 0

04h

Table 2. PCI Configuration Space

DS292PP3 CIRRUS LOGIC PRELIMINARY PRODUCT BULLETIN JUNE 30, 5:03 PM 13

CS4614

CrystalClear™ SoundFusion™ PCI Audio Accelerator

Class Code: R/ O 04010 0h

Class 04h (multimedia device), Sub-class 01h (audio), Interface 00h Revision ID: R/O 01h 08h

BIST: R/O 0 Header Type:

Bit 7: R/O 0

Bit 6-0: R/O 0 (type 0)

Latency Timer:

Bit 7-3: R/W,default 0

Bit 2-0: R/O 0

Cache Line Size :

R/O 0 0Ch

Base Address Regi ster 0

Device Contr ol Register space, memory mapped. 4 kByte size

Bit 31-12: R/W, default 0. Compare address for register space accesses

Bit 11 - 4: R/O 0, specifies 4 kByte si ze

Bit 3: R/O 0, Not Prefetchable ( Ca cheable)

Bit 2-1: R/O 00, Location Type - Anywhere in 32 bit address sp ace

Bit 0: R/O 0, Memory space indicator

10h

Base Address Regi ster 1

Device Memory Array mapped into host system memory space, 1 MBy te si ze

Bit 31-20: R/W, default 0. Compare address for memory array accesses

Bit 19 - 4: R/O 0, specifies 1 MByte size

Bit 3: R/O 0, Not Prefetchable ( Ca cheable)

Bit 2-1: R/O 00, Location Type - Anywhere in 32 bit address sp ace

Bit 0: R/O 0, Memory space indicator

14h

Base Address Regi ster 2: R/O 00000000h, Unused 18h

Base Address Regi ster 3: R/O 00000000h, Unused 1Ch

Base Address Regi ster 4: R/O 00000000h, Unused 20h

Base Address Regi ster 5: R/O 00000000h, Unused 24h

Cardbus CIS Pointer: R/O 0000000 0h, Unused 28h

Subsys tem ID

R/O 0000h if EXTEE not present, otherwise

R/W, loaded from EEPROM

Subsystem Vendor ID

R/O 0000h if EXTEE not present, otherwise

R/W, loaded from EEPROM

2Ch

Expansion ROM Base Address: R/O 00000000h, Unused 30h

Reserved: R/O 00000000h 34h

Reserved: R/O 00000000h 38h

Max_Lat: R/O 18h

24 x 0.25uS = 6 uS Min_Gnt: R/O 04h

4 x 0.25uS = 1uS Interrupt Pin:

R/O 01h, INTA used In terrupt Line:

R/W, default 0 3Ch

Byte 3Byte 2Byte 1Byte 0Offset

Table 2. PCI Configuration Space (cont.)

14 CIRRUS LOGIC PRELIMINARY PRODUCT BULLETIN JUNE 30, 5:03 PM DS292PP3

CS4614

CrystalC le ar™ SoundFusion™ PCI Audio Acce le rat or

Subsystem Vendor ID Fields

The Subsystem ID and Subsystem Vendor ID

fields in the PCI Configuration Space default to

value 0000h unless an external EEPROM device is

detected or unless the host has written to the appro-

priat e intern al registe r to progr am the values.

Interrupt Signal

The CS4614 PCI Interface includes an interrupt

controller function which receives interrupt re-

quests from multiple sources within the CS4614

devic e, and p rese nts a sin gl e interru pt line ( INTA)

to the host system. Interrupt control registers in the

CS4614 provide the host interrupt service routine

with the ability to identify the source of the inter-

rupt and to clear the interrupt sources. In the

CS4614, the single external interrupt is expanded

by the use of “virtual channels”. Each data stream

which is read from or written to a modular buffer is

assigned a virtual channel number. This virtual

channel number is signalled by the DMA sub-

system anytime the associated modulo buffer

point er passes the mi d-point or wraps around. Vir-

tual channels are also used for message passing be-

twee n the CS4614 a nd the host.

SERIAL PORT CONFIGURATIONS

A flexi ble serial au dio inte rface is prov ided whic h

allows connection to external Analog-to-Digital

Converters (ADCs), Digi tal-to-Analog Converters

(DACs) or Codecs (combined ADC and DAC

functions) in several different configurations. The

seria l audio in terface incl udes a pr im ary input /out-

put port with dedicated serial data pins (SDIN, SD-

OUT), two auxiliary audio output ports (SDO2,

SDO3) which share pins with the joystick interface

butto n inp ut funct ions, and one auxi lia ry aud io in -

put port (SDIN2). Each of these digital audio input

and output pins carry two channels of audio data.

These two channels may comprise the left and right

chan nels of a stereo audio signal, or t wo indep en-

dent monaural audio signals.

Each digital audio channel is internally buffered

through a 16 sample x 20-bit FIFO. The data format

PMC

Bit 15: PME# from D3cold: R/O 0

Bit 14: PME# from D3hot: R/O 1

Bit 13: PME# from D2: R/O 1

Bit 12: PME# from D1: R/O 1

Bit 11: PME# from D0: R/O 1

Bit 10: D2 suppor t: R/O 1

Bit 9: D1 suppor t: R/O 1

Bit 8-6: Reserved: R/O 000

Bit 5: Device Specific init: R/O 1

Bit 4: Auxi liary power: R/O 0

Bit 3: PME# clock: R/O 1

Bit 2-0: Version: R/O 001

Nex t Item Poin t e r:

R/O 0h Capa b il ity ID:

R/O 1h 40h

Data: R/O 0 PMCSR_BSE: R/O 0

PMCSR

Bit 15: PME# status: R/W 0

Bit 14-13: Data scale: R/O 00

Bit 12-9 : Dat a select: R/O 0000

Bit 8: PME_En: R/W 0

Bit 7-2: Reserved: R/O 000000

Bit 1-0: Power state: R/W 00

44h

Byte 3Byte 2Byte 1Byte 0Offset

Table 2. PCI Configuration Space (cont.)

DS292PP3 CIRRUS LOGIC PRELIMINARY PRODUCT BULLETIN JUNE 30, 5:03 PM 15

CS4614

CrystalClear™ SoundFusion™ PCI Audio Accelerator

for the serial digital audio ports varies depending

on the configuration. The primary configuration in-

clud es a CS4614 plus a CS 4297.

The CS4614 communicates with the CS4297 ove r

the AC-link as specified in the Intel® Audio Codec

‘97 Specification (version 1.03) with support for

the 2. 0 e x te nsi ons. A block diagram for t h e A C’97

Controller configuration is given in Figure 7. The

signal connections between the CS4614 and the

AC ’97 Codec are indicated in Figure 9. In this

configuration, the AC ’97 Codec is the timing mas-

ter for the digital aud io link. The ASDOUT out put

supports data transmission on all ten possible sam-

ple slots (output slots 3 - 12). The ASDIN input

supports receiving of audio sample data on all input

sample slots (input slots 3 - 12). The SDO2 and

SDO3 serial outputs are not suppo rted in this con-

figuration.

MIDI Port

In th e AC ’9 7 controller configuration, a bi-d irec-

tion al MIDI inte rfac e is provide d to a ll ow connec-

tion of exte rnal M IDI de vice s. Th e MID I in terfa ce

includes 16-b yte FIFOs for the MIDI transmit and

rece ive pa ths.

Joystick Port

In the AC ’97 controller configuration, a joystick

port is provided. The joystick port supports four

“coo rdina te” ch annel s and fou r “but ton” c hanne ls.

The c oordin at e chann el s provi de joyst i ck position-

al i nform at ion t o the h ost , and t he butt on ch an nels

provide user button event information. The joystick

interface is capable of operating in the traditional

“polled” mode, but also provides a “hardware ac-

celerated” mode of operation wherein internal

counters are provided to assist the host with coordi-

nat e posi ti on de term inat io n. The Joys tick schema t-

ic is il lustra ted in Fi gure 10 .

ABITCLK

ASYNC

ASDOUT

ASDIN

ARST#

MIDIIN

MIDIOUT

JACX, JACY, JBCX, JBCY

JAB1, J AB2, JBB1, J BB2

Joystick/

MIDI Port

BIT_CLK

SYNC

SDATA_OUT

SDATA_IN

RESET#

24.576 MHz

CS4297

12.288 MHz

48 kHz

Analog Interface

Figure 9. AC ‘97 Codec Connection Diagram

CS4614

16 CIRRUS LOGIC PRELIMINARY PRODUCT BULLETIN JUNE 30, 5:03 PM DS292PP3

CS4614

CrystalC le ar™ SoundFusion™ PCI Audio Acce le rat or

EEPROM INTERFACE

The EEPROM configuration interface allows the

connection of an optional external EEPROM de-

vice to provide power-up configuration informa-

tion. The external EEPROM is not required for

proper operation; however, in some applications

power-u p config uration settings other th an t he de-

fault values may be required to support specific

Ope rating S ys t em compatibility requireme nts.

After a ha r dw are rese t, an internal st ate m achine i n

the CS4614 will autom aticall y detect the presence

of an ext ernal EEPROM device and load the Sub-

system ID a nd Subsyst em Vendor ID field s, al ong

with two bytes of general configuration informa-

tion, into internal registers. At power-up, the

CS4614 will a ttemp t to read f rom the ext ernal de-

vice , and will check the data r eceive d from the de -

vice for a valid signature header. If the header data

is invalid, the data transfer is aborted. After power-

up, the host can read or write from/to the EEPROM

device by accessing specific registers in the

CS4614. Cirrus Logic provides software to read

and writ e th e EEPR O M.

The two-wire interface for the optional external

EEPROM device is depicted in Figure 11. During

data transfers, the data line (EEDAT) can change

state only while the clock signal (EECLK) is low.

A state change o f the d ata line w h i le th e clock sig-

nal is high indicate s a start or stop condi ti on to t he

EEPROM device.

+5 V

DSP

1 nF

5. 6 nF

5.6 n F

2.2 k

Ω

2.2 k

Ω

MIDIIN

MIDIOUT

JAB2

JBB2

JACY

JBCY

JBCX

JACX

JBB1

JAB1

1 nF

2.2 k

Ω

2.2 k

Ω

5. 6 nF

4.7 k

Ω

4.7 k

Ω

4.7 k

Ω

4.7 k

Ω

4.7 k

Ω

Figure 10. Joystick Logic

SLIMD SP

Core

EEDAT

EECLK

4.7 k

Ω

2-wire

Serial

EEPROM

Figure 11. External EEPROM Connection

DS292PP3 CIRRUS LOGIC PRELIMINARY PRODUCT BULLETIN JUNE 30, 5:03 PM 17

CS4614

CrystalClear™ SoundFusion™ PCI Audio Accelerator

The EEPROM device read access sequence is

shown in the Figure 12. T he timin g follows t hat of

a random read sequence. The CS4614 first

performs a “dummy” write operation, then

generates a start condition followed by the slave

device address and the byte address of zero. The

CS4614 alwa ys begins acce ss at byte address zer o

and continues access a byte at a time, using a

sequential read, until all needed bytes in the

EEPR OM are re ad . Since onl y 7 by tes are neede d,

the s mallest E EP ROM available w ill suffice .

GENERAL PURPOSE I/O PINS

Many of the CS4614 signal pins are internally mul-

tiplexed to serve dif ferent function s depending on

the environm ent in whi ch t h e de vice is bei ng used.

Sever al of the CS4614 signal pins may b e used a s

general purpose I/O pins when not required for oth-

er specific functions in a given application.

S10100000A00000000AS10100001A Data Data P1A

Start Part

Address Start Acknowledge No

Acknowledge

Stop

Acknowledge Data

EEPROM

Write Read

Bank

Address Part

Address

DSP

Figure 12. EEPROM Read Sequence

18 CIRRUS LOGIC PRELIMINARY PRODUCT BULLETIN JUNE 30, 5:03 PM DS292PP3

CS4614

CrystalC le ar™ SoundFusion™ PCI Audio Acce le rat or

PIN DESCRIPTION

100-p in MQFP

INTA# 81

RST# 82

PCICLK 83

GNT# 84

REQ# 85

PCIVDD[0] 86

PCIGND[0] 87

AD[31] 88

AD[30] 89

AD[29] 90

AD[28] 91

AD[27] 92

PCIGND[1] 93

PCIVDD[1] 94

AD[26] 95

AD[25] 96

AD[24] 97

C/BE[3]# 98

IDSEL 99

PCIVDD[2] 100

TEST 51

JACX 52

JACY 53

JBCX 54

JBCY 55

JAB1/SDO2 56

JAB2/SDO3 57

JBB1/LRCLK 58

JBB2/MCLK 59

MIDIIN 60

CVDD[2] 61

CGND[2] 62

MIDIOUT 63

CVDD[3] 64

CGND[3] 65

SDIN2/GPIO 66

CGND[4] 67

CVDD[4] 68

CRYVDD 69

VOLUP/XTALI 70

VOLDN/XTALO 71

CRYGND 72

VDD5REF 73

ABITCLK/SCLK 74

ASDOUT/SDOUT 75

ASDIN/SDIN 76

ASYNC/FSYNC 77

ARST# 78

EECLK/PCREQ# 79

EEDAT/PCGNT# 80

30 PCIGND[5]

29 AD[14]

28 AD[15]

27 C/BE[1]#

26 PAR

25 SERR#

24 PERR#

23 STOP#

22 PCIGND[4]

21 PCIVDD[4]

20 DEVSEL#

19 CVDD[0]

18 CGND[0]

17 TRDY#

16 IRDY#

15 FRAME#

14 C/BE[2]#

13 CGND[1]

12 CVDD[1]

11 AD[16]

10 AD[17]

9 AD[18]

8PCIVDD[3]

7PCIGND[3]

6 AD[19]

5 AD[20]

4 AD[21]

3 AD[22]

2 AD[23]

1PCIGND[2]

50 PCIVDD[7]

49 PCIGND[7]

48 AD[0]

47 AD[1]

46 AD[2]

45 AD[3]

44 AD[4]

43 AD[5]

42 AD[6]

41 AD[7]

40 PCIGND[6]

39 PCIVDD[6]

38 C/BE[0]#

37 AD[8]

36 AD[9]

35 AD[10]

34 AD[11]

33 AD[12]

32 AD[13]

31 PCIVDD[5]

CS4614-CM

DS292PP3 CIRRUS LOGIC PRELIMINARY PRODUCT BULLETIN JUNE 30, 5:03 PM 19

CS4614

CrystalClear™ SoundFusion™ PCI Audio Accelerator

A ‘#’ sign suffix on a pin names indicates an active-low signal.

PCI Int erface

AD[31:0] - Address/Data Bus, I/O, Pins 88-92, 95-97, 2-6, 9-11, 28-29, 32-37, 41-48

These pins form the multiple xed address / data bus for th e PCI interface.

C/BE[3:0]# - Command Type / Byte Enables, I/O, Pins 98, 14, 27, 38

These four pins are the multiplexed command / byte enables for the PCI interface. During the

address phase of a transaction, these pins indicate cycle type. During the data phases of a

transaction, active low byte enable information for the current data phase is indicated. These

pins are inputs during slave op eration an d they are outputs during bus mastering operatio n.

PAR - Parity, I/O, Pin 26

The Parity pin indicates even parity across AD[31:0] and C_BE[3:0] for both address and data

phases. The signal is delayed one PCI clock from either the address or data phase for which

parity is generated.

FRAME# - Cycle Frame, I/O, Pin 15

FRAME# is driven by the current PCI bus master to indicate the beginning and duration of a

transaction.

IRDY# - Initiator Ready, I/O, Pin 16

IRDY# is driven by the current PCI bus master to indicate that as the initiator it is ready to

transmit or receive da ta (complete the current data phase).

TRDY# - Target Ready, I/O, Pin 17

TRDY# is driven by the current PCI bus target to indicate that as the target device it is ready to

transmit or receive da ta (complete the current data phase).

STOP# - Transition Stop, I/O, Pin 23

STOP# is driven active by the current PCI bus target to indicate a request to the master to stop

the current transaction.

IDSEL - Initialize Device Select, Input, Pin 99

IDSEL is used as a chip select during PCI configuration read and write cycles.

DEVSEL# - Device Select, I/O, Pin 20

DEVSEL# is driven by the PCI bus target device to indicate that it has decoded the address of

the current tr ansaction as its own chip select range.

20 CIRRUS LOGIC PRELIMINARY PRODUCT BULLETIN JUNE 30, 5:03 PM DS292PP3

CS4614

CrystalC le ar™ SoundFusion™ PCI Audio Acce le rat or

REQ# - Master Request, Three-State Output, Pin 85

REQ# indicates to the system arbiter that this device is requesting access to the PCI bus. This

pin is high-imp edance when RST# is active.

GNT# - Master Grant, Input, Pin 84

GNT# is driven by the system arbiter to indicate to the device that the PCI bus has been

granted.

PERR# - Pari ty Error, I/O, Pin 24

PERR# is used for re porting data parity errors on the PCI bus.

SERR# - System Error, Open Drain Output, Pin 25

SERR# is used for re porting addr ess parity errors and othe r catastrophic system errors.

INTA# - Host Interrupt A (for SP), Open Drain Output, Pin 81

INTA# is the level triggered interrupt pin dedicated to servicing internal device interrupt

sources.

PCICLK - PCI Bus Clock, Input, Pin 83

PCICLK is the PCI bus clock for timing all PCI transactions. All PCI synchronous signals are

generated and samp led relative to the rising edge of this clock.

RST# - PCI Device Reset, Pin 82

RST# is the PCI bus master reset.

VDD5REF: Clean 5 V Power Supply, Pin 73

VDD5REF is the power connection pin for the 5 V PCI pseudo supply for the PCI bus drivers.

The internal core logic runs on 3.3 Volts. This pin enables the PCI interface to support and be

tolerant of 5 Volt signals. Must be connected to +5 Volts.

PCIVDD[7:0] - PCI Bus Driver Power Supply, Pins 50, 39, 31, 21, 8, 100, 94, 86

PCIVDD pins are the PCI driver power supply pins. These pins must have a nominal

+3.3 Volts.

PCIGND[7:0] - PCI Bus Driver Ground Pins, Pins 49, 40, 30, 22, 7, 1, 93, 87

PCIGND pins are the PCI driver ground reference pins.

DS292PP3 CIRRUS LOGIC PRELIMINARY PRODUCT BULLETIN JUNE 30, 5:03 PM 21

CS4614

CrystalClear™ SoundFusion™ PCI Audio Accelerator

External Interface Pins

TEST - Test Mode Strap, Input, Pin 51

This pin is sampled at reset for test mode entry. If it is high at reset, test mode is enabled. This

pin must be pul led to ground for normal op eration.

EEDAT/PCGNT# - EEPROM Data Line / PC/PCI Grant, I/O, Pin 80

For expansion card designs, this is the data line for external serial EEPROM containing device

configuration data. When used with an external EEPROM, a 4.7 kΩ pullup resistor is required.

In motherboard designs using PC/PCI, this pin is the PC/PCI serialized grant input. In designs

with neither of the above requirements, this pin can be used as a general purpose input or open

drain output (GPIO2).

EECLK/PCREQ# - EEPROM Clock Line / PC/PCI Request, Output, Pin 79

For expansion card designs, this is the clock line for external serial EEPROM containing device

configuration data. In motherboard designs using PC/PCI, this pin is the PC/PCI serialized

request output. In designs with neither of the above requirements, this pin can be used as a

general purpose output pin (GPOUT).

SDIN2/GPIO - Serial Data Input 2 / General Purpose I/O Pin, I/O, Pin 66

This dual function pin defaults as a general purpose I/O pin. In non-AC ’97 system

configurations, this pin can function as a second stereo dig ital data input pin if enable d.

VOLUP/XTALI - Volume-Up Button / Crystal In, Input, Pin 70

This d ual function pin is either the volume-up button control in put or the crystal oscillator input

pin, depending on system configuration. This pin may also be used as a general purpose input

if its primary function is not ne eded.

VOLDN/XTALO - Volume-Down Button / Crystal Output, I/O, Pin 71

This dual function pin is either the volume-down button control input or the crystal oscillator

output pin, depending on system configuration. This pin may also be used as a general purpose

input if its primary function is not needed .

22 CIRRUS LOGIC PRELIMINARY PRODUCT BULLETIN JUNE 30, 5:03 PM DS292PP3

CS4614

CrystalC le ar™ SoundFusion™ PCI Audio Acce le rat or

Cloc k / Misc ellaneous

CRYVDD - Crystal & PLL Power Supply, Pin 69

Power pin for crystal oscillator and internal phase locked loop. This pin must be connected to a

nominal +3.3 Volts.

CRYGND - Crystal & PLL Ground Supply, Pin 72

Ground pin for crystal oscillator and internal phase locked lo op.

JACX, JACY, JBCX, JBCY - Joystick A and B X/Y Coordinates, I/O, Pins 52, 53, 54, 55

These pins are the 4 axis coordinates for the joystick port. These pins may also be used as a

general purpose inputs or open drain outputs if their primary function is no t needed.

JAB1/S DO2 - Joystick A Button 1 / Serial Data Output 2, I/O, Pin 56

This dual function pin defaults as JAB1 (button 1 input for joystick A). In non-AC ’97 system

configurations, this pin can function as a second stereo digital data output pin if enabled. This

pin can also be a general purpo se polled input if a secon d data outp ut stream is not required.

JAB2/S DO3 - Joystick A Button 2 / Serial Data Output 3, I/O, Pin 57

This dual function pin defaults as JAB2 (button 2 input for joystick A). In non-AC ’97 system

configurations, this pin can function as a third stereo digital data output pin if enabled. This pin

can also be a general purpose polled input if a th ird data output stream is not required.

JBB1/LRCLK - Joystick B Button 1 / L/R Framing Clock, I/O, Pin 58

This dual function pin defaults as JBB1 (button 1 input for joystick B). In non-AC ’97 system

configurations, this pin can function as a left/right framing clock output pin for SDO2 and

SDO3. This pin can also be used as a general purpose polled input if alternate data output

streams are not required.

JBB2/MCLK - Joystick B Button 2 / Master Clock, I/O, Pin 59

This dual function pin defaults as JBB2 (button 2 input for joystick B). In non-AC ’97 system

configurations, this pin can function as a master (256x sample rate) output clock if enabled.

This pin can also be used as a general purpose polled input if alternate data output streams are

not required.

MIDIIN - MIDI Data Input, Pin 60

This is the serial inp ut pin for the internal MIDI port.

MIDIOUT - MIDI Data Output, Pin 63

This is the serial output pin for the internal MIDI port.

CVDD[4:0] - Core Power Supply, Pins 68, 64, 61, 12, 19

Core / Stream Processor power pins. These pins must be connected to a no minal +3.3 Volts.

DS292PP3 CIRRUS LOGIC PRELIMINARY PRODUCT BULLETIN JUNE 30, 5:03 PM 23

CS4614

CrystalClear™ SoundFusion™ PCI Audio Accelerator

CGND[4:0] - Core Ground Supply, Pins 67, 65, 62, 13, 18

Core / Stream Processor ground reference pins.

Serial Codec Int erf ace

ABITCLK/SCLK - AC ‘97 Bit Clock / Serial Audio Data Clock, I/O, Pin 74

Master timing clock for serial audio data. In AC ’97 configurations, this pin is an input which

drives the timing for the AC ’97 interface, along with providing the source clock for the

CS4614 . In ex ternal DAC configu rations, it an output, providing the serial bit clock.

ASYNC/FSYNC - AC ‘97 Frame Sync / Serial Audio Frame Sync, I/O, Pin 77

Framing clock for serial audio data. In AC ’97 configurations, this pin is an output which

indicates the framing for the AC ’97 link. In external DAC configurations, this pin is an

FSYNC output, providing the left/right framing clock.

ASDOUT/SDOUT - AC ‘97 Data Out / Serial Audio Data Out, Output, Pin 75

AC ‘97 serial data out / Serial audio output data.

ARST# - AC ‘97 Reset, Output, Pin 78

AC ’97 link reset pin. This pin also functions as a general purpose reset output in non-AC ’97

configurations an d will follow RST# to ground , but must be forced high by software.

ASDIN/SDIN - AC ‘97 Data In / Serial Audio Data In, Input, Pin 76

Serial audio input data.

24 CIRRUS LOGIC PRELIMINARY PRODUCT BULLETIN JUNE 30, 5:03 PM DS292PP3

CS4614

CrystalC le ar™ SoundFusion™ PCI Audio Acce le rat or

PACKAGE OUTLINE

‘M’ Package 100 -pi n MQ FP

∝

INCHES MILLIMETERS

DIM MIN MAX MIN MAX

A 0.000 0.134 0.000 3.400

A1 0.010 0.014 0.250 0.350

B 0.009 0.015 0.220 0.380

D 0.667 0.687 16.950 17.450

D1 0.547 0.555 13.900 14.100

E 0.904 0.923 22.950 23.450

E1 0.783 0.791 19.900 20.100

e 0.022 0.030 0.550 0.750

∝0.000 7.000 0.000 7.00

L 0.018 0.030 0.450 0.750