User's GuideSLAU193 – October 2006
TAS5518-5261K2EVM
This user's guide describes the operation of the evaluation module for the TAS5518Digital Audio PWM Processor and the TAS5261 Digital Amplifier Power Output Stagefrom Texas Instruments.
Contents1 Overview ............................................................................................. 22 Quick Setup Guide ................................................................................. 33 System Interfaces .................................................................................. 54 Protection ............................................................................................ 95 Related Documentation from Texas Instruments ............................................. 10
List of Figures
1 Integrated PurePath Digital™ Amplifier System ................................................ 22 Physical Structure for the TAS5518-5261K2EVM (Approximate Layout) ................... 33 TAS5518 GUI Window ............................................................................. 54 Recommended Power-Up Sequence ............................................................ 65 J901 and J900 Pin Numbers ...................................................................... 66 J902 Pin Numbers .................................................................................. 77 J100 and J200 Pin Numbers ...................................................................... 7
List of Tables
1 Recommended Supply Voltages ................................................................. 42 Recommended Supply Voltages ................................................................. 63 J901 Pin Description ............................................................................... 64 J900 Pin Description ............................................................................... 65 J900 Pin Description ............................................................................... 76 J100 and J200 Pin Description ................................................................... 77 J40 Pin Description ................................................................................. 88 J60 Pin Description ................................................................................. 99 TAS5621 Warning/Error Signal Decoding ..................................................... 1010 Related Documentation From Texas Instruments ............................................ 10
PurePath Digital, Equibit are trademarks of Texas Instruments.Windows is a trademark of Microsoft Corporation.
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1 Overview
1.1 TAS5518-5261K2EVM Features
I2S
Bus
TAS5518-526K2EVM
MODULE
I2CBus
Example
TIInput -USB
board
8-Channel
Analog
Input
USB
Interface
Optical
and
Coaxial
S/PDIFInput
ControlInterface
PowerSupply
2-Channel
SpeakerOutput
Overview
The TAS5518-5261K2EVM PurePath Digital™ customer evaluation amplifier module demonstrates thetwo audio integrated circuits TAS5518 and TAS5261 from Texas Instruments (TI).
TAS5518PAG is a high-performance, 32-bit (24-bit input) multichannel PurePath Digital™ pulse widthmodulator (PWM) based on Equibit™ technology with fully symmetrical AD modulation scheme. It acceptsinput sample rates from 32 kHz to 192 kHz. The device also has digital audio processing (DAP) thatprovides 48-bit signal processing, advanced performance, and a high level of system integration. Thedevice has interfaces for headphone output and power supply volume control (PSVC).
The TAS5261 is a high-performance, integrated mono digital amplifier power stage designed to drive 4- Ωto 8- Ωspeakers with low harmonic distortion. This system requires only a simple, passive demodulationfilter to deliver high-quality, high-efficiency audio amplification.
This EVM, together with a TI input-USB board, is a complete 2-channel stereo digital audio amplifiersystem which includes digital input (S/PDIF), analog inputs, interface to PC, and DAP features like digitalvolume control, input and output mixers, automute, tone controls, loudness, EQ filters, and dynamic rangecompression (DRC). Configuration options include power-stage failure protection and a mini-jackconnector for headphone.
This stereo system is designed for home theater applications such as A/V receivers.
•Two-channel PurePath Digital™ evaluation module.•Self-contained protection system (short circuit and thermal).•Standard I
2
S and I
2
C/control connector for TI input board•Double-sided plated-through PCB layout.
Figure 1. Integrated PurePath Digital™ Amplifier System
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1.2 PCB Key Map
TAS5518
OUTPUT STAGE
CHANNEL 1
5
V
Regulator
GateDrive
Regulator
PSU
INTERFACE
(J901)
PSU
CONTROL
(J902)
INPUT SIGNAL
INTERFACE (J60)
CONTROL
INTERFACE (J40)
J101
J102
PSU
INTERFACE
(J900)
OUTPUT STAGE
CHANNEL 2
2 Quick Setup Guide
2.1 Electrostatic Discharge Warning
Quick Setup Guide
Physical structure for the TAS5518-5261K2EVM is illustrated in Figure 2 .
Figure 2. Physical Structure for the TAS5518-5261K2EVM (Approximate Layout)
This section describes the TAS5518-5261K2EVM board in regards to power supplies and systeminterfaces. The section provides information regarding handling and unpacking, absolute operatingconditions, and a description of the factory default switch and jumper configuration.
This section provides a step-by-step guide to configuring the TAS5518-5261K2EVM for device evaluation.
Many of the components on the TAS5518-5261K2EVM are susceptible to damage by electrostaticdischarge (ESD). Customers are advised to observe proper ESD handling precautions when unpackingand handling the EVM, including the use of a grounded wrist strap at an approved ESD workstation.
CAUTION
Failure to observe ESD handling procedures can result in damage to EVMcomponents.
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2.2 Unpacking the EVM
2.3 Power Supply Setup
2.4 GUI Software Installation
Quick Setup Guide
On opening the TAS5518-5261K2EVM package, ensure that the following items are included:•1 pc. TAS5518-5261K2EVM board using one TAS5518PAG and two TAS5261DKD.•1 pc. TI Input-USB board for interfacing TAS5518-5261K2EVM w. SPDIF/analog sources and PC forcontrol.
•1 pc. Signal Interface IDC cable for connection to a I2S front-end like the attached TI Input-USB board.•1 pc. Control Interface IDC cable for connection to a I2C front-end like the attached TI Input-USBboard.
•1 pc Cable for connecting Input-USB board to a USB port on a PC for TAS5518 control by software.•1 pc. Power supply cable for two regulated power supplies (H-bridge and system supply).•1 pc. Power supply cable for one regulated power supply (H-bridge supply).•2 pc. Cables for speaker connection.•1 pc. PurePath Digital™ CD-ROM:
If any of these items is missing, contact the Texas Instruments Product Information Center nearest you toinquire about a replacement.
Connect Input-USB board to TAS5518-5261K2EVM using the two delivered IDC cables.
To power up the EVM, two power supplies are needed: one for system power, logic and gate drive, andone for output stage supply. Power supplies are connected to the EVM using delivered power cablered/black, white/black.
Table 1. Recommended Supply Voltages
Description Voltage Limitations Current Requirement Cable
System power supply 15–20 V 0.3 A Red/blackOutput stage power supply 0–50 V 5 A (10-A peak) White/black
CAUTION
Applying voltage above the limitations given in Table 1 can cause permanentdamage to your hardware.
The TAS5518 GUI provide easy control of all registers in TAS5518. To install the GUI, run the setup filefrom the PurePath Digital™ CD-ROM.
After installation, turn on the power supplies and connect the USB cable to the Input-USB board.
Start the GUI program from the Windows™ menu. The start-up of the GUI takes a few seconds.
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3 System Interfaces
3.1 Power Supply (PSU) Interface (J901 and J900)
System Interfaces
Figure 3. TAS5518 GUI Window
From the files menu, load the configuration file:
TAS5518-5261K2EVM Configuration (2.00).CFG
The file is located on the PurePath Digital™ CD-ROM. This file contains all settings for a default setup ofthe EVM.
For easy access of the file, it is recommended to copy the files into the directory where the GUI isinstalled. Default is C:\Program Files\Texas Instruments Inc\TAS5518\
For more advanced use of the GUI, see the GUI user’s guide and data sheet for the TAS5518.
This section describes the TAS5518-5261K2EVM board in regards to power supplies and systeminterfaces.
The TAS5518-5261K2EVM module must be powered from external power supplies. High-end audioperformance requires a stabilized power supply with low ripple voltage and low output impedance.
Note: The length of power supply cable must be minimized. Increasing the length of the PSUcable is equal to increasing the distortion for the amplifier at high output levels and lowfrequencies.
Maximum output stage supply voltage depends on the speaker load resistance. Check the recommendedmaximum supply voltage in the TAS5261 data sheet.
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Outputstagepowersupply
RESET
>1ms
Systempowersupply
4
1
2
3
System Interfaces
Table 2. Recommended Supply Voltages
Description Voltage Limitations Current Recommendations(4- ΩLoad)
System power supply 15–20 V 0.3 AOutput stage power supply 0–50 V 5 A (10-A peak)
(1)
(1)
The rated current corresponds to a 2-channel full scale (125 W each), which most likely is adequate for a standard 2-channelamplifier design. For 2-channel, continuously running 125 W at 500 Hz or below the peak current requirement is double – 10 A.
The recommended TAS5261 power-up sequence is shown in Figure 4 . For proper TAS5261 operation,the RESET signal should be kept low during power up. RESET is pulled low during power up for 200 msby the onboard reset generator (U904).
Figure 4. Recommended Power-Up Sequence
Figure 5. J901 and J900 Pin Numbers
Table 3. J901 Pin Description
Pin Net-Name on Schematics Description
1 PVDD Output stage power supply2 SYSTEM System Power Supply3 GND Ground4 GND Ground
Table 4. J900 Pin Description
Pin Net-Name on Schematics Description
1 PVDD Extra Output stage power supply2 PVDD Extra Output stage power supply3 GND Extra Ground4 GND Extra Ground
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3.2 PSU Control Interface (J902)
1
2
3
5
4
3.3 Loudspeaker Connectors (J100 and J200)
1
2
System Interfaces
This interface is used for onboard sensing of output supply voltage and for the power supply volumecontrol (PSVC) signal.
Figure 6. J902 Pin Numbers
Table 5. J900 Pin Description
Pin Net-Name on Schematics Description
1 – Reserved for future use2 PVDD Sense of output power supply3 GND Ground4 RESET System reset (bi-directional)5 PSVC Power Supply Volume Control Signal
CAUTION
Both positive and negative speaker outputs are floating and may not beconnected to ground (e.g., through an oscilloscope).
Figure 7. J100 and J200 Pin Numbers
Table 6. J100 and J200 Pin Description
Pin Net-Name on Schematics Description
1 OUT-1 Speaker negative output2 OUT-2 Speaker positive output
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3.4 Control Interface (J40)
System Interfaces
This interface connects the TAS5518-5261K2EVM board to a TI input-USB board.
Table 7. J40 Pin Description
Pin Net-Name on Schematics Description
1 GND Ground2 RESERVED —3 GND Ground4 RESET System reset (bi-directional). Activate MUTE before RESET for quiet reset5 RESERVED —6 MUTE Ramp volume from any setting to noiseless soft mute. Mute can also beactivated by I2C7 RESERVED —8 RESERVED —9 RESERVED —10 SDA I2C data clock11 GND Ground12 SCL I2C bit clock13 RESERVED —14 RESERVED —15 RESERVED —16 RESERVED —17 GND Ground18 RESERVED —19 RESERVED —20 SD Shutdown reporting. Activated if one or more TAS5261 has high currentor high temperature. See section 3: Protection21 RESERVED —22 OTW Temperature warning. Activated if one or more TAS5261 has reachedtemperature warning level23 RESERVED —24 RESERVED —25 GND Ground26 GND Ground27 RESERVED —28 RESERVED —29 RESERVED —30 RESERVED —31 GND Ground32 GND Ground33 +5V +5-Vdc power supply (output)34 +5V +5-Vdc power supply (output)
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3.5 Digital Audio Interface (J60)
4 Protection
4.1 Short-Circuit Protection and Fault-Reporting Circuitry
4.2 Fault Reporting
4.2.1 Overcurrent Protection (OCP)
Protection
The digital audio interface contains digital audio signal data (I2S), clocks etc. See the TAS5518 data sheet(SLES115 ) for signal timing and details not explained in this document.
Table 8. J60 Pin Description
Pin Net-Name on Schematics Description
1 GND Ground2 MCLK Master Clock input. Low jitter system clock for PWM generation andreclocking. Ground connection from source to TAS5518 must be alow-impedance connect3 GND Ground4 SDIN1 I2S Data 1, Channel 1 and 25 SDIN2 I2S Data 2, Channel 3 and 46 SDIN3 I2S Data 3, Channel 5 and 67 SDIN4 I2S Data 4, Channel 7 and 88 — Reserved9 — Reserved10 GND Ground11 SCLK I2S bit clock12 GND Ground13 LRCLK I2S left-right clock14 GND Ground15 — Reserved16 GND Ground
This section describes the short-circuit protection and fault-reporting circuitry of the TAS5261 device.
Overcurrent, overtemperature, and undervoltage protections are built into the TAS5261 device,safeguarding the H-bridge and speakers against output short-circuit conditions, overtemperatureconditions, and other fault conditions that could damage the system.
To protect the power stage from damage due to high currents, a VDS sensing system is implemented inthe TAS5261 device. Based on RDS(on) of the power MOSFETs and the maximum allowed current in theMOSFET, a voltage threshold can be calculated which, when exceeded, triggers the protection. Thedetector outputs are monitored closely by two protection systems. The first protection system controls thepower stage in order to prevent the output current from further increasing For instance, it performs acurrent-limiting function rather than prematurely shutting down during combinations of high-level musictransients and extreme speaker load impedance drops. If the high-current situation persists, i.e., the powerstage is being overloaded, a second protection system triggers a latching shutdown, resulting in the powerstage being set in the high-impedance (Hi-Z) state.
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4.2.2 Overtemperature Protection (OTP)
5 Related Documentation from Texas Instruments
5.1 Additional Documentation
Related Documentation from Texas Instruments
TAS5261 has an on-chip temperature-sensing system. If the chip temperature reaches a criticaltemperature, the overtemperature warning pin goes low. If the chip temperature continue to increase, theTAS5261 protects itself by shutting down the power stage. In this case, both OTW and SD are low.
The shutdown signals together with the temperature warning signal give chip-state information asdescribed in Table 9 . Device fault-reporting outputs are open-drain outputs.
The OTW and SD outputs from TAS5261 indicate fault conditions. See the TAS5261 data sheet for adescription of these pins.
Table 9. TAS5621 Warning/Error Signal Decoding
OTW SD Device Condition
0 0 High-temperature error and/or high-current error0 1 High-temperature warning1 0 Undervoltage lockout or high-current error1 1 Normal operation, no errors/warnings
The temperature warning signals at the TAS5518-5621K2EVM board are wired-OR to one temperaturewarning signal ( OTW– pin 22 in control interface connector). Shutdown signals are wired-OR into oneshutdown signal ( SD– pin 20 in control interface connector).
The shutdown signals together with the temperature warning signal give chip-state information asdescribed in Table 9 . Device fault-reporting outputs are open-drain outputs.
The following table contains a list of documents that have detailed descriptions of the integrated circuitsused in the design of the TAS5518-5261K2EVM. These documents can be obtained at the TI Web sitehttp://www.ti.com .
Table 10. Related Documentation From TexasInstruments
Part Number Literature Number
TAS5518 SLES115TAS5261 SLES188UA78M12 SLVS059TPS79133 SLVS325TPS3825-33 SLVS165TPS62112 SLVS585
•TAS5518-5261K2EVM Application Report (SLAA332 )•PC Configuration Tool for TAS5518 (TAS5518 GUI ver. 4.0 or later)
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EVALUATION BOARD/KIT IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATIONPURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling theproduct(s) must have electronics training and observe good engineering practice standards. As such, the goods being provided arenot intended to be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations,including product safety and environmental measures typically found in end products that incorporate such semiconductorcomponents or circuit boards. This evaluation board/kit does not fall within the scope of the European Union directives regardingelectromagnetic compatibility, restricted substances (RoHS), recycling (WEEE), FCC, CE or UL, and therefore may not meet thetechnical requirements of these directives or other related directives.Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BYSELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDINGANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from allclaims arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility totake any and all appropriate precautions with regard to electrostatic discharge.EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHERFOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or infringement ofpatents or services described herein.
Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide prior to handling theproduct. This notice contains important safety information about temperatures and voltages. For additional information on TI’senvironmental and/or safety programs, please contact the TI application engineer or visit www.ti.com/esh .No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, orcombination in which such TI products or services might be or are used.
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This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATIONPURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. It generates, uses, andcan radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of thisequipment in other environments may cause interference with radio communications, in which case the user at his own expensewill be required to take whatever measures may be required to correct this interference.
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of 0 V to 50 V for the output stage and 15 V to 20 V for thesystem supply and the output voltage range of 0 V to 50 V.Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there arequestions concerning the input range, please contact a TI field representative prior to connecting the input power.Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to theEVM. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the loadspecification, please contact a TI field representative.During normal operation, some circuit components may have case temperatures greater than 75 °C. The EVM is designed tooperate properly with certain components above 75 °C as long as the input and output ranges are maintained. These componentsinclude but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types ofdevices can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes nearthese devices during operation, please be aware that these devices may be very warm to the touch.
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