NX3P191UK - NXP - Product.Network

1. General description

The NX3P191 is a high-side load switch which features a low ON resistance P-channel

MOSFET with input inrush current reduction that support s more than 500 mA of

continuous current and an integrated output discharge resistor to discharge the output

capacit ance when disabled. Designe d for operation from 1.1 V to 3.6 V, it is used in power

domain isolation applications to reduce power dissipation and extend battery life. The

enable logic includes integrated logic level translation making the device compatible with

lower voltage processors and controllers. The NX3P191 is ideal for portable, battery

operated applications due to low ground current and ultra-low shutdown current.

2. Features and benefits

Wide supply voltage range from 1.1 V to 3.6 V

Very low ON resistance:

95 m (typical) at a supply voltage of 1.8 V

High noise immunity

Low-power mode when EN is LOW

Low ground current (2 A maximum)

1.2 V control logic at a supply voltage of 3.6 V

High current handling capability (500 mA continuous current)

Internal output discharge resistor

Turn-on slew rate limiting

ESD protection:

HBM JESD22-A114F Class 3A exceeds 4000 V

CDM AEC-Q100-011 revision B exceeds 500 V

Specified from 40 C to +85 C

3. Applications

Cell phone

Digital cameras and audio de vice s

Portable and battery-powered equipment

NX3P191

Logic controlled high-side power switch

Rev. 2 — 4 November 2011 Product data sheet

Product data sheet Rev. 2 — 4 November 2011 2 of 15

NXP Semiconductors NX3P191

Logic controlled high-side power switch

4. Ordering information

5. Marking

6. Functional diagram

7. Pinning information

7.1 Pinning

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

NX3P191UK 40 C to +85 C WLCSP4 wafer level chip-size package; 4 bumps; body

0.76  0.76  0.51 mm. (Backside Coating

included)

NX3P190/NX3P191

Table 2. Marking codes

Type number Marking code

NX3P191UK x1

Fig 1. Logic symbol Fig 2. Logic diagram (simp lified schematic )

001aao342

VIN VOUT

aaa-000036

LEVEL SHIFT,

SLEW RATE CONTROL

AND LOAD DISCHARGE

Rpd

Rdch

VIN VOUT

Fig 3. Pin configuration for WLCSP4 Fig 4. Ball mapping for WLCSP4

bump A1

index area

aaa-000037

Transparent top view

NX3P191

VIN VOUT

EN GND

001aao345

Transparent top view

Product data sheet Rev. 2 — 4 November 2011 3 of 15

NXP Semiconductors NX3P191

Logic controlled high-side power switch

7.2 Pin description

8. Functional description

[1] H = HIGH voltage level; L = LOW voltage level.

9. Limiting values

[1] The minimum input voltage rating may be exceeded if the input current rating is observed.

[2] The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed.

[3] The (absolute) maximum power dissipation depends on the junction temperature Tj. Higher power dissipation is allowed in conjunction

with lower ambient temperatures. The conditions to determine the specified values are Tamb = 85 °C and the use of a two layer PCB.

Table 3. Pin description

Symbol Pin Description

VIN A1 input voltage

EN B1 enable input (active HIGH)

VOUT A2 output voltage

GND B2 ground (0 V)

Table 4. Function table[1]

Input EN Switch

L switch OFF

H switch ON

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VIinput voltage input EN [1] 0.5 +4.0 V

input VIN [2] 0.5 +4.0 V

VSW switch voltage output VOUT [2] 0.5 VI(VIN) V

IIK input clamping current input EN: VI(EN) <0.5 V 50 - mA

ISK switch clamping current in put VIN: VI(VIN) <0.5 V 50 - mA

output VOUT: VO(VOUT) <0.5 V 50 - mA

output VOUT: VO(VOUT) >V

I(VIN) 0.5 V - 50 mA

ISW switch current VSW >0.5 V

Tamb = 25 °C - 1000 mA

Tamb = 85 °C - 500 mA

Tj(max) maximum junction

temperature 40 +125 C

Tstg storage temperature 65 +150 C

Ptot total power dissipation [3] -300mW

Product data sheet Rev. 2 — 4 November 2011 4 of 15

NXP Semiconductors NX3P191

Logic controlled high-side power switch

10. Recommended operating conditions

11. Thermal characteristics

[1] The overall Rth(j-a) can vary depending on the board layout. To minimize the effective Rth(j-a), all pins must have a solid connection to

larger Cu layer areas e.g. to the power and ground layer. In multi-layer PCB applications, the second layer should be used to create a

large heat spreader area right below the device. If this layer is either ground or power , it should be connected with several vias to the top

layer connecting to the device ground or supply.Try not to use any solder-stop varnish under the chip.

[2] Please rely on the measurement data given for a rough estimation of the Rth(j-a) in your application. The actual Rth(j-a) value may vary

in applications using different layer stacks and layouts

12. Static characteristics

Table 6. Recommended operating con ditions

Symbol Parameter Conditions Min Max Unit

VIinput voltage 1.1 3.6 V

Tamb ambient temperature 40 +85 C

Table 7. Thermal characteristics

Symbol Parameter Conditions Typ Unit

Rth(j-a) thermal resistance from junction to ambient [1][2] 130 K/W

Table 8. Static characteristics

VI(VIN) = VI(EN) , unless otherwise specified; Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Tamb = 25 C Tamb = 40 C to +85 CUnit

Min Typ Max Min Max

VIH HIGH-level input

voltage EN input

VI(VIN) = 1.1 V to 1.3 V - - - 1.0 - V

VI(VIN) = 1.3 V to 1.8 V - - - 1.2 - V

VI(VIN) = 1.8 V to 3.6 V - - - 1.2 - V

VIL LOW-level input

voltage EN input

VI(VIN) = 1.1 V to 1.3 V - - - - 0.3 V

VI(VIN) = 1.3 V to 1.8 V - - - - 0.4 V

VI(VIN) = 1.8 V to 3.6 V - - - - 0.45 V

Rpd pull-down resistance EN input - 4 - - - M

IGND ground curre nt VI(VIN) = 3.6 V; VOUTopen;

see Figure 5 and Figure 6 --- 2-A

IOFF power-off leakage

current VI(VIN) =3.6V; V

I(EN) =GND;

VO(VOUT) = GND; see Figure 8 -0.1- - 2 A

Rdch discharge resistance VOUT output - 280 - - - 

Product data sheet Rev. 2 — 4 November 2011 5 of 15

NXP Semiconductors NX3P191

Logic controlled high-side power switch

12.1 Graphs

VI(VIN) = 1.8 V; VI(EN) = 1.8 V; ILOAD = 500 mA. VI(EN) = VI(VIN); Tamb = 25 C; ILOAD = 500mA.

Fig 5. Waveform showing the groun d cu rre nt v ers us

temperature Fig 6. Waveform showing the ground current versus

input voltage on pin VIN

Tamb (°C)

-40 1108020 50-10

001aao346

0.9

IGND

(μA)

0.7

0.5

0.3

0.2

0.4

0.6

0.8

VI(VIN) (V)

1.2 3.23.22.2 2.71.7

001aao347

0.6

0.4

0.8

1.0

IGND

(μA)

0.2

Fig 7. Waveform showing th e additional ground current versus input voltage

VI(EN) (V)

04312

001aao348

IGND

(μA)

VI(VIN) = 3.6 V

VI(VIN) = 1.8 V

Product data sheet Rev. 2 — 4 November 2011 6 of 15

NXP Semiconductors NX3P191

Logic controlled high-side power switch

12.2 ON resistance

VI(EN) = GND.

(1) VI(VIN) = 3.6 V.

(2) VI(VIN) = 2.5 V.

(3) VI(VIN) = 1.8 V.

(4) VI(VIN) = 1.2 V.

Fig 8. Waveforms showing the power-off leakage current versus temperature

001aao349

0.7

IOFF

(μA)

0.1

0.2

0.3

0.4

0.5

0.6

Tamb (°C)

-40 0 40 80 1006020-20

(1)

(2)

(3)

(4)

Table 9. ON resistan ce

At recommended operating conditions; voltages are referenced to GND (ground = 0 V)

Symbol Parameter Conditions Tamb = 25 CUnit

Min Typ Max

RON ON resistance VI(EN) =1.5V; I

LOAD =200mA;

see Figure 9, Figure 10 and Figure 11

VI(VIN) =1.2V - 150 - m

VI(VIN) =1.5V - 110 - m

VI(VIN) = 1.8 V - 95 130 m

VI(VIN) =2.5V - 75 - m

VI(VIN) =3.6V - 65 - m

Product data sheet Rev. 2 — 4 November 2011 7 of 15

NXP Semiconductors NX3P191

Logic controlled high-side power switch

12.3 ON resistance test circuit and waveforms

RON = VSW / ILOAD.

Fig 9. Test circuit for measuring ON resistance

001aao350

VIN VOUT

GND

ILOAD

ILOAD = 100 mA.

(1) VI(VIN) = 1.2 V.

(2) VI(VIN) = 1.8 V.

(3) VI(VIN) = 3.6 V.

VI(EN) = VI(VIN); Tamb = 25 C.

(1) ILOAD = 10 mA.

(2) ILOAD = 100 mA.

(3) ILOAD = 250 mA.

(4) ILOAD = 350 mA.

(5) ILOAD = 500 mA.

Fig 10. Waveform showing the ON resistance versus

temperature Fig 11. Waveform showing the ON resistance versus

input voltage

Tamb (°C)

-40 1108020 50-10

001aao351

120

160

200

RON

(mΩ)

(1)

(2)

(3)

001aao352

VI(VIN) (V)

1.2 3.62.82.0

120

160

200

RON

(mΩ)

(1)

(2)

(3)

(4)

(5)

Product data sheet Rev. 2 — 4 November 2011 8 of 15

NXP Semiconductors NX3P191

Logic controlled high-side power switch

13. Dynamic characteristics

[1] ten is the same as tPZH.

13.1 Waveform and test circuits

Table 10. Dynam ic characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.

Symbol Parameter Conditions Tamb = 25 CUnit

Min Typ Max

ten enable time EN to VOUT; see Figure 12 [1]

VI(VIN) =1.8V - 80 - s

VI(VIN) =3.6V - 40 - s

Measurement points are given in Table 11.

Logic level: VOH is the typical output voltage that occurs with the output load.

Fig 12. Switching times

001aao353

EN input

VOUT output

tPHZ

GND

VOH

GND

tPZH

Table 11. Measurement points

Supply voltage EN Input Output

VI(VIN) VMVXVY

1.1 V to 3.6 V 0.5  VI(EN) 0.1  VOH 0.9  VOH

Product data sheet Rev. 2 — 4 November 2011 9 of 15

NXP Semiconductors NX3P191

Logic controlled high-side power switch

Test data is given in Table 12.

Definitions test circuit:

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

VEXT = External voltage for measuring switching times.

Fig 13. Test circuit for measuring switching times

001aao354

VOUT VIN

VIILOAD VEXT

GCL

Table 12. Test data

Supply voltage Input Load

VEXT VI(EN) CLILOAD

1.1 V to 3.6 V 1.5 V 1 F 200 mA

VI(VIN) = 1.8 V; VI(EN) = 1.8 V; CL = 1 F; ILOAD = 200 mA. VI(VIN) = 3.6 V; VI(EN) = 1.8 V; CL = 1.0 F;

ILOAD =200mA.

Fig 14. Waveform showing the enable time versus

inrush current Fig 15. Waveform showing the enable time versus

inrush current

aaa-000038

aaa-000039

Product data sheet Rev. 2 — 4 November 2011 10 of 15

NXP Semiconductors NX3P191

Logic controlled high-side power switch

VI(VIN) = 1.8 V; VI(EN) = 1.8 V. VI(VIN) = 3.6 V; VI(EN) = 3.6 V.

Fig 16. Waveform showing the disable time Fig 17. Waveform showing the disable time

aaa-000040

aaa-000041

Product data sheet Rev. 2 — 4 November 2011 11 of 15

NXP Semiconductors NX3P191

Logic controlled high-side power switch

14. Package outline

Fig 18. Package outline WLCSP4 (NX3P190/NX3P191)

References

Outline

version

European

projection Issue date

IEC JEDEC JEITA

NX3P190/NX3P191

nx3p190_191_po

11-05-24

11-06-09

Unit

max

nom

min

0.54 0.22 0.29 0.81 0.81

0.025 0.03

Dimensions

WLCSP4: wafer level chip-size package.

4 bumps; body 0.76 x 0.76 x 0.51 mm. (Backside Coating included) NX3P190/NX3P191

A1A2

0.32

0.51 0.20 0.26 0.76 0.76 0.400.31

bDEe v

0.025

0.48 0.18 0.23 0.71 0.710.30

0 2 mm

scale

detail X

ball A1

index area

ball A1

index area

bAC B

Product data sheet Rev. 2 — 4 November 2011 12 of 15

NXP Semiconductors NX3P191

Logic controlled high-side power switch

15. Abbreviations

16. Revision history

Table 13. Abbreviations

Acronym Description

MOSFET Metal-Oxide Semiconductor Field Effect Transistor

Table 14. Revision history

Document ID Release date Data sheet status Change notice Supersedes

NX3P191 v.2 20111104 Product data sheet - NX3P191 v.1

Modifications: •Legal pages updated.

NX3P191 v.1 20110831 Product data sheet - -

Product data sheet Rev. 2 — 4 November 2011 13 of 15

NXP Semiconductors NX3P191

Logic controlled high-side power switch

17. Legal information

17.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

17.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

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for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

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Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

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Objective [short] data sheet Development This document contains data from the objective specification for product development.

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Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 2 — 4 November 2011 14 of 15

NXP Semiconductors NX3P191

Logic controlled high-side power switch

Non-automotive qualified products — Unless this data sheet expressly

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17.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

18. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors NX3P191

Logic controlled high-side power switch

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 4 November 2011

Document identifier: NX3P191

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

19. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

5 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

6 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2

7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

8 Functional description . . . . . . . . . . . . . . . . . . . 3

9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3

10 Recommended operating conditions. . . . . . . . 4

11 Thermal characteristics . . . . . . . . . . . . . . . . . . 4

12 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4

12.1 Graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

12.2 ON resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 6

12.3 ON resistance test circuit and waveforms . . . . 7

13 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8

13.1 Waveform and test circuits . . . . . . . . . . . . . . . . 8

14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11

15 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 12

16 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12

17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13

17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13

17.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

17.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 13

17.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14

18 Contact information. . . . . . . . . . . . . . . . . . . . . 14

19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15