OUTPUT CURRENT (mA)
EFFICIENCY (%)
100
90
80
70
60
50
40
30
20
10
0
0.1 1 10 100 1000
2.7V
3.6V
2.3V
4.2V
COUT = 4.7 µF, TDK
L = 0.5 µH, FDK
LM8801
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SNVS597H –APRIL 2009–REVISED MAY 2013
LM8801 High Precision 6MHz, 600 mA Synchronous Step-Down DC-DC Converter for
Mobile Applications
Check for Samples: LM8801
1FEATURES APPLICATIONS
2• Over 90% Efficiency at 6 MHz Operation • Mobile Phones
• 600 mA Maximum Load Capability • MP3 players
• 6 MHz PWM Fixed Switching Frequency (typ.) • Wireless LAN
• 27 µA (typ.) Quiescent Current in PFM Mode • PDAs, Pocket PCs
• Wide Input Voltage Range: 2.3V to 5.5V • Portable Hard Disk Drives
• VOUT = 1.0V to 2.9V with 50 mV steps DESCRIPTION
• ±1.5% DC Output Voltage Precision Over The LM8801 step-down DC-DC converter is
Temperature optimized for powering ultra-low voltage circuits from
• Best-in-Class Load Transient Response a single Li-Ion cell and input voltage rails from 2.3V to
• Low Output Ripple in PFM Mode 5.5V. It provides up to 600 mA load current over the
entire input voltage range.
• Automatic PFM/PWM Mode Switching
• Current Overload and Thermal Shutdown The LM8801 has a mode-control pin that allows the
user to select continuous PWM operation over the
Protection complete load range or an auto PFM-PWM mode that
• Internal Soft-Start changes modes automatically depending on the load.
• 6-bump DSBGA Package During PWM mode, the device operates at a fixed-
frequency of 6 MHz (typ.). In Auto PFM-PWM mode,
– (1.065 x 1.265 , 0.6 mm or 0.25 mm height) hysteretic PFM extends the battery life through
• Total Solution Size < 7mm2(works with 0402 reduction of the quiescent current during light loads
capacitors) and system standby.
• UVLO The LM8801 is available in a 6-bump DSBGA
package. Only three compact external surface-mount
components, an inductor and two capacitors, are
required. Efficiency vs. Output Current
Typical Application Circuit (Auto Mode, VOUT = 1.82V)
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2009–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LM8801
SNVS597H –APRIL 2009–REVISED MAY 2013
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Connection Diagram
6-Bump DSBGA Package
See package numbers YFQ0006LCA and YQA0006LCA
Pin Descriptions
Pin Number Name Description
A1 Mode Auto mode and forced PWM mode selection. Forced PWM = HIGH; Auto = LOW.
A2 VIN Power supply input. Connect to the input filter capacitor (Typical Application Circuit, page 1).
B1 SW Switching node connection to the internal PFET switch and NFET synchronous rectifier.
B2 EN Enable pin. The device is in shutdown mode when voltage to this pin is < 0.4V and enabled
when > 1.2V. Do not leave this pin floating.
C1 FB Feedback analog input. Connect directly to the output filter capacitor (Typical Application
Circuit, page 1).
C2 GND Ground pin.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Dissipation Rating Table TA≤25°C TA= 60°C TA= 85°C
θJA Power Rating Power Rating Power Rating
85°CW (1)1176 mW 765 mW 470 mW
(1) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high power dissipation
exists, special care must be given to thermal dissipation issues in board design.
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Absolute Maximum Ratings (1)(2)
VIN Pin to GND −0.2V to 6.0V
EN, MODE pin to GND −0.2V to 6.0V
FB, SW pin (GND−0.2V) to
(VIN + 0.2V) w/ 6.0V max
Junction Temperature (TJ-MAX) +150°C
Storage Temperature Range −65°C to +150°C
Continuous Power Dissipation (3) Internally Limited
Maximum Lead Temperature 260°C
(Soldering, 10 sec.)
ESD Rating (4)
Human Body Model 2 kV
Machine Model 200V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test
conditions, see the Electrical Characteristics tables.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office / Distributors for
availability and specifications.
(3) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ= 150°C (typ.) and
disengages at TJ= 130°C (typ.).
(4) The Human Body Model is a 100 pF capacitor discharged through a 1.5 kΩresistor into each pin. The machine model is a 200 pF
capacitor discharged directly into each pin. MIL-STD-883–3015.7.
Operating Ratings (1) (2)
Input Voltage Range 2.3V to 5.5V
Recommended Load Current 0 mA to 600 mA
Junction Temperature (TJ) Range −30°C to +125°C
Ambient Temperature (TA) Range (3) −30°C to +85°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test
conditions, see the Electrical Characteristics tables.
(2) All voltages are with respect to the potential at the GND pin.
(3) In applications where high power dissipation and/or poor package resistance is present, the maximum ambient temperature may have to
be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C),
the maximum power dissipation of the device in the application (PD-MAX) and the junction-to-ambient thermal resistance of the
part/package (θJA) in the application, as given by the following equation: TA-MAX = TJ-MAX−(θJAx PD-MAX). Due to the pulsed nature of
testing the part, the temp in the Electrical Characteristic table is specified as TA= TJ.
ThermaL Characteristics
Junction-to-Ambient Thermal Resistance (θJA) (DSBGA) (1) 85°C/W
(1) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high power dissipation
exists, special care must be given to thermal dissipation issues in board design.
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Electrical Characteristics (1) (2) (3)
Limits in standard typeface are for TA= 25°C. Limits in boldface type apply over the operating ambient temperature range
(−30°C ≤TA= TJ≤+85°C). Unless otherwise noted, specifications apply to the LM8801 open loop Typical Application Circuit
with VOUT = 1.82V, VIN = EN = 3.6V.
Parameter Test Conditions Min Typ Max Units
VFB Feedback Voltage Tolerance PWM -1.5 +1.5 %
2.3V ≤VIN ≤5.5V; 0.2
IOUT = 10 mA (PFM)
Line Reg. (closed loop) %/V
2.3V ≤VIN ≤5.5V;
VOUT 0.048
IOUT = 200 mA (PWM)
0.1 mA ≤IOUT ≤600 mA;
Load Reg. (closed loop) 0.0019 %/mA
VIN = 3.6V (Auto)
ISHDN Shutdown Supply Current EN = 0V, SW = GND 0.08 1.0 µA
IQ_PFM Quiescent Current in PFM Mode No load, device is not switching 27 35 µA
IQ_PWM Quiescent Current in PWM Mode No load, device is not switching 0.57 0.7 mA
RDSON (P) Pin-Pin Resistance for PFET VIN = VGS = 3.6V 220 mΩ
RDSON (N) Pin-Pin Resistance for Sync NFET VIN = VGS = 3.6V 180 mΩ
ILIM PFET Peak Current Limit 900 1100 1300 mA
VIH Logic High Input, all control pins 1.2 V
VIL Logic Low Input 0.4 V
IEN,MODE Pin Input Current 0.01 1 µA
FOSC Internal Oscillator Frequency PWM Mode 5.6 6.0 6.4 MHz
UVLO Under-Voltage Lock Out 2.0 V
(1) All voltages are with respect to the potential at the GND pin.
(2) Min and Max limits are specified by design, test or statistical analysis. Typical numbers represent the most likely norm.
(3) The parameters in the electrical characteristic table are tested under open loop conditions at VIN = 3.6V unless otherwise specified. For
performance over the input voltage range and closed loop condition, refer to the datasheet curves.
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Ref1
Ref3
FB
EN VIN
PWM
Comparator
GND
Control Logic Driver
Undervoltage
Lockout
Ramp
Generator
Thermal
Shutdown
Error
Amp
Oscillator Output
Short
Protection
-
+
+
-
Reference Voltage
and Current Generator
SW
+
-
+
-
+
-
MODE
Ref4
+
-
PFM PWM
Comparator
Ref2
+
-
LM8801
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SNVS597H –APRIL 2009–REVISED MAY 2013
BLOCK DIAGRAM
Simplified Functional Diagram
ORDERING INFORMATION(1)(2)
DSBGA package
Orderable Voltage Option (V)
LM8801TME-1.2/NOPB 1.2
LM8801TMX-1.2/NOPB
LM8801TME-1.82/NOPB
LM8801TMX-1.82/NOPB 1.82
LM8801XUE-1.82/NOPB
LM8801XUX-1.82/NOPB
LM8801TME-2.9/NOPB 2.9
LM8801TMX-2.9/NOPB
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
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SUPPLY VOLTAGE (V)
OUTPUT VOLTAG E (V)
1.825
1.823
1.821
1.819
1.817
1.8152.3 2.8 3.3 3.8 4.3 4.8 5.3 5.8
IOUT = 160 mA
IOUT = 600 mA
IOUT = 300 mA
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
1.845
1.840
1.835
1.830
1.825
1.820
1.815 0 100 200 300 400 500 600 700
2.7V
3.6V
4.2V
PFM
PWM
OUTPUT CURRENT (mA)
EFFICIENCY (%)
100
90
80
70
60
50
400 100 200 300 400 500 600
2.7V
3.6V
4.2V
2.3V
OUTPUT CURRENT (mA)
EFFICIENCY (%)
100
90
80
70
60
50
40
30
0.1 1 10 100 1000
VIN = 2.3V VIN = 3.6V
VIN = 4.2V
OUTPUT CURRENT (mA)
EFFICIENCY (%)
100
90
80
70
60
50
40
30
0.1 1 10 100 1000
2.7V
3.6V
2.3V
4.2V
OUTPUT CURRENT (mA)
EFFICIENCY (%)
100
90
80
70
60
50
40
30
20
10
00.1 1 10 100 1000
3.6V
2.7V
4.2V
2.3V
LM8801
SNVS597H –APRIL 2009–REVISED MAY 2013
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Typical Performance Characteristics
LM8801TM-1.82, Typical Application Circuit (page 1), VOUT = 1.82V, VIN = 3.6V, TA= 25°C, CIN = 2.2 µF, 0402
(JMK105BJ225MV-F), COUT = 4.7 µF, 0402, 6.3V (CL05A475MQ5NRNC), L = 0.5 µH, 2012 (MIPSZ2012D0R5), unless
otherwise noted.
Efficiency Efficiency
vs. vs.
Output Current (Auto Mode) Output Current (PWM Mode)
Figure 1. Figure 2.
Efficiency
Efficiency vs.
vs. Output Current,
Output Current (PWM Mode) Auto Mode, VOUT = 1.2V
Figure 3. Figure 4.
Output Voltage Output Voltage
vs. vs.
Output Current (Auto Mode) Supply Voltage (PWM)
Figure 5. Figure 6.
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VIN (V)
LOAD (mA)
160
140
120
100
80
60
40
20
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
PFM to PWM
PWM to PFM
LM8801
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SNVS597H –APRIL 2009–REVISED MAY 2013
Typical Performance Characteristics (continued)
LM8801TM-1.82, Typical Application Circuit (page 1), VOUT = 1.82V, VIN = 3.6V, TA= 25°C, CIN = 2.2 µF, 0402
(JMK105BJ225MV-F), COUT = 4.7 µF, 0402, 6.3V (CL05A475MQ5NRNC), L = 0.5 µH, 2012 (MIPSZ2012D0R5), unless
otherwise noted. Typical Switching Waveform
PFM ↔PWM Mode Change Point (PWM Mode, IOUT = 300 mA)
Figure 7. Figure 8.
Typical Switching Waveform Load Transient Response
(PFM Mode IOUT = 50 mA) (0 ↔150 mA)
Figure 9. Figure 10.
Load Transient Response Load Transient Response
(50 ↔350 mA) (150 ↔400 mA)
Figure 11. Figure 12.
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Typical Performance Characteristics (continued)
LM8801TM-1.82, Typical Application Circuit (page 1), VOUT = 1.82V, VIN = 3.6V, TA= 25°C, CIN = 2.2 µF, 0402
(JMK105BJ225MV-F), COUT = 4.7 µF, 0402, 6.3V (CL05A475MQ5NRNC), L = 0.5 µH, 2012 (MIPSZ2012D0R5), unless
otherwise noted. Load Transient Response Load Transient Response
(250 ↔600 mA) (VOUT = 1.2V, 0 ↔150 mA)
Figure 13. Figure 14.
Load Transient Response Load Transient Response
(VOUT = 1.2V, 50 ↔350 mA) (VOUT = 1.2V, 150 ↔400 mA)
Figure 15. Figure 16.
Load Transient Response Line Transient Response
(VOUT = 1.2V, 250↔600 mA) (3.0 VIN ↔3.6 VIN, 250 mA)
Figure 17. Figure 18.
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Typical Performance Characteristics (continued)
LM8801TM-1.82, Typical Application Circuit (page 1), VOUT = 1.82V, VIN = 3.6V, TA= 25°C, CIN = 2.2 µF, 0402
(JMK105BJ225MV-F), COUT = 4.7 µF, 0402, 6.3V (CL05A475MQ5NRNC), L = 0.5 µH, 2012 (MIPSZ2012D0R5), unless
otherwise noted.Startup in PFM Mode (IOUT = 20 mA) Startup in PWM Mode (IOUT = 300 mA)
Figure 19. Figure 20.
Startup in PWM Mode Startup in PFM Mode
(VOUT = 1.2V, IOUT = 300 mA) (VOUT = 1.2V, IOUT = 20 mA)
Figure 21. Figure 22.
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OPERATION DESCRIPTION
DEVICE INFORMATION
The LM8801, a high-efficiency, step-down DC-DC switching buck converter, delivers a constant voltage from
either a single Li-Ion or three cell NiMH/NiCd battery to portable devices such as cell phones and PDAs. Using a
voltage mode architecture with synchronous rectification, the LM8801 has the ability to deliver up to 600 mA
depending on the input voltage and output voltage, ambient temperature, and the inductor chosen.
There are three modes of operation depending on the current required - PWM (Pulse Width Modulation), PFM
(Pulse Frequency Modulation), and shutdown. The device operates in PWM mode at load currents of
approximately 80 mA or higher, having voltage precision of ±1.5% with 90% efficiency or better. Lighter output
current loads cause the device to automatically switch into PFM for reduced current consumption (IQ= 27 µA
typ.) and a longer battery life. Shutdown mode turns off the device, offering the lowest current consumption
(ISHUTDOWN = 0.08 µA typ.).
Additional features include soft-start, under voltage protection, current overload protection, and thermal shutdown
protection. As shown in the Typical Application Circuit, only three external power components are required for
implementation.
CIRCUIT OPERATION
The LM8801 operates as follows. During the first portion of each switching cycle, the control block in the LM8801
turns on the internal PFET switch. This allows current to flow from the input through the inductor to the output
filter capacitor and load. The inductor limits the current to a ramp with a slope of (VIN −VOUT)/L, by storing energy
in a magnetic field. During the second portion of each cycle, the controller turns the PFET switch off, blocking
current flow from the input, and then turns the NFET synchronous rectifier on. The inductor draws current from
ground through the NFET to the output filter capacitor and load, which ramps the inductor current down with a
slope of –VOUT/L.
The output filter capacitor stores charge when the inductor current is high, and releases it when low, smoothing
the voltage across the load.
The output voltage is regulated by modulating the PFET switch on time to control the average current sent to the
load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and
synchronous rectifier at the SW pin to a low-pass filter formed by the inductor and output filter capacitor. The
output voltage is equal to the average voltage at the SW pin.
PWM OPERATION
During PWM operation, the converter operates as a voltage-mode controller with input voltage feed forward. This
allows the converter to achieve excellent load and line regulation. The DC gain of the power stage is proportional
to the input voltage. To eliminate this dependence, feed forward inversely proportional to the input voltage is
introduced.
While in PWM mode, the output voltage is regulated by switching at a constant frequency and then modulating
the energy per cycle to control power to the load. At the beginning of each clock cycle the PFET switch is turned
on and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The
current limit comparator can also turn off the switch in case the current limit of the PFET is exceeded. Then the
NFET switch is turned on and the inductor current ramps down. The next cycle is initiated by the clock turning off
the NFET and turning on the PFET.
AUTO MODE OPERATION
Setting Mode pin low places the LM8801 in Auto mode. By doing so the device will automatically switch between
PFM state and PWM (Pulse Width Modulation) state based on load demand. At light loads (less than 50 mA), the
device enters PFM mode and operates with reduced switching cycle and supply current to maintain high
efficiency. During PFM operation, the converter positions the output voltage slightly higher (+15 mV typ.) than the
nominal output voltage during PWM operation, allowing additional headroom for voltage drop during a load
transient from light to heavy load.
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High PFM Threshold
PFM Mode at Light Load
PWM Mode at Heavy Load
Load current increases
Low PFM Threshold
Z-
A
xi
s
Z-
Axis
Target Output Voltage
LM8801
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SNVS597H –APRIL 2009–REVISED MAY 2013
Figure 23. Operation in PFM Mode and Transfer to PWM Mode
INTERNAL SYNCHRONOUS RECTIFICATION
While in PWM mode, the LM8801 uses an internal NFET as a synchronous rectifier to reduce rectifier forward
voltage drop and associated power loss. Synchronous rectification provides a significant improvement in
efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier
diode.
CURRENT LIMITING
A current limit feature allows the LM8801 to protect itself and external components during overload conditions.
PWM mode implements current limit using an internal comparator that trips at 1.1A (typ). If the output is shorted
to ground the device enters a timed current limit mode where the NFET is turned on for a longer duration until
the inductor current falls below a low threshold, ensuring inductor current has more time to decay, thereby
preventing runaway.
SHUTDOWN MODE
Setting the EN input pin low (<0.4V) places the LM8801 in shutdown mode. During shutdown the PFET switch,
NFET switch, reference, control and bias circuitry of the LM8801 are turned off. Setting EN high (>1.2V) enables
normal operation. While turning on the device with EN soft-start is activated. EN pin should be set low to turn off
the LM8801 during system power up and under-voltage conditions when the supply is less than 2.3V. Do not
leave the EN pin floating.
SOFT-START
The LM8801 has a soft-start circuit that limits in-rush current during start-up. During start-up the switch current
limit is increased in steps. Soft start is activated only if EN goes from logic low to logic high after VIN reaches
2.3V.
THERMAL SHUTDOWN PROTECTION
The LM8801 has a thermal overload protection function that operates to protect itself from short-term misuse and
overload conditions. When the junction temperature exceeds around 150°C, the device inhibits operation. Both
the PFET and the NFET are turned off. When the temperature drops below 130°C, normal operation resumes.
Prolonged operation in thermal overload conditions may damage the device and is considered bad practice.
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x
x
xf
1
L
2
!
ISAT IOUTMAX + IRIPPLE
where IRIPPLE = VOUT
VIN
VIN - VOUT ¹
·
©
§¹
·
©
§
¹
·
©
§
LM8801
SNVS597H –APRIL 2009–REVISED MAY 2013
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UVLO (UNDER-VOLTAGE LOCK OUT)
The LM8801 has an UVP comparator to turn the power device off in the case the input voltage or battery voltage
is too low. The typical UVP threshold is around 2V with 100 mV hysteresis.
APPLICATION INFORMATION
INDUCTOR SELECTION
There are two main considerations when choosing an inductor; the inductor should not saturate, and the inductor
current ripple is small enough to achieve the desired output voltage ripple. Different manufacturers follow
different saturation current rating specifications, so attention must be given to details. Saturation current ratings
are typically specified at 25°C so ratings at maximum ambient temperature of application should be requested
from manufacturer.
Minimum value of inductance to ensure good performance is 0.3 µH at (ILIM typ.) bias current over the
ambient temperature range.
Shielded inductors radiate less noise and should be preferred. There are two methods to choose the inductor
saturation current rating.
Method 1:
The saturation current should be greater than the sum of the maximum load current and the worst case average
to peak inductor current. This can be written as:
(1)
• IRIPPLE: average to peak inductor current
• IOUTMAX: maximum load current (600 mA)
• VIN: maximum input voltage in application
• L: minimum inductor value including worst case tolerances (30% drop can be considered for method 1)
• f: minimum switching frequency (5.4 MHz)
• VOUT: output voltage
Method 2:
A more conservative and recommended approach is to choose an inductor that can handle the maximum current
limit of 1300 mA.
The inductor's resistance should be less than around 0.1Ωfor good efficiency. Table 1 lists suggested inductors
and suppliers.
INPUT CAPACITOR SELECTION
A ceramic input capacitor of 2.2 µF, 6.3V is sufficient for most applications. Place the input capacitor as close as
possible to the VIN pin of the device. A larger value or higher voltage rating may be used to improve input voltage
filtering. Use X7R or X5R types; do not use Y5V. DC bias characteristics of ceramic capacitors must be
considered when selecting case sizes like 0402 and 0603.
The input filter capacitor supplies current to the top switch of the LM8801 in the first half of each cycle and
reduces voltage ripple imposed on the input power source. A ceramic capacitor's low ESR provides the best
noise filtering of the input voltage spikes due to this rapidly changing current. Select an input filter capacitor with
sufficient ripple current rating.
The input current ripple can be calculated as:
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VPP-RMS = VPP-C2 + VPP-ESR2
VPP-C = 4*f*C
IRIPPLE
IRMS = IOUTMAX x
r =
VOUT
VIN
r2
12
1 - +
VOUT
VIN ¸
¸
¹
·
¨
¨
©
§
x
(VIN - VOUT) VOUT
x
L f IOUTMAX VIN
x x x
LM8801
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SNVS597H –APRIL 2009–REVISED MAY 2013
(2)
The worst case is when VIN =2xVOUT.
Table 1. Suggested Inductors and Suppliers
Model Vendor Dimensions LxWxH (mm)
MIPSZ2012D0R5 FDK 2.0 x 1.2 x 1.0
LQM21PNR54MG0D Murata 2.0 x 1.2 x 0.9
HSLI-201208AG-R47 Hitachi Metals 2.0 x 1.2 x 0.8
OUTPUT CAPACITOR SELECTION
Use a 4.7 μF, 6.3V ceramic capacitor, X7R or X5R types; do not use Y5V. DC bias characteristics of ceramic
capacitors must be considered when selecting case sizes 0402 and 0603. DC bias characteristics vary from
manufacturer to manufacturer, and DC bias curves should be requested from them as part of the capacitor
selection process. Minimum output capacitance to ensure good performance is 2.2 µF (for 4.7 µF
capacitor) at 1.8V DC bias including tolerances and over ambient temp range.
The output filter capacitor smooths out current flow from the inductor to the load, helps maintain a steady output
voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with
sufficient capacitance and sufficiently low ESR to perform these functions.
The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its
RESR and can be calculated as:
Voltage peak-to-peak ripple due to capacitance =
(3)
Voltage peak-to-peak ripple due to ESR =
VPP-ESR =(2*IRIPPLE)*RESR
Because these two components are out of phase, the rms value can be used to get an approximate value of
peak-to-peak ripple.
Voltage peak-to-peak ripple, root mean squared =
(4)
Note that the output voltage ripple is dependent on the current ripple and the equivalent series resistance of the
output capacitor (RESR). The RESR is frequency dependent (as well as temperature dependent); make sure the
value used for calculations is at the switching frequency of the part.
Table 2 lists suggested capacitors and suppliers.
Table 2. Suggested Capacitors and Suppliers
Case Size
Model Vendor Inch (mm)
GRM155R60J225ME15 (CIN) Murata 0402 (1005)
JMK105BJ225MV-F (CIN) Taiyo Yuden 0402 (1005)
CL05A475MQ5NRNC (CIN or COUT) Samsung 0402 (1005)
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DSBGA PACKAGE ASSEMBLY AND USE
Use of the DSBGA package requires specialized board layout, precision mounting and careful re-flow
techniques, as detailed in Application Note 1112. Refer to the section Surface Mount Technology (SMD)
Assembly Considerations. For best results in assembly, alignment ordinals on the PC board should be used to
facilitate placement of the device.
The pad style used with DSBGA package must be the NSMD (Non-Solder Mask Defined) type. This means that
the solder-mask opening is larger than the pad size. This prevents a lip that otherwise forms if the solder-mask
and pad overlap, from holding the device off the surface of the board and interfering with mounting. See
Application Note 1112 for specific instructions how to do this.
BOARD LAYOUT CONSIDERATIONS
PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance
of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss
in the traces. These can send erroneous signals to the DC-DC converter IC, resulting in poor regulation or
instability. Poor layout can also result in re-flow problems leading to poor solder joints between the DSBGA
package and board pads. Poor solder joints can result in erratic or degraded performance.
Good layout for the LM8801 can be implemented by following a few simple design rules, as illustrated in
Figure 24.
Figure 24. LM8801 Board Layout (Top View)
1. Place the LM8801 on 8.26 mil pads. As a thermal relief, connect each pad with a 7 mil wide, approximately 7
mil long trace, and then incrementally increase each trace to its optimal width. The important criterion is
symmetry to ensure the solder bumps re-flow evenly. See AN-1112 DSBGA Wafer Level Chip Scale
Package (SNVA009).
2. Place the LM8801, inductor and filter capacitors close together and make the traces short. The traces
between these components carry relatively high switching currents and act as antennas. Following this rule
reduces radiated noise. Special care must be given to place the input filter capacitor very close to the VIN
and GND pin.
3. Arrange the components so that the switching current loops curl in the same direction. During the first half of
each cycle, current flows from the input filter capacitor, through the LM8801 and inductor to the output filter
capacitor and back through ground, forming a current loop. In the second half of each cycle, current is pulled
up from ground, through the LM8801 by the inductor, to the output filter capacitor and then back through
ground, forming a second current loop. Routing these loops so the current curls in the same direction
prevents magnetic field reversal between the two half-cycles and reduces radiated noise.
4. Connect the ground pins of the LM8801, and filter capacitors together using generous component-side
copper fill as a pseudo-ground plane. Then connect this to the ground-plane (if one is used) with several
vias. This reduces ground-plane noise by preventing the switching currents from circulating through the
ground plane. It also reduces ground bounce at the LM8801 by giving it a low-impedance ground connection.
5. Use wide traces between the power components and for power connections to the DC-DC converter circuit.
This reduces voltage errors caused by resistive losses across the traces.
14 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: LM8801
LM8801
www.ti.com
SNVS597H –APRIL 2009–REVISED MAY 2013
6. Route noise sensitive traces such as the voltage feedback path away from noisy traces between the power
components. The voltage feedback trace must remain close to the LM8801 circuit and should be routed
directly from FB to VOUT at the output capacitor and should be routed opposite to noise components. This
reduces EMI radiated onto the DC-DC converter’s own voltage feedback trace.
7. Place noise sensitive circuitry, such as radio IF blocks, away from the DC-DC converter, CMOS digital blocks
and other noisy circuitry. Interference with noise-sensitive circuitry in the system can be reduced through
distance.
In mobile phones, for example, a common practice is to place the DC-DC converter on one corner of the board,
arrange the CMOS digital circuitry around it (since this also generates noise), and then place sensitive
preamplifiers and IF stages on the diagonally opposing corner. Often, the sensitive circuitry is shielded with a
metal pan and power to it is post-regulated to reduce conducted noise, using low-dropout linear regulators.
Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LM8801
LM8801
SNVS597H –APRIL 2009–REVISED MAY 2013
www.ti.com
REVISION HISTORY
Changes from Revision G (May 2013) to Revision H Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 15
16 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: LM8801
PACKAGE OPTION ADDENDUM
www.ti.com 13-Sep-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM8801TME-1.2/NOPB ACTIVE DSBGA YFQ 6 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM J
LM8801TME-1.82/NOPB ACTIVE DSBGA YFQ 6 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -30 to 85 E
LM8801TME-2.9/NOPB ACTIVE DSBGA YFQ 6 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM S
LM8801TMX-1.2/NOPB ACTIVE DSBGA YFQ 6 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM J
LM8801TMX-1.82/NOPB ACTIVE DSBGA YFQ 6 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -30 to 85 E
LM8801TMX-2.9/NOPB ACTIVE DSBGA YFQ 6 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM S
LM8801XUE-1.82/NOPB ACTIVE DSBGA YQA 6 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM L
LM8801XUX-1.82/NOPB ACTIVE DSBGA YQA 6 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM L
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 13-Sep-2014
Addendum-Page 2
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM8801TME-1.2/NOPB DSBGA YFQ 6 250 178.0 8.4 1.14 1.47 0.76 4.0 8.0 Q1
LM8801TME-1.82/NOPB DSBGA YFQ 6 250 178.0 8.4 1.14 1.47 0.76 4.0 8.0 Q1
LM8801TME-2.9/NOPB DSBGA YFQ 6 250 178.0 8.4 1.14 1.47 0.76 4.0 8.0 Q1
LM8801TMX-1.2/NOPB DSBGA YFQ 6 3000 178.0 8.4 1.14 1.47 0.76 4.0 8.0 Q1
LM8801TMX-1.82/NOPB DSBGA YFQ 6 3000 178.0 8.4 1.14 1.47 0.76 4.0 8.0 Q1
LM8801TMX-2.9/NOPB DSBGA YFQ 6 3000 178.0 8.4 1.14 1.47 0.76 4.0 8.0 Q1
LM8801XUE-1.82/NOPB DSBGA YQA 6 250 178.0 8.4 1.15 1.35 0.4 4.0 8.0 Q1
LM8801XUX-1.82/NOPB DSBGA YQA 6 3000 178.0 8.4 1.15 1.35 0.4 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 8-May-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM8801TME-1.2/NOPB DSBGA YFQ 6 250 210.0 185.0 35.0
LM8801TME-1.82/NOPB DSBGA YFQ 6 250 210.0 185.0 35.0
LM8801TME-2.9/NOPB DSBGA YFQ 6 250 210.0 185.0 35.0
LM8801TMX-1.2/NOPB DSBGA YFQ 6 3000 210.0 185.0 35.0
LM8801TMX-1.82/NOPB DSBGA YFQ 6 3000 210.0 185.0 35.0
LM8801TMX-2.9/NOPB DSBGA YFQ 6 3000 210.0 185.0 35.0
LM8801XUE-1.82/NOPB DSBGA YQA 6 250 210.0 185.0 35.0
LM8801XUX-1.82/NOPB DSBGA YQA 6 3000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 8-May-2013
Pack Materials-Page 2
MECHANICAL DATA
YFQ0006xxx
www.ti.com
TMD06XXX (Rev B)
E
0.600±0.075
D
A
. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
NOTES:
4215075/A 12/12
D: Max =
E: Max =
1.29 mm, Min =
1.09 mm, Min =
1.23 mm
1.03 mm
MECHANICAL DATA
YQA0006xxx
www.ti.com
XUD06XXX (Rev A)
0.250±0.045
D
E
4215207/A 12/12
A
. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
NOTES:
D: Max =
E: Max =
1.29 mm, Min =
1.09 mm, Min =
1.23 mm
1.03 mm
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