BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /
Memory ICs BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
I2C BUS compatible serial EEPROM
BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W /
BR24C01AFV-W / BR24C02-W / BR24C02F-W /
BR24C02FJ-W / BR24C02FV-W / BR24C04-W /
BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
The BR24C01A-W, BR24C02-W, and BR24C04-W series are 2-wire (I2C BUS type) serial EEPROMs which are
electrically programmable.
∗ I2C BUS is a registered trademark of Philips.
!
!!
!Applications
VCRs, TVs, printers, car stereos, cordless telephones, short wave radios, programmable DIP switches
!
!!
!Features
1) 128×8bits (1k) serial EEPROM.
(BR24C01A-W / AF-W / AFJ-W / AFV-W)
256×8bits (2k) serial EEPROM.
(BR24C02-W / F-W / FJ-W / FV-W)
512×8bits (4k) serial EEPROM.
(BR24C04-W / F-W / FJ-W / FV-W)
2) Two wire serial interface.
3) Operating voltage range : 2.7V∼5.5V
4) Low current consumption
Active (at 5V) : 1.5mA (Typ.)
Standby (at 5V) : 0.1µA (Typ.)
5) Auto erase and auto complete functions can be used
during write operations.
6) Page write function.
BR24C01A-W / AF-W / AFJ-W / AFV-W : 8 bytes
BR24C02-W / F-W / FJ-W / FV-W : 8 bytes
BR24C04-W / F-W / FJ-W / FV-W : 16 bytes
7) DATA security
Write protect feature
Inhibit to WRITE at low VCC
8) Noise filters at SCL and SDA pins.
9) Address can be incremented automatically during
read operations.
10) Compact packages.
11) Rewriting possible up to 100,000 times
12) Data can be stored for ten years without corruption.
!
!!
!Absolute maximum ratings (Ta = 25°C)
Parameter Symbol Limits Unit
Applied voltage −0.3~+6.5 V
Power dissipation mW
Storage temperature −65~+125 °C
Operating temperature °C
Input voltage −V
−40~+85
V
CC
−0.3~V
CC
+0.3
Pd
Tstg
Topr
300(SSOP−B8)
∗1
800(DIP8)
450(SOP8, SOP−J8)
∗2
∗3
∗1 Reduced by 3.0mW for each increase in Ta of 1°C over 25°C.
∗2 Reduced by 4.5mW for each increase in Ta of 1°C over 25°C.
∗3 Reduced by 8.0mW for each increase in Ta of 1°C over 25°C.
BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /
Memory ICs BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
!
!!
!Recommended operating conditions (Ta = 25°C)
Parameter Symbol Limits Unit
Power supply voltage V
V
Input voltage V
IN
V
V
CC
0~V
CC
2.7~5.5 (WRITE)
2.7~5.5 (READ)
!
!!
!Block diagram
BR24C01A-W / AF-W / AFJ-W / AFV-W
1kbits EEPROM ARRAY
CONTROL LOGIC
HIGH VOLTAGE GEN.
ACK
START STOP
7bits
7bits
8bits
DATA
REGISTER
ADDRESS
DECODER
A0
A1
A2
1
2
3
4
GND
WP
SCL
SDA
8
7
6
5
V
CC
V
CC
LEVEL DETECT
ADDRESS REGISTER
SLAVE WORD
·
BR24C02-W / F-W / FJ-W / FV-W
2kbits EEPROM ARRAY
CONTROL LOGIC
HIGH VOLTAGE GEN.
ACK
START STOP
8bits
8bits
8bits
DATA
REGISTER
ADDRESS
DECODER
A0
A1
A2
1
2
3
4
GND
WP
SCL
SDA
8
7
6
5
V
CC
VCC LEVEL DETECT
ADDRESS REGISTER
SLAVE WORD
·
BR24C04-W / F-W / FJ-W / FV-W
4kbits EEPROM ARRAY
CONTROL LOGIC
HIGH VOLTAGE GEN.
ACK
START STOP
9bits
9bits
8bits
DATA
REGISTER
ADDRESS
DECODER
A0
A1
A2
1
2
3
4
GND
WP
SCL
SDA
8
7
6
5
V
CC
VCC LEVEL DETECT
ADDRESS REGISTER
SLAVE WORD
·
!
!!
!Pin descriptions
Pin name Function
A0, A1, A2 Slave address setting pin
SCL Serial data clock
SDA Serial data input / output
WP Write protect pin
VCC Power supply
GND Ground
∗ An open drain output requires a pull-up resistor.
∗
Slave address setting pin
SCL
SDA
WP Write protect pin
Power supply
GND Ground
Pin name Function
Serial data clock
Serial data input / output
A0, A1, A2
VCC
∗ An open drain output requires a pull-up resistor.
∗
Pin name
A0 N.C.
SCL
SDA
WP Write protect pin
Power supply
GND Ground
Function
A1, A2 Slave address setting pin
Serial data clock
Serial data input / output
V
CC
∗ An open drain output requires a pull-up resistor.
∗
BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /
Memory ICs BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
!
!!
!Electrical characteristics
DC characteristics (unless otherwise noted, Ta = −40 to + 85 °C, VCC = 2.7 to 5.5V)
Parameter Symbol Min. Typ. Max. Unit Conditions
VIH −−V
VIL −−
0.3VCC V
VOL −−
0.4 V
Input leakage current ILI −1µAVIN=0V
~
VCC
Output leakage current ILO
−1
−1−1µA
operatingcurrent dissipation ICC −2.0 mA
Standby current ISB −
−
−2.0 µA
0.7VCC
−
−
IOL=3.0mA(SDA)
VCC=5.5V, f
SCL
=400kHz
A0, A1, A2=GND, WP=GND
VOUT=0V
~
VCC
Input high level voltage
Input low level voltage
Output low level coltage
VCC=5.5V, SDA
·
SCL=VCC
Not designed for radiation resistance.
Operating timing characteristics (unless otherwise noted, Ta = −40 to + 85 °C, VCC = 2.7 to 5.5V)
Parameter Symbol Vcc=5V±10% Vcc=3V±10% Unit
f
SCL
kHz
t
HIGH
Noise erase valid time (SCL / SDA pins) t
I
µs
Data clock HIGH time
SCL frequency
µs
Data clock LOW time t
LOW
µs
SDA / SCL rise time t
R
µs
SDA / SCL fall time t
F
µs
Start condition hold time t
HD
: STA µs
Start condition setup time t
SU
: STA µs
Input data hold time t
HD
: DAT ns
Input data setup time t
SU
: DAT ns
Output data delay time t
PD
µs
Output data hold time t
DH
µs
Stop condition setup time t
SU
: STO µs
Bus open time before start of transfer t
BUF
µs
t
WR
Min.
−
0.6
−
1.2
−
−
0.6
0.6
0
100
0.1
0.1
0.6
1.2
−
Typ.
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Max.
400
−
0.05
−
0.3
0.3
−
−
−
−
0.9
−
−
−
10
Min.
−
4.0
−
4.7
−
−
4.0
4.7
0
250
0.2
0.2
4.7
4.7
−
Typ.
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Max.
100
−
0.1
−
1.0
0.3
−
−
−
−
3.5
−
−
−
10 msInternal write cycle time
BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /
Memory ICs BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
!
!!
!Timing charts
t
BUF
t
DH
t
PD
t
HIGH
t
HD
:
STA
t
LOW
t
F
t
R
SDA
SDA
SCL
START BIT STOP BIT
SCL
SDA
· Data is read on the rising edge of SCL.
· Data is output in synchronization with the falling edge of SCL.
t
SU
: DAT t
HD
: DAT
t
SU
: STOt
HD
: STA t
SU
: STA
(output)
(input)
Fig.1 Synchronized data input / output timing
ACKD0
(n address) t
WR
SDA
SCL
Start conditionStop condition
Write data
Fig.2 Write cycle timing
!
!!
!Circuit operation
(1) Start condition (recognition of start bit)
Before executing any command, when SCL is HIGH, a start condition (start bit) is required to cause SDA to fall from
HIGH to LOW. This IC is designed to constantly detect whether there is a start condition (start bit) for the SDA and
SCL line, and no commands will be executed unless this condition is satisfied.
(See Fig.1 for the synchronized data input / output timing.)
(2) Stop condition (recognition of stop bit)
To stop any command, a stop condition (stop bit) is required. A stop condition is achieved when SDA goes from
LOW to HIGH while SCL is HIGH. This enables commands to be completed.
(See Fig.1 for the synchronized data input / output timing.)
(3) Precautions concerning write commands
In the WRITE mode, the transferred data is not written to the memory unless the stop bit is executed.
BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /
Memory ICs BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
(4) Device addressing
– BR24C01A-W / AF-W / AFJ-W / AFV-W, BR24C02-W / F-W / FJ-W / FV-W
1) Make sure the slave address is output from the master immediately after the start condition.
2) The upper four bits of the slave address are used to determine the device type. The device code for this IC is
fixed at “1010”.
3) The next three bits of the slave address (A2, A1, A0 … device address) are used to select the device. This IC
can address up to eight devices on the same bus.
4) The lowermost bit of the slave address (R / W … READ / WRITE) is used to set the write or read mode as follows.
R / W set to 0 … Write
(Random read word address setting is also 0)
R / W set to 1 … Read
A2 A1 A01010 R / W
– BR24C04-W / F-W / FJ-W / FV-W
1) Make sure the slave address is output from the master in continuation with the start condition.
2) The upper four bits of the slave address are used to determine the device type. The device code for this IC is
fixed at “1010”.
3) The next two bits of the slave address (A2, A1, … device address) are used to select the device. This IC can
address up to four devices on the same bus.
4) The next bit of the slave address (PS … Page Select) is used to select the page. As shown below, it can write to
or read from any of the 256 words in the two pages in memory.
PS set to 0 … Page 1 (000 to 0FF)
PS set to 1 … Page 2 (100 to 1FF)
5) The lowermost bit of the slave address (R / W … READ / WRITE) is used to set the write or read mode as follows.
R / W set to 0 … Write
(Random read word address setting is also 0)
R / W set to 1 … Read
A2 A1 PS1010 R / W
(5) Write protect (WP)
When WP pin set to VCC (High level), write protect is set by all address. When WP pin set to GND (Low level),
enable to write to all address. Either control this pin or connect to GND (or VCC). It is inhibited from being left
unconnected.
(6) ACK signal
The acknowledge signal (ACK signal) is determined by software and is used to indicate whether or not a data transfer
is proceeding normally. The transmitting device, whether the master or slave, opens the bus after an 8-bit data
output (µ-COM when a write or read command of the slave address input ; this IC when reading data).
For the receiving device during the ninth clock cycle, SDA is set to LOW and an acknowledge signal (ACK signal) is
sent to indicate that it received the 8-bit data (this IC when a write command or a read command of the slave address
input, µ-COM when a read command data output).
The ICs output a LOW acknowledge signal (ACK signal) after recognizing the start condition and slave address (8
bits).
When data is being write to the ICs, a LOW acknowledge signal (ACK signal) is output after the receipt of each eight
bits of data (word address and write data).
BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /
Memory ICs BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
When data is being read from the IC, eight bits of data (read data) are output and the IC waits for a returned LOW
acknowledge signal (ACK signal). When an acknowledge signal (ACK signal) is detected and a stop condition is not
sent from the master (µ-COM) side, the IC continues to output data. If an acknowledge signal (ACK signal) is not
detected, the IC interrupts the data transfer and ceases reading operations after recognizing the stop condition (stop
bit). The IC then enters the waiting or standby state.
(See Fig.3 for acknowledge signal (ACK signal) response.)
189
SCL
SDA
SDA
Start condition (start bit)
Acknowledge signal (ACK signal)
(from µ-COM)
(µ-COM output data)
(IC output data)
Fig.3 Acknowledge (ACK signal) response
(during write and read slave address input)
(7) Byte write cycle
BR24C01A-W / AF-W / AFJ-W / AFV-W
1 0 1 0 A2 A1 A0 D7 D0
S
T
O
P
DATA
A
C
K
A
C
K
A
C
K
WORD
ADDRESS
R
/
W
W
R
I
T
E
SLAVE
ADDRESS
S
T
A
R
T
SDA
LINE
WP
Fig.4
∗
WA
6WA
0
BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /
Memory ICs BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
BR24C02-W / F-W / FJ-W / FV-W
1 0 1 0 A2 A1 A0 D7 D0
S
T
O
P
DATA
A
C
K
A
C
K
A
C
K
WORD
ADDRESS
R
/
W
W
R
I
T
E
SLAVE
ADDRESS
S
T
A
R
T
SDA
LINE
WP
Fig.5
WA
7WA
0
BR24C04-W / F-W / FJ-W / FV-W
1 0 1 0 A2 A1 PS D7 D0
S
T
O
P
DATA
A
C
K
A
C
K
A
C
K
WORD
ADDRESS
R
/
W
W
R
I
T
E
SLAVE
ADDRESS
S
T
A
R
T
SDA
LINE
WP
Fig.6
WA
7WA
0
• Data is written to the address designated by the word address (n address).
• After eight bits of data are input, the data is written to the memory cell by issuing the stop bit.
(8) Page write cycle
BR24C01A-W / AF-W / AFJ-W / AFV-W
DATA(n+7)
D0
A
C
K
S
T
O
P
SDA
LINE
WP
S
T
A
R
TSLAVE
ADDRESS
10 01A2A1A0
A
C
K
R
/
W
W
R
I
T
EWORD
ADDRESS(n)
A
C
K
D7
DATA(n)
D0
A
C
K
Fig.7
∗
WA
6WA
0
BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /
Memory ICs BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
• A 8-byte write is possible using this command.
• Th page write command arbitrarily sets the upper four bits (WA6 to WA3) of the word address. The lower three bits
(WA2 and WA0) can write up to eight bytes of data with the address being incremented internally.
BR24C02-W / F-W / FJ-W / FV-W
SDA
LINE
WP
S
T
A
R
TSLAVE
ADDRESS
10 01A2A1A0
A
C
K
R
/
W
W
R
I
T
EWORD
ADDRESS(n)
A
C
K
D7
DATA(n) DATA(n+7)
D0 D0
A
C
K
A
C
K
S
T
O
P
Fig.8
WA
7WA
0
• A 8-byte write is possible using this command.
• Th page write command arbitrarily sets the upper five bits (WA7 to WA3) of the word address. The lower three bits
(WA2 and WA0) can write up to eight bytes of data with the address being incremented internally.
BR24C04-W / F-W / FJ-W / FV-W
SDA
LINE
WP
S
T
A
R
TSLAVE
ADDRESS
10 01A2A1PS
A
C
K
R
/
W
W
R
I
T
EWORD
ADDRESS(n)
A
C
K
D7
DATA(n) DATA(n+15)
D0 D0
A
C
K
A
C
K
S
T
O
P
Fig.9
WA
7WA
0
• A 16-byte write is possible using this command.
• Th page write command arbitrarily sets the upper four bits (WA7 to WA4) of the word address. The lower four bits
(WA3 and WA0) can write up to sixteen bytes of data with the address being incremented internally.
BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /
Memory ICs BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
(9) Current read cycle
BR24C01A-W / AF-W / AFJ-W / AFV-W
SDA
LINE
S
T
A
R
TSLAVE
ADDRESS
11
R
/
W
A
C
K
A
C
K
DATA
S
T
O
P
0 0 A2 A1 A0 D7 D0
R
E
A
D
Fig.10
BR24C02-W / F-W / FJ-W / FV-W
SDA
LINE
S
T
A
R
TSLAVE
ADDRESS
11
R
/
W
A
C
K
A
C
K
DATA
S
T
O
P
0 0 A2 A1 A0 D7 D0
R
E
A
D
Fig.11
BR24C04-W / F-W / FJ-W / FV-W
SDA
LINE
S
T
A
R
TSLAVE
ADDRESS
11
R
/
W
A
C
K
A
C
K
DATA
S
T
O
P
0 0 A2 A1 PS D7 D0
R
E
A
D
Fig.12
• In case the previous operation is random or current read (which includes sequential read respectively), the internal
address counter is increased by one from the last accessed address (n). Thus current read outputs the data of the
next word address (n+1).
If the last command is byte or page write, the internal address counter stays at the last address (n). Thus current
read outputs the data of the word address (n).
If the master does not transfer the acknowledge but does generate a stop condition, the current address read
operation only provides s single byte of data.
At this point, this IC discontinues transmission.
• When an ACK signal LOW is detected after D0 and a stop condition is not sent from the master (µ-COM), the next
word address data can be read. [All words all read enabled]
(See Fig.16 to 18 for the sequential read cycles.)
• This command is ended by inputting HIGH to the ACK signal after D0 and raising the SDA signal (stop condition) by
setting SCL to HIGH.
BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /
Memory ICs BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
(10) Random read cycle
BR24C01A-W / AF-W / AFJ-W / AFV-W
S
T
O
P
A
C
K
R
E
A
D
DATA(n)
SLAVE
ADDRESS SLAVE
ADDRESS
WORD
ADDRESS(n)
SDA
LINE
S
T
A
R
T
S
T
A
R
T
110 0 A2 A1A0
R
/
W
R
/
W
A
C
K
A
C
K
A
C
K
W
R
I
T
E
110 0 A2 A1A0 D7 D0
Fig.13
∗
WA
6WA
0
BR24C02-W / F-W / FJ-W / FV-W
S
T
O
P
A
C
K
R
E
A
D
DATA(n)
SLAVE
ADDRESS SLAVE
ADDRESS
WORD
ADDRESS(n)
SDA
LINE
S
T
A
R
T
S
T
A
R
T
110 0 A2 A1A0
R
/
W
R
/
W
A
C
K
A
C
K
A
C
K
W
R
I
T
E
110 0 A2A1A0 D7 D0
Fig.14
WA
7WA
0
BR24C04-W / F-W / FJ-W / FV-W
S
T
O
P
A
C
K
R
E
A
D
DATA(n)
SLAVE
ADDRESS SLAVE
ADDRESS
WORD
ADDRESS(n)
SDA
LINE
S
T
A
R
T
S
T
A
R
T
110 0 A2 A1PS
R
/
W
R
/
W
A
C
K
A
C
K
A
C
K
WA
7WA
0
W
R
I
T
E
110 0 A2A1PS D7 D0
Fig.15
• This command can read the designated word address data.
• When an ACK signal LOW is detected after D0 and a stop condition is not sent from the master (µ-COM), the next
word address data can be read. [All words all read enabled]
(See Fig.16 to 18 for the sequential read cycles.)
• This command is ended by inputting a HIGH signal to the ACK signal after D0 and raising the SDA signal (stop
condition) by raising SCL to HIGH.
BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /
Memory ICs BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
(11) Sequential read cycle (For a current read)
BR24C01A-W / AF-W / AFJ-W / AFV-W
S
T
A
R
TSLAVE
ADDRESS
R
/
W
A
C
K
A
C
K
A
C
K
A
C
K
R
E
A
D
DATA(n) DATA(n+x)
SDA
LINE 110 0 A2 A1A0 D7 D7D0 D0
S
T
O
P
Fig.16
BR24C02-W / F-W / FJ-W / FV-W
S
T
A
R
TSLAVE
ADDRESS
R
/
W
A
C
K
A
C
K
A
C
K
A
C
K
R
E
A
D
DATA(n) DATA(n+x)
SDA
LINE
110 0 A2 A1A0 D7 D7D0 D0
S
T
O
P
Fig.17
BR24C04-W / F-W / FJ-W / FV-W
S
T
A
R
TSLAVE
ADDRESS
R
/
W
A
C
K
A
C
K
A
C
K
A
C
K
R
E
A
D
DATA(n) DATA(n+x)
SDA
LINE
110 0 A2 A1PS D7 D7D0 D0
S
T
O
P
Fig.18
• When an ACK signal LOW is detected after D0 and a stop condition is not sent from the master (µ-COM), the next
word address data can be read. [All words can be read]
• This command is ended by inputting a HIGH signal to the ACK signal after D0 and raising the SDA signal (stop
condition) using the SCL signal HIGH.
• Sequential reading can also be done with a random read.
BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /
Memory ICs BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
!
!!
!Operation notes
(1) During power rise
During power rise, the VCC may rise passing though the low voltage domain in which the IC internal circuit does not
work. For this reason, there is a risk of misoperation when the power rises without full IC internal reset.
To prevent this, pay attention to the following points during a power rise.
1) Set SCL = SDA = “HIGH”
2) Raise the power so as to active the Power On Reset (P. O. R) circuit.
Follow the steps below as to operate the P. O. R. circuit properly.
1) Set the power rise time (tR) to within 10ms.
2) Set the OFF domain for once power has been cut to 100mS minimum.
V
CC
t
OFF
t
R
(2) SDA terminal pull-up resistance
The SDA terminal is an open drain output. Consequently, it requires an external pull-up resistance. The
appropriate pull-up resistance value is selected from the IC VOL-IOL features., which have been appended as
measuring data, as well as VIL and ILI and other personal icons that control the IC in question.
Recommended values 2.0k to 10kW
Fig.19 V
OL
−I
OL
features (Note : Typ.)
2
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
001
Ta=25°C
345
Ta=85°CTa=−40°C
V
CC
=3.0V V
CC
=5.0V V
CC
=3.0V
OUTPUT VOLTAGE : VOL (V)
V
CC
=3.0V V
CC
=5.0V V
CC
=5.0V
OUTPUT CURRENT : IOL (mA)
Note : All memory array data are set to “FF” status at time of shipping.
BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /
Memory ICs BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
!
!!
!External dimensions (Units : mm)
DIP8
0.5 ± 0.1
3.2 ± 0.2 3.4 ± 0.3
85
14
9.3 ± 0.3
6.5 ± 0.3
0.3 ± 0.1
0.51Min.
2.54
0 ~ 15
7.62
BR24C01A-W
BR24C02-W
BR24C04-W
SOP8
0.15
0.3Min.
0.15 ± 0.1
0.4 ± 0.1
0.11
6.2 ± 0.3
4.4 ± 0.2
5.0 ± 0.2
85
41
1.27
1.5 ± 0.1
BR24C01AF-W
BR24C02F-W
BR24C04F-W
SSOP-B8
5
4
8
1
0.1
6.4 ± 0.3
4.4 ± 0.2
3.0 ± 0.2
0.22 ± 0.1
1.15 ± 0.1
0.65
(0.52)
0.15 ± 0.1
0.3Min.
0.1
BR24C01AFV-W
BR24C02FV-W
BR24C04FV-W
BR24C01AFJ-W
BR24C02FJ-W
BR24C04FJ-W
SOP-J8
0.1
0.45Min.
0.42 ± 0.1
4.9 ± 0.2
85
4123
1.27
76
0.2 ± 0.1
0.175
6.0 ± 0.3
3.9 ± 0.2
1.375 ± 0.1
