CY2XF24LXI625T - CYPRESS SEMICONDUCTOR

CY2XF24

High Performance L VPECL Oscillator with

Frequency Margining – I2C Control

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document Number: 001-53146 Rev. *F Revised September 21, 2011

Features

■Low jitter crystal oscillator (XO)

■Less than 1 ps typical root mean square (RMS) phase jitter

■Differential low-voltage positive emitter coupled logic

(LVPECL) output

■Output frequency from 50 MHz to 690 MHz

■Frequency margining through I2C bus

■Factory-configured or field-programmable

■Integrated phase-locked loop (PLL)

■Pb-free package: 5.0 × 3.2 mm leadless chip carrier (LCC)

■Supply voltage: 3.3 V or 2.5 V

■Commercial and industrial temperature ranges

Functional Description

The CY2XF24 is a high-performance and high-frequency XO. It

uses a Cypress-proprietary low-noise PLL to synthesize the

frequency from an integrated crystal. The output frequency can

be changed using the I2C bus serial interface, allowing easy

frequency margin testing in applications.

The CY2XF24 is available as a factory-configured device or as

a field-programmable device. Factory-configured devices are

configured for general use (see Standard and Appli-

cation-S pecific Factory Configurations) or they can be customer

specific.

Logic Block Diagram

PROGRAMMABLE

CONFIGURATION

OUTPUT

DIVIDER

SDA

CRYSTAL

OSCILLATOR LOW-NOISE

PLL

CLK

CLK#

SCL

I2C

INTERFACE

CY2XF24

Document Number: 001-53146 Rev. *F Page 2 of 17

Pinouts

Figure 1. Pin Diagram – 6 Pin Ceramic LCC

SDA

VSS

VDD

CLK

25CLK#SCLK

Table 1. Pin Definitions

Pin Name I/O Type Description

1SDAI/OI

2C serial data

2 SCLK CMOS input I2C serial clock

4, 5 CLK, CLK# LVPECL output Differential output clock

DD Power Supply voltage: 2.5 V or 3.3 V

SS Power Ground

CY2XF24

Document Number: 001-53146 Rev. *F Page 3 of 17

Contents

Standard and Application-Specific

Factory Configurations ....................................................4

Functional Description ................... ... ............................ ...4

Configuration Software ....................................................4

Programming Description ...............................................4

Field-Programmable CY2XF24F .................................4

Factory-Configured CY2XF24 .....................................5

Programming Variables ...................................................5

Output Frequencies .....................................................5

Industrial versus Commercial Device Performance ....5

Memory Map ......................... ............................ .................5

Serial Interface Protocol and Timing ........................ ...5

Device Address ...........................................................5

Data Valid ............................... .....................................5

Data Frame .................... ............................ ... ..............5

Acknowledge Pulse .....................................................6

Write Operations .............................................. .................6

Writing Individual Bytes ...............................................6

Writing Multiple Bytes ..................................................6

Read Operations ............... ... ............................ .................6

Current Address Read .................................................6

Random Read .............................................................6

Sequential Read ..........................................................6

Absolute Maximum Conditions .......................................8

Operating Conditions .......................................................8

DC Electrical Characteristics ............ ... ...........................8

AC Electrical Characteristics ...........................................9

I2C Bus Timing Specifications ......................................10

Typical Output Characteristics ............ .........................10

Measurement Definitions ...............................................12

Termination Circuits ....... ... ............................ ... ..............12

Ordering Information ......................................................13

Possible Configurations ........... ..................................13

Package Drawings and Dimensions .............................14

Acronyms ........................................................................15

Document Conventions ............... ... ............................ ...15

Units of Measure ........................ ... ............................15

Document History Page ......................................... ........16

Sales, Solutions, and Legal Information ......................17

Worldwide Sales and Design Support .......................17

Products .................................................................... 17

PSoC Solutions ....................... ... ............................ ...17

CY2XF24

Document Number: 001-53146 Rev. *F Page 4 of 17

Functional Description

The CY2XF24 is a PLL-based high-performance clock

generator. It uses an internal crystal oscillator as a reference,

and outputs one differential LVPECL clock. It has an I2C bus

serial interface[1], which is used to change the output frequency.

The CY2XF24 comes configured for four different frequencies.

At power-on, the four configurations are transparently loaded

into an internal volatile memory which, in turn, controls the PLL.

You can switch between the four frequencies through the I2C

bus. You can also configure the CY 2XF24 with new output

frequencies by shifting new data into the internal memory.

Frequency margining is a common application for this feature.

One frequency is used for the standard operating mode of the

device, while additional frequencies are available for margin

testing, either during product development or in-system

manufacturing test.

Note that all configuration changes made using I2C are

temporary and are lost when power is removed from the device.

At power-on, the device returns to its original state.

The configuration for a particular frequency is stored in a 6-byte

block of memory , known as a word. The CY2XF24 has four such

words, labeled ‘Frequency Word 0’ through ‘Frequency Word 3’.

An additional register byte contains a 2-bit field, which selects

one of the four frequency words. By writing to this Select Byte,

you can switch back and forth between the four programmed

frequencies. The select byte can be configured to select any of

the four frequency words at power on.

When changing the output frequency , the frequency transition is

not guaranteed to be smooth. There can be frequency

excursions beyond the start frequency and the new frequency.

Glitches and runt pulses are possible, and time must be allowed

for the PLL to relock.

If more than four frequencies are needed, the I2C Bus can be

used to change any of the four frequency words. Whe n writing

frequency words through I2C, you should not change the

currently selected word. Instead, write on e of the three

unselected words before changing the select byte to select that

new word.

Figure 2 shows how the frequency words are arranged and

selected.

Figure 2. Frequency Words

Configuration Software

Cypress provides CyClockWizard™ software that enables users

to create data values for shifting into the frequency words. This

software is required because the algorithm is too complicated to

be described here.

The user specifies the output frequency. The software then

calculates the bit stream for up to four frequency words, as

outlined by the register addresses for each word seen in

Figure 2.

Programming Description

The CY2XF24 is a programmable device. Before being used in

an application, it must be programmed with the output

frequencies and other variables described in Programming

Variables on page 5. Two different device types are available,

each with its own programming flow. They are described in the

following section.

Field-Programmable CY2 XF24F

Field programmable de vices are shipped unprogrammed and

must be programmed before being in stalled on a printed circuit

board (PCB). Customers use CyClockWizard™ Software to

specify the device configuration and generate a joint electron

devices engineering council (JEDEC - extension .jed)

programming file. Programming of samples and prototype

quantities is available using the CyClockWizard software along

with a CY3675-CLKMAKER1 CyClockMaker Clock Programmer

Kit with a CY3675-LCC6A socket adapter. Cypress’s value

added distribution partners also provide programming services.

Field programmable devices are designated with an ‘F’ in the

Standard and Application-Specific Factory Configurations

Part Number Output Frequency Frequency Word RMS Phase Jitter (Random)

Offset Range Jitter (Typical)

CY2XF24LXI625T 78.125 MHz

156.25 MHz

312.50 MHz

625.00 MHz (default)

1.875 MHz to 20 MHz

0.37 ps

0.31 ps

0.29 ps

0.31 ps

CY2XF24LXI009T 100 MHz (default)

156.25 MHz

350 MHz

400 MHz

12 kHz to 20 MHz

0.85 ps

0.76 ps

0.71 ps

0.69 ps

Note

1. The serial interface i s I2C Bus compliant, with the following exceptions: SDA input leakage current, SDA input capacitance, SDA and SCLK are clamped

to VDD, setup time, and output hold time.

10h – 15h Freque n cy W o rd 0

PLL

Freque n cy W o rd 1

Freque n cy W o rd 2

Freque n cy W o rd 3

16h – 1Bh

1Ch – 21h

22h – 27h

Select Byte40h

Bits [1:0]

Address

Sel

Control

CY2XF24

Document Number: 001-53146 Rev. *F Page 5 of 17

part number. They are intended for quick prototyping and

inventory reduction. The software and programmer kit hardware

can be downloaded from www.cypress.com by clicking the

hyperlinks above.

Factory-Configured CY2XF24

For ready-to-use devices, the CY2XF24 is available with no field

programming required. Pre-configured devices (see Standard

and Application-Specific Factory Configurations) are available

for samples or orders, or a request for a custom configuration

can be made. All requests are submitted to the local Cypress

field application engineer (FAE) or sales representative. After the

request is processed, the user receives a new part number,

samples, and datasheet with the programmed values. This part

number is used for additional sample requests and production

orders. The CY2XF24 is one-time programmable (OTP).

Programming Variables

Output Frequencies

The CY2XF24 is programmed with up to four independent output

frequencies, which are then selected using the I2C interface. The

device can synthesize frequencies to a resolution of 1 part per

million (ppm), but the actual accuracy of the output frequency is

limited by the accuracy of the integrated reference crystal.

The CY2XF24 has an output frequency range of 50 MHz to

690 MHz, but the range is not continuous. The CY2XF24 cannot

generate frequencies in the ranges of 521 MHz to 529 MHz, and

596 MHz to 617 MHz.

Industrial versus Commercial Device Performance

Industrial and commercial devices have different internal

crystals. They have a potentially significant impact on

performance levels for applications requiring the lowest possible

phase noise. CyClockWIzard software allows the user to select

between and view the expected performance of both options.

Memory Map

Five fields can be wri tten through the I2C bus. Four frequency

words define the output frequency . As shown in Table 3, each of

these words is a 6-byte field. When writing to a frequency word,

all six bytes should be written. They may be written either as

individual byte writes, or as a block write. The currently selected

frequency word should not be written to. All four words are

symmetrical, meaning that a 6-byte value that is valid for one

word is also valid for any of the other words, and produce the

same frequency.

The fifth field is the select byte, located at byte address 40h. The

value written into the two least significant bits determines the

active frequency word. The other bits of the byte are rese rved

and must be written with the values indicated in the table.

Users should never write to any address other than the 25 bytes

described here .

Serial Interface Protocol and Timing

The CY2XF24 uses pins SDA and SCLK for an I2C bus that

operates up to 100 kbits/sec in read or write mode. The

CY2XF24 is always a slave on this bus, meaning that it never

initiates a bus transaction. The basic write protocol is as follows:

Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock

Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit

Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in

MA+2; ACK; and so on, until STOP Bit. The basic serial format

is illustrated in Figure 4 on page 7.

Device Address

The device address is a 7-bit value. The default serial interface

address is 69H.

Data Valid

Data is va li d wh en the clock is HIGH, and may only be

transitioned when the clock is LOW as illustrated in Figure 5 on

page 7.

Data Frame

Every new data frame is indicated by a start and stop sequence,

as illustrated in Figure 6 on page 7.

START sequence - Start frame is indicated by SDA going LOW

when SCLK is HIGH. Every time a st art signal is given, the next

8-bit data must be the device address (seven bits) and a R/W bit,

followed by register address (eight bits) and register data (eight

bits).

STOP sequence - Sto p frame is indicated by SDA going HIGH

when SCLK is HIGH. A stop frame frees the bus for writing to

another part on the same bus or writing to another random

Table 2. Device Programming Variables

Variable

Output frequency 0

Output frequency 1

Output frequency 2

Output frequency 3

Temperature range (commercial or industrial)

Table 3. Frequen cy Words

Frequency

Word Byte Addresses

(hex) Word Sel ect

(Select Byte 40h)

0 10h to 15h 00

1 16h to 1Bh 01

2 1Ch to 21h 10

3 22h to 27h 11

Table 4. Register 40h: Select Byte

Bits Default

Value

(binary) Name Description

7:2 000000 Reserved Reserved. Always write this value

1:0 User-

defined Word

Select Selects the Frequency Word to

determine the output frequency.

00 selects Wo rd 0; 01 select s

Word 1; 10 selects Word 2; 11

selects Word 3

CY2XF24

Document Number: 001-53146 Rev. *F Page 6 of 17

Acknowledge Pulse

During write mode, the CY2XF24 responds with an

Acknowledge (ACK) pulse after every eight bits. This is

accomplished by pulling the SDA line LOW during the N*9th clock

cycle as illustrated in Figure 7 on page 8. (N = the number of

bytes transmitted). After the data packet is sent during read

mode, the master generates the acknowledge.

Write Operations

Writing Individual Bytes

A valid write operation must have a full 8-bit registe r address

after the device address word from the master , which is followed

by an acknowledge bit from the slave (SDA = 0/LOW). The next

eight bits must contain the data word intended for storage. After

the data word is received, the slave responds with another

acknowledge bit (SDA = 0/LOW), and the master must end the

write sequence with a STOP condition.

Writing Multiple Bytes

To write more than one byte at a time, the master does not end

the write sequence with a stop condition. Instead, the master can

send multiple contiguous bytes of data to be stored. After each

byte, the slave responds with an acknowledge bit, just like after

the first byte, and accept data until the acknowledge bit is

responded to by the STOP condition. When receiving multi ple

bytes, the CY2XF24 internally increments the register address.

Read Operations

Read operations are initiated the same way as write operations

except that the R/W bit of the slave address is set to ‘1’ (HIGH).

There are three basic read operations: current address read,

random read, and sequential read.

Current Address Read

The CY2XF24 has an onboard address counter that retains 1

more than the address of the last word access. If the last word

written or read was word ‘n’, then a current address read

operation would return the value stored in location ‘n+1’. When

the CY2XF24 receives the slave address with the R/W bit set to

a ‘1’, the CY2XF24 issues an acknowledge and transmits the

8-bit word. The master device does not acknowledge the

transfer , but does generate a STOP condition, which causes the

CY2XF24 to stop transmission.

Random Read

Through random read operations, the master may access any

memory location. To perform this type of read operation, first the

word address must be set. This is accomplished by sending the

address to the CY2XF24 as part of a write op e r a ti o n. After the

word address is sent, the master generates a START condition

following the acknowledge. This terminates the write operation

before any data is stored in the address, but not before the

internal address pointer is set. Next the master reissues the

control byte with the R/W byte set to ‘1’. The CY2XF24 then

issues an acknowledge and transmits the 8-bit word. The master

device does not acknowledge the transfer , but does generate a

STOP condition which causes the CY2XF24 to stop

transmission.

Sequential Read

Sequential read operations follow the same process as random

reads except that the master issues an acknowledge instead of

a STOP co nd i ti o n a fter transmission of th e first 8-bit d a ta word.

This action results in an incrementing of the internal address

pointer , and subsequently output of the next 8-bit data word. By

continuing to issue acknowledges instead of STOP conditions,

the master may serially read the entire contents of the slave

device memory. When the internal address pointer points to the

FFh register, after the next increment, th e pointer points to the

00h register.

Figure 3. Data Transfer Sequ ence on the Serial Bus

SCLK

START

Condition

SDA

STOP

Data may Address or

Acknowledge

Valid be changed Condition

CY2XF24

Document Number: 001-53146 Rev. *F Page 7 of 17

Figure 4. Data Frame Architecture

Figure 5. Data Valid and Data Transition Periods

Figure 6. Start and Stop Frame

SDA Write

Start Signal

Device

Address

7-bit

R/W = 0

1 Bit

8-bit

Address

Slave

1 Bit

ACK Slave

1 Bit

ACK

8-bit

Data

Stop Signal

Multiple

Contiguous

Registers

Slave

1 Bit

ACK

8-bit

Data

(XXH) (XXH) (XXH+1)

Slave

1 Bit

ACK

8-bit

Data

(XXH+2)

Slave

1 Bit

ACK

8-bit

Data

(FFH)

Slave

1 Bit

ACK

8-bit

Data

(00H)

Slave

1 Bit

ACK Slave

1 Bit

ACK

SDA Read

Start Signal

Device

Address

7-bit

R/W = 1

1 Bit

8-bit

Data

Slave

1 Bit

ACK Slave

1 Bit

ACK

Stop Signal

SDA Read

Start Signal

Device

Address

7-bit

R/W = 0

1 Bit

8-bit

Address

Slave

1 Bit

ACK Slave

1 Bit

ACK

7-bit

Device

Stop Signal

Multiple

Contiguous

Registers

Master

1 Bit

ACK

8-bit

Data

Master

1 Bit

ACK

(XXH) (XXH)

Master

1 Bit

ACK

8-bit

Data

(XXH+1)

Master

1 Bit

ACK

8-bit

Data

(FFH)

Master

1 Bit

ACK

8-bit

Data

(00H)

Master

1 Bit

ACK Master

1 Bit

ACK

Current

Address

Read

Address

+R/W=1

Repeated

Start bit

SDA

SCLK

Data Valid Transition

to next Bit

CLK

LOW

CLK

HIGH

VIH

VIL

SDA

SCLK

START Transition

to next Bit STOP

CY2XF24

Document Number: 001-53146 Rev. *F Page 8 of 17

Figure 7. Frame Format (Device Address, R/W, Register Address, Register Data)

SDA

SCLK

DA6 DA5 DA0 R/W ACK RA7 RA6 RA1 RA0 ACK STOP

START ACK D7 D6 D1 D0

+++

Notes

2. The voltage on any input or IO pin cannot exceed the power pin during power up.

3. Simulated. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1 / 2 oz .). Th e int e rn a l layer s

are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.

4. IDD includes ~24 mA of current that is dissipated externally in the output termination re sistors.

Absolute Maximum Conditions

Parameter Description Condition Min Max Unit

VDD Supply voltage –0.5 4.4 V

VIN[2] Input voltage, DC Relative to VSS –0.5 VDD+0.5 V

TSTemperature, storage Non Operating –55 135 °C

TJTemperature, junction –40 135 °C

ESDHBM Electrostatic discharge (ESD) protection

human body model (HBM) JEDEC STD 22 -A114- B 2000 – V

JA[3] Thermal resistance, junction to ambient 0 m/s airflow 64 °C/W

Operating Conditions

Parameter Description Min Typ Max Unit

VDD 3.3-V supply voltage range 3.135 3.3 3.465 V

2.5-V supply voltage range 2.375 2.5 2.625 V

TPU Power-up time for VDD to reach minimum specified voltage (power ramp is

monotonic) 0.05 – 500 ms

TAAmbient temperature (commercial) 0 – 70 °C

Ambient temperature (industrial) –40 – 85 °C

DC Electrical Characteristics

Parameter Description Condition Min Typ Max Unit

IDD[4] Operating supply current VDD = 3.465 V, CLK = 150 MHz, output

terminated – – 150 mA

VDD = 2.625 V, CLK = 150 MHz, output

terminated – – 145 mA

VOH LVPECL high output voltage VDD = 3.3 V or 2.5 V, RTERM = 50  to

VDD – 2.0 V VDD – 1.15 – VDD –

0.75 V

VOL LVPECL low output voltage VDD = 3.3 V or 2.5 V, RTERM = 50  to

VDD – 2.0 V VDD – 2.0 – VDD –

1.625 V

VOD1 LVPECL output voltage swing

(VOH - VOL)VDD = 3.3 V or 2.5 V, RTERM = 50 to

VDD – 2.0 V 600 – 1000 mV

VOD2 LVPECL output voltage swing

(VOH - VOL)VDD = 2.5 V, RTERM = 50  to VDD –

1.5 V 500 – 1000 mV

VOCM LVPECL output common mode

voltage (VOH + VOL)/2 VDD = 2.5 V, RTERM = 50  to VDD –

1.5 V 1.2 – – V

CY2XF24

Document Number: 001-53146 Rev. *F Page 9 of 17

VOLS Output low voltage (SDA) IOL = 4 mA – – 0.1*VDD V

VIH Input high voltage 0.7*VDD –– V

VIL Input low voltage – – 0.3*VDD V

IIH0 Input high current (SDA) Input = VDD ––115A

IIH1 Input high current (SCLK) Input = VDD ––10A

IIL0 Input low current (SDA) Input = VSS –50 – – A

IIL1 Input low current (SCLK) Input = VSS –20 – – A

CIN0[5] Input capacitance (SDA) – 15 – pF

CIN1[5] Input capacitance (SCLK) – 4 – pF

DC Electrical Characteristics (continued)

Parameter Description Condition Min Typ Max Unit

Notes

5. Not 100% tested, guaranteed by design and characterization.

6. This parameter is specified in CyClockMaker software.

7. Frequency stability is the maximum variation in frequency from F0. It includes initial accuracy, plus variation from temperature and supply voltage.

8. Typical phase noise specs for factory programmed devices are listed in the Standard and App lication-Specific Factory Configurations t able on page 2.

AC Electrical Characteristics[5]

Parameter Description Condition Min Typ Max Unit

FOUT Output frequency[6] 50 – 690 MHz

FSC Frequency stability, commercial

devices[7] TA = 0 °C to 70 °C – – ±35 ppm

FSI Frequency stability, industrial

devices[7] TA = –40 °C to 85 °C – – ±55 ppm

AG Aging, 10 years – – ±15 ppm

TDC Output duty cycle F <= 450 MHz, measured at zero

crossing 45 50 55 %

F > 450 MHz, measured at zero

crossing 40 50 60 %

TR, TFOutput rise and fall time 20% and 80% of full output swing 0.2 0.4 1.0 ns

TLOCK Startup time Time for CLK to re ach valid frequency

measured from the time VDD =

VDD(min)

––10ms

TLSER Relock time Time for CLK to re ach valid frequency

from serial bus change to select bits in

––10ms

TJitter()RMS phase jitter (random) FOUT = 106.25 MHz (12 kHz to 20 MHz) – 1 – ps

Pre-defined factory configurations[8] See Note 8 ps

CY2XF24

Document Number: 001-53146 Rev. *F Page 10 of 17

Typical Output Characteristics

Figure 8. 2.5-V Supply and Terminatio n to VDD–1.5 V, minimum VDD and maximum TA

I2C Bus Timing Specifications

The I2C Bus Timing Specificati ons for part CY2XF24 are as follows [5]

Parameter Description Min Max Unit

fSCLK SCLK frequency – 100 kHz

tHD:STA Start mode time from SDA LOW to SCLK LOW 4 – s

tLOW SCLK LOW period 4.7 – s

tHIGH SCLK HIGH period 4–s

tSU:DAT In put data setup (SDA transition to SCLK rising edge ) 1000 – ns

tHD:DAT Input data hold (SCLK falling edge to SDA transition) 0 – ns

tHD:DO Output data hold (SCLK falling edge to SDA transiti on) 200 – ns

tSR Rise time of SCLK and SDA – 300 ns

tSF Fall time of SCLK and SDA – 300 ns

tSU:STO Stop mode time from SCLK HIGH to SDA HIGH 4 – s

tBUF Stop mode to Start mode 4.7 – s

1.20

1.25

1.30

1.35

1.40

0 100 200 300 400 500 600 700

F requency (MHz)

VOCM (V)

0.4

0.5

0.6

0.7

0.8

0.9

0 100 200 300 400 500 600 700

F r equency ( M Hz)

Swing (V)

CY2XF24

Document Number: 001-53146 Rev. *F Page 11 of 17

Figure 9. 2.5-V Sup ply and Terminat io n to VDD–2 V, minimum VDD and maximum TA

Figure 10. 3.3-V Supply and Termination to VDD–2 V, minimum VDD and maximum TA

0.70

0.75

0.80

0.85

0.90

0 100 200 300 400 500 600 700

F requency (MHz)

VOCM (V )

0.4

0.5

0.6

0.7

0.8

0.9

0 100 200 300 400 500 600 700

F requenc y (M Hz)

Swing (V)

0.4

0.5

0.6

0.7

0.8

0.9

0 100 200 300 400 500 600 700

Frequency (MHz)

Swing (V)

1.40

1.45

1.50

1.55

1.60

0 100 200 300 400 500 600 700

Frequency (MHz)

VOCM (V)

CY2XF24

Document Number: 001-53146 Rev. *F Page 12 of 17

Measurement Definitions

Figure 11. Ou tput DC Parameters

Figure 12. Duty Cycle Timing

Figure 13. Outp ut Rise an d Fa ll Time

Termination Circuits

Figure 14. LVPECL Termination

CLK VA

CLK# VOD VOCM = (V A + VB)/2

CLK

TPW

TPERIOD

TDC = TPW

TPERIOD

CLK#

20%

80%

CLK 20%

80%

CLK#



BUF

CLK 

VDD - 2V

(VD D = 3.3V )

CLK#



BUF

CLK 

VDD - 2V or VDD - 1.5V

(VDD = 2.5V)

CY2XF24

Document Number: 001-53146 Rev. *F Page 13 of 17

Some product offerings are factory-programmed customer-specific devices with customized part numbers. The Possible

Configurations table shows the available device types, but not complete part numbers. Contact your local Cypress FAE or sales

representative for more information.

Possible Configurations

Ordering Code Definitions

Ordering Information

Part Number Configuration Package Description Product Flow

Pb-free

CY2XF24FLXCT Field-programmable 6-pin ceramic LCC surface mount device

(SMD) - tape and reel Commercial, 0 °C to 70 °C

CY2XF24FLXIT Field-programmable 6-pin ceramic LCC SMD - tape and reel Industrial, –40 °C to 85 °C

CY2XF24LXI625T[9] Factory-Configured 6-pin ceramic LCC SMD - tape and reel Industrial, –40 °C to 85 °C

CY2XF24LXI009T[9] Factory-Configured 6-pin ceramic LCC SMD - tape and reel Industrial, –40 °C to 85 °C

Part Number[10] Configuration Package Description Product Flow

Pb-free

CY2XF24LXCxxxT Factory-configured 6-pin ceramic LCC SMD - tape and reel Commercial, 0 °C to 70 °C

CY2XF24LXIxxxT Factory-configured 6-pin ceramic LCC SMD - tape and reel Industrial, –40 °C to 85 °C

Base part number

2XF24

Company ID : CY = Cypress

Field programmable device

6-pin LCC package

LX C/I

C = Commercial

I = Industrial

Tape and Reel

XXX

Custom part configuration code

Notes

9. Device configuration details are described in the Standard and Application-Specific Factory Configurations tabl e o n page 2.

10.“xxx” indicates factory programmed parts based on customer specific configuration. For more details, contact your local Cypress FAE or Sales Representative.

CY2XF24

Document Number: 001-53146 Rev. *F Page 14 of 17

Package Drawings and Dimensions

Figure 15. 6-Pin 3.2 × 5.0 mm Ceramic LCC LZ06A

001-10044 *B

CY2XF24

Document Number: 001-53146 Rev. *F Page 15 of 17

Acronyms

Document Conventions

Units of Measure

Table 5. Acronyms Used in this Document

Acronym Description

ESD electrostatic discharge

FAE field application engineer

HBM human body model

JEDEC joint electron devices engineering council

LCC leadless chip carrier

LVDS Low-voltage differential signaling

OE output enable

PCB printed circuit board

PLL phase-locked loop

RMS root mean square

XO crystal oscillator

Symbol Unit of Measure

°C degree Celsius

µs microseconds

µA microamperes

mA milliamperes

mm millimeter

ms milliseconds

mV millivolts

kHz kilohertz

MHz megahertz

ns nanoseconds

pF picofarads

ps picoseconds

ppm parts per million

Vvolts

Wwatts

%percent

ohms

CY2XF24

Document Number: 001-53146 Rev. *F Page 16 of 17

Document History Page

Document Title: CY2XF24 High Performance LVPECL Oscillator with Frequency Margining – I2C Control

Document Number: 001-53146

Revision ECN Orig. of

Change Submission

Date Description of Change

** 2704379 KVM/PYRS 05/11/09 New datasheet

*A 2718898 WWZ 06/15/09 Minor ECN to post datasheet to external web

*B 2761926 KVM 09/10/09 Revised maximum output rise and fall times

*C 2896548 KVM 03/19/10 Moved parts with ‘xxx’ into new table, Possible Configurations

Updated package diagram

*D 2973338 CXQ 07/08/10 Added Standard and Application-Specific Factory Configurations table on

page 2.

Added phase jitter specs for pre-defined configurations into the AC Electrical

S pecifications table (note 8 refers users to the new table on page 2 for typical

specs).

Added CY2XF24LXI625T device to the Ordering Information table and added

note 9 to reference the configuration description of the new device.

Changed all references to CyberClocksOnline software to CyClockWizard.

Removed section on phase noise vs jitter SW optimization.

Changed description of Word Select feature from default Word 0 to

user-defined.

*E 3183855 BASH 05/06/11 Updated template as per current Cypress standards.

Added Units table.

Changed status from Preliminary to Final.

*F 3373963 PURU 09/21/11 Updated S t andard and Application-S pecific Factory Configurations on page 4

and Package Drawings and Dimensions on page 14.

Added new MPN CY2XF24LXI009T.

Document Number: 001-53146 Rev. *F Revised September 21, 2011 Page 17 of 17

All products and company names mentioned in this document may be the trademarks of their respective holders.

CY2XF24

© Cypress Semico nducto r Co rpor ation , 20 09-2 011. The information cont ai ned he rein is subj ect to chang e with out no tice. Cypr ess Semiconductor Corporation assumes no responsibility for the use of

any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypre ss pro duc ts are n ot war ran ted no r int end ed to be us ed for

medical, life supp or t, l if e savin g, cr it ical control or saf ety ap pl ic at io ns, unless pursuant to a n exp re ss wri tte n ag reement with Cypress. Furthermore, Cyp ress doe s not author i ze its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protec tion (Unit ed States and fore ign),

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and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product t o be used only in conju nction with a Cypress

integrated circui t as specified in the applicab le agreement. Any r eproduction, mod ification, translati on, compilatio n, or represent ation of this Sour ce Code except a s specified abo ve is prohibit ed without

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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

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a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

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