H57V1262GFR-50I - SK Hynix - Product.Network

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev. 1.0 / Aug. 2009 1

128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O

Document Title

4Bank x 2M x 16bits Synchronous DRAM

Revision History

Revision No. History Draft Date Remark

0.1 Initial Draft Jul. 2009 Preliminary

1.0 Release Aug. 2009

Rev. 1.0 / Aug. 2009 2

Synchronous DRAM Memory 128Mbit (8Mx16bit)

H57V1262GFR Series

DESCRIPTION

The Hynix H57V1262GFR series is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the memory applica-

tions which require wide data I/O and high bandwidth. H57V1262GFR series is organized as 4banks of 2,097,152 x 16.

H57V1262GFR is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs

are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high

bandwidth. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write

cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(se-

quential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or

can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not re-

stricted by a '2N' rule)

FEATURES

● This product is in compliance with the directive pertaining of RoHS.

ORDERING INFORMATION

1. H57V1262GFR-XXC Series: Normal power, Commercial Temp.(0oC to 70oC)

2. H57V1262GFR-XXI Series: Normal power, Industrial Temp. (-40oC to 85oC)

3. H57V1262GFR-XXL Series: Low power, Commercial Temp.(0oC to 70oC)

4. H57V1262GFR-XXJ Series: Low power, Industrial Temp. (-40oC to 85oC)

Part No. Clock Frequency Organization Interface Package

H57V1262GFR-50X 200MHz

4Banks x 2Mbits

x16 LVTTL 54 Ball FBGA

H57V1262GFR-60X 166MHz

H57V1262GFR-70X 143MHz

H57V1262GFR-75X 133MHz

• Voltage: VDD and VDDQ 3.3V supply voltage

• All device pins are compatible with LVTTL interface

• 54 Ball FBGA (Lead or Lead Free Package)

• All inputs and outputs referenced to positive edge of

system clock

• Data mask function by UDQM, LDQM

• Internal four banks operation

• Auto refresh and self refresh

• 4096 Refresh cycles / 64ms

• Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

• Programmable CAS Latency; 2, 3 Clocks

• Burst Read Single Write operation

• Operation temperature

HY5V26F(L)F(P)-XX Series: 0 ~ 70oC

HY5V26F(L)F(P)-X(I) Series: -40 ~ 85oC

Rev. 1.0 / Aug. 2009 3

Synchronous DRAM Memory 128Mbit (8Mx16bit)

H57V1262GFR Series

BALL CONFIGURATION

54 Ball

FBGA

0.8mm

Ball Pitch

987321

54 Ball

FBGA

0.8mm

Ball Pitch

987321

VSS

DQ14

DQ12

DQ10

DQ8

UDQM

VSS

DQ15

DQ13

DQ11

DQ9

CLK

A11

VSSQ

VDDQ

VSSQ

VDDQ

VSS

CKE

VDDQ

VSSQ

VDDQ

VSSQ

VDD

/CAS

BA0

DQ0

DQ2

DQ4

DQ6

LDQM

/RAS

BA1

VDD

DQ1

DQ3

DQ5

DQ7

/WE

/CS

A10

VDD

1 2 3 7 8 9

< Top View >

Rev. 1.0 / Aug. 2009 4

Synchronous DRAM Memory 128Mbit (8Mx16bit)

H57V1262GFR Series

FUNCTIONAL BLOCK DIAGRAM

2Mbit x 4banks x 16 I/O Synchronous DRAM

Internal Row

Counter

Column

Pre

Decoder

Column Add

Counter

Self refresh

logic & timer

Sense AMP & I/O Gate

I/O Buffer & Logic

Address

Counter

Mode Register

State Machine Address Buffers

Bank Select

Column

Active

Row Active

CAS Latency

CLK

CKE

RAS

CAS

U/LDQM

BA1

BA0

A11

Row

Pre

Decoder

Refresh

DQ0

DQ15

X-Decoder

Y-Decoder

2Mx16 BANK 0

2Mx16 BANK 1

2Mx16 BANK 2

2Mx16 BANK 3

Memory

Cell

Array

Data Out Control

Pipe Line

Control

Rev. 1.0 / Aug. 2009 5

Synchronous DRAM Memory 128Mbit (8Mx16bit)

H57V1262GFR Series

BASIC FUNCTIONAL DESCRIPTION

Mode Register

BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0000 OP Code 00 CAS Latency BT Burst Length

OP Code

A9 Write Mode

0Burst Read and Burst Write

1 Burst Read and Single Write

Burst Type

A3 Burst Type

0 Sequential

1 Interleave

Burst Length

A2 A1 A0 Burst Length

A3 = 0 A3=1

00 0 11

00 1 22

01 0 4 4

01 1 88

10 0 Reserved Reserved

10 1 Reserved Reserved

1 10 Reserved Reserved

1 11 Full Page Reserved

CAS Latency

A6 A5 A4 CAS Latency

0 0 0 R e s e r v e d

0 0 1 1

0 1 0 2

0 1 1 3

1 0 0 Reserved

1 0 1 R e s e r v e d

1 1 0 R e s e r v e d

1 1 1 Reserved

Rev. 1.0 / Aug. 2009 6

Synchronous DRAM Memory 128Mbit (8Mx16bit)

H57V1262GFR Series

ABSOLUTE MAXIMUM RATING

Notes:

1. Commercial (0 ~ 70oC)

2. Industrial (-40 ~ 85oC)

DC OPERATING CONDITION

Notes:

1. All voltages are referenced to VSS = 0V

2. VIH(max) is acceptable 5.6V AC pulse width with <=3ns of duration.

3. VIL(min) is acceptable -2.0V AC pulse width with <=3ns of duration

AC OPERATING TEST CONDITION (VDD=3.3±0.3V, VSS=0V)

Note: 1.

Parameter Symbol Rating Unit Note

Ambient Temperature TA 0 ~ 70oCoC1

-40 ~ 85oCoC2

Storage Temperature TSTG -55 ~ 125 oC

Voltage on Any Pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V

Voltage on VDD relative to VSS VDD, VDDQ -1.0 ~ 4.6 V

Short Circuit Output Current IOS 50 mA

Power Dissipation PD1W

Soldering Temperature / Time TSOLDER 260 / 10 oC / Sec

Parameter Symbol Min. Typ Max Unit Note

Power Supply Voltage VDD, VDDQ 3.0 3.3 3.6 V 1

Input High Voltage VIH 2.0 3.0 VDDQ + 0.3 V 1, 2

Input Low Voltage VIL -0.3 - 0.8 V 1, 3

Parameter Symbol Value Unit Note

AC Input High / Low Level Voltage VIH / VIL 2.4 / 0.4 V

Input Timing Measurement Reference Level Voltage Vtrip 1.4 V

Input Rise / Fall Time tR / tF 1 ns

Output Timing Measurement Reference Level Voltage Voutref 1.4 V

Output Load Capacitance for Access Time Measurement CL 50 pF 1

Z0 = 50 Output Output

Vtt = 1.4V

50pF

RT = 50

Vtt = 1.4V

50pF

DC Output Load Circuit AC Output Load Circuit

RT = 500

Ω

Rev. 1.0 / Aug. 2009 7

Synchronous DRAM Memory 128Mbit (8Mx16bit)

H57V1262GFR Series

CAPACITANCE (f=1MHz, VDD=3.3V)

DC CHARACTERISTICS I

Notes:

1. VIN = 0 to 3.3V, All other balls are not tested under VIN =0V

2. DOUT is disabled, VOUT=0 to 3.6

Parameter Pin Symbol Min Max Unit

Input capacitance

CLK CI1 2.0 4.0 pF

A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS,

WE, LDQM, UDQM CI2 2.0 4.0 pF

Data input / output capacitance DQ0 ~ DQ15 CI/O 3.0 5.5 pF

Parameter Symbol Min Max Unit Note

Input Leakage Current ILI -1 1 uA 1

Output Leakage Current ILO -1 1 uA 2

Output High Voltage VOH 2.4 - V IOH = -2mA

Output Low Voltage VOL -0.4VIOL = +2mA

Rev. 1.0 / Aug. 2009 8

Synchronous DRAM Memory 128Mbit (8Mx16bit)

H57V1262GFR Series

DC CHARACTERISTICS II

Notes:

1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open

2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II

3. H57V1262GTR-XXC Series: Normal Power

H57V1262GTR-XXL Series: Low Power

Parameter Symbol Test Condition Speed Unit Note

5 6 7 H

Operating Current IDD1

Burst length=1, One bank active

tRC ≥ tRC(min), IOL=0mA 100807070mA1

Precharge Standby Current

in Power Down Mode

IDD2P CKE ≤ VIL(max), tCK = 15ns 2 mA

IDD2PS CKE ≤ VIL(max), tCK = ∞ 2mA

Precharge Standby Current

in Non Power Down Mode

IDD2N

CKE ≥ VIH(min), CS ≥ VIH(min), tCK =

15ns

Input signals are changed one time

during 2clks.

All other pins ≥ VDD-0.2V or ≤ 0.2V

IDD2NS

CKE ≥ VIH(min), tCK = ∞

Input signals are stable. 15

Active Standby Current

in Power Down Mode

IDD3P CKE ≤ VIL(max), tCK = 15ns 5 mA

IDD3PS CKE ≤ VIL(max), tCK = ∞ 5

Active Standby Current

in Non Power Down Mode

IDD3N

CKE ≥ VIH(min), CS ≥ VIH(min), tCK =

15ns

Input signals are changed one time

during 2clks.

All other pins ≥ VDD-0.2V or ≤ 0.2V

IDD3NS

CKE ≥ VIH(min), tCK = ∞

Input signals are stable. 35

Burst Mode Operating Cur-

rent IDD4

tCK ≥ tCK(min), IOL=0mA

All banks active 120 100 100 100 mA 1

Auto Refresh Current IDD5 tRC ≥ tRC(min), All banks active 210 200 190 190 mA 2

Self Refresh Current IDD6 CKE ≤ 0.2V

Normal 2 mA

Low

power 800 uA

Rev. 1.0 / Aug. 2009 9

Synchronous DRAM Memory 128Mbit (8Mx16bit)

H57V1262GFR Series

AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)

Notes:

1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.

2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns,

then (tR/2-0.5)ns should be added to the parameter.

Parameter Sym-

bol

5 6 7 H

Unit Note

Min Max Min Max Min Max Min Max

System Clock Cycle Time

CL = 3 tCK3 5.0

1000

6.0

1000

7.0

1000

7.5

1000

CL = 2 tCK2 ---10ns

Clock High Pulse Width tCHW 1.75-2.0-2.0-2.5- ns 1

Clock Low Pulse Width tCLW 1.75-2.0-2.0-2.5- ns 1

Access Time From Clock

CL = 3 tAC3 -4.5-5.4-5.4-5.4ns

CL = 2 tAC2 -------6.0ns

Data-out Hold Time tOH 2.0 - 2.0 - 2.5 - 2.7 - ns

Data-Input Setup Time tDS 1.5 - 1.5 - 1.5 - 1.5 - ns 1

Data-Input Hold Time tDH 0.8 - 0.8 - 0.8 - 0.8 - ns 1

Address Setup Time tAS 1.5 - 1.5 - 1.5 - 1.5 - ns 1

Address Hold Time tAH 0.8 - 0.8 - 0.8 - 0.8 - ns 1

CKE Setup Time tCKS 1.5 - 1.5 - 1.5 - 1.5 - ns 1

CKE Hold Time tCKH 0.8 - 0.8 - 0.8 - 0.8 - ns 1

Command Setup Time tCS 1.5 - 1.5 - 1.5 - 1.5 - ns 1

Command Hold Time tCH 0.8 - 0.8 - 0.8 - 0.8 - ns 1

CLK to Data Output in Low-Z Time tOLZ 1.0 - 1.0 - 1.5 - 1.5 - ns

CLK to Data Output

in High-Z Time

CL = 3 tOHZ3 -4.5-5.4-5.4-5.4ns

CL = 2 tOHZ2 -------6.0ns

Rev. 1.0 / Aug. 2009 10

Synchronous DRAM Memory 128Mbit (8Mx16bit)

H57V1262GFR Series

AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)

Note:

1. A new command can be given tRRC after self refresh exit.

Parameter Symbol

5 6 7 H Uni

Not

Min Max Min Max Min Max Min Max

RAS Cycle Time Operation tRC 55 - 60 - 63 - 63 - ns

RAS Cycle Time Auto

Refresh tRRC 55 - 60 - 63 - 63 - ns

RAS to CAS Delay tRCD 15 - 18 - 20 - 20 - ns

RAS Active Time tRAS 38.7 100K 42 100K 42 100K 42 120

Kns

RAS Precharge Time tRP 15 - 18 - 20 - 20 - ns

RAS to RAS Bank Active Delay tRRD 10 - 12 - 14 - 15 - ns

CAS to CAS Delay tCCD 1-1-1-1-CLK

Write Command to

Data-In Delay tWTL 0 -0 -0 -0 -CLK

Data-in to Precharge Command tDPL 2-2-2-2-CLK

Data-In to Active Command tDAL tDPL + tRP

DQM to Data-Out Hi-Z tDQZ 2-2-2-2-CLK

DQM to Data-In Mask tDQM 0-0-0-0-CLK

MRS to New Command tMRD 2-2-2-2-CLK

Precharge to Data

Output High-Z

CL = 3 tPROZ3 3-3-3-3-CLK

CL = 2 tPROZ2 ------2-CLK

Power Down Exit Time tDPE 1-1-1-1-CLK

Self Refresh Exit Time tSRE 1-1-1-1-CLK1

Refresh Time tREF -64-64-64-64ms

Rev. 1.0 / Aug. 2009 11

Synchronous DRAM Memory 128Mbit (8Mx16bit)

H57V1262GFR Series

COMMAND TRUTH TABLE

Command CKEn-1 CKEn CS RAS CAS WE DQM ADDR A10/AP BA Note

Mode Register Set H X L L L L X OP code

No Operation H X

HX XX

LHHH

Bank Active H X L L H H X RA V

Read

HXLHLHXCA

Read with Autoprecharge H

Write

HXLHLLXCA

Write with Autoprecharge H

Precharge All Banks

HXLLHLXX

Precharge selected Bank LV

Burst Stop H X L H H L X X

DQM H X V X

Auto Refresh H H L L L H X X

Burst-Read-Single-WRITE H X L L L L X A9 ball High

(Other balls OP code)

MRS

Mode

Self Refresh1

Entry H L L L L H X

Exit L H

HX XX

LHHH

Precharge

power down

Entry H L

HX XX

LHHH

Exit L H

HX XX

LHHH

Clock Suspend

Entry H L

HX XX

XLVVV

Exit L H X X

Rev. 1.0 / Aug. 2009 12

Synchronous DRAM Memory 128Mbit (8Mx16bit)

H57V1262GFR Series

PACKAGE INFORMATION

54 Ball FBGA 8.0mm x 8.0mm

Unit

[mm]

0.8±0.1

Bottom

View

0.35

+0.025/- 0.05

0.80 Typ.

0.80

Typ. 1.0 max

0.45

+/- 0.05

A1 INDEX MARK

1.60

8.00

Typ.

0.8±

0.1

8.00 Typ.

6.4