This is information on a product in full production.
March 2014 DocID025317 Rev 2 1/17
STA333SML
2-channel microless high-efficiency digital audio system
Sound Terminal®
Datasheet - production data
Features
Wide-range supply voltage (4.5 V - 18 V)
2 channels of ternary PWM (stereo mode)
2 channels of 24-bit FFXTM
100 dB SNR and dynamic range
Digital gain +24dB
Sample rates (fs) from 32 to 48 kHz
Fixed MCLK at 256 x fs
Automatic zero-detect mute
Automatic invalid input detect mute
Short-circuit detection at startup (Out-VCC,
Out-Gnd, Out 1b-Out 2a)
2-channel I²S input data interface
2 Hz DC cut filter (input)
96 kHz internal processing sample rate, 24-b it
precision
Embedded thermal-ove rload and short-circuit
protection
Applications
LCDs
DVDs
Cradles
Digital speakers
Wireless-speaker cradles
Description
The STA333SML is an integrated circuit
comprising digital audio processing, digital
amplifier control and an FFX power output stage
to create a high-power, single-chip FFX solution
for all-digital amplification with high quality and
high efficiency.
The STA333SML power section consists of four
independent half-bridge stages. Two channels
can be provided by two full bridges, providing up
to 10 W + 10 W of power.
Also featured in the STA3 33 SM L are ne w
advanced modes for AM radio interference
reduction. The serial audio data input interface
accepts the popular I²S format. Two channels of
FFXTM processing are pr ovided.
The STA333SML is part of the Sound Terminal®
family that provides full digital audio streaming to
the speaker, offering cost effectiveness, low-
power dissipation and so un d enri chm e nt .
CSP 5 x 6 array
Table 1. Devi ce summary
Order code Package Packaging
STA333SML CSP 5x6 array Tube
STA333SMLTR CSP 5x6 array Tape and reel
www.st.com
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Contents STA333SML
2/17 DocID025317 Rev 2
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.4 Electrical specifications - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.5 Electrical specifications - power section . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.6 Power-off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.7 Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.8 Serial audio interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.8.1 Serial audio interface protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.9 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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STA333SML Block diagram
17
1 Block diagram
Figure 1. Block diagram
Protection
current/thermal
Logic
Regulators
Bias
Power
control
FFX
PLL
Volume
control
Channel
1A
Channel
1B
Channel
2A
Channel
2B
I²S
interface
PowerDigital DSP
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Pin description STA333SML
4/17 DocID025317 Rev 2
2 Pin description
2.1 Pinout
Figure 2. Pin connections (pack age top view)
12345
A
GND1 OUT1A
BGND1 VCC1 VDD_DIG
COUT1B VCC1 GNDREG BICKI GND_DIG
DOUT2A VCC2 VCCRE INTLINE XTI
EGND2 VCC2 NC PWDN VDD_PLL
FGND2 OUT2B NC VSS GND_PLL
VDDREG SDI
NC
NC LRCKI
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STA333SML Pin description
17
2.2 Pin list
Table 2. Pin description
Pin n° Name Description Pad information
I/O pins
B4 LRCKI I²S Left/Right clock
C4 BICKI I²S serial clock
A5 SDI I²S serial data channels 1 & 2
D5 XTI Master clock input
E4 PWDN -’0’ = power-down; ‘1’=normal operation
D4 INTLINE -’0’ = power bridge in fault; ‘1’=normal operation
Power output pins
A2 OUT1A Positive output 1
C1 OUT1B Negative output 1
D1 OUT2A Positive output 2
F2 OUT2B Negative output 2
Power supplies (preliminary)
B2/C2 VCC1 Positive supply (upper MOSFET) to left H-bridge P output
E2/D2 VCC2 Positive supply (upper MOSFET) to right H-bridge P output
A1/B1 GND1 Negative supply (lower MOSFET) to left H-bridge P output
E1/F1 GND2 Negative supply (lower MOSFET) to right H-bridge P output
D3 VCCREG Reference voltage to VCC These pins are output pins
that must be externally
filtered. Do not connect
these pins to external supply
voltage.
C3 GNDREG Reference voltage to ground
A4 VDDREG Reference volt age to 3.3 V
F4 VSS Reference voltage to VCC - 3.3 V
B5 VDD_DIG Digital supply
C5 GND_DIG Digital ground
E5 VDD_PLL PLL supply
F5 GND_PLL PLL grou nd
A3, B3,
E3, F3 NC Not connected
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Electrical specifications STA333SML
6/17 DocID025317 Rev 2
3 Electrical specifications
3.1 Absolute maximum ratings
Warning: Stresses bey ond those listed in Table 3: Absolute maximum
ratings may cau se permanent damage to the device. These
are stress rating s only , and func tional operation of the device
at these or any other conditions beyond those indicated in
T able 5: Recommended operat ing conditions are not implied.
Exposure to absolute maximum rated conditions for
extended periods may affect device reliability. In the real
application, a power supply with nominal value rated within
the limit s of the recommended o perating cond itions ma y rise
beyond the maximum operating conditions for a short time
when no or very low current is sunk (amplifier in mu te state).
In this case the reliability of the device is guaranteed,
provided that the absolute maximum ratings are not
exceeded.
3.2 Thermal data
Table 3. Absolute maximum ratings
Symbol Parameter Min. Typ. Max. Unit
VCC Analog supply voltage (pins VCCx) -0.3 - 20 V
VDD Digital supply voltage (pins VDD_DIG) -0.3 - 4.0 V
ILLogic input interface -0.3 - 4.0 V
Top Operating junction temperature 0 - 150 °C
Tstg Storage temperature -40 - 150 °C
Table 4. Thermal data
Symbol Parameter Min. Typ. Max. Unit
RTh(j-case) Thermal resistance junction to ambient - 51.5 °C/W
Tsd Thermal-shutdown junction temperature 140 150 160 °C
TwThermal-warning temperature - 130 - °C
Thsd Thermal-shutdown hysteresis 18 20 22 °C
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STA333SML Electrical specifications
17
3.3 Recommended operating conditions
3.4 Electrical specifications - digital section
Table 5. Recommended operating conditions
Symbol Parameter Min. Typ. Max. Unit
VCC Analog supply voltage (VCCx) 4.5 - 18 V
VDD Digital supply voltage (VDD_DIG) 3.0 3.3 3.6 V
ILLogic input interface 3.0 3.3 3.6 V
Tamb Ambient temperature 0 - 70 °C
Table 6. Electrical characteristics for digital section
Symbol Parameter Conditions Min. Typ. Max. Unit
Iil Input current, no pull-up or
pull-down resistor Vi = 0 V - - ±10 µA
Iih Vi = VDD = 3.6 V - - ±10 µA
Vil Low-level input voltage - - - 0.2 *
VDD V
Vih High-level input voltage - 0.8 *
VDD --V
Vol Low-level output voltage Iol = 2 mA - - 0.4 *
VDD V
Voh High-level output voltage Ioh = 2 mA 0.8 *
VDD --V
Ipu Pull-up current - 25 66 125 µA
Rpu Equivalent pull-up
resistance --50-k
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Electrical specifications STA333SML
8/17 DocID025317 Rev 2
3.5 Electrical specifications - power section
The specifications in Table 7 below are given for the conditions VCC = 13 V, VDD = 3.3 V,
fSW = 384 kHz, Tamb = 25 °C and RL = 8 , unless otherwise spec ified .
Table 7. Electrical specifications for power section
Symbol Parameter Conditions Min. Typ. Max. Unit
Po Output power BTL THD = 1% - 8 - W
THD = 10% - 10 -
RdsON
Power P-
channel/N-channel
MOSFET (total bridge) ld = 1 A - 106 m
ldss Power P-
channel/N-channel leakage VCC = 18 V - - 10 µA
gP Power P-channel RdsON
matching ld = 1 A 95 - - %
gN Power N-channel RdsON
matching ld = 1 A 95 - - %
ILDT Low-current dead time
(static) Resistive load,
refer to Figure 4 - 5 10 ns
IHDT High-current dead time
(dynamic) Refer to Figure 5 -1020ns
trRise time Resistive load,
refer to Figure 4 - 8 10 ns
tfFall time Resistive load,
refer to Figure 4 - 8 10 ns
VCC Supply voltage - 4.5 - 18 V
IVCC
Supply current from VCC in
power down PWRDN = 0 30 60 200 µA
Supply current from VCC in
operation
PCM input signal = -60 dBFS
Switching frequency =
384 kHz
No LC filters
-3050mA
IVDD_DIG
Supply current for FFX
processing (reference only) Internal clock = 49.152 MHz 10 30 50 mA
Supply current in standby - 8 11 25 mA
Av_DIG Digital Gain 24 dBFS
ISCP Short-circuit protection High-impedance output (1) 2.7 3.8 5.0 A
VOVP Overvoltage protection
threshold 22.9 V
VUVP Undervoltage protection
threshold --3.5 4.3V
tmin Output minimum pulse
width No load 20 30 60 ns
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STA333SML Electrical specifications
17
THD+N Total harmonic distortion
and noise FFX stereo mode, Po = 1 W,
f = 1 kHz - 0.05 0.2 %
DR Dynamic range - - 100 - dB
SNR
Signal to noise ratio in
ternary mode A-weighted - 100 - dB
Signal to noise ratio in
binary mode A-weighted - 90 -
PSRR Power supply rejection ratio FFX stereo mode, < 5 kHz,
VRIPPLE = 1 V RMS
audio input = dither only -80-dB
XTALK Crosstalk FFX stereo mode, < 5 kHz,
One channel driven at 1 W
the other channel measured -80-dB
Peak efficiency
in FFX mode Po = 2 x 10 W into 8 -90-%
1. The ISCP current limit data is for 1 channel of BTL configuration, thus, 2 * ISCP drives the 2-channel BTL
configuration.
Table 7. Electrical specifications for power section (continued)
Symbol Parameter Conditions Min. Typ. Max. Unit
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Electrical specifications STA333SML
10/17 DocID025317 Rev 2
3.6 Power-off sequence
The power-off sequence shown in Figure 3 below ensures a pop-free turn-off.
Figure 3. Power-off sequence
3.7 Testing
Figure 4. Test circuit
Figure 5. Current deadtime test circuit
Don’t careDon’t care
Don’t care
Don’t careDon’t care
Don’t care
No specific VCC and VDD_DIG turn-off sequence is required
VCC
VDD_DIG
XTI
Low current dead time = MAX(DTr,DTf)
OUTxY
Vcc
(3/4)Vcc
(1/2)Vcc
(1/4)Vcc
t
DTfDTr
Duty cycle = 50%
INxY OUTxY
gnd
+Vcc
M58
M57
R 8Ω
+
-
V67 =
vdc = Vcc/2
D03AU1458
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))
+V
CC
Rload=8Ω
Q2
OUTB )B(niTD)B(tuoTD
DTout(A)
C71 470nF C70
470nF
C69
470nF
Iout=4AIout=4A
Q4
Q1
Q3
M64
INB
M63
D03AU1517
M58
INA
M57
DTin(A)
Duty cycle=A Duty cycle=B
Duty cycle A and B: Fixed to have DC output current of 4A in the direction shown in figure
L68 22μL67 22μ
OUTA
Lout = 1.5 A Lout = 1.5 A
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STA333SML Electrical specifications
17
3.8 Serial audio interface description
3.8.1 Serial audio interface protocols
The STA333SML serial audio input was designed to interface with standard digital audio
components and to accept I²S formats. The STA333SML always acts as a slave when
receiving audio input from standard digital audio components. Serial data for two channels
is provided using 3 input pins: left/right clock LRCKI (pin B4), serial clock BICKI (pin C4),
and serial data SDI (pin A5).
The available formats are shown in Figure 6, Figure 7 and Figure 8.
Figure 6. I²S -16 fs
Figure 7. I²S - 24fs
Figure 8. I²S - 32fs
LRCKI
Left Channel Right Channel
16 Clks 16 Clks
BICKI
14
80
14
8
SDI
0
LRCKI
Left Channel Right Channel
24 Clks 24 Clks
BICKI
22 11 0
19
15 0
70
22 11
SDI
0
19
15 0
11 0
LRCKI
Left Channel Right Channel
32 Clks 32 Clks
BICKI
23 80
19
15 0
40
23 8
19
15 0
40
SDI
0
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Electrical specifications STA333SML
12/17 DocID025317 Rev 2
3.9 Application information
Figure 9. Application diagram
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STA333SML Package mechanical data
17
4 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
The STA333SML comes in a CSP 5x6 array package.
Figure 10 below shows the package outline and gives the dimensions.
Figure 10. CSP 5x6 array outline drawing
7224730_I
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Package mechanical data STA333SML
14/17 DocID025317 Rev 2
Table 8. CSP 5x6 array package dimension s
Symbol mm
Min. Typ. Max.
A 0.585 0.65 0.715
A1 0.210 0.25 0.29
A2 0.38 0.4 0.42
b 0.265 0.315 0.365
D 2.52 2.57 2.62
D1 2
E 3.19 3.24 3.29
E1 2.5
e 0.45 0.5 0.55
se 0.2 0.25 0.3
fD 0.277 0.285 0.293
fE 0.362 0.370 0.378
ccc 0.08
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STA333SML Package mechanical data
17
4.1 Soldering information
Figure 11. Recommended soldering reflow profile for mounting on PCB
Table 9. Recommended soldering reflow values for mounting on PCB
Profile Typ. Max.
Temp. gradient in preheat (T = 70 - 180 °C) 0.9 °C/s 3 °C/s
Temp.gradient (T = 200 - 225 °C) 2 °C/s 3 °C/s
Peak temp. in reflow 240 - 245 °C 260 °C
Time above 220 °C 60 s 90 s
Temp. gradient in cooling -2 to -3 °C -6 °C
Time from 50 to 220 °C 160 to 220 s
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STA333SML
17
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