54AC161 •54ACT161
Synchronous Presettable Binary Counter
General Description
The ’AC/’ACT161 are high-speed synchronous modulo-16
binary counters. They are synchronously presettable for ap-
plication in programmable dividers and have two types of
Count Enable inputs plus a Terminal Count output for versa-
tility in forming synchronous multistage counters. The ’AC/
’ACT161 has an asynchronous Master Reset input that over-
rides all other inputs and forces the outputs LOW.
Features
nI
CC
reduced by 50%
nSynchronous counting and loading
nHigh-speed synchronous expansion
nTypical count rate of 125 MHz
nOutputs source/sink 24 mA
n’ACT161 has TTL-compatible inputs
nStandard Microcircuit Drawing (SMD)
— ’AC161: 5962-89561
— ’ACT161: 5962-91722
Logic Symbols Pin Names Description
CEP Count Enable Parallel Input
CET Count Enable Trickle Input
CP Clock Pulse Input
MR Asynchronous Master Reset Input
P
0
–P
3
Parallel Data Inputs
PE Parallel Enable Inputs
Q
0
–Q
3
Flip-Flop Outputs
TC Terminal Count Output
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
FACT™is a trademark of Fairchild Semiconductor Corporation.
DS100274-1
IEEE/IEC
DS100274-2
November 1998
54AC161
•
54ACT161 Synchronous Presettable Binary Counter
© 1998 National Semiconductor Corporation DS100274 www.national.com
Connection Diagrams
Functional Description
The ’AC/’ACT161 count in modulo-16 binary sequence.
From state 15 (HHHH) they increment to state 0 (LLLL). The
clock inputs of all flip-flops are driven in parallel through a
clock buffer. Thus all changes of the Q outputs (except due
to Master Reset of the ’161) occur as a result of, and syn-
chronous with, the LOW-to-HIGH transition of the CP input
signal. The circuits have four fundamental modes of opera-
tion, in order of precedence: asynchronous reset, parallel
load, count-up and hold. Five control inputs—Master Reset,
Parallel Enable (PE), Count Enable Parallel (CEP) and
Count Enable Trickle (CET)—determine the mode of opera-
tion, as shown in the Mode Select Table. A LOW signal on
MR overrides all other inputs and asynchronously forces all
outputs LOW. A LOW signal on PE overrides counting and
allows information on the Parallel Data (P
n
) inputs to be
loaded into the flip-flops on the next rising edge of CP. With
PE and MR HIGH, CEP and CET permit counting when both
are HIGH. Conversely, a LOW signal on either CEP or CET
inhibits counting.
The ’AC/’ACT161 use D-type edge-triggered flip-flops and
changing the PE, CEP and CET inputs when the CP is in ei-
ther state does not cause errors, provided that the recom-
mended setup and hold times, with respect to the rising edge
of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is HIGH
and counter is in state 15. To implement synchronous multi-
stage counters, the TC outputs can be used with the CEP
and CET inputs in two different ways.
Figure 1
shows the connections for simple ripple carry, in
which the clock period must be longer than the CP to TC de-
lay of the first stage, plus the cumulative CET to TC delays of
the intermediate stages, plus the CET to CP setup time of
the last stage. This total delay plus setup time sets the upper
limit on clock frequency. For faster clock rates, the carry loo-
kahead connections shown in
Figure 2
are recommended. In
this scheme the ripple delay through the intermediate stages
commences with the same clock that causes the first stage
to tick over from max to min in the Up mode, or min to max
in the Down mode, to start its final cycle. Since this final
cycle requires 16 clocks to complete, there is plenty of time
for the ripple to progress through the intermediate stages.
The critical timing that limits the clock period is the CP to TC
delay of the first stage plus the CEP to CP setup time of the
last stage. The TC output is subject to decoding spikes due
to internal race conditions and is therefore not recom-
mended for use as a clock or asynchronous reset for
flip-flops, registers or counters.
Logic Equations: Count Enable =CEP •CET •PE
TC =Q
0
•Q
1
•Q
2
•Q
3
•CET
Mode Select Table
PE CET CEP Action on the Rising
Clock Edge (N)
X X X Reset (Clear)
L X X Load (P
n
→Q
n
)
H H H Count (Increment)
H L X No Change (Hold)
H X L No Change (Hold)
H=HIGH Voltage Level
L=LOW Voltage Level
X=Immaterial
State Diagram
Pin Assignment
for DIP and Flatpak
DS100274-3
Pin Assignment
for LCC
DS100274-4
DS100274-5
www.national.com 2
State Diagram (Continued)
DS100274-8
FIGURE 1. Multistage Counter with Ripple Carry
DS100274-9
FIGURE 2. Multistage Counter with Lookahead Carry
www.national.com3
Block Diagram
DS100274-6
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.national.com 4
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
) −0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
=−0.5V −20 mA
V
I
=V
CC
+ 0.5V +20 mA
DC Input Voltage (V
I
) −0.5V to V
CC
+ 0.5V
DC Output Diode Current (I
OK
)
V
O
=−0.5V −20 mA
V
O
=V
CC
+ 0.5V +20 mA
DC Output Voltage (V
O
) −0.5V to V
CC
+ 0.5V
DC Output Source
or Sink Current (I
O
)±50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)±50 mA
Storage Temperature (T
STG
) −65˚C to +150˚C
Junction Temperature (T
J
)
CDIP 175˚C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
’AC 2.0V to 6.0V
’ACT 4.5V to 5.5V
Input Voltage (V
I
) 0VtoV
CC
Output Voltage (V
O
) 0VtoV
CC
Operating Temperature (T
A
)
54AC/ACT −55˚C to +125˚C
Minimum Input Edge Rate (∆V/∆t)
’AC Devices
V
IN
from 30%to 70%of V
CC
V
CC
@3.3V, 4.5V, 5.5V 125 mV/ns
Minimum Input Edge Rate (∆V/∆t)
’ACT Devices
V
IN
from 0.8V to 2.0V
V
CC
@4.5V, 5.5V 125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT™circuits outside databook specifications.
DC Characteristics for ’AC Family Devices
54AC
Symbol Parameter V
CC
T
A
=Units Conditions
(V) −55˚C to +125˚C
Guaranteed Limits
V
IH
Minimum High Level 3.0 2.1 V
OUT
=0.1V
Input Voltage 4.5 3.15 V or V
CC
− 0.1V
5.5 3.85
V
IL
Maximum Low Level 3.0 0.9 V
OUT
=0.1V
Input Voltage 4.5 1.35 V or V
CC
− 0.1V
5.5 1.65
V
OH
Minimum High Level 3.0 2.9 I
OUT
=−50 µA
Output Voltage 4.5 4.4 V
5.5 5.4 (Note 2)
V
IN
=V
IL
or V
IH
3.0 2.4 I
OH
= −12 mA
4.5 3.7 V I
OH
= −24 mA
5.5 4.7 I
OH
= −24 mA
V
OL
Maximum Low Level 3.0 0.1 I
OUT
=50 µA
Output Voltage 4.5 0.1 V
5.5 0.1 (Note 2)
V
IN
=V
IL
or V
IH
3.0 0.5 I
OL
=12mA
4.5 0.5 V I
OL
=24mA
5.5 0.5 I
OL
=24mA
I
IN
Maximum Input 5.5 ±1.0 µA V
I
=V
CC
, GND
Leakage Current
I
OLD
Minimum Dynamic
Output Current (Note 3) 5.5 50 mA V
OLD
=1.65V Max
I
OHD
5.5 −50 mA V
OHD
=3.85V Min
I
CC
Maximum Quiescent 5.5 160 µA V
IN
=V
CC
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DC Characteristics for ’AC Family Devices (Continued)
54AC
Symbol Parameter V
CC
T
A
=Units Conditions
(V) −55˚C to +125˚C
Guaranteed Limits
Supply Current or GND
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @3.0V are guaranteed to be less than or equal to the respective limit @5.5V VCC.
ICC for 54AC @25˚C is identical to 74AC @25˚C.
DC Characteristics for ’ACT Family Devices
54ACT
Symbol Parameter V
CC
T
A
=Units Conditions
(V) −55˚C to +125˚C
Guaranteed Limits
V
IH
Minimum High Level 4.5 3.0 V V
OUT
=0.1V
Input Voltage (Note 7) 5.5 3.0 or V
CC
− 0.1V
V
IL
Maximum Low Level 4.5 0.8 V V
OUT
=0.1V
Input Voltage 5.5 0.8 or V
CC
− 0.1V
V
OH
Minimum High Level 4.5 4.4 V I
OUT
=−50 µA
Output Voltage 5.5 5.4 (Note 5)
V
IN
=V
IL
or 3.0V
4.5 3.70 V I
OH
= −24 mA
5.5 4.70 I
OH
= −24 mA
V
OL
Maximum Low Level 4.5 0.1 V I
OUT
=50 µA
Output Voltage 5.5 0.1 (Note 5)
V
IN
=V
IL
or V
IH
4.5 0.50 V I
OL
=24mA
5.5 0.50 I
OL
=24mA
I
IN
Maximum Input 5.5 ±1.0 µA V
I
=V
CC
, GND
Leakage Current
I
CCT
Maximum 5.5 1.6 mA V
I
=V
CC
− 2.1V
I
CC
/Input
I
OLD
Minimum Dynamic
Output Current (Note 6) 5.5 50 mA V
OLD
=1.65V Max
I
OHD
5.5 −50 mA V
OHD
=3.85V Min
I
CC
Maximum Quiescent 5.5 160 µA V
IN
=V
CC
Supply Current or GND
Note 5: All outputs loaded; thresholds on input associated with output under test.
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
Note 7: For dynamic operation, a VIH level between 2.0 and 3.0V may be recognized by this device as a high logic level input. For static operation, a VIH ≥2.0V will
be recognized by this device as a high logic level input. Users are cautioned to verify that this will not affect their system.
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AC Electrical Characteristics
54AC
V
CC
T
A
=−55˚C Fig.
Symbol Parameter (V) to +125˚C Units No.
(Note 8) C
L
=50 pF
Min Max
f
max
Maximum Count 3.3 55 MHz
Frequency 5.0 80
t
PLH
Propagation Delay CP to Q
n
3.3 1.0 14.0 ns
(PE Input HIGH or LOW) 5.0 1.0 10.0
t
PHL
Propagation Delay CP to Q
n
3.3 1.0 14.0 ns
(PE Input HIGH or LOW) 5.0 1.0 10.0
t
PLH
Propagation Delay 3.3 3.0 18.0 ns
CP to TC 5.0 3.0 13.0
t
PHL
Propagation Delay 3.3 1.0 17.5 ns
CP to TC 5.0 1.0 13.0
t
PLH
Propagation Delay 3.3 1.0 13.0 ns
CET to TC 5.0 1.0 8.5
t
PHL
Propagation Delay 3.3 1.0 13.5 ns
CET to TC 5.0 1.0 10.5
t
PHL
Propagation Delay 3.3 1.0 14.5 ns
MR to Q
n
5.0 1.0 10.5
t
PHL
Propagation Delay 3.3 1.0 18.5 ns
MR to TC 5.0 1.0 14.0
Note 8: Voltage Range 3.3 is 3.3V ±0.3V
Range 5.0 is 5.0V ±0.5V
AC Operating Requirements
54AC
V
CC
T
A
=−55˚C Fig.
Symbol Parameter (V) to +125˚C Units No.
(Note 9) C
L
=50 pF
Guaranteed Minimum
t
s
Setup Time, HIGH or LOW 3.3 16.0 ns
P
n
to CP 5.0 10.5
t
h
Hold Time, HIGH or LOW 3.3 0.5 ns
P
n
to CP 5.0 1.5
t
s
Setup Time, HIGH or LOW 3.3 15.0 ns
PE to CP 5.0 10.5
t
h
Hold Time, HIGH or LOW 3.3 −1.0 ns
PE to CP 5.0 0.0
t
s
Setup Time, HIGH or LOW 3.3 7.5 ns
CEP or CET to CP 5.0 5.5
t
h
Hold Time, HIGH or LOW 3.3 2.0 ns
CEP or CET to CP 5.0 2.0
t
w
Clock Pulse Width 3.3 5.0 ns
(Load) HIGH or LOW 5.0 5.0
t
w
Clock Pulse Width 3.3 5.0 ns
(Count) HIGH or LOW 5.0 5.0
t
w
MR Pulse Width, 3.3 5.0 ns
LOW 5.0 5.0
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AC Operating Requirements (Continued)
54AC
V
CC
T
A
=−55˚C Fig.
Symbol Parameter (V) to +125˚C Units No.
(Note 9) C
L
=50 pF
Guaranteed Minimum
t
rec
Recovery Time 1.5 ns
MR to CP 2.0
Note 9: Voltage Range 3.3 is 3.3V ±0.3V
Voltage Range 5.0 is 5.0V ±0.5V
AC Electrical Characteristics
54ACT
V
CC
T
A
=−55˚C Fig.
Symbol Parameter (V) to +125˚C Units No.
(Note 10) C
L
=50 pF
Min Max
f
max
Maximum Count 5.0 85 MHz
Frequency
t
PLH
Propagation Delay CP to Q
n
5.0 1.0 10.5 ns
(PE Input HIGH or LOW)
t
PHL
Propagation Delay CP to Q
n
5.0 1.0 10.5 ns
(PE Input HIGH or LOW)
t
PLH
Propagation Delay 5.0 1.0 14.0 ns
CP to TC
t
PHL
Propagation Delay 5.0 1.0 12.5 ns
CP to TC
t
PLH
Propagation Delay 5.0 1.0 9.5 ns
CET to TC
t
PHL
Propagation Delay 5.0 1.0 9.5 ns
CET to TC
t
PHL
Propagation Delay 5.0 1.0 10.0 ns
MR to Q
n
t
PHL
Propagation Delay 5.0 1.0 11.5 ns
MR to TC
Note 10: Voltage Range 5.0 is 5.0V ±0.5V
AC Operating Requirements
54ACT
V
CC
T
A
=−55˚C Fig.
Symbol Parameter (V) to +125˚C Units No.
(Note
11) C
L
=50 pF
Guaranteed Minimum
t
s
Setup Time, HIGH or LOW 5.0 13.0 ns
P
n
to CP
t
h
Hold Time, HIGH or LOW 5.0 0 ns
P
n
to CP
t
s
Setup Time, HIGH or LOW 5.0 11.0 ns
PE to CP
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AC Operating Requirements (Continued)
54ACT
V
CC
T
A
=−55˚C Fig.
Symbol Parameter (V) to +125˚C Units No.
(Note
11) C
L
=50 pF
Guaranteed Minimum
t
h
Hold Time, HIGH or LOW 5.0 0 ns
PE to CP
t
s
Setup Time, HIGH or LOW 5.0 7.0 ns
CEP or CET to CP
t
h
Hold Time, HIGH or LOW 5.0 0.5 ns
CEP or CET to CP
t
w
Clock Pulse Width, 5.0 5.0 ns
(Load) HIGH or LOW
t
w
Clock Pulse Width, 5.0 5.0 ns
(Count) HIGH or LOW
t
w
MR Pulse Width, LOW 5.0 6.5 ns
t
rec
Recovery Time 5.0 0.5 ns
MR to CP
Note 11: Voltage Range 5.0 is 5.0V ±0.5V
Capacitance
Symbol Parameter Typ Units Conditions
C
IN
Input Capacitance 4.5 pF V
CC
=OPEN
C
PD
Power Dissipation Capacitance 45.0 pF V
CC
=5.0V
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10
Physical Dimensions inches (millimeters) unless otherwise noted
20 Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
16 Lead Ceramic Dual-In-Line Package (D)
NS Package Number J16A
www.national.com11
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-
CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose fail-
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Tel: 1-800-272-9959
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16 Lead Ceramic Flatpak (F)
NS Package Number W16A
54AC161
•
54ACT161 Synchronous Presettable Binary Counter
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
