PCX7447AMGH1333LB - Atmel Corporation

5387A–HIREL–04/04

Features

•3000 Dhrystone 2.1 MIPS at 1.3 GHz

•Selectable Bus Clock (30 CPU Bus Dividers up to 28x)

•Selectable MPx/60x Interface Voltage (1.8V, 2.5V)

•PD Typically 18W at 1.33 GHz at VDD = 1.3V; 8.0W at 1 GHz at VDD = 1.1V

Full Operating Conditions

•Nap, Doze and Sleep Power Saving Modes

•Superscalar (Four Instructions Fetched Per Clock Cycle)

•4 GB Direct Addressing Range

•Virtual Memor y: 4 Hexabytes (252)

•64-bit Data and 36-bit Address Bus Interface

•Integrated L1: 32 KB Instruction and 32 KB Data Cache

•Integrated L2: 512 KB

•11 Independent Execution Units and 3 Register Files

•Write-back and Write-through Operatio ns

•fINT Max = 1.33 GHz (1.42 GHz to be Confirmed)

•fBUS Max = 133 MHz/166 MHz

Description

The PC7447A host processor is a high-performance, low-power, 32-bit implementa-

tions of the PowerPC Reduced Instruction Set Computer (RISC) architecture

combined with a full 128-bit implementation of Motorola®’s AltiVec™ technology.

This microproce ssor is ideal for leading-edge embedded computing a nd signal pro-

cessing applications. The PC7447A features 512 KB of on-chip L2 cache. The

PC7447A microproc essor has no backside L3 cache, allowing for a smaller package

designed as a pin-for-pin replacement for the PC7447 microprocessor. This device

benefits from a silicon-on-insulator (SOI) CMOS process technology, engineered to

help deliv er tr emendous power savings without sacrificing speed. A lo w-po w er version

of the PC7447A microprocessor is also available.

Figure 1 shows a block diagram of the PC7447A. The core is a high-perfor mance

superscalar design supp orting a double-precision floati ng-point unit an d a SIMD m ulti -

media unit. The mem ory storage subsystem suppor ts the MPX bus protocol and a

subset of the 60x bus protocol to the main memory and other system resources.

Note that the PC7447A is a footprint-compatible, drop-in replacement in a PC7447

application if the core power supply is 1.3V.

Screening

• Full Military Te mperature Range (Tj = -55°C, +125°C),

• Industrial Temperature Range (Tj = -40°C, +110°C)

GH suffix

HITCE 360

Ceramic Ball Grid Array (TBC)

PowerPC®

7447A

RISC

Microprocessor

PC7447A

Preliminary

Rev. 5387A–HIREL–04/04

2 PC7447A [Preliminary] 5387A–HIREL–04/04

Block Diagram

Figure 1. PC7447A Microprocessor Block Diagram

Additional Features

• Time Base Counter/Decrementer

Clock Multiplier

JTAG/COP Interface

Thermal/Power Management

Performance Monitor

Dynamic Frequency Switching (DFS)

Temperature Dioder

x ÷

FPSCR

+ x ÷

Instruction Unit Instruction Queue

(12-Word)

96-Bit (3 Instructions)

Reservation

32-Bit

Floating-

Point Unit

64-Bit

Load/Store Unit

(EA Calculation)

Finished

32-Bit

Completion Unit

(16-Entry)

36-bit 64-bit

Stations (2)

FPR File

16 Rename

Buffers

GPR File

16 Rename

Buffers

VR File

16 Rename

Buffers

64-Bit

128-Bit

Completes up

SRs

(Shadow) 128-Entry

ITLB

Stores

Load Miss

CTR

Vector Touch Engine

32-Bit

L1 Castout

Status

L2 Store Queue (L2SQ)

Vector

FPU

Vector

Integer

Unit 1

Vector

Integer

Unit 2

Vector

Permute

Unit

Status

Block 1 (32-Byte)

Memory Subsystem

Snoop Push/

Interventions

L1 Castouts

Bus Accumulator

L1 Push

(4)

to three

per clock

instructions

L1 Load Queue (LLQ)

L1 Load Miss (5)

Instruction Fetch (2)

Cacheable Store Request (1)

L1 Service

Queues

L1 Store Queue

(LSQ)

L2 Prefetch (3)

Address Bus Data Bus

Castout

Queue (9) /

Push

Queue (10)2

Bus Store Queue

Load

Queue (11)

Completion Queue

Reservation

Station Reservation

Station

Branch Processing Unit

BTIC (128-Entry)

BHT (2048-Entry)

VR Issue

(4-Entry/2-Issue) GPR Issue

(6-Entry/3-Issue) FPR Issue

(2-Entry/1-Issue)

Fetcher

Dispatch

Unit

Instruction MMU

IBAT Array

Data MMU

DBAT Array

128-Bit (4 Instructions)

Tags 32-Kbyte

I Cache

32-Kbyte

D Cache

Tags

SRs

(Original) 128-Entry

DTLB

Reservation

Stations (2-Entry)

Vector

Touch

Queue

Completed

Stores

512-Kbyte Unified L2 Cache Controller

Line

Tags Block 0 (32-Byte)

System Bus Interface

Notes: The castout queue and push queue share resources such for a combined total of entries.

The castout queue itself is limited to 9 entries, ensuring 1 entry will be available for a push.

Integer

Unit 2

Reservation

Stations (2) Reservation

Station

Integer

Unit 1

(3)

PC7447A [Preliminary]

5387A–HIREL–04/04

General Parameters Table 1 provides a summary of the general parameters of the PC7477A.

Features This section summarizes features of the PC7447A implementation of the PowerPC

architecture.

Major features of the PC7447A are as follows:

• High-performance, superscalar microprocessor

– Up to four instructions can be fetched from the instruction cache at a time

– Up to 12 instructions can be in the instruction queue (IQ)

– Up to 16 instructions can be at some stage of execution simultaneously

– Single-cycle execution for most instructions

– One instruction per clock cycle throughput for most instructions

– Seven-stage pipeline control

• Eleven independent execution units and three register files

– Branch processing unit (BPU) f eatures static and dynamic branch prediction

128-entry (32-set, four-way set-associative) branch target instruction cache

(BTIC), a cache of branch instructions that have been encountered in

branch/loop code sequences. If a target instruction is in the BTIC, it is

fetched into the instruction queue a cycle sooner than it can be made

available from the instruction cache. Typically, a fetch that hits the BTIC

provides the first four instructions in the targ et stream.

2048-entry branch history table ( BHT) with tw o bits per entry f or f our levels of

prediction: not taken, strongly not taken, taken, and strongly taken

Up to three ou tst an d i ng spe c u lative branches

Branch instructions that do not update the count register (CTR) or link

Eight-entry link register stack to predict the target address of Branch

Conditional to Link Register (BCLR) instructions

Table 1. Device Parameters

Parameter Description

Technology 0.13 µm CMOS, nine-layer metal

Die size 7.3 mm × 9.32 mm

Transistor count 48.6 million

Logic design Fully-static

Packages Surface mount 360 ceramic ball grid array (HITCE)

Core po wer supply 1.3V ±50 mV DC nominal

I/O power supply 1.8V ±5% DC, or 2.5V ±5% DC

4 PC7447A [Preliminary] 5387A–HIREL–04/04

– Four integer units (IUs) that share 32 GPRs for integer oper ands

Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer

instructions except multiply, divide, and move to/from special-purpose

IU2 execut es misce lla ne ou s ins tructions includin g th e CR log ica l op erations,

integer multiplication and division instructions, and move to/from special-

purpose register instructions.

– Five-stage FPU and a 32-entry FPR file

Fully IEEE 754-1985-compliant FPU for both single- and double-precision

operations

Supports non-IEEE mode f or time-critical operations

Hardware support for denormalized n umber

Thirty-two 64-bit FPRs for single- or doubl e-precision operan ds

– Four vector units and 32-entry vector register file (VRs)

Vector permute unit (VPU)

Vector integer unit 1 (VIU1) handles short-latency AltiVec™ integer

instructions, such as v e ctor add inst ructions (f or example, v addsb s, v addsh s,

and vaddsws).

Vector integer unit 2 (VIU2) handles longer-latency AltiVec integer

instructions, such as vector multiply add instructions (for example,

vmhaddshs, vmhraddsh s, and vmladduhm).

Vector floating-point unit (VFPU)

– Three-stage load/store unit (LSU)

Supports integer, floating-point, and vector instruction load/store traffic

Four-entry vector touch queue (VTQ) supports all four architectures of the

AltiVec data stream operations

Three-cycle GPR and AltiVec load latency (byte, half word, word, v ector) with

one-cycle throughput

Four-cycle FPR load latency (single, double) with one-cycle throughput

No additional delay for misaligned access within double-word boundary

Dedicated adder calculates eff ective addresses (EAs)

Supports store gathering

PC7447A [Preliminary]

5387A–HIREL–04/04

Performs alignment, normalization, and precision conversion for floating-

point data

Executes cache control and TLB instr uc tio ns

Performs alignment, zero padding, and sign extension for integer data

Supports hits under misses (multiple ou tstanding misses)

Supports both big- and little-e ndian mo des , including misalig ned litt le-endian

accesses

• Three issue queue s, FIQ, VIQ, and GIQ, can accep t as many as on e, tw o , and three

instructions, respectively, in a cycle. Instruction dispatch requires the following:

– Instructions can only be dispatched from the three lowest IQ entries: IQ0,

IQ1, and IQ2.

– A maximum of three instructions can be dispatched to the issue queues per

clock cycle.

– Space must be available in the CQ for an instruction to dispatch (this

includes instructions that are assigned a space in the CQ but not in an issue

queue).

• Rename buffers

– 16 GPR rename buff ers

– 16 FPR rename buffers

– 16 VR rename buffers

• Dispatch unit

– Decode/dispatch stage fully decodes each instruction

• Completion unit

– The completion unit retires an instruction from the 16-entry completion

queue (CQ) when all instructions ahead of it have been completed, the

instruction has finished execution, and no exceptions are pending

– Guarantees sequential programming model (precise exception model)

– Monitors all dispatched instructions and retires them in order

– Tracks unresolved branches and flushes instructions after a mispredicted

branch

– Retires as many as three instructions per clock cycle

• Separate on-chip L1 instruction and data caches (Harvard Architecture)

– 32-Kb yte, eight-way set-associative instruction and data caches

– Pseudo least-recently-used (PLRU) replacement al gorithm

– 32-byte (eight-word) L1 cache block

– Physically indexed/physical tags

– Cache write-back or write-thr ough o per ation prog r amma b l e on a p er-p age or

per-block basis

– Instruction cache can provide four instructions per clock cycle; data cache

can provide four words per clo ck cycle

– Caches can be disabled in software

– Caches can be locked in software

– MESI data cache coherency maintained in hardware

6 PC7447A [Preliminary] 5387A–HIREL–04/04

– Separate copy of data cache tags for efficient snooping

– Parity support on cache and tags

– No snooping of instruction cache except for icbi instruction

– Data cache supports AltiVec LRU and transient instructions

– Critical double- and/or quad-word forwarding is performed as needed.

Critical quad-word forwarding is used for AltiVec loads and instruction

fetches. Other accesses use critical double-word forwarding.

• Level 2 (L2) cache interface

– On-chip, 512-Kbyte, eight-way set-associative unified instruction and data

cache

– Fully pipelined to provide 32 bytes per clock cycle to the L1 caches

– A total nine-cycle load latency for an L1 data cache miss that hits in L2

– Cache write-back or write-thr ough o per ation prog r amma b l e on a p er-p age or

per-block basis 64-byte, two-sectored line size

– Parity support on cache

• Separate memory management units (MMUs) for instructions and data

– 52-bit virtual address, 32- or 36-bit physical address

– Address translation for 4-Kbyte pages, variable-sized blocks, and 256-Mbyte

segments

– Memory programmable as write-back/write-through, caching-

inhibited/caching-allowed, and memory coherency enforced/memory

coherency not enforced on a page or block basis

– Separate I BATs and DBATs (eight each) also def ined as SPRs

– Separate instruction and data translation look aside buffers (TLBs)

Both TLBs are 128-entry, two-way set-associative, and use a LRU

replacement algorithm

TLBs are hardware- or software-reloadable (that is, a page table search is

performed in ha rd wa re or by syste m so ftwa r e on a TLB mi ss) .

• Efficient data flow

– Although the VR/LSU interface is 128 bits, the L1/L2 bus interface allows up

to 256 bits

– The L1 data cache is fully pipelined to provide 128 bits/cycle to or from the

VRs

– L2 cache is fully pipelined to provide 256 bits per processor clock cycle to

the L1 cache

– As many as eight outstanding, out-of-order, cache misses are allowed

between the L1 data cache and the L2 bus

– As man y as 16 out-of-order transactions can be present on the MPX bus

– Store merging for multiple store misses to the same line. Only coherency

action taken (address-only) for store misses merged to all 32 bytes of a

cache block (no data tenure needed)

– Three-entry finished store queue and five-entry completed store queue

between the LSU and the L1 data cache

– Separate additional queues for efficient buffer ing of outbound data (such as

castouts and write-through stores) from the L1 data cache and L2 cache

PC7447A [Preliminary]

5387A–HIREL–04/04

• Multiprocessing support features include the following:

– Hardware-enforced, MESI cache coherency protocols for data cache

– Load/store with reservation instruction pair for atomic memory references,

semaphores, and other multiprocessor operations

• Power and thermal management

– A new dynamic frequency switching (DFS) feature allows the processor core

frequency to be halved through softw are to reduce po wer consumption

– The following three power-sa ving modes are available to the system:

Nap: Instruction fetching is halted. Only the clocks for the time base,

decrementer, and JTAG logic remain running. The part goes into the doze

state to snoop memory operations on the bus and then back to nap using a

QREQ/QACK processor-system handshake protocol.

Sleep: Power consumption is further reduced by disabling bus snooping,

leaving only the PLL in a locked and running state. All internal functional

units are disabled.

Deep sleep: When the part is in the deep Sleep state, the system can

disable the PLL. The system can then disable the SYSCLK source for

greater system power savings. Po we r- on reset proced ur es fo r resta rt ing and

relocking the PLL must be followed upon exiting the deep sleep state.

– Instruction cache throttling provides control of instruction fetching to limit

device temperature

– A new temperature diode that can determine the temperature of the

microprocessor

• Performance monitor can be used to help debug system designs and improve

software efficiency

• In-system testability and debugging features through JTAG boundary-scan

capability

• Testability

– LSSD scan design

– IEEE 1149.1 JTAG interface

– Array built-in self test (ABIST), factory test only

• Reliability and serviceability

– Parity checking on system bus

– Parity checking on the L1 and L2 caches

8 PC7447A [Preliminary] 5387A–HIREL–04/04

Signal Description

Figure 2. PC7447A Microprocessor Signal Gr oups

Notes: 1. For the PC7447A, there are 5 PLL_CFG signals, (PLL_CFG[0:4]

PC7447A

INT

SMI

MCP

SRESET

HRESET

CKSTP_IN

CKSTP_OUT

TBEN

QREQ

QACK

BVSEL

BMODE[0:1]

PMON_IN

PMON_OUT

SYSCLK

PLL_CFG[0:3](2)

PLL_EXT

EXT_QUAL

CLK_OUT

TCK

TDI

TDO

TMS

TRST

A[0:35]

AP[0:4]

TT[0:4]

TBST

TSIZ[0:2]

GBL

AACK

ARTRY

SHD0/SHD1

HIT

DBG

DTI[0:3]

DRDY

D[0:63]

DP[0:7]

TEA

Address

Arbitration

Address

Transfer

Address

Transfer

Attributes

Address

Transfer

Termination

Data

Arbitration

Data

Transfer

Data

Transfer

Termination

Interrupts/Resets

Processor

Status/Control

Clock Control

Test Interface

(JTAG)

AVDD

GND

VDD

OVDD

PC7447A [Preliminary]

5387A–HIREL–04/04

Detailed

Specification This specification describes the specific requirements for the microprocessor PC7447A

in compliance with Atmel standard screening.

Applicable

Documents 1. MIL-STD-883: Test methods and procedures for electronics

2. MIL-PRF-38535: Appendix A: General specifications for microcircuits

The microcircuits are in accordance with the applicable documents and as specified

herein.

Design and Construction

Termina l Co nn e ct io n s Depending on the package, the terminal connections are as shown in Table 8 , Table 3

and Figure 2.

Absolute Maximum

Ratings The tables in this section describe the PC7447A DC electrical characteristics. Table 2

provides the ab so lut e ma xim u m ra tin gs.

Notes: 1. Functional and tested operating conditions are given in Table 3 on page 10. Absolute maximum ratings are stress ratings

only, and functional operation at the maximums is not guaranteed . Stresses beyond those listed may affect device reliability

or cause permanent damage to the device.

2. Caution: VDD/AVDD must not exceed OVDD by more than 1V during nor mal operati on; this limit may be exceeded for a maxi-

mum of 20 ms during the power-on reset and power-down sequences.

3. Caution: OVDD must not exceed VDD/AVDD by more than 2V dur ing normal operation; this limit may be exceeded for a maxi-

mum of 20 ms during the power-on reset and power-down sequences.

4. BVSEL must be set to 0, such that the bus is in 1.8V mode.

5. BVSEL must be set to HRESET or 1, such that the bus is in 2.5V mode.

6. Caution: VIN must not exceed OVDD by more than 0.3V at any time including during power-on reset.

7. VIN may overshoot/undershoot to a voltage and for a maximum duration shown in Figure 3 on page 10.

Table 2. Absolute Maximum Ratings(1)

Symbol Characteristic Maxim um Value Unit

VDD(2) Core supply voltage -0.3 to 1.60 V

AVDD(2) PLL supply voltage -0.3 to 1.60 V

OVDD(3)(4) Processor bus supply voltage BVSEL = 0 -0.3 to 1.95 V

OVDD(3)(5) BVSEL = HRESET or OVDD -0.3 to 2.7 V

VIN(6)(7) Input voltage Processor bu s -0.3 to OVDD + 0.3 V

VIN JTAG signals -0.3 to OVDD + 0.3 V

TSTG Storage temperature range -55 to 150 °C

10 PC7447A [Preliminary] 5387A–HIREL–04/04

Recommended

Operating Conditions Table 3 provides the recommended operating conditions for the PC7447A.

Notes: 1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not

guaranteed.

2. This voltage is the input to the filter discussed in Section “PLL Power Supply Filtering” on page 3 7 and not necessar ily the

voltage at the AVDD pin, which may be reduced from VDD by the filter.

Figure 3. Overshoot/Undershoot Voltage

The PC7447A provides several I/O voltages to support both compatibility with existing

systems and migration to future systems. The PC7447A core voltage must always be

provided at a nomin al 1.3V (see Table 3 o n page 10 for the actua l recommended core

voltage). The input voltage threshold for each bus is selected by sampling the state of

the voltage select pins at the negation of the signal HRESET. The output voltage will

swing from GND to the maximum voltage applied to the OVDD power pins. Table 4 on

page 11 provides the input threshold voltage settings. Because these settings may

change in fu ture products, it is recommended that BVSEL be configured using resistor

options, jumpers, or some other flexible means, with the capability to reconfigure the ter-

mination of this signal in the future if necessary.

Table 3. Recommended Operating Conditions(1)

Symbol Characteristic

Recommended Value

UnitMin Max

VDD Core supply voltage 1.3V ±50 mV or 1.1V ±50 mV V

AVDD(2) PLL supply voltage 1.3V ±50 mV or 1.1V ±50 mV V

OVDD Processor bus supply voltage BVSEL = 0 1.8V ±5% V

OVDD BVSEL = HRESET or OVDD 2.5V ±5%

VIN Input voltage Processor bus GND OVDD V

VIN JTAG signals GND OVDD

TjDie-junction temperature -55 125°C°C

GND

GND – 0.3V

GND – 0.7V

Not to exceed 10% of tSYSCLK

OVDD + 20%

OVDD + 5%

OVDD

VIH

VIL

PC7447A [Preliminary]

5387A–HIREL–04/04

Notes: 1. Caution: The input threshold selection must agree with the OVDD voltages supplied.

See notes in Table 2 on page 9.

2. If used, pull-down resistors should be less than 250Ω.

Thermal Characteristics

Package Characteristics

Notes: 1. See “Thermal Management Information” on page 13 for details about thermal management.

2. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) tempera-

ture, ambient temperature, airflow, power dissipation of other components on th e board, and board thermal resistance.

3. Per SEMI G38-87 and JEDEC JESD51-2 with the sing le-layer board horizontal.

4. Per JEDEC JESD51-6 with the board horizontal.

5. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

6. This is the thermal resistance between the die and the case top surface as measured with the cold plate method (MIL

SPEC-883 Method 1012 .1) with the calculated case temperature. The actual value of RθJC for the part is less than 0.1°C/W.

Table 4. Input Threshold Voltage Setting(1)

BVSEL Signal Processor Bus Input Threshold is Relative to: Notes

01.8V (2)

¬HRESET Not available

HRESET 2.5V

12.5V

Table 5. Package Thermal Characteristics(1)

Symbol Characteristic Value Unit

RθJA(2)(3) Junction-to-ambient thermal resistance, natural convection, single-layer (1s) board 26 °C/W

RθJMA(2)(4) Junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board 19 °C/W

RθJMA(2)(4) Junction-to-ambient thermal resistance, 200 ft./min. airflow, single-layer (1s) board 20 °C/W

RθJMA(2)(4) Junction-to-ambient thermal resistance, 200 ft./min. airflow, four-layer (2s2p) board 16 °C/W

RθJB(5) Junction-to-board thermal resistance 10 °C/W

RθJC(6) Junction-to-case thermal resistance < 0.1 °C/W

12 PC7447A [Preliminary] 5387A–HIREL–04/04

Internal Package Conduction

Resistance For the exposed-die pa ckaging technology de scribed in Table 5 on page 11, the intrinsic

conduction thermal resistance paths are as follows:

• The die junction-to-case thermal resistance (the case is actually the top of the

exposed silicon die)

• The die junction-to-ball thermal resistance

Figure 19 depicts the primary heat transfer path for a package with an attached heat

sink mounted to a printed -circuit board.

Figure 4. C4 Package with Heat Sink Mounted to a Printed-Circuit Board

Note the internal versus external package resistance.

Heat generated on the active side of the chip is conducted through the silicon, through

the heat sink attach material (or thermal interface material), and finally to the heat sink

where it is removed by forced-air convection.

Because the silicon thermal resistance is quite small, the temperature drop in the silicon

may be neglected for a first-order analysis. Thus, the thermal interface material and the

heat sink conduction/ convective thermal resistances are the dominant terms.

External Resistance

Internal Resistance

Radiation Convection

Heat Sink

Thermal Interface Material

Die/Package

Die Junction

Package/Leads

Printed-Circuit Board

Radiation Convection

PC7447A [Preliminary]

5387A–HIREL–04/04

Thermal Management

Information This section provides thermal management information for the high coefficient of the

thermal expansion ceramic ball grid array (HITCE) package for air-cooled applications.

Proper thermal control design is primarily dependent on the system-level design – the

heat sink, airflow, and thermal int erface materi al. The PC7447A implements several fea-

tures designed to assist with thermal management, including DFS and the temperature

diode. DFS reduces the power consumption of the device by reducing the core fre-

quency; see Table 7 on page 19 for specific information regarding power reduction and

DFS. The temperat ur e di ode a llows an ext ernal de vice to mo nit or t he die t emp erat ur e in

order to detect excessive temperature conditions and alert the system; see section

“Temperature Diode” on page 16 for more information.

To reduce the die-junction temperature, heat sinks may be attached to the package by

several methods – spring clips to holes in the printed-circuit board or package, and

mounting clips and screw assembly (see Figure 5); however, due t o the pot e ntially lar ge

mass of the heat sink, attachment through the printed-circuit board is suggested. If a

spring clip is used, the spring force should not exceed ten pounds.

Figure 5. Package Exploded Cross-sectional View with Several Heat Sink Options

Printed-Circuit Board

Thermal Interface

Material

Heat Sink

Clip

Heat Sink HCTE Package

14 PC7447A [Preliminary] 5387A–HIREL–04/04

Thermal Interface Mate rials A thermal interface material is recommended at the package lid-to-heat sink interface to

minimize the thermal contact resistance. For those applications where the heat sink is

attached by spring clip mechanism, Figure 6 on page 14 shows the thermal perfor -

mance of three thin-sheet thermal-interface materials (silicone, graphite/oil, floroether

oil), a bare joint, and a joint with thermal grease as a function of contact pressure.

As shown, the performance of these thermal interface materials improves with increas-

ing contact pressure.

The use of thermal gre ase significantly reduces t he interface thermal resist ance. That is,

the bare joint results in a th er mal resist an ce appr oxima tel y seven times gr ea te r than the

thermal grease joint.

Often, heat sinks are attached to the package by means of a spring clip to holes in the

printed-circuit board (see Figure 5 on page 13). Therefore, synthetic grease offers the

best thermal performance, considering the low interface pressure, and is recommended

due to the high power dis sipation of the PC74 47A. Of course, the selec tion of any ther-

mal interface material depends on many factors – thermal performance requirements,

manufacturability, service temperature, dielectric properties, cost, and so on.

Figure 6. Thermal Perform ance of Select Thermal Interface Ma terial

Heat Sink Selection Example For preliminary heat sink sizing, the die-junction temperature can be expressed as

follows:

Tj = TI + Tr + (RθJC + Rθint + Rθsa) × Pd

where:

Tj is the die-junction temperature

0.5

1.5

010 20304050607080

Silicone Sheet (0.006 in.)

Bare Joint

Floroether Oil Sheet (0.007 in.)

Graphite/Oil Sheet (0.005 in.)

Synthetic Grease

Contact Pressure (psi)

Specific Thermal Resistance (K-in.2/W)

PC7447A [Preliminary]

5387A–HIREL–04/04

Ti is the inlet cabinet ambient temperature

Tr is the air temperature rise within the computer cabinet

RθJC is the junction-to-case thermal resistance

Rθint is the adhesive or interface material thermal resistance

Rθsa is the heat sink base-to-am bient thermal resistance

Pd is the power dissipated by the device

During operation, the die-junction temperatures (Tj) should be maintained less than the

value specified in Table 3 on page 10. The temperature of air cooling the component

greatly depends on the ambient inlet air temperature and the air temperature rise within

the electronic cabinet. An electron ic cabinet inlet-air temperature (Ti) may range from

30° to 40°C. The air temperature rise within a cabinet (Tr) may be in the range of 5° to

10°C. The thermal resistance of the thermal interface material (Rθint) is typically ab out

1.5°C/W. For example, assuming a Ti of 30°C, a Tr of 5°C, an HITCE package RθJC =

0.1, and a typical power consumption (Pd) of 18.7W, the following expre ssion for Tj is

obtained:

Die-junction temperature: Tj = 30°C + 5°C + (0.1°C/W + 1.5°C/W + θsa) × 18.7W

For this example, a Rθsa value of 2.1°C/W or less is required to maintain the die junction

temperature below the maximum value of Table 3 on page 10.

Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances

are a common figu re-of-merit used for compa ring the thermal performa nce of various

microelectronic packaging technologies, one should exercise caution when only using

this metric in determining thermal management because no single parameter can ade-

quately describe three-dimensional heat flow. The final die-junction operating

temperature is not only a function of the component-level thermal resistance, but the

system-level design and its operating conditions. In addition to the component's power

consumption, a number of factors affect the final operating die-junction temperature –

airflow, board population (local heat flux of adjacent components), heat sink efficiency,

heat sink attach, heat sink placement, next-level interconnect technology, system air

temperature rise, altitude, and so on.

Due to the complexity and variety of system-level bound ary conditions fo r today's micr o-

electronic equipment, the combined effects of the heat transfer mechanisms (radiation,

convection, and conduction) may vary widely. For these reasons, we recommend using

conjugate heat transfer models for the board, as well as system-level designs.

For system thermal modelin g, the PC7447A ther mal model is shown in Figure 7 on page

16. Four volumes represent this device. Two of the volumes, solder ball-air and sub-

strate, are modeled using the package outline size of the package. The other two, die,

and bump-underfill, have the same size as the die. The silicon die should be modeled

9.5 × 9.5 × 0.7 mm with the he at sour ce applied as a uniform source at the bottom of the

volume. The bump and underfill layer is modeled as 7.3 × 9.3 × 0.7 mm (or as a col-

lapsed volume) with orthotropic material properties: 0.6 W/(m × K) in the xy-plane and

1.9 W/(m × K) in the direction of the z-axis. The substrate volume is 25 × 25 × 1.2 mm,

and has 8.1 W/(m × K) isotropic conductivity in the xy-plane and 4 W/(m × K) in the

direction of the z-axis. The solder ball and air layer are modeled with the same horizon-

tal dimensions as the substrate and are 0.6 mm thick. They can also be mo deled as a

collapsed volume using orthotropic material properties: 0.034 W/(m × K) in the xy-plane

direction and 3.8 W/(m × K) in the direction of the z-axis.

16 PC7447A [Preliminary] 5387A–HIREL–04/04

Figure 7. Recommended Thermal Model of PC7447A

Temperature Diode The PC7447A has a temperature diode on the microprocessor that can be used in con-

junction with other system temperature monitoring devices. These devices use the

negative temperature coefficient of a diode operated at a constant current to determine

the temperature of the microprocesso r and its environment. For proper operation, the

monitoring device used should auto-calibrate the device by canceling out the VBE varia-

tion of each PC7447A’s internal diode.

The following are the specifications of the PC7447A on-board temperature diode:

Vf > 0.40V

Vf < 0.90V

Operating range 2 - 300 µA

Diode leakage < 10 nA at 125°C

Ideality factor over 5 µA – 150 µA at 60°C: 1 <= n <= TBD

Ideality factor is defi ned as the deviation from the ideal diode equation:

Another usef ul eq ua tio n is:

Bump and Underfill

Die

Substrate

Solder and Air

Die

Substrate

Side View of Model (Not to Scale)

Conductivity Value Unit

Bump and Underfill (7.3 x 9.3 x 0.070 mm)

W/(m x K)

Substrate (25 x 25 x 1.2 mm)

Solder Ball and Air (25 x 25 x 0.6 mm)

kx0.6

ky0.6

kz1.9

kx8.1

ky8.1

kz4.0

0.034

3.8

IfW Ise

qVf

nKT

-----------1–=

VHVL

–nKT

------- InIH

-----

PC7447A [Preliminary]

5387A–HIREL–04/04

Where:

Ifw = Forward current

Is = Saturation current

Vd = Voltage at diode

Vf = Voltage forward biased

VH = Diode voltage while IH is flowing

VL = Diode voltage while IL is flowing

IH = Larger diode bias current

IL = Smaller diode bias current

q = Charge of electron (1.6 × 10-19 C)

n = Ideality factor (normally 1.0)

K = Boltzman’s constant (1.38 × 10-23 Joules/K)

T = Temperature (Kelvins)

The ratio of IH to IL is usually selected to be 10:1. The above simplifies to the following:

VH - VL = 1.986 × 10-4 × nT

Solving for T, the equa tio n beco m es :

Dynamic Frequency Switching

(DFS) The new DFS feature in the PC7447A adds the ability to divide the processor-to-system

bus ratio by two du ring normal functional op eration by setting the HI D1[DFS1] bit. The

frequency change occurs in 1 clock cycle, and no idle waiting period is required to

switch between modes. Additional information regarding DFS can be found in the

MPC7450 RISC Microprocessor Family User’s Manual.

Power Consumption with DFS

Enabled Power consumption with DFS enabled can be approximated using the following formula:

Where:

PDFS = Power consumption with DFS enabled

fDFS = Core frequency with DFS enabled

f = Core frequency prior to enabling DFS

P = Power consumption prior to enabling DFS (see Table 7 on page 19)

PDS = Deep sleep mode power consumption (see Table 7 on page 19)

The above is an approx imation only. Power con sumption with DFS enable d is not tested

or guaranteed.

VHV–L

1986 104–

×,

----------------------------------=

PDFS

fDFS

-----------PP

–()

PDS

18 PC7447A [Preliminary] 5387A–HIREL–04/04

Bus-to-Core Multiplier

Constraints with DFS DFS is not available for all bus-to-core mu ltipliers as configured by PLL_CFG[0:4] dur-

ing hard reset. Specifically, because the PC7447A does not support quarter clock ratios

or the 1x multiplier, the DFS feature is limited to integer PLL multipliers of 4x and higher.

The complete listing is shown in Table 6 on page 18.

Table 6. Valid Divide Ratio Configurations

Bus-to-Core Multiplier Configured by

PLL_CFG[0:4] (see Table 13 on page 35)Bus-to-Core Multiplier with

HID1[DFS1] = 1 (÷2)

2x N/A

3x N/A

4x 2x

5x 2.5x

5.5x 2x

6x 3x

6.5x N/A

7x 3.5x

7.5x N/A

8x 4x

8.5x N/A

9x 4.5x

9.5x N/A

10x 5x

10.5x N/A

11x 5.5x

11.5x N/A

12x 6x

12.5x N/A

13x 6.5x

13.5x N/A

14x 7x

15x 7.5x

16x 8x

17x 8.5x

18x 9x

20x 10x

21x 10.5x

24x 12x

28x 14x

PC7447A [Preliminary]

5387A–HIREL–04/04

Minimum Core Frequency

Requirements with DFS In many systems, enabling DFS can result in very low processor core frequencies. How-

ever, care must be taken to ensure that the resulting processor core frequency is within

the limits specified in Table 10 on page 25. Pr oper oper ation of the device is not guaran-

teed at core frequencies below the specified minimum fcore.

Power Consumption Table 7 provides the power consumption for the PC7447A. For information regarding

power consumption when dynamic frequency switching is enabled, See “Dynamic Fre-

quency Switching (DFS)” on page 17.

Notes: 1. These values apply for all valid processor buses. The values do not include I/O supply power (OVDD) or PLL supply power

(AVDD). OVDD power is system dependent but is typically < 5% of VDD power. Worst case power consumption for AVDD <

3 mW.

2. Typical power is an average value measured at the nominal recommended VDD (see Table 3 o n page 10) and 65°C while

running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz

3. Maximum power is the average measured at nominal VDD and maximum operating junction temperature (see Table 3 on

page 10) while running an entirely cache-resident, contrived sequence of instructions which keep all the execution units

maximally busy.

4. Doze mode is not a user-definable state; it is an inter mediate state between full-power and either nap or sleep mode. As a

result, power consumption for this mode is not tested.

5. Power consumption for these devices is artificially constrained during screening to assure lower power consumption than

other speed grades.

Table 7. Power Consumpt ion for PC7447A

Processor (CPU) Frequency

1000 1167 1267 1333(5) 1420 Unit

Full-Power Mode

Core Power Supply 1.1 1.1 1.3 1.3 1.3

Typical(1)(2) 89.2 18.3 18 21 W

Maximum(1)(3) 26 25 30 W

Nap Mode 11.5 13

Typical(1)(2) 1.3 1.3 4.1 3.3 4.1 W

Sleep Mode

Typical(1)(2) 1.3 1.3 4.1 3.3 4.1 W

Deep Sleep Mode (PLL Disabled)

Typical(1)(2) 1.2 1.2 43.2 4 W

20 PC7447A [Preliminary] 5387A–HIREL–04/04

Pin Assignment Figure 8 shows the pinout of the PC7447A, 360 high coefficient of the thermal expan-

sion ceramic ball grid array (HITCE) p ackage as viewed from the top surface. Figure 9

shows the side profile of the HITCE package to indicate the direction of the top surface

view.

Figure 8. Pinout of the PC7447 A, 360 HITCE Packag e as Viewed from the Top Surfa ce

Figure 9. Side View of the CBGA Package

321456 1617 18 19

151413121110987

Substrate Assembly

Encapsulant

View Die

PC7447A [Preliminary]

5387A–HIREL–04/04

Pinout Listings Table 11 provides the pinout listing for the PC7447A, 360 HITCE package. The pinouts

of the PC7447A and PC7447 are pin compatible but there have been some changes. A

PC7447A may be populated on a board designed for a PC7447 provided all pins

defined as ‘No t Connected’ for the PC7447 ar e unterminated as req uired by the PC7457

RISC Microprocessor Specification. T he PC7447A uses pins previously marked ‘Not

Connected’ for th e tempe ra tu re di ode pin s an d for a ddit ion al po wer a nd gr ound connec-

tions. Because these ‘Not Connected’ pins in the PC7447 360 pin package are not

driven in functional mode, a PC7447 can be populated in a PC7447A board. See sec-

tion “Connection Recommendations” on page 38 for additional information.

Note: This pinout is not compatible with the PC750, PC7400, or PC7410 360 BGA package.

Table 8. Pinout Listing for the PC7447A, 360 HITCE Package

Signal Name Pin Number Active I/O I/F Select(1)

A[0:35](2) E11, H1, C11, G3, F10, L2, D11, D1, C10, G2, D12, L3, G4, T2, F4, V1,

J4, R2, K5, W2, J2, K4, N4, J3, M5, P5, N3, T1, V2, U1, N5, W1, B12,

C4, G10, B11 High I/O BVSEL

AACK R1 Low Input BVSEL

AP[0:4](2) C1, E3, H6, F5, G7 High I/O BVSEL

ARTRY(3) N2 Low I/O BVSEL

AVDD A8 –Input BVSEL

BG M1 Low Input BVSEL

BMODE0(4) G9 Low Input BVSEL

BMODE1(5) F8 Low Input BVSEL

BR D2 Low Output BVSEL

BVSEL(1)(6) B7 High Input BVSEL

CI(3) J1 Low Output BVSEL

CKSTP_IN A3 Low Input BVSEL

CKSTP_OUT B1 Low Output BVSEL

CLK_OUT H2 High Output BVSEL

D[0:63]

R15, W15, T14, V16, W16, T15, U15, P14, V13, W13, T13, P13, U14,

W14, R12, T12, W12, V12, N11, N10, R11, U11, W11, T11, R10, N9,

P10, U10, R9, W10, U9, V9, W5, U6, T5, U5, W7, R6, P7, V6, P17,

R19, V18, R18, V19, T19, U19, W19, U18, W17, W18, T16, T18, T17,

W3, V17, U4, U8, U7, R7, P6, R8, W8, T8

High I/O BVSEL

DBG M2 Low Input BVSEL

DP[0:7] T3, W4, T4, W 9, M6, V3, N8, W6 High I/O BVSEL

DRDY(7) R3 Low Output BVSEL

DTI[0:3](8) G1, K1, P1, N1 High Input BVSEL

EXT_QUAL(9) A11 High Input BVSEL

GBL E2 Low I/O BVSEL

GND

B5, C3, D6, D13, E17, F3, G17, H4, H7, H9, H11, H13, J6, J8, J10,

J12, K7, K3, K9, K11, K13, L6, L8, L10, L12, M4, M7, M9, M11, M13,

N7, P3, P9, P12, R5, R14, R17, T7, T10, U3, U13, U17, V5, V8, V11,

V15

– – N/A

22 PC7447A [Preliminary] 5387A–HIREL–04/04

GND(15) A17, A19, B13, B16, B18, E12, E19, F13, F16, F18, G19, H18, J14,

L14, M15, M17, M19, N14, N16, P15, P19 – – N/A

GND_SENSE(19) G12, N13 – – N/A

HIT(7) B2 Low Output BVSEL

HRESET D8 Low Input BVSEL

INT D4 Low Input BVSEL

L1_TSTCLK(9) G8 High Input BVSEL

L2_TSTCLK(10) B3 High Input BVSEL

No Connect(11) A6, A14, A15, B14, B15, C14, C15, C16, C17, C18, C19, D14, D15,

D16, D17, D18, D19, E14, E15, F14, F15, G14, G15, H15, H16, J15 ,

J16, J17, J18, J19, K15, K16, K17, K18, K19, L15, L16, L17, L18, L19 – – –

LSSD_MODE(6)(12) E8 Low Input BVSEL

MCP C9 Low Input BVSEL

OVDD B4, C2, C12, D5, F2, H3, J5, K2, L5, M3, N6, P2, P8, P11, R4, R13,

R16, T6, T9, U2, U12, U16, V4, V7, V10, V14 – – N/A

OVDD_SENSE(16) E18, G18 – – N/A

PLL_CFG[0:4] B8, C8, C7, D7, A7 High Input BVSEL

PMON_IN(13) D9 Low Input BVSEL

PMON_OUT A9 Low Output BVSEL

QACK G5 Low Input BVSEL

QREQ P4 Low Output BVSEL

SHD[0:1](3) E4, H5 Low I/O BVSEL

SMI F9 Low Input BVSEL

SRESET A2 Low Input BVSEL

SYSCLK A10 –Input BVSEL

TA K6 Low Input BVSEL

TBEN E1 High Input BVSEL

TBST F11 Low Output BVSEL

TCK C6 High Input BVSEL

TDI(6) B9 High Input BVSEL

TDO A4 High Output BVSEL

TEA L1 Low Input BVSEL

TEMP_ANODE(17) N18

TEMP_CATHODE(17) N19

TEST[0:3](12) A12, B6, B10, E10 –Input BVSEL

TEST[4](9) D10 –Input BVSEL

TMS(6) F1 High Input BVSEL

Table 8. Pinout Listing for t he PC7447A, 360 HITCE Package (Continued)

Signal Name Pin Number Active I/O I/F Select(1)

PC7447A [Preliminary]

5387A–HIREL–04/04

Notes: 1. OVDD suppli es power to the processor bus, JTAG , and all control signals; V DD supplies power to the processor core and the

PLL (after filtering to become AVDD). To program the I/O voltage, connect BVSEL to either GND (selects 1.8V), or to

HRESET or OVDD (selects 2.5V); see Table 4 on page 11. If used, the pull-down resistor should be less than 250Ω. Because

these settings may change in future products, it is recommended BVSEL be configured using resistor options, jumpers, or

some other flexible means, with the capability to reconfigure the termination of this signal in the future if necessary. For

actual recommended value of VIN or supply voltages see Table 3 on page 10.

2. Unused address pins must be pulled down to GND and corresponding address parity pins pulled up to OVDD.

3. These pins require weak pull-up resistors (for example, 4.7 KΩ) to maintain the control signals in the negated state after they

have been actively negated and released by the PC7447A and other bus masters.

4. This signal selects between MPX bus mode (asser ted) and 60x bus mode (negate d) and will be sampled at HRESET going

high.

5. This signal must be negated during reset, by pull-up resistor to OVDD or negation by ¬HRESET (inverse of HRESET), to

ensure proper operation.

6. Internal pull up on die.

7. Ignored in 60x bus mode.

8. These signals must be pulled down to GND if unused, or if the PC7447A is in 60x bus mode.

9. These input signals are for factory use only and must be pulled down to GND for normal machine operation.

10.This test signal is recommende d to be tied to HRESET; however, other configurations will not adversely affect performance.

11.These signals are for factory use only and must be left unconnected for normal machine operation. Some pins that were

NCs on the PC7447, have now been defined for other purposes.

12.These input signals ar e for factory use only and must be pulled up to OVDD for nor mal machine operation.

13.This pin can externally cause a performance monitor event. Counting of the event is enabled through software.

14.This signal must be asserted during reset, by pull down to GND or assertion by HRESET, to ensure proper operation.

15.These pi ns were NCs on the PC7 447. They may be left unconnected for backward compatibility with these devices, but it is

recommended they be connected in new designs to facilitate future products. See section “Conn ection Recommendations”

on page 38 for more information.

16.These pins were O VDD pins on the PC7447. These pins are internally connected to OVDD and are intended to allow an exter-

nal device to detect the I/O voltage leve l present inside the device package. If unused, they must be connected directly to

OVDD or left unconnected.

17.These pins provide connectivity to the on-chip temperature diode that can be used to determine the die junction temperature

of the processor. Thes e pins may be left unterminated if unused.

18.These pins are internally connected to VDD and are intended to allow an e xternal device to detect the processor core voltage

level present inside the device package. If unused, they must be connected directly to VDD or left unconnected.

19.These pins are internally connected to GND and are intended to allow an external device to detect the processor ground

voltage level present inside the device package. If unused, they must be connected directly to GND or left unconnected.

Note: Caution must be exercised when perform ing boundary scan test operations on a board designed for a PC7447A but populated

with an PC7447. This is because in the PC7447 it is po ssible to drive the latches associated with the former ‘No Connect’ pins

in the PC7447, pote ntially causing contenti on on those pins. To prevent this, ensure that these pins are not connected on the

board or, if they are connected, ensure that the states of inter nal PC744 7 latches do not cause these pins to be driven duri ng

board testing.

TRST(6)(14) A5 Low Input BVSEL

TS(3) L4 Low I/O BVSEL

TSIZ[0:2] G6, F7, E7 High Output BVSEL

TT[0:4] E5, E6, F6, E9, C5 High I/O BVSEL

WT(3) D3 Low Output BVSEL

VDD H8, H10, H12, J7, J9, J11, J13, K8, K10, K12, K14, L7, L9, L11, L13 ,

M8, M10, M12 – – N/A

VDD(15) A13, A16, A18, B17, B19, C13, E13, E16, F12, F17, F19, G11, G16,

H14, H17, H19, M14, M16, M18, N15, N17, P16, P18 – – N/A

VDD_SENSE(18) G13, N12 – – N/A

Table 8. Pinout Listing for t he PC7447A, 360 HITCE Package (Continued)

Signal Name Pin Number Active I/O I/F Select(1)

24 PC7447A [Preliminary] 5387A–HIREL–04/04

Electrical

Characteristics

Static Characteristics

Table 9 pro vides the DC electrical characteristics for the PC7447A.

Notes: 1. Nominal voltages; see Table 3 on page 10 for recommended operating conditions.

2. For processor bus signals, the reference is OVDD while GVDD is the reference for the L3 bus signals.

3. Excludes test signals and IEEE 1149.1 boundary scan (JTAG) signals.

4. The leakage is measured for nominal OVDD/GVDD and VDD, or both OVDD/GVDD and VDD must vary in the same direction (f or

example, both OVDD and VDD vary by either +5% or -5%).

5. Capacitance is periodically sampled rather than 100% tested.

6. Excludes signals with internal pull ups: BVSEL, LSSD_MODE, TDI, TMS , and TRST. Characterization of leakage current fo r

these signals is currently being conducted.

Table 9. DC Electrical Specifications (see Table 3 on page 10 for Recommended Operating Conditions)

Symbol Characteristic Nominal Bus

Voltage(1) Min Max Unit Notes

VIH Input high voltage (all inputs) 1.8 OVDD × 0.65 OVDD + 0. 3 V(2)

2.5 1.7 OVDD + 0.3

VIL Input low voltage (all inputs) 1.8 -0.3 OVDD × 0.35 V(2)(6)

2.5 -0.3 0.7

IIN

Input leakage current,

VIN = GVDD/ODD

VIN = GND – – 30

-30 µA (2)(3)

ITSI

High-impedance (off-state) leakage current,

VIN = GVDD/ODD

VIN = GND – – 30

-30 µA (2)(3)(4)

VOH Output high voltage at IOH = -5 mA 1.8 OVDD - 0.45 –V

2.5 1.8 –

VOL Output low voltage at IOL = 5 mA 1.8 –0.45 V

2.5 –0.6

CIN

Capacitance,

VIN = 0V

f = 1 MHz All other inputs – 8 pF (5)

VIH Input high voltage (all inputs) 1.8 OVDD × 0.65 OVDD + 0. 3 V(2)

2.5 1.7 OVDD + 0.3

VIL Input low voltage (all inputs) 1.8 -0.3 OVDD × 0.35 V(2)(6)

2.5 -0.3 0.7

IIN

Input leakge current,

VIN = GVDD/OVDD

VIN = GND – – 30

-30 µA (2)(3)

PC7447A [Preliminary]

5387A–HIREL–04/04

Dynamic Characteristics This section provides the AC electrical characteristics for the PC7447A. After fabrica-

tion, functional parts are sorted by maximum processor core frequency as shown in

Section “Clock AC Specifications” on page 25 an d tested for conformance to the AC

specifications for that frequency. The processor core frequency is determined by the

bus (SYSCLK) frequency and the settings of the PLL_CFG[0:4] signals, and can be

dynamically modified using dynamic frequency switching (DFS). Parts are sold by maxi-

mum processor core frequency; See “Orderin g Information” on page 42 for information

on ordering parts. DFS is described in Section “Dynamic Frequency Switching (DFS)”

on page 17.

Clock AC Specifications Table 8 provides the clock AC timing specifications as defined in Figure 10 on page 26

and represents the tested operating frequencies of the devices. The maximum system

bus frequency, fSYSCLK, g iven in T able 10 on p age 25 is considered a practical maximum

in a typical single-processor system. The actual maximum SYSCLK frequency for any

application of the PC7447A will be a function of the AC timings of the PC7447A, the AC

timings for the system controller, bus loading, printed-circuit board topology, trace

lengths, and so forth, and may be less than the value given in Table 10 on page 25.

Table 10. Clock AC Timing Specifications (See Table 3 on page 10 for Recommended Operating Conditions)

Symbol Characteristic

Maximum Pr ocessor Core Frequency

Unit Notes

1267 MHz 1333 MHz 1420 MHz

VDD = 1.3V VDD = 1.3 VDD = 1.3

Min Max Min Max Min Max

fCORE Processor core frequency 600 1267 600 1333 600 1420 MHz (1)(8)

fVCO VCO frequency 1200 2533 1200 2667 1200 2840 MHz (1)

fSYSCLK SYSCLK frequency 33 167 33 167 33 167 MHz (1)(2)(8)

tSYSCLK SYSCLK cycle time 630 630 630 ns (2)

tKR, tKF SYSCLK rise and fall time – 1 – 1 – 1 ns (3)

tKHKL/tSYSCLK SYSCLK duty cycle measured at OVDD/2 40 60 40 60 40 60 %(4)

SYSCLK jitter(5)(6) –±150 –±150 –±150 ps (5)(6)

Internal PLL relock time(7) –100 –100 –100 µs (7)

26 PC7447A [Preliminary] 5387A–HIREL–04/04

Notes: 1. Caution: The SYSCLK frequency and PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus) fre-

quency, processor core frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum

operating frequencies. Refer to the PLL_CFG[0:4] signal description in Section “PLL Configuration” on page 35 for valid

PLL_CFG[0:4] settings.

2. Assumes a lightly-loaded, single-processor system.

3. Rise and fall times for the SYSCLK input measured from 0.4V to 1.4V.

4. Timing is guaranteed by design and characterization.

5. This represents total input jitter, short-term and long-term combined, and is guaranteed by design.

6. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set low to allow

cascade connected PLL-based devices to track SYSCLK drivers with the specified jitter.

7. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for

PLL lock after a stabl e VDD and SYSCLK are reached during the power-on reset sequence. This specification also applies

when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held

asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.

8. Caution: If DFS is enabled, the SYSCLK frequency and PLL_CFG[0:4] settings must be chosen such that the resulting pro-

cessor frequency is greater than or equal to the minimum core frequency.

Figure 10 provides the SYSCLK input timing diagram.

Figure 10. SYSCLK Input Timing Diagram

VM = Midpoint Voltage (OVDD/2)

Symbol Characteristic

Maximum Pr ocessor Core Frequency

Unit Notes

1000 MHz 1167 MHz

VDD = 1.1V VDD = 1.1V

Min Max Min Max

fCORE Processor core frequency 500 1000 500 1167 MHz (1)(8)

fVCO VCO frequency 1200 2000 1000 2233 MHz (1)

fSYSCLK SYSCLK frequency 33 167 33 167 MHz (1)(2)(8)

tSYSCLK SYSCLK cycle time 6 30 6 30 ns (2)

tKR, tKF SYSCLK rise and fall time – 1 – 1 ns (3)

tKHKL/tSYSCLK SYSCLK duty cycle measured at OVDD/2 40 60 40 60 % (4)

SYSCLK jitter(5)(6) – ±150 – ±150 ps (5)(6)

Internal PLL relock time(7) –100–100µs(7)

SYSCLK VMVMVM

tKHKL

tSYSCLK

CVIL CVIH

tKR tKF

PC7447A [Preliminary]

5387A–HIREL–04/04

Processor Bus AC

Specifications Table 11 provides the processor bus AC timing specifications for the PC7447A as

defined in Figure 9 on page 20 and Figure 11 on page 28..

Notes: 1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input

SYSCLK. All output specifications a re measured from the midpoi nt of the r ising edg e of SYSCLK to the mi dpoint of the sig-

nal in question. All output timings assume a purely resistive 50Ω load (see Figure 9 on page 20). Input and output timings are

measured at the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2. The symbology used for timing specifications herein follows the pattern of t(signal)(state)(reference)(state) for inputs and

t(reference)(state)(signal)(state) f or outputs. F or e xample , tIVKH symbolizes the time input signals (I) reach the valid state (V) relative to

the SYSCLK reference (K) going to the high (H) state or input setup time. And tKHOV symbolizes the time from SYSCLK (K)

going high (H) until outputs (O) are v alid (V) or output valid time . Input hold time can be read as the time that the input signal

(I) went invali d (X) with respect to the r ising clock edge (KH) (note the po sition o f the reference and its state for inputs) and

output hold time can be read as the time from the rising edge (KH) until th e output went invalid (OX).

Table 11. Processor Bus AC Timing Specifications(1) (at Recommended Operating Conditions, see Table 3 on page 10.)

Symbol(2) Parameter

All Speed Grades

UnitMin Max

tAVKH

tDVKH

tIVKH

tMVKH(8)

Input setup times:

A[0:35], AP[0:4]

D[0:63], DP[0:7]

AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL,

TT[0:3], QACK, TA, TBEN, TEA, TS,

EXT_QUAL, PMON_IN, SHD[0:1],

BMODE[0:1], BVSEL

1.8

–

tAXKH

tDXKH

tIXKH

tMXKH(8)

Input hold times:

A[0:35], AP[0:4]

D[0:63], DP[0:7]

AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL,

TT[0:3], QACK, TA, TBEN, TEA, TS, EXT_QUAL,

PMON_IN, SHD[0:1]

BMODE[0:1], BVSEL

–

tKHAV

tKHDV

tKHOV

Output valid times:

A[0:35], AP[0:4]

D[0:63], DP[0:7]

AACK, ARTRY, BR, CI, CKSTP_IN, DRDY, DTI[0:3],

GBL, HIT, PMON_OUT, QREQ, TBST, TSIZ[0:2], TT[0:3],

TS, SHD[0:1], WT

–

2ns

tKHAX

tKHDX

tKHOX

Output hold times:

A[0:35], AP[0:4]

D[0:63], DP[0:7]

AACK, ARTRY, BR, CI, CKSTP_IN, DRDY, DTI[0:3],

GBL, HIT, PMON_OUT, QREQ, TBST, TSIZ[0:2], TT[0:3],

TS, SHD[0:1], WT

0.5

–

–ns

tKHOE(5) SYSCLK to output enable 0.5 –ns

tKHOZ(5) SYSCL K to output high impeda nce (all except TS, ARTRY, SHD0,

SHD1)–3.5 ns

tKHTSPZ(3)(4)(5) SYSCLK to TS high impedance after precharge – 1 tSYSCLK

tKHARP(3)(5)(6)(7) Maximum delay to ARTRY/SHD0/SHD1 precharge – 1 tSYSCLK

tKHARPZ(3)(5)(6)(7) SYSCLK to ARTRY/SHD0/SHD1 high impedance after precharge – 2 tSYSCLK

28 PC7447A [Preliminary] 5387A–HIREL–04/04

3. tSYSCLK is the period of the external clock ( SYSCLK) in ns. The n umbers given in the table must be multiplied b y the period of

SYSCLK to compute the actual time duration (in ns) of the parameter in question.

4. According to the bus protocol, TS is driven only by the currently active bus master. It is asser ted low and precharged high

bef ore returning to high impedance, as shown in Figure 12 on page 29. The nominal precharge width for TS is 0.5 × tSYSCLK,

that is, less than the minimum tSYSCLK period, to ensure that another master asserting TS on the following clock will not con-

tend with the pre charge. Output valid and output hold timing is tested for the signal asser ted. Output valid time is tested for

precharge.The high-impedance behavior is guaranteed by design.

5. Guaranteed by design and not tested.

6. According to the bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately following

AACK. Bus contention is not an issue because any master asserting ARTRY will be driving it low. Any master asserting it low

in the first clock f ollowing AACK will then go to high impedance f or 1 cloc k bef ore precharging it high during the second cycle

after the asse rtio n of AACK. The nominal precharge width for ARTRY is 1.0 tSYSCLK; that is, it should be hig h impedance as

shown in Figure 12 on page 29 before the first opportunity for another master to assert ARTRY. Output valid and output hold

timing is tested for the signal asserted.The high-impedance behavior is guaranteed by design.

7. According to the MPX bus protocol, SHD0 and SHD1 can be driven b y m ultiple bus masters beginning the cycle of TS. Tim -

ing is the same as ARTRY, that is, the signal is high impedance for a fraction of a cycle, then negated for up to an entire

cycle (crossing a bus cycle boundary) before being three-stated again. The nominal precharge width for SHD0 and SHD1 is

1.0 tSYSCLK. The edges of the precharge vary depen ding on the programmed ratio of core to bus (PLL configurations).

8. BMODE[0:1] and BVSEL are mod e select inputs and are sampled before and after HRESET negation. The se parameters

represent the input setup and hold times for each sample. These values are guaranteed by design and not tested. These

inputs must remain stable after the second sample. See Figure 11 on page 28 for sample timing.

Figure 11 pro vides the m ode select input tim ing diag r am f o r the PC7447A. The mod e select inputs a re sampled t wice, once

before and once after HRESET negation.

Figure 11. Mode Input Sample Timing Diagram

HRESET

Mode Signals

VMVM

VM = Midpoint Voltage (OVDD/2)

SYSCLK

1st Sample 2nd Sample

PC7447A [Preliminary]

5387A–HIREL–04/04

Figure 12 prov ides the input/output timing diagram for the PC7447A.

Figure 12. Input/Out pu t Tim i n g Diagram

Note: VM = Midpoint Voltage (OVDD/2)

SYSCLK

All Inputs

All Outputs

(Except TS,

All Outputs

tKHOE

ARTRY, SHD0, SHD1)

(Except TS,

ARTRY, SHD0, SHD1)

ARTRY,

SHD0,

SHD1

tAVKH

tKHAV

tMVKH

tIVKH

tAXKH

tIXKH

tMXKH

tKHDV

tKHOV

tKHAX

tKHDX

tKHOX

tKHOZ

tKHTSPZ

tKHTSX

tKHTSV

tKHARV tKHARP

tKHARX

tKHARPZ

30 PC7447A [Preliminary] 5387A–HIREL–04/04

IEEE 1149.1 AC Timing

Specifications Table 12 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure

14 through Figure 17 on page 32.

Notes: 1. All outputs are measured from the mi dpoint voltage of the falling/rising edge of TCLK to the midpoint of the si gnal in ques-

tion. The output timings are measured at the pins. All output timings assume a purely resistive 50Ω load (see Figure 13).

Time-of-flight dela ys must be added for trace lengths, vias and connectors in the system.

2. TRST is an asynchronous level sensitive signal. The time is for test purposes only.

3. Non-JTAG signal input timing with respect to TCK.

4. Non-JTAG signal output timing with respect to TCK.

5. Guaranteed by design and characterization

Figure 13 provides the AC test load for TDO and the bounda ry-scan outputs of the PC7457.

Figure 13. Alternate AC Test Load for the JTAG Interface

Table 12. JTAG AC Timing Specifications (Independent of SYSCLK)(1)at Recommended Operating Conditions

(see Table 3 on page 10)

Symbol Parameter Min Max Unit

fTCLK TCK frequency of operation 033.3 MHz

tTCLK TCK cycle time 30 –ns

tJHJL TCK clock pulse width measured at 1.4V 15 –ns

tJR and tJF TCK rise and fall times – 2 ns

tTRST(2) TRST assert time 25 –ns

tDVJH(3)

tIVJH

Input Setup Times:

Boundary-scan data

TMS, TDI 4

0–

–ns

tDXJH(3)

tIXJH

Input Hold Times:

Boundary-scan data

TMS, TDI 20

25 –

–ns

tJLDV(4)

tJLOV

Valid Times:

Boundary-scan data

TDO 4

420

25 ns

tJLDX(4)

tJLOX

Output hold times:

Boundary-scan data

TDO

30 –

–

tJLDZ(4)(5)

tJLOZ

TCK to output high impedance:

Boundary-scan data

TDO 3

319

9ns

Output Z0 = 50

RL = 50 OVDD/2

PC7447A [Preliminary]

5387A–HIREL–04/04

Figure 14. JTAG Clock Input Timing Diagram

Note: VM = Midpoint Voltage (OVDD/2)

Figure 15. TRST Timing Diagram

Note: VM = Midpoint Voltage (OVDD/2)

Figure 16. Boundary-scan Timing Diagram

Note: VM = Midpoint Voltage (OVDD/2)

VMVMVM

tTCLK

tJR tJF

tJHJL

TCLK

TRST

VMTCK

Boundary

Data Inputs

Boundary

Data Outputs

Boundary

Data Outputs

tDXJH

tDVJH

tJLDV

tJLDZ

Output Data Valid

tJLDX

Input

Data Valid

Output Data Valid

32 PC7447A [Preliminary] 5387A–HIREL–04/04

Figure 17. Test Access Port Timing Diagram

Note: VM = Midpoint Voltage (OVDD/2)

Preparation for

Delivery

Handling MOS devices must be handled with certain precautions to avoid damage due to accu-

mulation of static charge. Input protection devices have been designed in the chip to

minimize the effect of static buildup. However, the following handling practices are

recommended:

• Devices should be handled on benches with conductive and grounded surfaces.

• Ground test equipment, tools and operator.

• Do not handle devices by the leads.

• Store devices in conductive foam or carriers.

• Avoid use of plastic, rubber or silk in MOS areas.

• Maintain relative humidity above 50% if practical.

tJLOX

Input Data

Valid

tIVJH tIXJH

tJLOV

tJLOZ

Output Data Valid

TCK

TDI, TMS

TDO

PC7447A [Preliminary]

5387A–HIREL–04/04

Mechanical Dimensions for the PC7447A, 360 HITCE

Figure 18 prov ides the mechanical dimensions and bottom surface nomenclature for the PC7447A, 360 HITCE package.

Figure 18. Mechanical Dimensions and Bottom Surface Nomenclature for the PC7447A, 360 CBGA Package

Notes: 1. Dimensioning and tolerance per ASME Y14.5M, 1994

2. Dimensions in millimeters

3. Top side A1 corner inde x is a metallized f eature with v arious shapes. Bottom side A1 corner is designated with a ball missing

from the array

360X

B0.3

0.15

12345678910111213141516171819

0.2

A1 CORNER

0.2

D3 D1

Capacitor Region

0.15 A

0.35 A

AA1

Millimeters

DIM MIN MAX

A 2.72 3.20

A1 0.80 1

A2 1.10 1.30

A3 – 0.6

b 0.82 0.93

D 25 BSC

D1 – 11.3

D2 8 –

D3 – 6.5

D4 9.2 9.4

e 1.27 BSC

E 25 BSC

E1 – 11.3

E2 8 –

E3 – 6.5

E4 7.2 7.4

34 PC7447A [Preliminary] 5387A–HIREL–04/04

Substrate Capacitors for the PC7447A, 360 HITCE

Figure 19 shows the conne ctivity of the substrate capacitor pads for the PC7447A, 360 HITCE. All capacitors are 100 nF.

Figure 19. Substrate Bypass Capacitors for th e PC7447A, 360 HITCE

C1-2

C1-1 C2-1 C3-1 C4-1 C5-1 C6-1

C6-2C5-2C4-2C3-2C2-2

C18-1

C18-2 C17-2 C16-2 C15-2 C14-2 C13-2

C13-1C14-1C15-1C16-1C17-1

C12-1

C12-2 C11-2 C10-2 C9-2 C8-2 C7-2

C7-1C8-1C9-1

C10-1C11-1

C19-2

C19-1 C20-1 C21-1 C22-1 C23-1 C24-1

C24-2C23-2C22-2C21-2C20-2

A1 CORNER

C1 GND VDD

C2 GND VDD

C3 GND OVDD

C4 GND VDD

C5 GND VDD

C6 GND VDD

C7 GND VDD

C8 GND VDD

C9 GND VDD

C10 GND VDD

C11 GND VDD

C12 GND VDD

C13 GND VDD

C14 GND VDD

C15 GND VDD

C16 GND OVDD

C17 GND VDD

C18 GND OVDD

C19 GND OVDD

C20 GND VDD

C21 GND OVDD

C22 GND VDD

C23 GND OVDD

C24 GND VDD

Capacitor Pad Number

-1 -2

PC7447A [Preliminary]

5387A–HIREL–04/04

System Design

Information This section provides system and thermal de sign recommendations for successf ul appli-

cation of the PC7447A.

PLL Configuration The PC7447A PLL is configure d by the PLL_CFG[0:4] signals. For a given SYSCLK

(bus) frequency, the PLL configuration signals set the internal CPU and VCO frequency

of operation. The PLL configuration for the PC7447A is shown in Ta ble 13 on page 35

for a set of example frequencies. In this example, shaded cells represent settings that,

for a given SYSCLK frequency, result in core and/or VCO frequencies that do not com-

ply with the 1400 MHz column in Table 10 on page 25. When enabled, dynamic

frequency switching (DFS) also affects the core frequency by halving the bus-to-core

multiplier; see section “Dynamic Frequency Switching (DFS) ” on page 17 f or mo re info r-

mation. Note that when DFS is enabled the resulting core frequency must meet the

minimum core freque ncy requirements descri bed in Table 10 on page 25.

Table 13. PC7447A Microprocessor PLL Configuration Example for 1420-MHz Parts

PLL_CFG[0:4]

Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)

Bus-to-Core

Multiplier Core-to-VCO

Multiplier

Bus (SYSCLK) Frequency

33.33

MHz 50

MHz 66.66

MHz 75

MHz 83

MHz 100

MHz 133.33

MHz 166.66

MHz

01000 2x 2x

10000 3x 2x

10100 4x 2x 667

(1333)

10110 5x 2x 667

(1333) 835

(1670)

10010 5.5x 2x 733

(1466) 919

(1837)

11010 6x 2x 600

(1200) 800

(1600) 1002

(2004)

01010 6.5x 2x 650

(1300) 866

(1730) 1086

(2171)

00100 7x 2x 700

(1400) 931

(1862) 1169

(2338)

00010 7.5x 2x 623

(1245) 750

(1500) 1000

(2000) 1253

(2505)

11000 8x 2x 600

(1200) 664

(1328) 800

(1600) 1064

(2128) 1336

(2672)

01100 8.5x 2x 638

(1276) 706

(1412) 850

(1700) 1131

(2261) 1417

(2833)

01111 9x 2x 600

(1200) 675

(1350) 747

(1494) 900

(1800) 1197

(2394)

01110 9.5x 2x 633

(1266) 712

(1524) 789

(1578) 950

(1900) 1264

(2528)

36 PC7447A [Preliminary] 5387A–HIREL–04/04

Notes: 1. PLL_CFG[0:4] settings not listed are reserved.

2. The sample bus-to-core frequencies shown are for reference onl y. Some PLL configurations may select bus, core, or VCO

frequencies that are not useful, not suppor ted, or not tested for by the PC7455; see Section “Clock AC Specifications” on

page 25 for valid SYSCLK, core, and VCO frequencies.

PLL_CFG[0:4]

Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)

Bus-to-Core

Multiplier Core-to-VCO

Multiplier

Bus (SYSCLK) Frequency

33.33

MHz 50

MHz 66.66

MHz 75

MHz 83

MHz 100

MHz 133.33

MHz 166.66

MHz

10101 10x 2x 667

(1333) 750

(1500) 830

(1660) 1000

(2000) 1333

(2667)

10001 10.5x 2x 700

(1400) 938

(1876) 872

(1744) 1050

(2100) 1397

(2793)

10011 11x 2x 733

(1466) 825

(1650) 913

(1826) 1100

(2200)

00000 11.5x 2x 766

(532) 863

(1726) 955

(1910) 1150

(2300)

10111 12x 2x 600

(1200) 800

(1600) 900

(1800) 996

(1992) 1200

(2400)

11111 12.5x 2x 600

(1200) 833

(1666) 938

(1876) 1038

(2076) 1250

(2500)

01011 13x 2x 650

(1300) 865

(1730) 975

(1950) 1079

(2158) 1300

(2600)

11100 13.5x 2x 675

(1350) 900

(1800) 1013

(2026) 1121

(2242) 1350

(2700)

11001 14x 2x 700

(1400) 933

(1866) 1050

(2100) 1162

(2324) 1400

(2800)

00011 15x 2x 750

(1500) 1000

(2000) 1125

(2250) 1245

(2490)

11011 16x 2x 800

(1600) 1066

(2132) 1200

(2400) 1328

(2656)

00001 17x 2x 850

(1900) 1132

(2264) 1275

(2550) 1411

(2822)

00101 18x 2x 600

(1200) 900

(1800) 1200

(2400) 1350

(2700)

00111 20x 2x 667

(1334) 1000

(2000) 1332

(2664)

01001 21x 2x 700

(1400) 1050

(2100) 1399

(2797)

01101 24x 2x 800

(1600) 1200

(2400)

11101 28x 2x 933

(1866) 1400

(2800)

00110 PLL bypass PLL off, SYSCLK clocks core circuitry directly

11110 PLL off PLL off, no core clocking occurs

Table 13. PC7447A Microprocessor PLL Configuration Example for 1420-MHz Parts (Continued)

PC7447A [Preliminary]

5387A–HIREL–04/04

3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly and the PLL is disabled. However, the

bus interface unit requires a 2x clock to function. Therefore, an additional signal, EXT_QUAL, must be driven at one-half the

frequency of SYSCLK and offset in phase to meet the required input setup tIVKH and hold time tIXKH (see Table 11 on

page 27). The result will be that the processor bus frequency will be one-half SYSCLK while the internal processor is

clocked at SYSCLK frequency. This mode is intended for factory use and emulator tool use only.

Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.

4. In PLL-off mode, no clocking occurs inside the PC7447A regardless of the SYSC LK input.

PLL Power Supply

Filtering The AVDD power signal is provided on the PC7447A to provide power to the clock gen-

eration PLL. To ensure stability of the internal clock, the power supplied to the AV DD

input signal shoul d be filtered of any no ise in the 500 KHz to 10 MHz r esonant frequency

range of the PLL. A circuit similar to the one shown in Figure 20 using surface m ount

capacitors with minimum effective series inductance (ESL) is recommended.

The circuit should be placed as clo se as possible to the AVDD pi n to minimize noise co u-

pled from nearby circuits. It is often possible to route directly from the capacitors to the

AVDD pin, which is on the periphery of the 360 HITCE footprint.

Figure 20. PLL Power Supply Filter Circuit

Decoupling

Recommendations Due to the PC7447A dynamic power management feature, large address and data

buses, and high operating frequencies, the PC7447A can generate transient power

surges and high frequency noise in its power supply, especially while driving large

capacitive loads. This noise must be preve nted from reaching other components in the

PC7447A system, and the PC7447A itself requires a clean, tightly regulated source of

power. Ther efore, it is recommended t hat the system designer use sufficient decoupling

capacitors, typica lly on e cap acitor fo r ever y 1- 2 VDD pins, and a similar or le sser amou nt

for the OVDD pins, placed as close as possible to the power pins of the PC7447A. It is

also recommended that these decoupling capacitors receive their power from separate

VDD, OVDD, and GND power planes in the PCB, utilizing short traces to minimize

inductance.

These capacitor s should have a value of 0.0 1 or 0.1 µF. Only ceramic surfa ce mount

technology (SMT) capacitors should be used to minimize lead inductance. Orientations

where connections are made along the length of the part, such as 0204, are preferable

but not mandatory. Consistent with the recommendations of Dr. Howard Johnson in

High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993) and con-

trary to previous recommendatio ns for decoupling Motorola microprocessors, multiple

small capacitors of equal value are recommended over using multiple values of

capacitance.

In addition, it is recommended that there be several bulk storage capacitors distributed

around the PCB, feeding the VDD and OVDD planes, to enable q uick recharging of the

smaller chip capacitors. These bulk capacitors should have a low equivalent series

resistance (ESR) rating to ensure the quick response time necessary. They should also

be connected to the power and ground planes through two vias to minimize inductance.

Suggested bulk capacitors are: 100-330 µF (AVX TPS tantalum or Sanyo OSCON).

VDD

2.2 µF2.2 µF

GND

AVDD

Low ESL surface mount capacitors

38 PC7447A [Preliminary] 5387A–HIREL–04/04

Connection

Recommendations To ensure r eliable operation, it is highly recomm ended to con nect unused inp uts to an

appropriate signal level. Unless otherwise noted, unused active low inputs should be

tied to OVDD, and unused active high in puts should be connected to GND. All NC (no

connect) signals must remain unconnected.

Power and ground connections must be made to all external VDD, OVDD, and GND pins

in the PC7447A.

For backward compatibility with the PC7447 to the PC7447A, the new power and

ground signals (formerly NC, see Table 8 on page 21) may be left unconnected. There

is no performance degradation associated with leaving these pins unconnected. How-

ever, future devices may require these additional power and ground signals to be

connected to achieve maximum performance, and it is recommended that new designs

include the additional connections to facilitate future upgrades. See also section “Pinout

Listings” on page 21 for additional information.

Output Buffer DC

Impedance The PC7447A processor bus drivers are characterized over process, voltage, and tem-

perature. To measur e Z0, an ext ernal re sist or is co nn ecte d fr om t he chip pa d t o OV DD or

GND. The value of each resistor is varied until the pad voltage is OVDD/2. Figure 21 on

page 38 shows the driver impedance measurement.

The output impedance is the average of two components–the resistances of the pull-up

and pull-down devices. Wh en data is h eld low, SW 2 is clos ed (SW1 is open), an d RN is

trimmed until the voltage at the pad equals OVDD/2. RN then becomes the resistance of

the pull-down devices. When data is held high, SW1 is closed (SW2 is open), and RP is

trimmed until the voltage at the pad equals OVDD/2. RP then becomes th e resistance o f

the pull-up device s. RP and RN are designe d to be close to e ach other in valu e. Then, Z0

= (RP + RN)/2.

Figure 21. Driver Impedance Measurement

OVDD

OGND

SW2

SW1

Pad

Data

PC7447A [Preliminary]

5387A–HIREL–04/04

Table 14 summarizes the sign al impedance re sults. The impedance in creases with junc -

tion temperature and is relatively unaffect ed by bus voltage.

Pull-up/Pull-down

Resistor Requirements The PC7447A requires high-resistive (weak: 4.7-KΩ) pull-up resistors on several control

pins of the bus interface to maintain the control signals in the negated state after they

have been actively negated and released by the PC7447A or other bus masters. These

pins are: TS, ARTRY, SHDO, and SHD1.

Some pins designated as being factory test pins must be pulled up to OVDD or down to

GND to ensure proper device operat ion. For the PC7447A, 360 BGA, the pin s that must

be pulled up to OVDD are LSSD_MODE and TEST[0:3]; the pins that must be pulled

down to GND are: L1_TSTCLK and TEST[4]. The CKSTP_IN signal should likewise be

pulled up throug h a pull-up resistor (weak or str onger: 4.7–1 KΩ) to prevent erroneous

assertions of this signal.

In addition, the PC7447A h as one open -drain style o utput t hat re quires a pull- up re sistor

(weak or stro ng e r: 4. 7– 1 KΩ) if it is used by the system. This pin is CKSTP_OUT.

If pull-down resistors are used to configure BVSEL, the resistors should be less than

250Ω (see Table 8 on page 21). Because PLL_CFG[0:4] must remain stable during nor-

mal operation, strong pull-up and pull-down re sistors (1 KΩ or less) are recommended to

configure these sign als in order to protect against err oneous switching due to groun d

bounce, power supply noise or noise coupling.

During inactive periods on the bus, the address and transfer attributes may not be

driven by any master and may, therefore, float in the high-impedance state for relatively

long periods of time. Because the PC 7447A must continually monitor these signals for

snooping, this float condition ma y cause exce ssive power draw by t he input receivers on

the PC7447A or by other receivers in the system. These signals can be pulled up

through weak (10-KΩ) pull-up resistors by the system, address bus driven mode

enabled (see the MPC7450 RISC Microprocessor Family Users’ Manual for more inf or-

mation on this mode), or they may be otherwise driven by the system during inactive

periods of the bus to avoid this additional power draw. Preliminary studies have shown

the additional powe r draw by the PC7447A inpu t receivers to be negligible an d, in any

event, none o f these measure s are necessary f or p roper de vice op eration. The snoo ped

address and transfer attribute inputs are: A[0:35], AP[0:4], TT[0:4], CI, WT, and GBL.

If address or data parity is not used by the system, and respective parity checking is dis-

abled through HID1, the input receivers for those pins are disabled and do not require

pull-up resistors, and may be left unconnected by the system. If extended addressing is

not used (HID0[XAEN] = 0), A[0:3] are unused and must be pulled low to GND through

weak pull-down resistors; additionally, if address parity checking is enabled (HID1[EBA]

= 1) and extended add ressing is not used, AP[0] must be pulled up to OVDD thro ugh a

weak pull-up resistor. If th e PC744 7A is in 60x bus mode, DTI[0: 3] must be pu lled low to

GND through weak pull-down resistors. The data bus input receivers are normally

turned off when no read operation is in progress and, therefore, do not require pull-up

resistors on the bus. Other data bus receivers in the system, however, may require pull-

ups, or that those signals be otherwise driven by the system during inactive periods by

the system. The data bus signals are: D[0:63] and DP[0:7].

Table 14. Impedance Characteristics with VDD = 1.5V, OVDD = 1.8V ±5%, Tj = 5° - 85°C

Impedance Processor bus L3 Bus Unit

Z0Typical 33 – 42 34 – 42 Ω

Maximum 31 – 51 32 – 44 Ω

40 PC7447A [Preliminary] 5387A–HIREL–04/04

JTAG Configuration

Signals Boundary-s can testing is enab led throug h the JTAG interfa ce signals. Th e TRST signal

is optional in the IEEE 1149.1 specification but is provided on all processors that imple-

ment the PowerPC ar chitecture. While it is possible to force the TAP controller to the

reset state using only the TCK and TMS sign als, more reliable power-on reset perfor-

mance will be obtained if the TRST signal is asserted during pow er-on reset. Because

the JTAG interface is also used for accessing the com mon on-chip processor (COP)

function, simply tying TRST to HRESET is not practical.

The COP function of these processors allows a remote computer system (typically a PC

with dedicated hardware an d debugging software) to access and control the in ternal

operations of the processor. The COP interface connects primarily through the JTAG

port of the processor, with some additional status monitoring signals. The COP port

requires the ability to independently assert HRESET or TRST in order to fully control the

processor. If the target system has independent reset sources, such as voltage moni-

tors, watchdog timers, power supply failures, or push-button switches, then the COP

reset signals must be merged into these signals with logic.

The arrangement shown in Figure 22 on page 41 allows the COP port to independently

assert HRESET or TRST, while ensuring that the target can drive HRESET as well. If

the JTAG interface and COP header will not be used, TRST should be tied to HRESET

through a 0Ω. isolation resistor so that it is asserted when the system reset signal

(HRESET) is asserted , ensuring that t he JTAG scan chain is initialized du ring power -on.

Although Motorola recommends that the COP header be designed into the system as

shown in Figure 22 on page 41, if this is not possible, the isolation resistor will allow

future access to TRST in the case where a JTAG interface may need to be wired onto

the system in debug situations. The COP header shown in Figure 22 on pag e 41 adds

many benefits—breakpoints, watchpoints, register and memory examination/modifica-

tion, and othe r stand ar d de bugge r f eatu res ar e p ossible t hr ough t his inter fa ce—and can

be as inexpensive as an unpopulated footprint for a header to be added when needed.

The COP interface ha s a st an dar d hea der f or conn ect ion to the ta rg et syst em , b ased on

the 0.025 inch square- post, 0.100 inch centered header assembly (of ten called a Berg

header). The connector typically has pin 14 removed as a connector key.

There is no standardized way to numbe r the COP header shown in Figure 22 on pa ge

41; consequently, many different pin numbers have been observed from emulator ven-

dors. Some are nu mbered top-to-b ottom then left-to-rig ht, while others use left-t o-right

then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as

with an IC). Regardless of the numbering, the signal placement recommended in Figure

22 on page 41 is common to all known emulators.

The QACK signal shown in Figure 22 on page 41 is usually connected to the PCI bridge

chip in a system and is a n inpu t to the PC7 447A info rming it t hat it can go into th e quies -

cent state. Under normal operation this occurs during a low-power mode selection. In

order for COP to work, the PC7447A must see this signal asserted (pulled down). While

shown on the COP header, not all emulator products drive this signal. If the product

does not, a pull-down resistor can be populated to assert this signal. Additionally, some

emulator products implement open-drain type outputs and can only drive QACK

asserted; for these tools, a pull-up resistor can b e implemented to ensure this signal is

negated when it is no t being driven by the tool. Note that t he pull-up and pull -down resis -

tors on the QACK signal are mutually exclusive and it is never necessary to populate

both in a system. To preserve correct power-down operation, QACK should be merged

through logic so that it also can be driven by the PCI bridge.

PC7447A [Preliminary]

5387A–HIREL–04/04

Figure 22. JTAG Interface Connection

Notes: 1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the PC7447A. Connect pin 5 of the COP

header to OVDD with a 10 kΩ pull-up resistor.

2. Key location; pin 14 is not physically present on the COP header.

3. Component not populated. Populate only if debug tool does not drive QACK.

4. Populate only if debug tool uses an open-drain type output and does not actively de-assert QACK.

5. If the JTAG interface is implemented, connect HRESET from the target source to TRST from the COP header though an

AND gate to TRST of the part. If the JTAG interf ac e is not implemented, connect HRESET from the target source to TRST of

the part through a 0Ω isolation resistor.

6. The COP port and target board should be able to independently assert HRESET and TRST to the processor in order to fully

control the processor as shown above.

HRESET HRESET(6)

HRESET

13 SRESET

SRESET SRESET

VDD_SENSE

5(1)

2 k 10 k

10 k

OVDD

CHKSTP_IN CHKSTP_IN

8TMS

TDO

TDI

TCK

TMS

TDO

TDI

TCK

4TRST

14(2)

Key

QACK

OVDD

TRST(6)

10 k

OVDD

QACK

CHKSTP_OUT

KEY

No Pin

COP Connector

Physical Pin Out

10 k (4) OVDD

OVDD

2 k (3)

0(5)

From Target

Board Sources

(if any)

COP Header

10 k

42 PC7447A [Preliminary] 5387A–HIREL–04/04

Packa ge Mechanical

Data The following sections provide the package parameters and mechanical dimensions for

the HITCE package.

Pac k age Parameters for

the PC7447A, 360 HITCE The package parameters are as provided in the following list. The package type is 25 ×

25 mm, 360-lead high coefficient of the thermal expansion ceramic ball grid array

(HITCE).

Package outline 25 mm × 25 mm

Interconnects 360 (19 × 19 ball array - 1)

Pitch 1.27 mm (50 mil)

Minimum module height 2.72 mm

Maximum module height 3.24 mm

Ball diameter 0.89 mm (35 mil)

Ordering Information

Note: 1. For availability of the different versions, contact your local Atmel sales office.

PC 7447A V GH 1000 Lx

Prefix

Type

Revision Level(1)

Rev. B

Application modifier(1)

L: 1.3V ± 50 mV

N: 1.1V ± 50 mV

Max internal processor speed(1)

1000 MHz (N-Spec)

1167 MHz (N-Spec) TBC

1333 MHz (L-Spec)

1420 MHz (L-Spec) TBC

Temperature Range: Tj(1)

Prototype

(X)

V: -40˚C, 110˚C

M: -55˚C +125˚C

Package

GH: HITCE

PC7447A [Preliminary]

5387A–HIREL–04/04

Definitions

Datasheet Status

Description

Life Support

Applications These products are not designed for use in life support appliances, devices or systems

where malfunction of these products can reasonably be expected to result in personal

injury. Atmel customers using or selling these products for use in such applications do

so at their own risk and agree to fully indemnify Atmel for any damages resulting from

such improper use or sale.

Document Revision

History Table 16 provides a revision history for this hardware specification.

Table 15. Datasheet Status

Datasheet Status Validity

Objective specification This datasheet contains target and goal

specifications for discussion with customer and

application validation. Bef ore design phase

Target specification This datasheet contains target or goa l

specifications for product de velopment. Valid during the design phase

Preliminar y specification

α-site

This datasheet contains preliminary data.

Additional data ma y be published later; could

include simulation results. Valid before characterization phase

Preliminar y specification β-site This datasheet also con tains characterization

results. Valid before the industrialization ph ase

Product specification This datasheet contains final product

specification. Valid for production purposes

Limiting Values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the

limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at

any other conditions above those giv en in the Characteristics sections of the specification is not implied. Exposure to limiting values for

extended periods may affect device reliability.

Application Information

Where application information is given, it is advisory and does not form part of the specification.

Table 16. Document Revision History

Revision

Number Substantive Change(s)

AInitial revision

44 PC7447A [Preliminary] 5387A–HIREL–04/04

PC7447A [Preliminary]

5387A–HIREL–04/04

Table of Contents Screening ............................................................................................. 1

Block Diagram ......................................................................................2

General Parameters............................................................................. 3

Features................................................................................................ 3

Signal Description ...............................................................................8

Detailed Specification .........................................................................9

Applicable Documents ........................................................................9

Design and Cons tru ct ion ............... ................... .................... ................... .............9

Absolute Maximu m Ra ting s...... ... ... ... .... ................... ... ................... .... .................. 9

Recommende d Op e ra tin g Con di tio ns............. ... .... ... ... ... .... ................... ... .......... 10

Thermal Characteristics.......................................................................................11

Pin Assignment ..................................................................................20

Pinout Listings....................................................................................21

Electrical Characteristics ..................................................................24

Static Characteristics ..........................................................................................24

Dynamic Characteristics .....................................................................................25

Preparation for Delivery ....................................................................32

Handling .............................................................................................32

Mechanical Dimensions for the PC7447A, 360 HITCE ................... 33

Substrate Capacitors for the PC7447A, 360 HITCE........................ 34

System Design Information .............................................................. 35

PLL Configu ra tio n ............. ... .................... ................... ................... .................... .35

PLL Power Supply Filt er ing .............. .... ... ... ... ... .................... ... ................... .... ....37

Decoupling Rec om m e nd at ion s ... ... ... .... ... ... ................... .... ... ................... ... ........3 7

Connection Recommendations ...........................................................................38

Output Buffer DC Impedance ..............................................................................38

Pull-up/Pull-down Resistor Requirements ..........................................................39

JTAG Configuration Signals ...............................................................................40

Package Mechanical Data .................................................................42

Package Parameters for the PC7447A, 360 HITCE ...........................................42

ii PC7447A [Preliminary] 5387A–HIREL–04/04

Definitions ..........................................................................................43

Datasheet Statu s Desc rip tio n .. ... ... ... .... ................... ... ................... .................... .43

Life Support Applications.....................................................................................43

Document Revision History ..............................................................43

Printed on recycled paper.

Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard

warranty which is detailed in Atmel’s Ter ms and Conditions located on th e Company’s web site. The Company assumes no responsibility fo r any

errors which may appear in this document, reser ves the right to change devices or specifications detailed herein at any time without notice, and

does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are

granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s prod ucts are not authorized for use

as critical components in life suppor t devices or systems.

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5387A–HIREL–04/04

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