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Rev.1.00 May 11, 2006 page 1 of 8
RD151TS3315ARP, RD151TS3325ARP
Spread Spectrum Clock for EMI Solution REJ03D0796-0100
Rev.1.00
May 11, 2006
Description
RD151TS3315ARP and RD151TS3325ARP is a high-performance Spread Spectrum Clock generator. It is suitable for
EMI solution of electric systems.
Features
• Supports 20 MHz to 40 MHz operations. Multiple rate (XIN: SSCOUT) = 1: 4
Input frequency 8 0 MHz to 160 MHz
• Spread spectrum modulation ; RD151TS3315ARP : ±1.5%, ±0.5% (Central spread modulation)
RD151TS3325ARP : –3.0%, –1.0% (Down spread modulation)
Key Specifications
• Supply volta ges: VDD = 3.3 V ±0.3 V
• Cycle to cycle jitter = ±100 ps typ.
• Clock output duty cycle = 50 ±5%
• Output slew ra t e = 0.7 V/ns t y p.
• Ordering In formation
Part Name Package Type Package Code
(Previous Code) Package
Abbreviation Taping Abbreviation
(Quantity)
RD151TS3315ARPH0
RD151TS3325ARPH0 SOP-8 pin
(JEDEC) PRSP0008DD-C
(FP-8DCV) RP H (2,500 pcs / Reel)
Block Diagram
Synthesizer
Mode Control
1/N
OSC
SSC Modulator
VDD
SSCOUT
NC
GND
SEL
XIN
XOUT
SSN
1/M
R = 350 kΩ
R = 350 kΩ
R = 1 MΩ
RD151TS3315ARP, RD151TS3325ARP
Rev.1.00 May 11, 2006 page 2 of 8
Pin Arrangement
(Top view)
8 VDD
1
7 SEL
6SSCOU
T
5 GND
XIN
2
XO UT
3
4
SSN
NC
Pin Descriptions
Pin name No. Type Description
GND 5 Ground GND pin
VDD 8 Power Power supply pin.
NC 3 NC Don’t connect any VDD or GND.
SSCOUT 6 Output Spread spectrum modulated clock output.
XIN 1 Input Oscillator input.
XOUT 2 Output Oscillator output.
SEL 7 Input
SSC% mode select pin. LVCMOS level input.
Pull-down by internal resistor (350 kΩ).
SSN 4 Input
SSC ON/OFF select pin. LVCMOS level input.
Pull–down by internal resistor (350 kΩ).
SSC Function Table
STB SEL RD151TS3315ARP(Cen t ral spread) RD151TS3325ARP(Down spread)
0 0 ±1.5%*1 –3.0%*1
0 1 ±0.5% –1.0%
1 0
1 1 OFF OFF
Note: 1. ±1.5%(TS3315ARP) / -3.0%(TS3325ARP) S SC is selected for default by internal pull-down resistors.
Clock Frequency Table
PRODUCT XIN(MHz) SSCOUT(MHz) Multiply rate (XIN: SSCOUT)
RD151TS3315ARP 20 to 40 80 to 160 1:4
RD151TS3325ARP 20 to 40 80 to 160 1:4
RD151TS3315ARP, RD151TS3325ARP
Rev.1.00 May 11, 2006 page 3 of 8
Absolute Maximum Ratings
Item Symbol Ratings Unit Conditions
Supply voltage VDD –0.5 to 4.6 V
Input voltage VI –0.5 to 4.6 V
Output voltage *1 V
O –0.5 to VDD+0.5 V
Input clamp current IIK –50 mA VI < 0
Output clamp current IOK –50 mA VO < 0
Continuous output current IO ±50 mA VO = 0 to VDD
Maximum power dissipation 0.7 W Ta = 55°C (in still air)
Storage temperature Tstg –65 to +150 °C
Notes: Stresses beyond those listed und er “absolute maximum rat ings” may cause permanent damage to the device.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings
are observed.
Recommended Operating Conditions
Item Symbol Min Typ Max Unit Conditions
Supply voltage VDD 3.0 3.3 3.6 V
DC input signal voltage –0.3 — VDD+0.3 V
High level input voltage VIH 0.7×VDD — VDD+0.3 V
Low level input voltage VIL –0.3 — 0.3×VDD V
Input clock duty cycle 45 50 55 %
Operating temperature Ta –20 — 85 °C
DC Electrical Characteristics
Ta = –20 to 85 °C, VDD = 3.0 to 3.6 V
Item Symbol Min Typ Max Unit Test Conditions
— — ±20 VI = 0 V or 3.6 V, VDD = 3.6 V,
XIN pin
Input current II
— — ±100
µA
VI = 0 V or 3.6 V, VDD = 3.6 V,
SEL, SSN pins
Input capacitance CI — 3 — pF SEL, SSN pins
DC Electrical Characteristics / SSC Clock Output
Ta = –20 to 85 °C, VDD = 3.0 to 3.6 V
Item Symbol Min Typ Max Unit Test Conditions
VOH V
DD–0.2 — — V IOH = –1 mA Output voltage VOL — — 200 mV IOL = 1 mA
IOH — –44 — VOH = 1.5 V, VDD = 3.3 V Output current IOL — 44 —
mA VOL = 1.5 V, VDD = 3.3 V
Output impedance — 40 — Ω
Note: Parameters are target of design. Not 100% tested in production.
RD151TS3315ARP, RD151TS3325ARP
Rev.1.00 May 11, 2006 page 4 of 8
AC Electrical Characteristics / SSC Clock Output
Ta = 25°C, VDD = 3.3 V, CL = 15 pF
Item Symbol Min Typ Max Unit Test Conditions Notes
Operating current IDD — 24 30 mA
VDD = 3.3 V, CL = 15 pF,
XIN = 40 MHz
Cycle to cycle jitter *1 t
CCS — |100| — ps SEL = 0, CL = 0 pF
SSC = ±1.5% (TS3315ARP)
SSC = –3.0% (TS3325ARP)
Figure 1
Slew rate tSL — 2.0 5.0 V/ns
VDD = 3.3 V,
0.2 × VDD to 0.8 × VDD
Clock duty cycle 45 50 55 %
Stabilization time *2 — — 2 ms
Notes: Parameters are target of design. Not 100% tested in production.
1. Cycle to cycle jitter is included spread spectrum modulation.
2. Stabilization time is the time required for the integrated circ uit to obtain phase lock of its input signal after
power up.
SSCOUT
tcycle n
t
CCS
= (tcycle n)
–
(tcycle n+1)
tcycle n+1
Figure 1 Cycle to cycle jitter
RD151TS3315ARP, RD151TS3325ARP
Rev.1.00 May 11, 2006 page 5 of 8
Application Information
1. Recommended Circuit Configuration
The power supply circuit of the optimal performance on the application of a system should refer to Figure 2.
VDD decoupling is important to both reduce Jitter and EMI radiation.
The C1 decoupling capacitor should be placed as close to the VDD pin as possible, otherwise the increased trace
inductance will negate its deco upling capability.
8
1
7
SSCOUT
6
SEL
SSN 5
2
3
4
XIN
XOUT
R1
C1 C2
GND GND
GND
VDD
(Crystal or Reference input)
(Crystal or Not connection)
NC
Notes: C1 = High frequency supply decoupling capacito r.
(0.1 µF recommended)
C2 = Low frequency supply decoupling capacitor.
(22 µF recommended)
R1 = Match value to line impedance.
Figure 2 Recommended circuit configuration
RD151TS3315ARP, RD151TS3325ARP
Rev.1.00 May 11, 2006 page 6 of 8
2. Example Board Layout Configuration
1
7
6
5
3
2
4
Crystal connection
or Reference input
Crystal connection
or No connection
SSCOUT
P
G
G
G
0.1 µF
22 µF
FB
VDD
(+3.3V Supply)
G
Note: Via to GND plane
R1 = Match value to line impedance.
FB = Ferrite bead.
R1
Figure 3 Example Board Layout
RD151TS3315ARP, RD151TS3325ARP
Rev.1.00 May 11, 2006 page 7 of 8
3. Example of TS33XX EMI Solution IC’s Application
TS33XXA
System BUS
Memory
Graphics
System Cont.
SSCOUT
Spread Spectrum
Modulated Clock
CPU & ASIC
XTAL
Ref.
Clock
XIN
XOUT
3.3 V CMOS level ref. Clock
Figure 4 Ref. Clock Input Example
TS33XXA
System BUS
Memory
Graphics
System Cont.
SSCOUT
Spread Spectrum
Modulated Clock
CPU & ASIC
XIN
XOUT
XTAL
Figure 5 XTAL Ref. Clock Input Example
RD151TS3315ARP, RD151TS3325ARP
Rev.1.00 May 11, 2006 page 8 of 8
Package Dimensions
58
4
F
*1
*2
*3
pMx
y
1
E
Index mark
A
D
Z
H
E
b
p
Terminal cross section
( Ni/Pd/Au plating )
c
b
1
1
Detail F
A
L
L
θ
0.75
0.10
1.27
5.80 6.20
0.400.34
A1
5.30
MaxNomMin
Dimension in Millimeters
Symbol
Reference
1.75
1.270.600.40
3.95
0.250.140.10
0.46
0.250.200.15
6.10
8°0°
0.25
1.08
4.90
L1
Z
HE
y
x
θ
c
bp
A2
E
D
b1
c1
e
e
L
A
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
P-SOP8-3.95x4.9-1.27 0.085g
MASS[Typ.]
FP-8DCVPRSP0008DD-C
RENESAS CodeJEITA Package Code Previous Code
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