MR0DL08B Rev. 1.2, 6/20151Copyright © Everspin Technologies 2015
MR0DL08B
Dual Supply 128K x 8 MRAM
FEATURES
• 3.3VoltVDDpowersupplywitharangeof2.7Vto3.6V
• I/OVoltagerangesupportswide+1.65to+3.6Voltinterfaces
• Fast45nsread/writecycle
• SRAMcompatibletiming
• Unlimitedread&writeendurance
• Dataalwaysnon-volatilefor>20-yearsattemperature
• AllproductsmeetMSL-3moisturesensitivitylevel
• RoHS-compliantsmallfootprintBGApackage
INTRODUCTION
TheMR0DL08Bisadualpowersupply1,048,576-bitmagnetoresistiverandomaccessmemory(MRAM)
deviceorganizedas131,072wordsof8bits.ItsupportsI/Ovoltagesfrom+1.65to+3.6volts.The
MR0DL08BoersSRAMcompatible45nsread/writetimingwithunlimitedendurance.Dataisalways
non-volatileforgreaterthan20-years.Dataisautomaticallyprotectedonpowerlossbylow-voltageinhibit
circuitrytopreventwriteswithvoltageoutofspecication.TheMR0DL08Bistheidealmemorysolution
forapplicationsthatmustpermanentlystoreandretrievecriticaldataandprogramsquickly.
TheMR0DL08Bisavailableinsmallfootprint8mmx8mm,48-pinballgridarray(BGA)packagewith0.75
mmballcenters.
TheMR0DL08Bprovideshighlyreliabledatastorageoverawiderangeoftemperatures.Theproductis
oeredwithcommercialtemperature(0to+70°C).
RoHS
CONTENTS
1.DEVICEPINASSIGNMENT.........................................................................2
2.ELECTRICALSPECIFICATIONS.................................................................4
3.TIMINGSPECIFICATIONS.......................................................................... 8
4.ORDERINGINFORMATION.......................................................................13
5.MECHANICALDRAWING..........................................................................14
6.REVISIONHISTORY......................................................................................15
HowtoReachUs..........................................................................................15
BENEFITS
• OnememoryreplacesFLASH,SRAM,EEPROMandBBSRAMinsystems
forsimpler,moreecientdesigns
• Improvesreliabilitybyreplacingbattery-backedSRAM
MR0DL08B Rev. 1.2, 6/20152Copyright © Everspin Technologies 2015
CHIP
ENABLE
BUFFER
OUTPUT
ENABLE
BUFFER
ADDRESS
BUFFER
WRITE
ENABLE
BUFFER
G
E
17
OUTPUT ENABLE
128Kx 8 BIT
MEMORY
ARRAY
ROW
DECODER
COLUMN
DECODER
SENSE
AMPS
OUTPUT
BUFFER
WRITE
DRIVER
FINAL
WRITE
DRIVERS
WRITE ENABLE
W
A[16:0] 10
7
88
8
8
8
8
DQ[7:0]
1. DEVICE PIN ASSIGNMENT
Figure 1.1 Block Diagram
Table 1.1 Pin Functions
Signal Name Function
A AddressInput
E ChipEnable
W WriteEnable
G OutputEnable
DQ DataI/O
VDD PowerSupply
VDDQ I/OPowerSupply
VSS Ground
DC DoNotConnect
NC NoConnection,BallD3,H1,H6,G2ReservedforFutureExpansion
MR0DL08B
MR0DL08B Rev. 1.2, 6/20153Copyright © Everspin Technologies 2015
123456
G A A A A
AAEB
DQ AA
DQ
DQ C
VSS
DQ
VDDQ D
VDDQ
DQ
VSS E
DQ
A A
DQ F
NC
AA
WG
NC
A
AH
NC
NC
NC
DCDC
DC
A
DQ3
NC
DC
VDD
NC
NC
NC
NC
VDD
Figure 1.2 Pin Diagrams for Available Packages (Top View)
48 Pin FBGA
Table 1.2 Operating Modes
E1G1W1Mode VDD Current DQ[7:0]2
HX X Notselected ISB1,ISB2 Hi-Z
L H H Outputdisabled IDDR Hi-Z
L L H ByteRead IDDR DOut
LXL ByteWrite IDDW Din
1H=high,L=low,X=don’tcare
2Hi-Z=highimpedance
DEVICE PIN ASSIGNMENT MR0DL08B
MR0DL08B Rev. 1.2, 6/20154Copyright © Everspin Technologies 2015
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Thisdevicecontainscircuitrytoprotecttheinputsagainstdamagecausedbyhighstaticvoltagesor
electricelds;however,itisadvisedthatnormalprecautionsbetakentoavoidapplicationofany
voltagegreaterthanmaximumratedvoltagestothesehigh-impedance(Hi-Z)circuits.
Thedevicealsocontainsprotectionagainstexternalmagneticelds.Precautionsshouldbetaken
toavoidapplicationofanymagneticeldmoreintensethanthemaximumeldintensityspecied
inthemaximumratings.
Parameter Symbol Value Unit
CoreSupplyvoltage2VDD -0.5to4.0 V
I/OPowerSupplyvoltage2VDDQ -0.5to4.0 V
Voltageonanypin2
VIN -0.5to+4.0or
VDDQ+0.5
whichever is less
V
Outputcurrentperpin IOUT ±20 mA
Packagepowerdissipation3PD0.600 W
Temperatureunderbias TBIAS -10to85 °C
StorageTemperature Tstg -55to150 °C
Leadtemperatureduringsolder(3minutemax) TLead 260 °C
Maximummagneticeldduringwrite Hmax_write 2000 A/m
Maximummagneticeldduringreadorstandby Hmax_read 8000 A/m
1Permanentdevicedamagemayoccurifabsolutemaximumratingsareexceeded.Functionalopera-
tionshouldberestrictedtorecommendedoperatingconditions.Exposuretoexcessivevoltagesor
magneticeldscouldaectdevicereliability.
2AllvoltagesarereferencedtoVSS.
3 Powerdissipationcapabilitydependsonpackagecharacteristicsanduseenvironment.
Table 2.1 Absolute Maximum Ratings1
MR0DL08B
MR0DL08B Rev. 1.2, 6/20155Copyright © Everspin Technologies 2015
Table 2.2 Operating Conditions
MR0DL08B
Electrical Specications
Parameter Symbol Min Typical Max Unit
CorePowersupplyvoltage VDD 2.713.3 3.6 V
I/OPowersupplyvoltage VDDQ 1.651- 3.6 V
WriteinhibitvoltageVDD VWIDD 2.3 2.5 2.71V
WriteinhibitvoltageVDDQ VWIDDQ 1.2 1.4 1.651V
Inputhighvoltage(VDDQ=1.65-2.2V) VIH 1.4 - VDDQ+0.22 V
Inputhighvoltage(VDDQ=2.2-2.7V) VIH 1.8 - VDDQ+0.22 V
Inputhighvoltage(VDDQ=2.7-3.6V) VIH 2.2 - VDDQ+0.22 V
Inputlowvoltage(VDDQ=1.65-2.2V) VIL -0.23- 0.4 V
Inputlowvoltage(VDDQ=2.2-2.7V) VIL -0.23- 0.6 V
Inputlowvoltage(VDDQ=2.7-3.6V) VIL -0.23- 0.8 V
AccessTime TA0 70 °C
Notes:
1. VDDQ≤VDD.WriteinhibitoccurswheneitherVDDorVDDQdropsbelowitswriteinhibitvoltage.Thereisa2msstartuptimeonce
VDDexceedsVDD(min).SeePowerUpandPowerDownSequencing.
2. VIH(max)=VDDQ+0.2VDC;VIH(max)=VDDQ+0.5VAC(pulsewidth≤20ns)forI≤20.0mA.
3. VIL(min)=-0.2VDC;VIL(min)=-2.0VAC(pulsewidth≤20ns)forI≤20.0mA.
MR0DL08B Rev. 1.2, 6/20156Copyright © Everspin Technologies 2015
Figure 2.1 Power Up and Power Down Sequencing
MR0DL08B
Electrical Specications
Power Up and Power Down Sequencing
Initial Power Up
TheMRAMisprotectedfromwriteoperationswheneverVDDislessthanVWIDD.UponpowerupVDDmustgo
above3.0V,anda2msstartuptimemustbeobservedbeforereadorwriteoperationscanstart.Thistime
allowsmemorypowersuppliestostabilize.
Power Loss or Brownout
DuringpowerlossorbrownoutwhereVDDgoesbelowVWIDDwritesareinhibited.Toreturntonormalopera-
tionandexitWriteInhibit,VDDmustgoabove3.0V,anda2msstartuptimemustbeobserved.Oncepow-
eredup,VDDminimumcangoaslowas2.7V.
Chip Enable and Write Enable
TheEandWcontrolsignalsshouldtrackVDDonpoweruptoVDD-0.2VorVIH(whicheverislower)andremain
highforthestartuptime.Inmostsystems,thismeansthatthesesignalsshouldbepulledupwitharesis-
torsothatsignalremainshighifthedrivingsignalisHi-Zduringpowerup.AnylogicthatdrivesEandW
shouldholdthesignalshighwithapower-onresetsignalforlongerthanthestartuptime.
BROWNOUT or POWER LOSS
NORMAL
OPERATION
VDD / VDDQ
READ/WRITE
INHIBITED
VWIDD
VWIDDQ
2 ms
READ/WRITE
INHIBITED
VIH
STARTUP
NORMAL
OPERATION
2 ms
E
W
RECOVER
VIH
MR0DL08B Rev. 1.2, 6/20157Copyright © Everspin Technologies 2015
Parameter Symbol Typical Max Unit
ACactivesupplycurrent-readmodes1
(IOUT=0mA,VDD=max) IDDR 25 30 mA
ACactivesupplycurrent-writemodes1
(VDD=max) IDDW 55 65 mA
ACactiveoperatingcurrent
(VDDQ=VIH=3.6V,VIL=0V)
input transitions <2ns, no output load
IDDQ 0.50 2 mA
ACstandbycurrent
(VDD=max,E=VIH)
no other restrictions on other inputs
ISB1 6 8 mA
CMOSstandbycurrent
(E≥VDD-0.2VandVIn≤VSS+0.2Vor≥VDDQ-0.2V)
(VDD=max,f=0MHz)
ISB2 5 7 mA
1 Allactivecurrentmeasurementsaremeasuredwithoneaddresstransitionpercycleandatminimumcycletime.
Parameter Symbol Min Typical Max Unit
Inputleakagecurrent Ilkg(I) - - ±1 μA
Outputleakagecurrent Ilkg(O) - - ±1 μA
Outputlowvoltage(VDDQ=1.65-2.2V@0.1mA) VOL - - 0.2 V
Outputlowvoltage(VDDQ=2.2-2.7V@0.1mA) VOL - - 0.4 V
Outputlowvoltage(VDDQ=2.7-3.6V@2.1mA) VOL - - 0.4 V
Outputhighvoltage(VDDQ=1.65-2.2V@-0.1mA) VOH 1.4 - - V
Outputhighvoltage(VDDQ=2.2-2.7V@-0.1mA) VOH 2 - - V
Outputhighvoltage(VDDQ=2.7-3.6V@-1.0mA) VOH 2.4 - - V
Table 2.3 DC Characteristics
Table 2.4 Power Supply Characteristics
MRD08B
Electrical Specications
MR0DL08B Rev. 1.2, 6/20158Copyright © Everspin Technologies 2015
MR0DL08B
3. TIMING SPECIFICATIONS
Table 3.1 Capacitance1
Parameter Symbol Typical Max Unit
Addressinputcapacitance CIn - 6 pF
Controlinputcapacitance CIn - 6 pF
Input/Outputcapacitance CI/O - 8 pF
1 f=1.0MHz,VDDQ=VDDQ(typ),TA=25°C,periodicallysampledratherthan100%tested.
Table 3.2 AC Measurement Conditions
Figure 3.1 Output Load Test Low and High
Figure 3.2 Output Load Test All Others
Parameter VDDQ=1.8 VDDQ=2.5 VDDQ=3.3 Unit
Logicinputtimingmeasurementreferencelevel 0.8 0.8 0.8 V
Logicoutputtimingmeasurementreferencelevel 0.8 0.8 0.8 V
Logicinputpulselevels 0or1.8 0or2.5 0or3.3 V
Outputloadvoltage(VL)forlow&highimpedance
parameters(Figure3.1) 0.8 1.2 1.75 V
Outputloadresistor(R1)forallothertiming 13,500 16,600 1,103 Ω
Outputloadresistor(R2)forallothertiming 10,800 15,400 1,554 Ω
V
Output
L
RL= 50 Ω
ZD= 50 Ω
Output
R2
R1
30 pF
VDDQ
MR0DL08B Rev. 1.2, 6/20159Copyright © Everspin Technologies 2015
MR0DL08B
Timing Specications
Parameter Symbol Min Max Unit
Readcycletime tAVAV 45 - ns
Addressaccesstime tAVQV - 45 ns
Enableaccesstime2tELQV - 45 ns
Outputenableaccesstime tGLQV - 20 ns
Outputholdfromaddresschange tAXQX 3- ns
Enablelowtooutputactive3tELQX 3- ns
Outputenablelowtooutputactive3tGLQX 0 - ns
EnablehightooutputHi-Z3tEHQZ 0 15 ns
OutputenablehightooutputHi-Z3tGHQZ 0 15 ns
1 Wishighforreadcycle.Powersuppliesmustbeproperlygroundedanddecoupled,andbuscontentionconditionsmustbe
minimizedoreliminatedduringreadorwritecycles.
2 AddressesvalidbeforeoratthesametimeEgoeslow.
3 Thisparameterissampledandnot100%tested.Transitionismeasured±200mVfromthesteady-statevoltage.
Table 3.3 Read Cycle Timing1
Read Mode
Figure 3.3A Read Cycle 1
Figure 3.3B Read Cycle 2
A (ADDRESS)
E (CHIP ENABLE)
G (OUTPUT ENABLE)
Q (DATA OUT) Data Valid
tAVAV
tAVQV
tELQV
tELQX
tGHQZ
tEHQZ
tGLQV
tGLQX
A (ADDRESS)
Q (DATA OUT)
tAVAV
tAXQX
tAVQV
Previous Data Valid Data Valid
NOTE:Deviceiscontinuouslyselected(E≤VIL,G≤VIL)
MR0DL08B Rev. 1.2, 6/201510Copyright © Everspin Technologies 2015
MR0DL08B
Timing Specications
Table 3.4 Write Cycle Timing 1 (W Controlled)1
Parameter Symbol Min Max Unit
Writecycletime2tAVAV 45 - ns
Addressset-uptime tAVWL 0 - ns
Addressvalidtoendofwrite(Ghigh) tAVWH 25 - ns
Addressvalidtoendofwrite(Glow) tAVWH 25 - ns
Writepulsewidth(Ghigh) tWLWH
tWLEH
20 - ns
Writepulsewidth(Glow) tWLWH
tWLEH
20 - ns
Datavalidtoendofwrite tDVWH 15 - ns
Dataholdtime tWHDX 0 - ns
WritelowtodataHi-Z3tWLQZ 0 15 ns
Writehightooutputactive3tWHQX 3- ns
Writerecoverytime tWHAX 12 - ns
1 AllwritesoccurduringtheoverlapofElowandWlow.Powersuppliesmustbeproperlygroundedanddecoupledandbus
contentionconditionsmustbeminimizedoreliminatedduringreadandwritecycles.IfGgoeslowatthesametimeorafter
Wgoeslow,theoutputwillremaininahighimpedancestate.AfterWorEhasbeenbroughthigh,thesignalmustremainin
steady-statehighforaminimumof2ns.TheminimumtimebetweenEbeingassertedlowinonecycletoEbeingasserted
lowinasubsequentcycleisthesameastheminimumcycletimeallowedforthedevice.
2 Allwritecycletimingsarereferencedfromthelastvalidaddresstothersttransitionaddress.
3 Thisparameterissampledandnot100%tested.Transitionismeasured±200mVfromthesteady-statevoltage.Atanygiven
voltageortemperature,tWLQZ(max)<tWHQX(min)
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
Q (DATA OUT)
D (DATA IN)
tAVAV
tAVWH tWHAX
tWLEH
tWHDX
tDVWH
tWHQX
tAVWL
t
Hi-Z Hi-Z
WLQZ
tWLWH
Data Valid
Figure 3.4 Write Cycle Timing 1 (W Controlled)
MR0DL08B Rev. 1.2, 6/201511Copyright © Everspin Technologies 2015
MR0DL08B
Timing Specications
Table 3.5 Write Cycle Timing 2 (E Controlled)1
Figure 3.5 Write Cycle Timing 2 (E Controlled)
Parameter Symbol Min Max Unit
Writecycletime2tAVAV 45 - ns
Addressset-uptime tAVEL 0 - ns
Addressvalidtoendofwrite(Ghigh) tAVEH 25 - ns
Addressvalidtoendofwrite(Glow) tAVEH 25 - ns
Enabletoendofwrite(Ghigh) tELEH
tELWH
20 - ns
Enabletoendofwrite(Glow)3tELEH
tELWH
20 - ns
Datavalidtoendofwrite tDVEH 15 - ns
Dataholdtime tEHDX 0 - ns
Writerecoverytime tEHAX 12 - ns
1 AllwritesoccurduringtheoverlapofElowandWlow.Powersuppliesmustbeproperlygroundedanddecoupledandbus
contentionconditionsmustbeminimizedoreliminatedduringreadandwritecycles.IfGgoeslowatthesametimeorafter
Wgoeslow,theoutputwillremaininahighimpedancestate.AfterWorEhasbeenbroughthigh,thesignalmustremainin
steady-statehighforaminimumof2ns.TheminimumtimebetweenEbeingassertedlowinonecycletoEbeingasserted
lowinasubsequentcycleisthesameastheminimumcycletimeallowedforthedevice.
2 Allwritecycletimingsarereferencedfromthelastvalidaddresstothersttransitionaddress.
3 IfEgoeslowatthesametimeorafterWgoeslow,theoutputwillremaininahigh-impedancestate.IfEgoeshighatthe
sametimeorbeforeWgoeshigh,theoutputwillremaininahigh-impedancestate.
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
Q (DATA OUT)
D (DATA IN)
t
AVAV
t
AVEH
t
EHAX
t
ELEH
t
EHDX
t
DVEH
t
AVEL
Hi-Z
t
ELWH
Data Valid
MR0DL08B Rev. 1.2, 6/201512Copyright © Everspin Technologies 2015
MR0DL08B
Timing Specications
Table 3.6 Write Cycle Timing 3 (Shortened tWHAX, W and E Controlled)1
Table 3.6 Write Cycle Timing 3 (Shortened tWHAX, W and E Controlled)
Parameter Symbol Min Max Unit
Writecycletime2tAVAV 45 - ns
Addressset-uptime tAVWL 0 - ns
Addressvalidtoendofwrite(Ghigh) tAVWH 25 - ns
Addressvalidtoendofwrite(Glow) tAVWH 25 - ns
Writepulsewidth tWLWH
tWLEH
20 - ns
Datavalidtoendofwrite tDVWH 15 - ns
Dataholdtime tWHDX 0 - ns
Enablerecoverytime tEHAX -2 - ns
Writerecoverytime3tWHAX 6 - ns
Writetoenablerecoverytime3tWHEL 12 - ns
1 AllwritesoccurduringtheoverlapofElowandWlow.Powersuppliesmustbeproperlygroundedanddecoupledandbus
contentionconditionsmustbeminimizedoreliminatedduringreadandwritecycles.IfGgoeslowatthesametimeorafter
Wgoeslow,theoutputwillremaininahighimpedancestate.AfterWorEhasbeenbroughthigh,thesignalmustremainin
steady-statehighforaminimumof2ns.TheminimumtimebetweenEbeingassertedlowinonecycletoEbeingasserted
lowinasubsequentcycleisthesameastheminimumcycletimeallowedforthedevice.
2 Allwritecycletimingsarereferencedfromthelastvalidaddresstothersttransitionaddress.
3 IfEgoeslowatthesametimeorafterWgoeslow,theoutputwillremaininahigh-impedancestate.IfEgoeshighatthe
sametimeorbeforeWgoeshigh,theoutputwillremaininahigh-impedancestate.
tAVWL
tAVAV
tAVWH
t
WLWH
t
WLEH
t
DVWH
t
WHDX
tWHAX
t
WHEL
W (WRITE ENABLE)
A (ADDRESS)
E (CHIP ENABLE)
D (DATA IN)
MR0DL08B Rev. 1.2, 6/201513Copyright © Everspin Technologies 2015
MR0DL08B
4. ORDERING INFORMATION
Figure 4.1 Part Numbering System
Carrier (Blank= Tray,R=Tape & Reel)
Speed (45 = 45 ns)
Package (MA = FBGA)
Temperature Range (Blank= 0 to +70 °C)
Revision (B = Revision)
Data Width (08 = 8-Bit)
Type (DL= Dual Supply Low Voltage)
Density (0 = 1Mb)
Part Type (MR = Magnetoresistive
RAM)
MR 0 DL 08 B MA 45 R
Part Number Description Temperature
MR0DL08BMA45 DualSupply128x8MRAM48-BGA Commercial
MR0DL08BMA45R DualSupply128x8MRAM48-BGA
Tape&Reel Commercial
Table 4.1 Available Parts
MR0DL08B Rev. 1.2, 6/201514Copyright © Everspin Technologies 2015
TOP VIEW
BOTTOM VIEW SIDE VIEW
0.41
0.31 0.32
0.22
Figure 5.1 FBGA
Print Version Not To Scale
1. DimensionsinMillimeters.
2. DimensionsandtolerancesperASMEY14.5M-1994.
3. MaximumsolderballdiametermeasuredparalleltoDATUMA
4. DATUMA,theseatingplaneisdeterminedbythesphericalcrownsof
thesolderballs.
5. Parallelismmeasurementshallexcludeanyeectofmarkontopsur-
faceofpackage.
MR0DL08B
Mechanical Drawings
MR0DL08B Rev. 1.2, 6/201515Copyright © Everspin Technologies 2015
MR0DL08B
Revision Date Description of Change
1Nov19,2013 InitialDataSheetRelease
1.1 May19,2015 Revisedcontactinformation.
1.2 June11,2015 CorrectedJapanSalesOcetelephonenumber.
6. REVISION HISTORY
MR0DL08B Rev. 1.2, 6/201516Copyright © Everspin Technologies 2015
Everspin Technologies, Inc.
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tionorguaranteeregardingthesuitabilityofitsproductsforanyparticular
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parametersincluding“Typicals”mustbevalidatedforeachcustomerap-
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ifsuchclaimallegesthatEverspinTechnologieswasnegligentregarding
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