REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R232-94. 94-09-30 Michael A. Frye B Update drawing to reflect current requirements. Editorial changes throughout. - gap 01-02-26 Raymond Monnin C Boilerplate update and part of five year review. tcr 06-09-26 Raymond Monnin THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV C C C C C C C C C SHEET 15 16 17 18 19 20 21 22 23 REV STATUS REV C C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Tuan Nguyen STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http://www.dscc.dla.mil CHECKED BY Jeff Bowling APPROVED BY THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A Michael A. Frye MICROCIRCUIT, MEMORY, CMOS, 1K X 9 PARALLEL FIFO, MONOLITHIC SILICON DRAWING APPROVAL DATE 93-10-08 REVISION LEVEL C SIZE CAGE CODE A 67268 SHEET DSCC FORM 2233 APR 97 1 OF 5962-91585 23 5962-E597-06 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 91585 Federal stock class designator \ RHA designator (see 1.2.1) 01 M X X Device type (see 1.2.2) Device class designator (see 1.2.3) Case outline (see 1.2.4) Lead finish (see 1.2.5) / \/ Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type 01 02 03 04 05 06 Generic number Circuit function 7202SA 7202SA 7C424, 7C425 7C424, 7C425 7C424, 7C425 7C424, 7C425 1K X 9 FIFO 1K X 9 FIFO 1K X 9 FIFO 1K X 9 FIFO 1K X 9 FIFO 1K X 9 FIFO Access time 120 ns 80 ns 65 ns 50 ns 40 ns 30 ns 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, nonJAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter X Y Z U Descriptive designator CDIP3-T28 or GDIP4-T28 CDIP2-T28 or GDIP1-T28 GDFP2-F28 CQCC1-N32 Terminals Package style 28 28 28 32 Dual-in-line package Dual-in-line package Flat pack Rectangular chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91585 A REVISION LEVEL C SHEET 2 1.3 Absolute maximum ratings. 1/ Supply voltage range to ground potential (VCC) .............................. DC voltage range applied to outputs in High Z state ..................... DC input voltage range (VIN) .......................................................... DC output current ......................................................................... Maximum power dissipation .......................................................... Lead temperature (soldering, 10 seconds) ................................... Thermal resistance, junction-to-case (JC) .................................... Junction temperature (TJ) ............................................................. Storage temperature range (TSTG) ................................................ Temperature under bias ............................................................... -0.5 V dc to +7.0 V dc -0.5 V dc to +7.0 V dc -0.5 V dc to +7.0 V dc 20 mA 1.0 W +260C See MIL-STD-1835 +175C -65C to +150C -55C to +125C 1.4 Recommended operating conditions. Supply voltage (VCC) ..................................................................... Ground voltage (GND) .................................................................. Input high voltage (VIH) ................................................................. Input low voltage (VIL) ................................................................... Case operating temperature range (TC) ........................................ +4.5 V dc minimum to +5.5 V dc maximum 0 V dc 2.2 V dc minimum 0.8 V dc maximum -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 MIL-STD-1835 - Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 MIL-HDBK-780 - List of Standard Microcircuit Drawings. Standard Microcircuit Drawings. (Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91585 A REVISION LEVEL C SHEET 3 2.2 Non-Government publications. The following documents form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation. ELECTRONIC INDUSTRIES ALLIANCE (EIA) JEDEC Standard EIA/JESD 78 - IC Latch-Up Test. (Applications for copies should be addressed to the Electronics Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201; http://www.jedec.org.) (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91585 A REVISION LEVEL C SHEET 4 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 105 (see MIL-PRF-38535, appendix A). 4. VERIFICATION 4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. 4.2.1 Additional criteria for device class M. a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015. (2) TA = +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table IIA herein. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91585 A REVISION LEVEL C SHEET 5 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TC +125C 4.5 V VCC 5.5 V unless otherwise specified VCC = 4.5 V, IOH = -2.0 mA VIN = VIH(Min), VIL(Max) VCC = 4.5 V, IOL = 8.0 mA VIN = VIH(Min), VIL(Max) Group A subgroups Device type 1, 2, 3 All 1, 2, 3 All 1, 2, 3 All 1, 2, 3 All Limits Min 2.4 Unit Max Output high voltage VOH Output low voltage VOL Input high voltage Input leakage current VIH 2/ VIL 2/ IIX VIN = 5.5 V to GND 1, 2, 3 All -10 10 A Output leakage current IOZ VCC = 5.5 V, 1, 2, 3 All -10 10 A Operating supply current ICC1 R = VIH, VOUT = 5.5 V and GND VCC = 5.5 V, IOUT = 0 mA f = 1/tRC 1, 2, 3 01-04 115 mA 05 130 06 140 1, 2, 3 All 30 mA 1, 2, 3 All 25 mA 4 All 8 pF 4 All 12 pF 7, 8A, 8B All Input low voltage W , R , DO - D8 pins are toggling between 0 V and 3 V V 0.4 V 2.2 V 0.8 V FF , XO / HF = 0 mA Q0 - Q8 = 0 mA Standby current Power down current Input capacitance MR , FL / FT = 3.0 V VCC = 5.5 V, IOUT = 0 mA All inputs = VIH ICC2 FF , XO / HF = 0 mA Q0 - Q8 = 0 mA VCC = 5.5 V, IOUT = 0 mA All inputs = VCC -0.2 V ICC3 CIN 3/ Output capacitance COUT 3/ Functional tests FF , XO / HF = 0 mA Q0 - Q8 = 0 mA VCC = 5.0 V, VIN = 0 V TA = +25C, f = 1 MHz See 4.4.1e VCC = 5.0 V, VOUT = 0 V TA = +25C, f = 1 MHz See 4.4.1e See 4.4.1c See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91585 A REVISION LEVEL C SHEET 6 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ -55C TC +125C 4.5 V VCC 5.5 V unless otherwise specified See figure 4 Group A subgroups Device type 9, 10, 11 01 02 03 04 05 06 01 02 03 04 05 06 01, 02 Read cycle time tRC Access time tA 9, 10, 11 Read recovery time tRR 9, 10, 11 tPR 9, 10, 11 tLZR 9, 10, 11 03, 04 05, 06 01 02 03 04 05 06 All tDVR 9, 10, 11 All tHZR 9, 10, 11 Write cycle time tWC 9, 10, 11 Write pulse width tPW 9, 10, 11 01 02-04 05 06 01 02 03 04 05 06 01 02 03 04 05 06 Read pulse width 4/ Read low to low Z 3/, 5/ Read high to data valid 6/ Read high to high Z 3/, 5/, 6/ 4/ Limits Min 140 100 80 65 50 40 Unit Max ns 120 80 65 50 40 30 ns 20 ns 15 10 120 80 65 50 40 30 3 ns ns 3 ns 35 30 25 20 ns 140 100 80 65 50 40 120 80 65 50 40 30 ns ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91585 A REVISION LEVEL C SHEET 7 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ -55C TC +125C 4.5 V VCC 5.5 V Group A subgroups Limits 9, 10, 11 All Min 10 tWR 9, 10, 11 Data setup time tSD 9, 10, 11 Data hold time tHD 9, 10, 11 Master reset cycle time tMRSC 9, 10, 11 Master reset pulse width 4/ tPMR 9, 10, 11 Master reset recovery time tRMR 9, 10, 11 Read high to master reset high 8/ tRPW 9, 10, 11 Write high to master reset high 8/ tWPW 9, 10, 11 Retransmit cycle time tRTC 9, 10, 11 01, 02 03, 04 05, 06 01, 02 03, 04 05 06 01-03 04 05, 06 01 02 03 04 05 06 01 02 03 04 05 06 01, 02 03, 04 05, 06 01 02 03 04 05 06 01 02 03 04 05 06 01 02 03 04 05 06 20 15 10 40 30 20 18 10 5 0 140 100 80 65 50 40 120 80 65 50 40 30 20 15 10 120 80 65 50 40 30 120 80 65 50 40 30 140 100 80 65 50 40 Write high to low Z 3/, 5/, 7/ Write recovery time tHWZ unless otherwise specified See figure 4 Device type Unit Max ns ns ns ns ns ns ns ns ns ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91585 A REVISION LEVEL C SHEET 8 TABLE I. Electrical performance characteristics - Continued. Test Retransmit pulse width Symbol tPRT Conditions 1/ -55C TC +125C 4.5 V VCC 5.5 V Group A subgroups unless otherwise specified See figure 4 9, 10, 11 4/ Retransmit recovery time tRTR 9, 10, 11 Master reset to empty flag low tEFL 9, 10, 11 Master reset to halffull flag high tHFH 9, 10, 11 Master reset to full flag high tFFH 9, 10, 11 Read low to empty flag low tREF 9, 10, 11 Read high to full flag high tRFF 9, 10, 11 Write high to empty flag high tWEF 9, 10, 11 Write low to full flag low tWFF 9, 10, 11 Device type 01 02 03 04 05 06 01, 02 03, 04 05, 06 01 02 03 04 05 06 01 02 03 04 05 06 01 02 03 04 05 06 01-03 04 05 06 01-03 04 05 06 01-03 04 05 06 01-03 04 05 06 Limits Min 120 80 65 50 40 30 20 15 10 Unit Max ns ns 140 100 80 65 50 40 140 100 80 65 50 40 140 100 80 65 50 40 60 45 35 30 60 45 35 30 60 45 35 30 60 45 35 30 ns ns ns ns ns ns ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91585 A REVISION LEVEL C SHEET 9 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ -55C TC +125C 4.5 V VCC 5.5 V Group A subgroups unless otherwise specified See figure 4 tWHF Read high to half-full flag high tRHF 9, 10, 11 Effective read pulse width after empty flag high tRPE 9, 10, 11 Effective write pulse width after full flag high tWPF 9, 10, 11 Expansion out low delay from clock tXOL 9, 10, 11 Expansion out high delay from clock tXOH 9, 10, 11 2/ 3/ 4/ 5/ 6/ 7/ 8/ Limits Min Write low to half-full flag low 1/ Device type 9, 10, 11 01 02 03 04 05 06 01 02 03 04 05 06 01 02 03 04 05 06 01 02 03 04 05 06 01 02 03 04 05 06 01 02 03 04 05 06 Unit Max 140 100 80 65 50 40 140 100 80 65 50 40 ns ns 120 80 65 50 40 30 120 80 65 50 40 30 ns ns 120 80 65 50 40 30 120 80 65 50 40 30 ns ns AC tests are performed with input rise and fall times of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and the output load in figure 3, circuit A, unless otherwise specified. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. Tested initially and after any design or process changes that affect that parameter, and therefore shall be guaranteed to the limits specified in table I. Pulse widths less than minimum are not allowed. Transition is measured at steady-state high level -500 mV or steady-state low level +500 mV on the output from the 1.5 V level on the input. Use output load figure 3 (circuit B). Only applies to read data flow-through mode. If not tested, these parameter limits shall be guaranteed by design. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91585 A REVISION LEVEL C SHEET 10 Device types Case outlines Terminal number 1 2 All X, Y, Z U Terminal symbol 3 4 5 6 7 D3 D2 D1 D0 8 FF Q0 9 10 11 12 13 14 15 16 17 18 NC W D8 W D8 D3 D2 D1 D0 XI XI FF Q0 Q1 NC Q2 Q3 Q8 Q1 Q2 Q3 Q8 GND R Q4 Q5 Q6 GND NC 19 20 XO / HF R Q4 Q5 21 EF Q6 22 MR Q7 23 FL / RT XO / HF 24 D7 EF 25 D6 MR 26 D5 27 28 29 30 31 32 D4 VCC --------- FL / RT NC D7 D6 D5 D4 VCC Q7 NC = no connection FIGURE 1. Terminal connections. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91585 A REVISION LEVEL C SHEET 11 Reset and retransmit Single device configuration/width expansion mode Inputs Mode MR 0 1 1 Reset Retransmit Read/write RT X 0 1 XI 0 0 0 Internal status Read pointer Write pointer Location zero Location zero Increment 1/ Outputs EF 0 X X Location zero Unchanged Increment 1/ FF 1 X X HF 1 X X 1/ Pointer will increment if flag is high. Reset and first load truth table Depth expansion/compound expansion mode Inputs Mode Reset first device Reset all other devices Read/write MR 0 0 1 FL 0 1 X XI 1/ 1/ 1/ Internal status Read pointer Write pointer Location zero Location zero X Location zero Location zero X Outputs EF 0 0 X FF 1 1 X 1/ XI is connected to XO of previous device. NOTE: MR = Reset input, FL / RT = First load/retransmit EF = Empty flag output, FF = Full flag output, XI = Expansion input, and HF = Half-full flag output 0 = Low level voltage 1 = High level voltage X = Don't care FIGURE 2. Truth table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91585 A REVISION LEVEL C SHEET 12 Circuit A Output load Circuit B Output load NOTE: Including scope and jig. (minimum values) AC test conditions Input pulse levels GND to 3.0 V Input rise and fall times 5 ns Input timing reference levels 1.5 V Output reference levels 1.5 V FIGURE 3. Output load circuit and test conditions. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91585 A REVISION LEVEL C SHEET 13 Asynchronous read and write timing diagram FIGURE 4. Timing waveforms. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91585 A REVISION LEVEL C SHEET 14 Last read to first write empty flag timing diagram Retransmit timing diagram (See note 2) (See note 1) NOTES: 1. tRTC = tPRT + tRTR 2. EF , HF and FF may change state during retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTC. FIGURE 4. Timing waveforms - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91585 A REVISION LEVEL C SHEET 15 Empty flag and read bubble-through mode timing diagram Master reset timing diagram NOTES: 1. tMRSC = tPMR + tRMR 2. W and R = VIH around the rising edge of MR . FIGURE 4. Timing waveforms - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91585 A REVISION LEVEL C SHEET 16 Half-full flag timing diagram Last write to first read full flag timing diagram FIGURE 4. Timing waveforms - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91585 A REVISION LEVEL C SHEET 17 Full flag and write bubble-through mode timing diagram FIGURE 4. Timing waveforms - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91585 A REVISION LEVEL C SHEET 18 Expansion timing diagrams NOTE: Expansion out of device 1 ( XO 1) is connected to expansion in of device 2 ( XI 2) FIGURE 4. Timing waveforms - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91585 A REVISION LEVEL C SHEET 19 4.2.2 Additional criteria for device classes Q and V. a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as specified in table IIA herein. c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in MIL-PRF-38535, appendix B. 4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4.1 Group A inspection. a. Tests shall be as specified in table IIA herein. b. Subgroups 5 and 6 of table I of method 5005 of MIL-STD-883 shall be omitted. c. For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table. For device classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device. d. O/V (latch-up) tests shall be measured only for initial qualification and after any design or process changes which may affect the performance of the device. For device class M, procedures and circuits shall be maintained under document revision level control by the manufacturer and shall be made available to the preparing activity or acquiring activity upon request. For device classes Q and V, the procedures and circuits shall be under the control of the device manufacturer's TRB in accordance with MIL-PRF-38535 and shall be made available to the preparing activity or acquiring activity upon request. Testing shall be on all pins, on five devices with zero failures. Latch-up test shall be considered destructive. Information contained in JEDEC Standard EIA/JESD 78 may be used for reference. e. Subgroup 4 (CIN and COUT measurements) shall be measured only for initial qualification and after any process or design changes which may affect input or output capacitance. Capacitance shall be measured between the designated terminal and GND at a frequency of 1 MHz. Sample size is 15 devices with no failures, and all input and output terminals tested. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91585 A REVISION LEVEL C SHEET 20 TABLE IIA. Electrical test requirements. Line No. 1 Test requirements Subgroups (in accordance with MIL-STD-883, method 5005, table I) Device class M Interim electrical parameters (see 4.2) Static burn-in I and II method 1015 Same as line 1 2 3 4 6 Final electrical parameters Group A test requirements Group C end-point electrical parameters Group D end-point electrical parameters Group E end-point electrical parameters 7 8 9 10 1/ 2/ 3/ 4/ 5/ Subgroups (per MIL-PRF-38535, table III) Device class Q 1, 7, 9 Not required Not required Required Required Dynamic burn-in (method 1015) Same as line 1 5 1/, 2/, 3/, 4/, 5/ Device class V 1, 7, 9 Required 1*, 7* Required 1*, 2, 3, 7*, 8A, 8B, 9, 10, 11 1*, 2, 3, 7*, 8A, 8B, 9, 10, 11 1*, 7* 1*, 2, 3, 7*, 8A, 8B, 9, 10, 11 1, 2, 3, 4**, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 4**, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 4**, 7, 8A, 8B, 9, 10, 11 2, 3, 7, 8A, 8B 2, 3, 7, 8A, 8B 1, 2, 3, 7, 8A, 8B, 9, 10, 11 2, 3, 7, 8A, 8B 2, 3, 7, 8A, 8B 2, 3, 7, 8A, 8B 1, 7, 9 1, 7, 9 1, 7, 9 Blank spaces indicate tests are not applicable. Any or all subgroups may be combined when using high-speed testers. * indicates PDA applies to subgroup 1 and 7. ** see 4.4.1e. indicates delta limit (see table IIB) shall be required where specified, and the delta values shall be computed with reference to the previous interim electrical parameters (line 1). TABLE IIB. Delta limits at +25C. Parameter 1/ IIX IOZ Device types All 10 percent of specified value in table I 10 percent of specified value in table I 10 percent of specified value in table I 1/ The above parameter shall be recorded before and after the required burn-in and life tests to determine the delta. ICC2 standby STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91585 A REVISION LEVEL C SHEET 21 4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein. 4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883: a. Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MILSTD-883. b. TA = +125C, minimum. c. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. 4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD883. 4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein. 4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured (see 3.5 herein). a. End-point electrical parameters shall be as specified in table IIA herein. b. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device classes must meet the postirradiation end-point electrical parameter limits as defined in table I at TA = +25C 5C, after exposure, to the subgroups specified in table IIA herein. 4.5 Delta measurements for device class Q and V. Delta measurements, as specified in table IIA, shall be made and recorded before and after the required burn-in screens and steady-state life tests to determine delta compliance. The electrical parameters to be measured, with associated delta limits are listed in table IIB. The device manufacturer may, at his option, either perform delta measurements or within 24 hours after burn-in perform final electrical parameter tests, subgroups 1, 7, and 9. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor prepared specification or drawing. 6.1.2 Substitutability. Device class Q devices will replace device class M devices. 6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91585 A REVISION LEVEL C SHEET 22 6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544. 6.4 Comments. Comments on this drawing should be directed to DSCC-VA , Columbus, Ohio 43218-3990, or telephone (614) 692-0547. 6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-PRF-38535 and MIL-HDBK-1331. CIN ......................................................Input terminal capacitance. COUT ...................................................Output and bidirectional output terminal capacitance. GND...................................................Ground zero voltage potential. ICC ......................................................Supply current. IIX........................................................Input current. IOZ ......................................................Output current. TC .......................................................Case temperature. VCC .....................................................Positive supply voltage. 6.5.1 Waveforms. Waveform Input Output symbol MUST BE VALID WILL BE VALID CHANGE FROM H TO L WILL CHANGE FROM H TO L CHANGE FROM L TO H WILL CHANGE FROM L TO H DON'T CARE ANY CHANGE PERMITTED CHANGING STATE UNKNOWN HIGH IMPEDANCE 6.6 Sources of supply. 6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535. The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to this drawing. 6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103. The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by DSCC-VA. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91585 A REVISION LEVEL C SHEET 23 STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 06-09-26 Approved sources of supply for SMD 5962-91585 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of supply at http://www.dscc.dla.mil/Programs/Smcr/. Standard microcircuit drawing PIN 1/ 5962-9158501MXA 5962-9158501MYA 5962-9158501MZA 5962-9158501MUA 5962-9158502MXA 5962-9158502MYA 5962-9158502MZA 5962-9158502MUA 5962-9158503MXA 5962-9158503MYA 5962-9158503MZA 5962-9158503MUA 5962-9158504MXA 5962-9158504MYA 5962-9158504MZA 5962-9158504MUA Vendor CAGE number 3/ Vendor similar PIN 2/ IDT7202SA120TCB 0C7V7 CY7C425-120DMB 3/ IDT7202SA120DB 0C7V7 CY7C424-120DMB 3/ IDT7202SA120XEB 0C7V7 CY7C425-120KMB 3/ IDT7202SA120LB 0C7V7 CY7C425-120LMB 3/ IDT7202SA80TCB 0C7V7 CY7C425-80DMB 3/ IDT7202SA80DB 0C7V7 CY7C424-80DMB 3/ IDT7202SA80XEB 0C7V7 CY7C425-80KMB 3/ IDT7202SA80LB 0C7V7 CY7C425-80LMB 0C7V7 CY7C425-65DMB 3/ IDT7202SA65TCB 3/ IDT7202SA65DB 0C7V7 CY7C424-65DMB 3/ IDT7202SA65XEB 0C7V7 CY7C425-65KMB 3/ IDT7202SA65LB 0C7V7 CY7C425-65LMB 3/ IDT7202SA50TCB 0C7V7 CY7C425-50DMB 3/ IDT7202SA50DB 0C7V7 CY7C424-50DMB 3/ IDT7202SA50XEB 0C7V7 CY7C425-50KMB 3/ IDT7202SA50LB 0C7V7 CY7C425-50LMB The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin. 1 of 2 Standard microcircuit drawing PIN 1/ 5962-9158505MXA 5962-9158505MYA 5962-9158505MZA 5962-9158505MUA 5962-9158506MXA 5962-9158506MYA 5962-9158506MZA 5962-9158506MUA Vendor CAGE number 3/ Vendor similar PIN 2/ IDT7202SA40TCB 0C7V7 CY7C425-40DMB 3/ IDT7202SA40DB 0C7V7 CY7C424-40DMB 3/ IDT7202SA40XEB 0C7V7 CY7C425-40KMB 3/ IDT7202SA40LB 0C7V7 CY7C425-40LMB 0C7V7 CY7C425-30DMB 3/ IDT7202SA30TCB 3/ IDT7202SA30DB 0C7V7 CY7C424-30DMB 3/ IDT7202SA30XEB 0C7V7 CY7C425-30KMB 0C7V7 CY7C425-30LMB 3/ IDT7202SA30LB 1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed contact the vendor to determine its availability. 2/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. 3/ Not available from an approved source of supply. Vendor CAGE number Vendor name and address 0C7V7 QP Semiconductor 2945 Oakmead Village Court Santa Clara, CA 95051 2