General Description
The MAX1277/MAX1279 are low-power, high-speed, seri-
al-output, 12-bit, analog-to-digital converters (ADCs) with
an internal reference that operates at up to 1.5Msps.
These devices feature true-differential inputs, offering bet-
ter noise immunity, distortion improvements, and a wider
dynamic range over single-ended inputs. A standard
SPI™/QSPI™/MICROWIRE™ interface provides the clock
necessary for conversion. These devices easily interface
with standard digital signal processor (DSP) synchronous
serial interfaces.
The MAX1277/MAX1279 operate from a single +2.7V to
+3.6V supply voltage. The MAX1277/MAX1279 include a
2.048V internal reference. The MAX1277 has a unipolar
analog input, while the MAX1279 has a bipolar analog
input. These devices feature a partial power-down mode
and a full power-down mode for use between conver-
sions, which lower the supply current to 2mA (typ) and
1µA (max), respectively. Also featured is a separate
power-supply input (VL), which allows direct interfacing to
+1.8V to VDD digital logic. The fast conversion speed,
low-power dissipation, excellent AC performance, and DC
accuracy (±1 LSB INL) make the MAX1277/MAX1279
ideal for industrial process control, motor control, and
base-station applications.
The MAX1277/MAX1279 come in a 12-pin TQFN pack-
age, and are available in the extended (-40°C to +85°C)
temperature range.
Applications
Data Acquisition Communications
Bill Validation Portable Instruments
Motor Control
Features
o1.5Msps Sampling Rate
oOnly 22mW (typ) Power Dissipation
oOnly 1µA (max) Shutdown Current
oHigh-Speed, SPI-Compatible, 3-Wire Serial Interface
o68.5dB S/(N + D) at 525kHz Input Frequency
oInternal True-Differential Track/Hold (T/H)
oInternal 2.048V Reference
oNo Pipeline Delays
oSmall 12-Pin TQFN Package
MAX1277/MAX1279
1.5Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
________________________________________________________________
Maxim Integrated Products
1
12
AIN+
11
N.C.
10
SCLK
45
N.C.
6
GND
1
2REF
3
9
8
7RGND
CNVST
DOUT
VL
MAX1277
MAX1279
AIN-
VDD
TQFN
TOP VIEW
PART
TEMP RANGE
PIN-
PACKAGE
INPUT
MAX1277AETC-T
-40°C to +85°C
12 TQFN
Unipolar
MAX1277BETC-T
-40°C to +85°C
12 TQFN
Unipolar
MAX1279AETC-T
-40°C to +85°C
12 TQFN
Bipolar
MAX1279BETC-T
-40°C to +85°C
12 TQFN
Bipolar
Pin Configuration
Ordering Information
MAX1277
MAX1279
DOUT
AIN+
4.7μF
10μF10μF
+2.7V TO +3.6V
0.01μF
0.01μF
0.01μF
+1.8V TO VDD
AIN-
REF
VDD
DIFFERENTIAL
INPUT
VOLTAGE
RGND
VL
GND
CNVST
SCLK
μC/DSP
+
-
Typical Operating Circuit
19-3365; Rev 1; 4/09
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
MAX1277/MAX1279
1.5Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +3.6V, VL= VDD, fSCLK = 24MHz, 50% duty cycle, TA= -40°C to +85°C, unless otherwise noted. Typical values are
at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to GND..............................................................-0.3V to +6V
VLto GND ................-0.3V to the lower of (VDD + 0.3V) and +6V
Digital Inputs
to GND .................-0.3V to the lower of (VDD + 0.3V) and +6V
Digital Output
to GND....................-0.3V to the lower of (VL+ 0.3V) and +6V
Analog Inputs and
REF to GND..........-0.3V to the lower of (VDD + 0.3V) and +6V
RGND to GND .......................................................-0.3V to +0.3V
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA= +70°C)
12-Pin TQFN (derate 16.9mW/°C above +70°C) ......1349mW
Operating Temperature Range
MAX127_ _ ETC..............................................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
DC ACCURACY
Resolution 12 Bits
MAX127_A
-1.0 +1.0
Relative Accuracy (Note 1) INL MAX127_B
-1.5 +1.5
LSB
MAX127_A
-1.0 +1.0
Differential Nonlinearity (Note 2) DNL MAX127_B
-1.0 +1.5
LSB
Offset Error
±8.0
LSB
Offset-Error Temperature
Coefficient ±1
Gain Error Offset nulled
±6.0
LSB
Gain Temperature Coefficient ±2
DYNAMIC SPECIFICATIONS (fIN = 525kHz sine wave, VIN = VREF, unless otherwise noted.)
Signal-to-Noise Plus Distortion
SINAD 66
68.5
dB
Total Harmonic Distortion THD Up to the 5th harmonic -80 -76 dB
Spurious-Free Dynamic Range SFDR -83 -76 dB
Intermodulation Distortion IMD fIN1 = 250kHz, fIN2 = 300kHz -78 dB
Full-Power Bandwidth -3dB point, small-signal method 15
Full-Linear Bandwidth S/(N + D) > 68dB, single ended 1.2
CONVERSION RATE
Minimum Conversion Time tCONV (Note 3)
0.667
µs
Maximum Throughput Rate 1.5
M i ni m um Thr oug hp ut Rate ( N ote 4) 10
Track-and-Hold Acquisition Time
tACQ (Note 5) 125 ns
Aperture Delay 5ns
Aperture Jitter (Note 6) 30 ps
External Clock Frequency fSCLK (Note 7) 24
MAX1277/MAX1279
1.5Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +3.6V, VL= VDD, fSCLK = 24MHz, 50% duty cycle, TA= -40°C to +85°C, unless otherwise noted. Typical values are
at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
ANALOG INPUTS (AIN+, AIN-)
AIN+ - AIN-, MAX1277 0
VREF
Differential Input Voltage Range
VIN AIN+ - AIN-, MAX1279
-VREF / 2 +VREF / 2
V
Absolute Input Voltage Range 0
VDD
V
DC Leakage Current ±1 µA
Input Capacitance Per input pin 16 pF
Input Current (Average)
Time averaged at maximum throughput rate
75 µA
REFERENCE OUTPUT (REF)
REF Output Voltage Range Static, TA = +25°C
2.038 2.048 2.058
V
Voltage Temperature Coefficient
±50 ppm/°C
ISOURCE = 0 to 2mA
0.35
Load Regulation ISINK = 0 to 100µA 1.0
mV/mA
Line Regulation VDD = 2.7V to 3.6V, static
0.25 mV/V
DIGITAL INPUTS (SCLK, CNVST)
Input Voltage Low VIL
0.3 x VL
V
Input Voltage High VIH 0.7 x VLV
Input Leakage Current IIL
0.05 ±10
µA
DIGITAL OUTPUT (DOUT)
Output Load Capacitance COUT For stated timing performance 30 pF
Output Voltage Low VOL ISINK = 5mA, VL ≥ 1.8V 0.4 V
Output Voltage High VOH ISOURCE = 1mA, VL ≤ 1.8V
V
L - 0.5V
V
Output Leakage Current IOL Output high impedance
±0.2 ±10
µA
POWER REQUIREMENTS
Analog Supply Voltage VDD 2.7 3.6 V
Digital Supply Voltage VL1.8
VDD
V
Static, fSCLK = 24MHz 6 8
Static, no SCLK 5 7
Analog Supply Current,
Normal Mode IDD
Operational, 1.5Msps 7 9
mA
fSCLK = 24MHz 2
Analog Supply Current,
Partial Power-Down Mode IDD No SCLK 2 mA
fSCLK = 24MHz 1
Analog Supply Current,
Full Power-Down Mode IDD No SCLK 0.3 1 µA
Operational, full-scale input at 1.5Msps 0.3 1
Static, fSCLK = 24MHz
0.15
0.5
Partial/full power-down mode,
fSCLK = 24MHz 0.1 0.3
mA
Digital Supply Current (Note 8)
Static, no SCLK, all modes 0.1 1 µA
Positive-Supply Rejection PSR VDD = 3V +20% -10%, full-scale input
±0.2 ±3.0
mV
MAX1277/MAX1279
1.5Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
4 _______________________________________________________________________________________
Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and the offset
error have been nulled.
Note 2: No missing codes over temperature.
Note 3: Conversion time is defined as the number of clock cycles (16) multiplied by the clock period.
Note 4: At sample rates below 10ksps, the input full-linear bandwidth is reduced to 5kHz.
Note 5: The listed value of three SCLK cycles is given for full-speed continuous conversions. Acquisition time begins on the 14th ris-
ing edge of SCLK and terminates on the next falling edge of CNVST. The IC idles in acquisition mode between conversions.
Note 6: Undersampling at the maximum signal bandwidth requires the minimum jitter spec for SINAD performance.
Note 7: 1.5Msps operation guaranteed for VL> 2.7V. See the
Typical Operating Characteristics
section for recommended sampling
speeds for VL< 2.7V.
Note 8: Digital supply current is measured with the VIH level equal to VL, and the VIL level equal to GND.
TIMING CHARACTERISTICS
(VDD = +2.7V to +3.6V, VL= VDD, fSCLK = 24MHz, 50% duty cycle, TA= -40°C to +85°C, unless otherwise noted. Typical values are
at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
VL = 2.7V to VDD
18.7
SCLK Pulse-Width High tCH VL = 1.8V to VDD, minimum recommended
(Note 7)
22.5
ns
VL = 2.7V to VDD
18.7
SCLK Pulse-Width Low tCL VL = 1.8V to VDD, minimum recommended
(Note 7)
22.5
ns
CL = 30pF, VL = 2.7V to VDD 17
SCLK Rise to DOUT Transition tDOUT CL = 30pF, VL = 1.8V to VDD 24 ns
DOUT Remains Valid After SCLK tDHOLD
VL = 1.8V to VDD 4ns
CNVST Fall to SCLK Fall tSETUP VL = 1.8V to VDD 10 ns
CNVST Pulse Width tCSW VL = 1.8V to VDD 20 ns
Power-Up Time; Full Power-Down tPWR-UP
2ms
Restart Time; Partial Power-Down
tRCV 16
Cycles
CNVST
SCLK
DOUT
tDHOLD
tDOUT
tSETUP
tCSW
tCL tCH
Figure 1. Detailed Serial-Interface Timing
GND
6kΩCL
DOUT DOUT
CL
GND
VL
a) HIGH-Z TO VOH, VOL TO VOH,
AND VOH TO HIGH-Z
b) HIGH-Z TO VOL, VOH TO VOL,
AND VOL TO HIGH-Z
6kΩ
Figure 2. Load Circuits for Enable/Disable Times
MAX1277/MAX1279
1.5Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
_______________________________________________________________________________________
5
Typical Operating Characteristics
(VDD = +3V, VL= VDD, fSCLK = 24MHz, fSAMPLE = 1.5Msps, TA= -40°C to +85°C, unless otherwise noted. Typical values are mea-
sured at TA= +25°C.)
MAXIMUM RECOMMENDED fSCLK vs. VL
MAX1277/79 toc01
VL (V)
fSCLK (MHz)
3.33.02.72.42.1
19
21
23
25
17
1.8 3.6
-1.00
-0.75
-0.50
-0.25
0
0.25
0.50
0.75
1.00
0 1024 2048 3072 4096
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1277)
MAX1277/79 toc02
DIGITAL OUTPUT CODE
INL (LSB)
-1.00
-0.75
-0.50
-0.25
0
0.25
0.50
0.75
1.00
-2048 -1024 0 1024 2048
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1279)
MAX1277/79 toc03
DIGITAL OUTPUT CODE
INL (LSB)
-1.00
-0.75
-0.50
-0.25
0
0.25
0.50
0.75
1.00
0 1024 2048 3072 4096
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1277)
MAX1277/79 toc04
DIGITAL OUTPUT CODE
DNL (LSB)
-1.00
-0.75
-0.50
-0.25
0
0.25
0.50
0.75
1.00
-2048 -1024 0 1024 2048
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1279)
MAX1277/79 toc05
DIGITAL OUTPUT CODE
DNL (LSB)
-6
-4
-5
-2
-3
-1
0
-40 10-15 35 60 85
OFFSET ERROR
vs. TEMPERATURE (MAX1277)
MAX1277/79 toc06
TEMPERATURE (°C)
OFFSET ERROR (LSB)
-6
-4
-5
-2
-3
-1
0
-40 10-15 35 60 85
OFFSET ERROR
vs. TEMPERATURE (MAX1279)
MAX1277/79 toc07
TEMPERATURE (°C)
OFFSET ERROR (LSB)
-2
0
-1
2
1
3
4
-40 10-15 35 60 85
GAIN ERROR
vs. TEMPERATURE (MAX1277)
MAX1277/79 toc08
TEMPERATURE (°C)
GAIN ERROR (LSB)
-4
-2
-3
0
-1
1
2
-40 10-15 35 60 85
GAIN ERROR
vs. TEMPERATURE (MAX1279)
MAX1277/79 toc09
TEMPERATURE (°C)
GAIN ERROR (LSB)
Typical Operating Characteristics (continued)
(VDD = +3V, VL= VDD, fSCLK = 24MHz, fSAMPLE = 1.5Msps, TA= -40°C to +85°C, unless otherwise noted. Typical values are mea-
sured at TA= +25°C.)
MAX1277/MAX1279
1.5Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
6 _______________________________________________________________________________________
70.0
69.5
69.0
68.5
68.0
100 300200 400 500
DYNAMIC PERFORMANCE
vs. INPUT FREQUENCY (MAX1277)
MAX1277/79 toc10
ANALOG INPUT FREQUENCY (kHz)
DYNAMIC PERFORMANCE (dB)
SINAD
SNR
70.0
69.5
69.0
68.5
68.0
100 300200 400 500
DYNAMIC PERFORMANCE
vs. INPUT FREQUENCY (MAX1279)
MAX1277/79 toc11
ANALOG INPUT FREQUENCY (kHz)
DYNAMIC PERFORMANCE (dB)
SINAD
SNR
-80
-84
-88
-92
-96
100 300200 400 500
THD vs. INPUT FREQUENCY
MAX1277/79 toc12
ANALOG INPUT FREQUENCY (kHz)
THD (dB)
MAX1277
MAX1279
82
84
88
86
90
92
SFDR vs. INPUT FREQUENCY
MAX1277/79 toc13
ANALOG INPUT FREQUENCY (kHz)
SFDR (dB)
100 300200 400 500
MAX1277
MAX1279
-140
-100
-120
-60
-80
-20
-40
0
0 250 375125 500 625 750
FFT PLOT (MAX1277)
MAX1277/79 toc14
ANALOG INPUT FREQUENCY (kHz)
AMPLITUDE (dB)
fIN = 500kHz
SINAD = 68.7dB
SNR = 68.9dB
THD = -83.1dB
SFDR = 85.0dB
-140
-100
-120
-60
-80
-20
-40
0
0 250 375125 500 625 750
FFT PLOT (MAX1279)
MAX1277/79 toc15
ANALOG INPUT FREQUENCY (kHz)
AMPLITUDE (dB)
fIN = 500kHz
SINAD = 69.0dB
SNR = 69.1dB
THD = -88.9dB
SFDR = 85.9dB
MAX1277/MAX1279
TOTAL HARMONIC DISTORTION
vs. SOURCE IMPEDANCE
MAX1277/79 toc16
SOURCE IMPEDANCE (Ω)
THD (dB)
100
-90
-80
-70
-60
-50
-100
10 1000
fIN = 500kHz
fIN = 100kHz
TWO-TONE IMD PLOT (MAX1277)
MAX1277/79 toc17
ANALOG INPUT FREQUENCY (kHz)
AMPLITUDE (dB)
625500375250125
-120
-100
-80
-60
-40
-20
0
-140
0 750
fIN1 = 250.102kHz
fIN2 = 299.966kHz
IMD = -88.4dB
fIN1 fIN2
TWO-TONE IMD PLOT (MAX1279)
MAX1277/79 toc18
ANALOG INPUT FREQUENCY (kHz)
AMPLITUDE (dB)
625500375250125
-120
-100
-80
-60
-40
-20
0
-140
0 750
fIN1 = 250.102kHz
fIN2 = 299.966kHz
IMD = -85.2dB
fIN1 fIN2
1.5Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
_______________________________________________________________________________________
7
0
0.20
0.60
0.40
0.80
1.00
-40 10-15 35 60 85
VDD/VL FULL POWER-DOWN
SUPPLY CURRENT vs. TEMPERATURE
MAX1277/79 toc19
TEMPERATURE (°C)
VDD/VL SUPPLY CURRENT (μA)
VDD, SCLK = 24MHz
VDD, NO SCLK
VL, NO SCLK
0
50
25
75
100
-40 10-15 35 60 85
VL PARTIAL/FULL POWER-DOWN
SUPPLY CURRENT vs. TEMPERATURE
MAX1277/79 toc20
TEMPERATURE (°C)
VL SUPPLY CURRENT (μA)
VL, = 3V, SCLK = 24MHz
VL, = 1.8V, SCLK = 24MHz
0
3.0
1.5
6.0
4.5
7.5
9.0
-40 10-15 35 60 85
VDD SUPPLY CURRENT
vs. TEMPERATURE
MAX1277/79 toc21
TEMPERATURE (°C)
VDD SUPPLY CURRENT (mA)
CONVERSION
PARTIAL POWER-DOWN
Typical Operating Characteristics (continued)
(VDD = +3V, VL= VDD, fSCLK = 24MHz, fSAMPLE = 1.5Msps, TA= -40°C to +85°C, unless otherwise noted. Typical values are mea-
sured at TA= +25°C.)
MAX1277/MAX1279
1.5Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
8 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VDD = +3V, VL= VDD, fSCLK = 24MHz, fSAMPLE = 1.5Msps, TA= -40°C to +85°C, unless otherwise noted. Typical values are mea-
sured at TA= +25°C.)
8
6
4
2
0
0 750250 500 1000 1250 1500
VDD SUPPLY CURRENT
vs. CONVERSION RATE
MAX1277/79 toc22
fSAMPLE (kHz)
VDD SUPPLY CURRENT (mA)
0
0.10
0.30
0.20
0.40
0.50
-40 10-15 35 60 85
VL SUPPLY CURRENT
vs. TEMPERATURE
MAX1277/79 toc23
TEMPERATURE (°C)
VL SUPPLY CURRENT (mA)
CONVERSION, VL = 3V
CONVERSION, VL = 1.8V
0
50
150
100
200
250
0 500250 750 1000 1250 1500
VL SUPPLY CURRENT
vs. CONVERSION RATE
MAX1277/79 toc24
fSAMPLE (kHz)
VL SUPPLY CURRENT (μA)
VL = 3V
VL = 1.8V
2.00
2.02
2.01
2.04
2.03
2.05
2.06
-40 10-15 35 60 85
REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1277/79 toc25
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
2.05
2.04
2.03
2.02
2.01
04268
REFERENCE VOLTAGE
vs. LOAD CURRENT (SOURCE)
MAX1277/79 toc26
LOAD CURRENT (mA)
REFERENCE VOLTAGE (V)
2.08
2.07
2.06
2.05
2.04
0 10050 150 200
REFERENCE VOLTAGE
vs. LOAD CURRENT (SINK)
MAX1277/79 toc27
LOAD CURRENT (μA)
REFERENCE VOLTAGE (V)
MAX1277/MAX1279
1.5Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
_______________________________________________________________________________________ 9
Pin Description
PIN NAME FUNCTION
1 AIN- Negative Analog Input
2 REF Reference Voltage Output. Internal 2.048V reference output. Bypass REF with a 0.01µF capacitor and
a 4.7µF capacitor to RGND.
3 RGND Reference Ground. Connect RGND to GND.
4V
DD Positive Analog Supply Voltage (+2.7V to +3.6V). Bypass VDD with a 0.01µF capacitor and a 10µF
capacitor to GND.
5, 11 N.C. No Connection
6 GND Ground. GND is internally connected to EP.
7V
LPositive Logic Supply Voltage (1.8V to VDD). Bypass VL with a 0.01µF capacitor and a 10µF capacitor
to GND.
8 DOUT Serial Data Output. Data is clocked out on the rising edge of SCLK.
9 CNVST Convert Start. Forcing CNVST high prepares the part for a conversion. Conversion begins on the
falling edge of CNVST. The sampling instant is defined by the falling edge of CNVST.
10 SCLK Serial Clock Input. Clocks data out of the serial interface. SCLK also sets the conversion speed.
12 AIN+ Positive Analog Input
— EP Exposed Paddle. EP is internally connected to GND.
Detailed Description
The MAX1277/MAX1279 use an input T/H and succes-
sive-approximation register (SAR) circuitry to convert
an analog input signal to a digital 12-bit output. The
serial interface requires only three digital lines (SCLK,
CNVST, and DOUT) and provides easy interfacing to
microprocessors (µPs) and DSPs. Figure 3 shows the
simplified internal structure for the MAX1277/MAX1279.
RGND
AIN +
GND
DOUT
SCLK
CNVST
CONTROL
LOGIC AND
TIMING
AIN -
VL
VDD
REF
12-BIT
SAR
ADC
MAX1277
MAX1279
TRACK AND
HOLD
OUTPUT
BUFFER
REF
2.048V
Figure 3. Functional Diagram
CIN+ RIN+
RIN-
CIN-
VAZ
AIN+
AIN-
CONTROL
LOGIC
CAPACITIVE
DAC
COMP
ACQUISITION MODE
CIN+ RIN+
RIN-
CIN-
VAZ
AIN+
AIN-
CONTROL
LOGIC
CAPACITIVE
DAC
COMP
HOLD/CONVERSION MODE
Figure 4. Equivalent Input Circuit
MAX1277/MAX1279
True-Differential Analog Input T/H
The equivalent circuit of Figure 4 shows the input archi-
tecture of the MAX1277/MAX1279, which is composed
of a T/H, a comparator, and a switched-capacitor digi-
tal-to-analog converter (DAC). The T/H enters its track-
ing mode on the 14th SCLK rising edge of the previous
conversion. Upon power-up, the T/H enters its tracking
mode immediately. The positive input capacitor is con-
nected to AIN+. The negative input capacitor is con-
nected to AIN-. The T/H enters its hold mode on the
falling edge of CNVST and the difference between the
sampled positive and negative input voltages is convert-
ed. The time required for the T/H to acquire an input sig-
nal is determined by how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens. The acquisition time,
tACQ, is the minimum time needed for the signal to be
acquired. It is calculated by the following equation:
tACQ ≥9 ×(RS + RIN) ×16pF
where RIN = 200Ω, and RS is the source impedance of
the input signal.
Note: tACQ is never less than 125ns and any source
impedance below 12Ωdoes not significantly affect the
ADC’s AC performance.
Input Bandwidth
The ADC’s input-tracking circuitry has a 15MHz small-
signal bandwidth, making it possible to digitize high-
speed transient events and measure periodic
signals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Analog Input Protection
Internal protection diodes that clamp the analog input
to VDD and GND allow the analog input pins to swing
from GND - 0.3V to VDD + 0.3V without damage. Both
inputs must not exceed VDD or be lower than GND for
accurate conversions.
Serial Interface
Initialization After Power-Up
and Starting a Conversion
Upon initial power-up, the MAX1277/MAX1279 require a
complete conversion cycle to initialize the internal cali-
bration. Following this initial conversion, the part is ready
for normal operation. This initialization is only required
after a hardware power-up sequence and is not required
after exiting partial or full power-down mode.
To start a conversion, pull CNVST low. At CNVST’s
falling edge, the T/H enters its hold mode and a conver-
sion is initiated. SCLK runs the conversion and the data
can then be shifted out serially on DOUT.
1.5Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
10 ______________________________________________________________________________________
DOUT
MODE
SCLK
CNVST
DOUT GOES HIGH IMPEDANCE ONCE CNVST GOES HIGH
CONVST MUST GO HIGH AFTER THE 3RD BUT BEFORE THE 14TH SCLK RISING EDGE
ONE 8-BIT TRANSFER
1ST SCLK RISING EDGE
PPD
0 0 0 D11 D10 D9 D8 D7
NORMAL
REF ENABLED (2.048V)
Figure 6. SPI Interface—Partial Power-Down Mode
Figure 5. Interface-Timing Sequence
tACQUIRE
CONTINUOUS-CONVERSION
SELECTION WINDOW
CNVST
tSETUP
DOUT
SCLK 41412 83 16
HIGH IMPEDANCE D1D4D6 D5D9 D8 D7D11 D10
POWER-MODE SELECTION WINDOW
D0D2D3
Timing and Control
Conversion-start and data-read operations are con-
trolled by the CNVST and SCLK digital inputs. Figures 1
and 5 show timing diagrams, which outline the serial-
interface operation.
A CNVST falling edge initiates a conversion sequence;
the T/H stage holds the input voltage, the ADC begins
to convert, and DOUT changes from high impedance to
logic low. SCLK is used to drive the conversion
process, and it shifts data out as each bit of the conver-
sion is determined.
SCLK begins shifting out the data after the 4th rising
edge of SCLK. DOUT transitions tDOUT after each
SCLK’s rising edge and remains valid 4ns (tDHOLD)
after the next rising edge. The 4th rising clock edge
produces the MSB of the conversion at DOUT, and the
MSB remains valid 4ns after the 5th rising edge. Since
there are 12 data bits and 3 leading zeros, at least 16
rising clock edges are needed to shift out these bits.
For continuous operation, pull CNVST high between the
14th and the 16th SCLK rising edges. If CNVST stays
low after the falling edge of the 16th SCLK cycle, the
DOUT line goes to a high-impedance state on either
CNVST’s rising edge or the next SCLK’s rising edge.
Partial Power-Down and
Full Power-Down Modes
Power consumption can be reduced significantly by plac-
ing the MAX1277/MAX1279 in either partial power-down
mode or full power-down mode. Partial power-down
mode is ideal for infrequent data sampling and fast wake-
up time applications. Pull CNVST high after the 3rd SCLK
rising edge and before the 14th SCLK rising edge to
enter and stay in partial power-down mode (see Figure
6). This reduces the supply current to 2mA. While in par-
tial power-down mode, the reference remains enabled to
allow valid conversions once the IC is returned to normal
mode. Drive CNVST low and allow at least 14 SCLK
cycles to elapse before driving CNVST high to exit partial
power-down mode.
Full power-down mode is ideal for infrequent data sam-
pling and very low supply current applications. The
MAX1277/MAX1279 have to be in partial power-down
mode to enter full power-down mode. Perform the
SCLK/CNVST sequence described above to enter par-
tial power-down mode. Then repeat the same
sequence to enter full power-down mode (see Figure
7). Drive CNVST low, and allow at least 14 SCLK cycles
to elapse before driving CNVST high to exit full power-
down mode. While in full power-down mode, the refer-
ence is disabled to minimize power consumption. Be
sure to allow at least 2ms recovery time after exiting full
power-down mode for the reference to settle. In
partial/full power-down mode, maintain a logic low or a
logic high on SCLK to minimize power consumption.
Transfer Function
Figure 8 shows the unipolar transfer function for the
MAX1277. Figure 9 shows the bipolar transfer function for
the MAX1279. The MAX1277 output is straight binary,
while the MAX1279 output is two’s complement.
Applications Information
Internal Reference
The MAX1277/MAX1279 have an on-chip voltage refer-
ence trimmed to 2.048V. The internal reference output
is connected to REF and also drives the internal capac-
itive DAC. The output can be used as a reference volt-
age source for other components and can source up to
2mA. Bypass REF with a 0.01µF capacitor and a 4.7µF
capacitor to RGND.
The internal reference is continuously powered up dur-
ing both normal and partial power-down modes. In full
power-down mode, the internal reference is disabled.
Be sure to allow at least 2ms recovery time after hard-
ware power-up or exiting full power-down mode for the
reference to reach its intended value.
MAX1277/MAX1279
1.5Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
______________________________________________________________________________________ 11
Figure 7. SPI Interface—Full Power-Down Mode
1ST SCLK RISING EDGE 1ST SCLK RISING EDGE
0 0 0 D11 D10 D9 D8 D7
DOUT
MODE
SCLK
CNVST
0000000
FPDRECOVERYPPDNORMAL
0
DOUT ENTERS TRI-STATE ONCE CNVST GOES HIGH
EXECUTE PARTIAL POWER-DOWN TWICE
FIRST 8-BIT TRANSFER SECOND 8-BIT TRANSFER
REF ENABLED (2.048V) DISABLED
MAX1277/MAX1279
How to Start a Conversion
An analog-to-digital conversion is initiated by CNVST,
clocked by SCLK, and the resulting data is clocked out on
DOUT by SCLK. With SCLK idling high or low, a falling
edge on CNVST begins a conversion. This causes the
analog input stage to transition from track to hold mode,
and for DOUT to transition from high impedance to being
actively driven low. A total of 16 SCLK cycles are required
to complete a normal conversion. If CNVST is low during
the 16th falling SCLK edge, DOUT returns to high imped-
ance on the next rising edge of CNVST or SCLK, enabling
the serial interface to be shared by multiple devices. If
CNVST returns high after the 14th, but before the 16th
SCLK rising edge, DOUT remains active so continuous
conversions can be sustained. The highest throughput is
achieved when performing continuous conversions. Figure
10 illustrates a conversion using a typical serial interface.
Connection to
Standard Interfaces
The MAX1277/MAX1279 serial interface is fully compati-
ble with SPI/QSPI and MICROWIRE (see Figure 11). If a
serial interface is available, set the CPU’s serial interface
in master mode so the CPU generates the serial clock.
Choose a clock frequency up to 24MHz.
SPI and MICROWIRE
When using SPI or MICROWIRE, the MAX1277/ MAX1279
are compatible with all four modes programmed with the
CPHA and CPOL bits in the SPI or MICROWIRE control
register. Conversion begins with a CNVST falling edge.
DOUT goes low, indicating a conversion is in progress.
Two consecutive 1-byte reads are required to get the full
12 bits from the ADC. DOUT transitions on SCLK rising
edges. DOUT is guaranteed to be valid tDOUT later and
remains valid until tDHOLD after the following SCLK rising
edge. When using CPOL = 0 and CPHA = 0, or CPOL = 1
and CPHA = 1, the data is clocked into the µP on the fol-
lowing rising edge. When using CPOL = 0 and CPHA = 1,
or CPOL = 1 and CPHA = 0, the data is clocked into the
µP on the next falling edge. See Figure 11 for connections
and Figures 12 and 13 for timing. See the
Timing
Characteristics
section to determine the best mode to use.
QSPI
Unlike SPI, which requires two 1-byte reads to acquire
the 12 bits of data from the ADC, QSPI allows the mini-
mum number of clock cycles necessary to clock in the
data. The MAX1277/MAX1279 require 16 clock cycles
from the µP to clock out the 12 bits of data. Figure 14
shows a transfer using CPOL = 1 and CPHA = 1. The
conversion result contains three zeros, followed by the
12 data bits, and a trailing zero with the data in MSB-
1.5Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
12 ______________________________________________________________________________________
OUTPUT CODE
FULL-SCALE
TRANSITION
111...111
12 3
0FS
FS - 3/2 LSB
FS = VREF
DIFFERENTIAL INPUT
VOLTAGE (LSB)
1 LSB = VREF
4096
111...110
111...101
000...011
000...010
000...001
000...000
ZS = 0
Figure 8. Unipolar Transfer Function (MAX1277 Only)
OUTPUT CODE
FULL-SCALE
TRANSITION
FS0-FS
FS - 3/2 LSB
DIFFERENTIAL INPUT
VOLTAGE (LSB)
011...111
011...110
000...010
000...001
000...000
111...111
111...110
111...101
100...001
100...000
1 LSB = VREF
4096
FS = VREF
2
- FS = -VREF
2
ZS = 0
Figure 9. Bipolar Transfer Function (MAX1279 Only)
MAX1277/MAX1279
1.5Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
______________________________________________________________________________________ 13
Figure 11. Common Serial-Interface Connections to the MAX1277/MAX1279
0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0
DOUT
SCLK
CNVST
0
1
11614
Figure 10. Continuous Conversion with Burst/Continuous Clock
MAX1277
MAX1279
+3V TO +5V
CNVST
SCLK
DOUT
I/O
SCK
MISO
SS
A) SPI
MAX1277
MAX1279
+3V TO +5V
CNVST
SCLK
DOUT
CS
SCK
MISO
SS
B) QSPI
MAX1277
MAX1279
CNVST
SCLK
DOUT
I/O
SK
SI
C) MICROWIRE
first format.
DSP Interface to the TMS320C54_
The MAX1277/MAX1279 can be directly connected
to the TMS320C54_ family of DSPs from Texas
Instruments, Inc. Set the DSP to generate its own
clocks or use external clock signals. Use either the
standard or buffered serial port. Figure 15 shows the
simplest interface between the MAX1277/MAX1279 and
the TMS320C54_, where the transmit serial clock
(CLKX) drives the receive serial clock (CLKR) and
SCLK, and the transmit frame sync (FSX) drives the
receive frame sync (FSR) and CNVST.
For continuous conversion, set the serial port to trans-
mit a clock, and pulse the frame sync signal for a clock
period before data transmission. The serial-port config-
uration (SPC) register should be set up with internal
frame sync (TXM = 1), CLKX driven by an on-chip clock
source (MCM = 1), burst mode (FSM = 1), and 16-bit
word length (FO = 0).
This setup allows continuous conversions provided that
the data transmit register (DXR) and the data-receive
register (DRR) are serviced before the next conversion.
Alternatively, autobuffering can be enabled when using
the buffered serial port to execute conversions and
MAX1277/MAX1279
1.5Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
14 ______________________________________________________________________________________
SCLK
DOUT
916
8
1
D2
D11 D10 D8 D7 D6 D5 D4 D3
D9
HIGH-Z HIGH-Z
CNVST
D1 D0
Figure 13. SPI/MICROWIRE Serial-Interface Timing—Continuous Conversion (CPOL = CPHA = 0), (CPOL = CPHA = 1)
0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0
DOUT
SCLK
CNVST
0
11
14 16
Figure 12. SPI/MICROWIRE Serial-Interface Timing—Single Conversion (CPOL = CPHA = 0), (CPOL = CPHA = 1)
Figure 14. QSPI Serial-Interface Timing—Single Conversion (CPOL = 1, CPHA = 1)
SCLK
DOUT
CNVST
16
D0
D1
D11 D10 D6D7D8 D5 D4 D3 D2
HIGH-Z
D9
HIGH-Z
2
MAX1277/MAX1279
1.5Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
______________________________________________________________________________________ 15
read the data without CPU intervention. Connect the VL
pin to the TMS320C54_ supply voltage when the
MAX1277/MAX1279 are operating with an analog sup-
ply voltage higher than the DSP supply voltage. The
word length can be set to 8 bits with FO = 1 to imple-
ment the power-down modes. The CNVST pin must idle
high to remain in either power-down state.
Another method of connecting the MAX1277/MAX1279
to the TMS320C54_ is to generate the clock signals
external to either device. This connection is shown in
Figure 16, where serial clock (CLOCK) drives the
CLKR, and SCLK and the convert signal (CONVERT)
drive the FSR and CNVST.
The serial port must be set up to accept an external
receive-clock and external receive-frame sync.
The SPC register should be written as follows:
TXM = 0, external frame sync
MCM = 0, CLKX is taken from the CLKX pin
FSM = 1, burst mode
FO = 0, data transmitted/received as 16-bit words
This setup allows continuous conversion, provided that
the DRR is serviced before the next conversion.
Alternatively, autobuffering can be enabled when using
the buffered serial port to read the data without CPU
intervention. Connect the VL pin to the TMS320C54_
supply voltage when the MAX1277/MAX1279 are oper-
ating with an analog supply voltage higher than the
DSP supply voltage.
The MAX1277/MAX1279 can also be connected to the
TMS320C54_ by using the data transmit (DX) pin to
drive CNVST and the CLKX generated internally to
drive SCLK. A pullup resistor is required on the CNVST
signal to keep it high when DX goes high impedance
and 0001hex should be written to the DXR continuously
for continuous conversions. The power-down modes
may be entered by writing 00FFhex to the DXR (see
Figures 17 and 18).
DSP Interface to the ADSP21_ _ _
The MAX1277/MAX1279 can be directly connected to
the ADSP21_ _ _ family of DSPs from Analog Devices,
Inc. Figure 19 shows the direct connection of the
MAX1277/MAX1279 to the ADSP21_ _ _. There are two
modes of operation that can be programmed to interface
with the MAX1277/MAX1279. For continuous conver-
sions, idle CNVST low and pulse it high for one clock
cycle during the LSB of the previous transmitted word.
The ADSP21_ _ _ STCTL and SRCTL registers should be
Figure 15. Interfacing to the TMS320C54_ Internal Clocks
Figure 16. Interfacing to the TMS320C54_ External Clocks
MAX1277
MAX1279
TMS320C54_
VL
SCLK
CNVST
DOUT
DVDD
CLKR
FSR
CLKX
FSX
DR
MAX1277
MAX1279
TMS320C54_
VLDVDD
SCLK CLKR
CNVST FSR
DOUT DR
CLOCK
CONVERT
0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0
DOUT
SCLK
CNVST
00D0
1 1
Figure 17. DSP Interface—Continuous Conversion
MAX1277/MAX1279
configured for early framing (LAFR = 0) and for an
active-high frame (LTFS = 0, LRFS = 0) signal. In this
mode, the data-independent frame-sync bit (DITFS = 1)
can be selected to eliminate the need for writing to the
transmit-data register more than once. For single conver-
sions, idle CNVST high and pulse it low for the entire
conversion. The ADSP21_ _ _ STCTL and SRCTL regis-
ters should be configured for late framing (LAFR = 1)
and for an active-low frame (LTFS = 1, LRFS = 1) signal.
This is also the best way to enter the power-down modes
by setting the word length to 8 bits (SLEN = 1001).
Connect the VL pin to the ADSP21_ _ _ supply voltage
when the MAX1277/MAX1279 are operating with a sup-
ply voltage higher than the DSP supply voltage (see
Figures 17 and 18).
Layout, Grounding, and Bypassing
For best performance, use PC boards. Wire-wrap
boards are not recommended. Board layout should
ensure that digital and analog signal lines are separat-
ed from each other. Do not run analog and digital
(especially clock) lines parallel to one another, or digital
lines underneath the ADC package.
Figure 20 shows the recommended system ground
connections. Establish a single-point analog ground
(star ground point) at GND, separate from the logic
ground. Connect all other analog grounds and DGND
to this star ground point for further noise reduction. The
ground return to the power supply for this ground
should be low impedance and as short as possible for
noise-free operation.
High-frequency noise in the VDD power supply can
affect the ADC’s high-speed comparator. Bypass this
supply to the single-point analog ground with 0.01µF
and 10µF bypass capacitors. Minimize capacitor lead
lengths for best supply-noise rejection.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on
an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The static
linearity parameters for the MAX1277/MAX1279 are mea-
sured using the end-points method.
1.5Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
16 ______________________________________________________________________________________
MAX1277
MAX1279 ADSP21_ _ _
VL
SCLK
CNVST
DOUT
VDDINT
RCLK
RFS
TCLK
TFS
DR
Figure 19. Interfacing to the ADSP21_ _ _
10μF
0.1μF
10μF
0.1μF
GND VL
SUPPLIES
DGND VL
DIGITAL
CIRCUITRY
VDD GND RGND VL
MAX1277
MAX1279
Figure 20. Power-Supply Grounding Condition
0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0
DOUT
SCLK
CNVST
0 0
11
Figure 18. DSP Interface—Single-Conversion, Continuous/Burst Clock
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A DNL
error specification of 1 LSB or less guarantees no missing
codes and a monotonic transfer function.
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between the samples.
Aperture Delay
Aperture delay (tAD) is the time defined between the
falling edge of CNVST and the instant when an actual
sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital sam-
ples, signal-to-noise ratio (SNR) is the ratio of the full-
scale analog input (RMS value) to the RMS quantization
error (residual error). The theoretical minimum analog-to-
digital noise is caused by quantization error, and results
directly from the ADC’s resolution (N bits):
SNR = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quantiza-
tion noise, including thermal noise, reference noise, clock
jitter, etc. Therefore, SNR is computed by taking the ratio
of the RMS signal to the RMS noise, which includes all
spectral components minus the fundamental, the first five
harmonics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals:
SINAD(dB) = 20 x log (SignalRMS / NoiseRMS)
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantiza-
tion noise only. With an input range equal to the full-scale
range of the ADC, calculate the ENOB as follows:
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
where V1is the fundamental amplitude, and V2
through V5are the amplitudes of the 2nd- through 5th-
order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest distor-
tion component.
Full-Power Bandwidth
Full-power bandwidth is the frequency at which the
input signal amplitude attenuates by 3dB for a full-scale
input.
Full-Linear Bandwidth
Full-linear bandwidth is the frequency at which the sig-
nal to noise plus distortion (SINAD) is equal to 68dB.
Intermodulation Distortion (IMD)
Any device with nonlinearities creates distortion prod-
ucts when two sine waves at two different frequencies
(f1 and f2) are input into the device. Intermodulation
distortion (IMD) is the total power of the IM2 to IM5
intermodulation products to the Nyquist frequency rela-
tive to the total input power of the two input tones, f1
and f2. The individual input tone levels are at -7dBFS.
The intermodulation products are as follows:
• 2nd-order intermodulation products (IM2): f1+ f2,
f2- f1
• 3rd-order intermodulation products (IM3): 2f1- f2,
2f2- f1, 2f1+ f2, 2f2+ f1
• 4th-order intermodulation products (IM4): 3f1- f2,
3f2- f1, 3f1+ f2, 3f2+ f1
• 5th-order intermodulation products (IM5): 3f1- 2f2,
3f2- 2f1, 3f1+ 2f2, 3f2+ 2f1
THD x VVVV
V
log=+++
⎛
⎝
⎜
⎜
⎜
⎞
⎠
⎟
⎟
⎟
20 2
2
3
2
4
2
5
2
1
ENOB SINAD
( .)
.
=−176
602
MAX1277/MAX1279
1.5Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
______________________________________________________________________________________ 17
Chip Information
TRANSISTOR COUNT: 13,016
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
12 TQFN T1244+3 21-0139
MAX1277/MAX1279
1.5Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 8/04 Initial release —
1 4/09 Removed commercial temperature grade parts from data sheet 1–8