Application Note April 1999 Interfacing the TTSI4K32T, TTSI2K32T, and TTSI1K16T to a Microprocessor Introduction This document describes how to interface the TTSI4K32T, TTSI2K32T, or TTSI1K16T time-slot interchanger device to an asynchronous microprocessor, such as a Motorola* MC68360 or MC68302 and or synchronous microprocessor such as the Motorola MPC860 power QUICC. For readability, this family of three time-slot interchangers will be referred to as the TSI. Asynchronous Motorola Microprocessor Interface Connections VCC R1 VCC 4.7 k NC OE NC SIZ[1--0] DSACK1 DT MM DSACK0 NC A[14--0] TSI (TTSI4K32T, TTSI2K32T, OR TTSI1K16T) PCLK D[7--0] A[31--15] A[14--0] NC D[23--0] D[31--24] CS CSX AS AS DS DS R/W R/W INT IRQX ASYNCHRONOUS MOTOROLA MICROPROCESOR (MC68360 OR MC68302) 5-7428(F)r.1 Figure 1. Glueless Asynchronous Motorola Microprocessor and TSI Interface All of the TSI microprocessor interface signals can be connected directly to the asynchronous Motorola microprocessor, see Figure 1. The asynchronous mode of the TSI is selected by tying MM low; consequently, the PCLK input is not used and thus should be tied high or low but not left floating. The least significant 15 bits of the address bus are used to access the TSI registers and memories. Note that D[7--0] of the TSI are connected to the D[31--24] of the MC68302/360. * Motorola is a registered trademark of Motorola, Inc. Interfacing the TTSI4K32T, TTSI2K32T, and TTSI1K16T to a Microprocessor Application Note April 1999 Asynchronous Motorola Microprocessor Interface Connections (continued) The DSACK1 input of the microprocessor is pulled high and DSACK0 is connected to the TSI's DT output, to indicate a byte transfer, whenever the microprocessor accesses (reads or writes) the TSI. The DT output of the TSI is driven high when the TSI detects an access (i.e., CS, AS, and DS inputs are all sensed low) and within 183 ns of sensing the access, the TSI asserts DT low to indicate the completion of the access. Driving AS or DS high will then cause DT to go high. However, driving CS high causes DT to tristate. If CS, AS, and DS are all aligned, then DT will be tristated before it is pulled high. It is then up to the pull-up resistor R1 to pull DT up to VCC before the start of the next microprocessor access, which may be a TSI access or an access of another device on the microprocessors address and data buses. See Figure 2 for such an access. TSI ACCESS NEXT ACCESS CS AS, DS UNAMBIGUOUS LOGIC 1 REACHED BY THE TIME THE NEXT MICROPROCESSOR ACCESS STARTS DT 183 ns 5-7429(F)r.1 Figure 2. Typical TSI Access by an Asynchronous Microprocessor with CS, AS, and DS Aligned Interfacing to a Fast Asynchronous Microprocessor In a system where a fast microprocessor is being used (typically >25 MHz), the time it takes the pull-up resistor R1 to pull up to an unambiguous logic 1 (~2.1 V), can be of the same order as the gap between consecutive microprocessor accesses (typically 1 microprocessor clock cycle). The next access may start before DT has been pulled up high enough and the microprocessor may sense it as a logic 0. Hence, the next access may terminate prematurely, or the microprocessor may hang if DT is detected low too early in a microprocessor access. See Figure 3. TSI ACCESS NEXT ACCESS TERMINATES PREMATURELY SINCE DT WAS DETECTED LOW BY MICROPROCESSOR CS AS, DS DT 183 ns UNAMBIGUOUS LOGIC 1 NOT REACHED BY THE TIME THE NEXT MICROPROCESSOR ACCESS STARTS 5-7430(F)r.2 Figure 3. TSI Access by a Fast Asynchronous Microprocessor with CS, AS, and DS Aligned 2 Agere Systems Inc. Interfacing the TTSI4K32T, TTSI2K32T, and TTSI1K16T to a Microprocessor Application Note April 1999 Interfacing to a Fast Asynchronous Microprocessor (continued) There are several ways to avoid this problem. Use a stronger (lower resistance) pull-up resistor and thus decrease the resistance capacitance (RC) delay for the rise time on DT. However, the noise margin on a logic 0 may be compromised as the strong pull up competes with the DT buffer in the TSI device which tries to pull it low. See Table 1 for the trade-off between the value of the pull-up resistor and the voltage of a logic 0 (VOL) that results on the DT signal. The DT from the TSI should not be wire-ORed with the DTACK from all the other devices on the board, but combined using an AND gate. This should reduce the RC delay for DT, since the capacitance of the trace from the TSI to the AND gate will probably be smaller than a bused DT signal that goes all over the board. Delay the CS going to the TSI, compared to the AS. This may already be occurring if an external address decode is being performed to generate the CS for the TSI. This delay needs to be a minimum of 4 ns (timing parameter t3 in Figure 16, Asynchronous Read Cycle Timing Using DT Handshake and Figure 17, Asynchronous Write Cycle Timing Using DT Handshake in the TSI data sheets (TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger (DS99-045T1E1), TTSI1K16T 1024-Channel, 16-Highway Time-Slot Interchanger (DS99-177PDH), and TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger (DS99-178PDH)). See Figure 4 below. Access the TSI using a preprogrammed number of wait-states in the microprocessor, rather than relying on the DT handshake signal. The number of wait states that need to be used can be calculated from the fact that once an access is detected by the TSI (i.e., CS, AS, and DS inputs are all sensed low) the TSI will complete the access and drive DT low within 183 ns. Table 1. VOL on the DT Signal, for Different Values of Pull-Up Resistor R1 470 680 1.0k 1.5k 2.0k 2.2k 3.3k 4.7k Max VOL (mV) @ VCC = 3.3 V 190 130 80 60 40 40 10 4 Max VOL (mV) @ VCC = 5.25 V 300 210 130 90 60 60 40 20 R1 Resistance () TSI ACCESS NEXT ACCESS CS AS, DS DT 183 ns 5-7431(F) Figure 4. TSI Access by a Microprocessor with a Delayed CS Agere Systems Inc. 3 Interfacing the TTSI4K32T, TTSI2K32T, and TTSI1K16T to a Microprocessor Application Note April 1999 Synchronous Motorola Microprocessor Interface Connections VCC VCC VCC 4.7 k 4.7 k MM DS TSI (TTSI4K32T, TTSI2K32T, OR TTSI1K16T) CS CSX AS TS DT TA R/W RD/WR PCLK CLKOUT NC A[0--15] A[16--31] A[14--0] NC D[7--0] INT SYNCHRONOUS MOTOROLA MICROPROCESOR (MPC860 POWER QUICC IN BIG-ENDIAN MODE) D[8--31] D[0--7] IRQX 5-7428(F)r.3 Figure 5. Glueless Asynchronous Motorola Microprocessor and TSI Interface Note that in the MPC860 microprocessor, the least significant address bit is A31. Hence, A[16--31] of the MPC860 should be connected to A[14--0], respectively, of the TSI. D0 always carries the most significant bit of the transfer on the data bus of the MPC860. The least significant bit on the data bus of the MPC860 is D31 for 32-bit acceses, D15 for 16-bit acceses, and D7 for byte accesses. Since the TSI has an 8-bit data bus, D0 on the MPC860 should be connected to D7 of the TSI and D7 of the microprocessor to D0 of the TSI. This connection of the data bus also assumes that the big-endian format of the MPC860 has been selected, which is its default. For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere, Agere Systems, and the Agere logo are trademarks of Agere Systems Inc. Copyright (c) 2002 Agere Systems Inc. All Rights Reserved April 1999 AP99-013T1E1