2
INDUSTRIAL TEMPERATURE RANGE
IDT5V927
QUAD OUTPUT CLOCK GENERATOR
REF
X1
X2
VDD
Q0
GND
Q1
VDDQ
1
2
3
4
5
6
7
8
S0
S1
OE
GND
Q3
GND
Q2
VDDQ
9
10
11
12
13
14
15
16
PIN CONFIGURATION
TSSOP
TOP VIEW
CRYSTAL SPECIFICATION
The crystal oscillators should be fundamental mode quartz crystals:
overtone crystals are not suitable. Crystal frequency should be specified
for parallel resonance with 50Ω maximum equivalent series resonance.
Crystal tuning capacitors should be connected from X2/REF to GND and from
X1 to GND.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max. Unit
VDD/VDDQ Supply Voltage to Ground – 0.5 to +4.6 V
VIInput Voltage – 0.5 to +4.6 V
IOOutput Current ±50 mA
TSTG Storage Temperature – 65 to +150 °C
TJJunction Temperature 150 °C
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
PIN DESCRIPTION
Pin Name Type Description
S[1:0] I Three level divider/mode select pins. Float to MID.
OE I Output enable bar. OE has a pull-down. Output Q[1:3] tristated
when HIGH. Output Q0 remains running when in PLL mode
and tri-states when in TEST mode.
X1I Crystal oscillator input. Connect to GND if oscillator not required.
X2I Crystal oscillator output. Leave unconnected for clock input.
REF I Input clock. Connect to X2 if crystal oscillator is used.
Q[1:3] O Output at N*REF frequency
Q0O Output at N*REF internally connected for PLL feedback
VDDQ PWR Power supply for the device outputs. Connect to VDD on PCB.
VDD PWR Power supply for the device core and inputs. Connect to VDD
on PCB.
GND PWR Ground supply
NOTES:
1. H = HIGH
M = MEDIUM
L = LOW
2. Test mode for low frequency testing. In this mode, REF clock bypasses the VCO (VCO powered down) and the crystal oscillator is powered down.
DIVIDE SELECTION TABLE(1)
S1 S0 Divide-by-N Value Mode
L L 2 PLL
L M 3 PLL
L H 4 PLL
M L 4.25 PLL
M M 5 PLL
M H 6 PLL
H L 6.25 PLL
H M 8 PLL
H H TEST TEST (2)