E SEE NEW DESIGN RECOMMENDATIONS REFERENCE ONLY 28F016SA FlashFileTM MEMORY Includes Commercial and Extended Temperature Specifications n n n n n n n n User-Selectable 3.3 V or 5 V V CC User-Configurable x8 or x16 Operation 70 ns Maximum Access Time 28.6 MB/sec Burst Write Transfer Rate 1 Million Typical Erase Cycles per Block 56-Lead, 1.2 mm x 14 mm x 20 mm TSOP Package 56-Lead, 1.8 mm x 16 mm x 23.7 mm SSOP Package n n n n Revolutionary Architecture Pipelined Command Execution Program during Erase Command Superset of Intel 28F008SA 1 mA Typical I CC in Static Mode 1 A Typical Deep Power-Down 32 Independently Lockable Blocks State-of-the-Art 0.6 m ETOXTM IV Flash Technology Intel's 28F016SA 16-Mbit FlashFileTM memory is a revolutionary architecture which is the ideal choice for designing embedded direct-execute code and mass storage data/file flash memory systems. With innovative capabilities, low-power, extended temperature operation and high read/program performance, the 28F016SA enables the design of truly mobile, high-performance communications and computing products. The 28F016SA is the highest density, highest performance nonvolatile read/program solution for solid-state storage applications. Its symmetrically-blocked architecture (100% compatible with the 28F008SA 8-Mbit FlashFile memory), extended cycling, extended temperature operation, flexible VCC, fast program and read performance and selective block locking provide highly flexible memory components suitable for Resident Flash Arrays, high-density memory cards and PCMCIA-ATA flash drives. The 28F016SA dual read voltage enables the design of memory cards which can be interchangeably read/written in 3.3 V and 5.0 V systems. Its x8/x16 architecture allows optimization of the memory-to-processor interface. Its high read performance and flexible block locking enable both storage and execution of operating systems and application software. Manufactured on Intel's 0.6 m ETOX IV process technology, the 28F016SA is the most cost-effective, highest density monolithic 3.3 V FlashFile memory. New Design Recommendations: For new 3.3 V VCC designs with this device, Intel recommends using 16-Mbit Word-Wide FlashFileTM memory. Reference Word-Wide FlashFileTM Memory Family 28F160S3, 28F320S3 datasheet, order number 290608. For new 3.3 V VCC x8 I/O designs with this device, Intel recommends using the 16-Mbit Byte-Wide Smart 3 FlashFileTM memory. Reference Byte-Wide Smart 3 FlashFileTM Memory Family datasheet, order number 290598. For new 5 V VCC designs with this device, Intel recommends using the 16-Mbit Word-Wide FlashFileTM memory. Reference Word-Wide FlashFileTM Memory Family 28F160S5, 28F320S5 datasheet, order number 290609. For new 5 V VCC x8 I/O designs with this device, Intel recommends using the 16-Mbit Byte-Wide Smart 5 FlashFileTM memory. Reference Byte-Wide Smart 5 FlashFileTM Memory Family datasheet, order number 290597. These documents December 1997 are also available at Intel's website, http://www.intel.com/design/flcomp. Order Number: 290489-005 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 28F016SA may contain design defects or errors known as errata. Current characterized errata are available upon request. *Third-party brands and names are the property of their respective owners. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 5937 Denver, CO 80217-9808 or call 1-800-548-4725 or visit Intel's website at http://www.intel.com COPYRIGHT (c) INTEL CORPORATION, 1997 *Third-party brands and names are the property of their respective owners. CG-041493 E 28F016SA CONTENTS PAGE 1.0 INTRODUCTION .............................................5 1.1 Product Overview.........................................5 2.0 DEVICE PINOUT .............................................6 2.1 Lead Descriptions ........................................8 3.0 MEMORY MAPS ...........................................12 3.1 Extended Status Register Memory Map .....13 4.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS .............14 4.1 Bus Operations for Word-Wide Mode (BYTE# = VIH) ...........................................14 4.2 Bus Operations for Byte-Wide Mode (BYTE# = VIL) ...........................................14 4.3 28F008SA-Compatible Mode Command Bus Definitions ..........................................15 4.4 28F016SA-Performance Enhancement Command Bus Definitions.........................16 4.5 Compatible Status Register........................18 4.6 Global Status Register ...............................19 4.7 Block Status Register .................................20 PAGE 5.6 AC Characteristics-Read Only Operations ................................................ 32 5.7 Power-Up and Reset Timings .................... 37 5.8 AC Characteristics for WE#-Controlled Command Write Operations...................... 38 5.9 AC Characteristics for CE#-Controlled Command Write Operations...................... 42 5.10 AC Characteristics for Page Buffer Write Operations ................................................ 46 5.11 Erase and Word/Byte Program Performance, Cycling Performance and Suspend Latency ...................................... 49 6.0 DERATING CURVES.................................... 50 7.0 MECHANICAL SPECIFICATIONS FOR TSOP ........................................................... 52 8.0 MECHANICAL SPECIFICATIONS FOR SSOP ........................................................... 53 9.0 Device Nomenclature and Ordering Information ................................................. 54 10.0 Additional Information .............................. 55 5.0 ELECTRICAL SPECIFICATIONS .................21 5.1 Absolute Maximum Ratings........................21 5.2 Capacitance ...............................................22 5.3 Timing Nomenclature .................................23 5.4 DC Characteristics (VCC = 3.3V 10%) .....26 5.5 DC Characteristics (VCC = 5.0V 10%, 5.0V 5%) ................29 SEE NEW DESIGN RECOMMENDATIONS 3 E 28F016SA REVISION HISTORY Number Original Version -002 Added 56-Lead SSOP Package Separated AC Reading Timing Specs tAVEL, tAVGL for Extended Status Register Reads Modified Device Nomenclature Added Ordering Information Added Page Buffer Typical Program Performance numbers Added Typical Erase Suspend Latencies For ICCD (Deep Power-Down current) BYTE# must be at CMOS levels Added SSOP package mechanical specifications Revised document status from "Advanced Information" to "Preliminary" -003 Section 5.11: Renamed specification "Erase Suspend Latency Time to Program" as "Auto Erase Suspend Latency Time to Program" Section 5.7: Added specifications t PHEL3, tPHEL5 TSOP dimension A1 = 0.05 mm (min) SSOP dimension B = 0.40 mm (max) Minor cosmetic changes -004 Update: Changed Deep Power Down Current Changed Standby Current Changed Sleep Mode Current Combined Commercial and Extended Temperature information into single datasheet Added New Design Recommendations section to cover page -005 4 Description -001 SEE NEW DESIGN RECOMMENDATIONS E 1.0 28F016SA INTRODUCTION The documentation of the Intel 28F016SA memory device includes this datasheet, a detailed user's manual, and a number of application notes, all of which are referenced at the end of this datasheet. The datasheet is intended to give an overview of the chip feature-set and of the operating AC/DC specifications. The 16-Mbit Flash Product Family User's Manual provides complete descriptions of the user modes, system interface examples and detailed descriptions of all principles of operation. It also contains the full list of software algorithm flowcharts, and a brief section on compatibility with Intel 28F008SA. 1.1 Product Overview The 28F016SA is a high-performance 16-Mbit (16,777,216 bit) block erasable nonvolatile random access memory organized as either 1 Mword x 16 or 2 Mbyte x 8. The 28F016SA includes thirtytwo 64-KB (65,536) blocks or thirty-two 32-KW (32,768) blocks. A chip memory map is shown in Figure 4. The implementation of a new architecture, with many enhanced features, will improve the device operating characteristics and results in greater product reliability and ease-of-use. Internal algorithm automation allows word/byte programs and block erase operations to be executed using a two-write command sequence to the CUI in the same way as the 28F008SA 8-Mbit FlashFile memory. A superset of commands have been added to the basic 28F008SA command-set to achieve higher program performance and provide additional capabilities. These new commands and features include: * Page Buffer Writes to Flash * Command Queueing Capability * Automatic Data Programs during Erase * Software Locking of Memory Blocks * Two-Byte Systems * Erase All Unlocked Blocks Successive Programs in 8-bit Writing of memory data is performed in either byte or word increments typically within 6 s, a 33% improvement over the 28F008SA. A block erase operation erases one of the 32 blocks in typically 0.6 sec, independent of the other blocks, which is a 65% improvement over the 28F008SA. the Each block can be written and erased a minimum of 100,000 cycles. Systems can achieve typically onemillion block erase cycles by providing wear-leveling algorithms and graceful block retirement. These techniques have already been employed in many flash file systems. Additionally, wear leveling of block erase cycles can be used to minimize the program/erase performance differences across blocks. A 3/5# input pin reconfigures the device internally for optimized 3.3V or 5.0V read/program operation. The 28F016SA incorporates two Page Buffers of 256 bytes (128 words) each to allow page data writes. This feature can improve a system write performance by up to 4.8 times over previous flash memory devices. Among the 28F016SA: significant enhancements on * 3.3V Low Power Capability * Improved Program Performance * Dedicated Block Program/Erase Protection The 28F016SA will be available in a 56-lead, 1.2 mm thick, 14 mm x 20 mm TSOP type I package or a 56-lead, 1.8 mm thick, 16 mm x 23.7 mm SSOP package. The TSOP form factor and pinout allow for very high board layout densities. SSOP packaging provides relaxed lead spacing dimensions. A Command User Interface (CUI) serves as the system interface between the microprocessor or microcontroller and the internal memory operation. All operations are started by a sequence of command writes to the device. Three Status Registers (described in detail later) and a RY/BY# output pin provide information on the progress of the requested operation. While the 28F008SA requires an operation to complete before the next operation can be requested, the 28F016SA allows queueing of the next operation while the memory executes the current operation. This eliminates system overhead SEE NEW DESIGN RECOMMENDATIONS 5 E 28F016SA when writing several bytes in a row to the array or erasing several blocks at the same time. The 28F016SA can also perform program operations to one block of memory while performing erase of another block. The 28F016SA provides user-selectable block locking to protect code or data such as device drivers, PCMCIA card information, ROM-executable O/S or application code. Each block has an associated nonvolatile lock-bit which determines the lock status of the block. In addition, the 28F016SA has a master Write Protect pin (WP#) which prevents any modifications to memory blocks whose lock-bits are set. The 28F016SA contains three types of Status Registers to accomplish various functions: * A Compatible Status Register (CSR) which is 100% compatible with the 28F008SA FlashFile memory's Status Register. This register, when used alone, provides a straightforward upgrade capability to the 28F016SA from a 28F008SAbased design. * A Global Status Register (GSR) which informs the system of Command Queue status, Page Buffer status, and overall Write State Machine (WSM) status. * 32 Block Status Registers (BSRs) which provide block-specific status information such as the block lock-bit status. The GSR and BSR memory maps for byte-wide and word-wide modes are shown in Figures 5 and 6. The 28F016SA incorporates an open drain RY/BY# output pin. This feature allows the user to OR-tie many RY/BY# pins together in a multiple memory configuration such as a Resident Flash Array. Other configurations of the RY/BY# pin are enabled via special CUI commands and are described in detail in the 16-Mbit Flash Product Family User's Manual. The 28F016SA also incorporates a dual chip-enable function with two input pins, CE0# and CE1#. These pins have exactly the same functionality as the regular chip-enable pin CE# on the 28F008SA. For minimum chip designs, CE1# may be tied to ground to use CE0# as the chip enable input. The 28F016SA uses the logical combination of these 6 two signals to enable or disable the entire chip. Both CE0# and CE1# must be active low to enable the device and, if either one becomes inactive, the chip will be disabled. This feature, along with the open drain RY/BY# pin, allows the system designer to reduce the number of control pins used in a large array of 16-Mbit devices. The BYTE# pin allows either x8 or x16 read/programs to the 28F016SA. BYTE# at logic low selects 8-bit mode with address A0 selecting between low byte and high byte. On the other hand, BYTE# at logic high enables 16-bit operation with address A1 becoming the lowest order address and address A0 is not used (don't care). A device block diagram is shown in Figure 1. The 28F016SA is specified for a maximum access time of 70 ns (tACC) at 5.0V operation (4.75V to 5.25V) over the commercial temperature range (0C to +70C). A corresponding maximum access time of 120 ns at 3.3V (3.0V to 3.6V and 0C to +70C) is achieved for reduced power consumption applications. The 28F016SA incorporates an Automatic Power Saving (APS) feature which substantially reduces the active current when the device is in the static mode of operation (addresses not switching). In APS mode, the typical ICC current is 1 mA at 5.0V (0.8 mA at 3.3V). A deep power-down mode of operation is invoked when the RP# (called PWD# on the 28F008SA) pin transitions low. This mode brings the device power consumption to less than 1.0 A, typically, and provides additional write protection by acting as a device reset pin during power transitions. A reset time is required from RP# switching high until outputs are again valid. In the deep power-down state, the WSM is reset (any current operation will abort) and the CSR, GSR and BSR registers are cleared. A CMOS standby mode of operation is enabled when either CE0# or CE1# transitions high and RP# stays high with all input control pins at CMOS levels. In this mode, the device typically draws an ICC standby current of 50 A. 2.0 DEVICE PINOUT The 28F016SA 56-lead TSOP Type I pinout configuration is shown in Figure 2. The 56-lead SSOP pinout configuration is shown in Figure 3. SEE NEW DESIGN RECOMMENDATIONS E 28F016SA DQ DQ 8-15 Output Buffer 0-7 Output Buffer Input Buffer Input Buffer 3/5# I/O Logic BYTE# Data Queue Registers Output Multiplexer ID Register CSR Page Buffers CE0# ESRs CE1# CUI 0-20 OE# A Data Comparator WE# WP# Input Buffer RP# Y Decoder WSM 64-Kbyte Block 31 64-Kbyte Block 30 X Decoder 64-Kbyte Block 1 RY/BY# 64-Kbyte Block 0 Address Queue Latches Y Gating/Sensing Program/Erase Voltage Switch VPP 3/5# VCC Address Counter GND 0489_01 Figure 1. 28F016SA Block Diagram Architectural Evolution Includes Page Buffers, Queue Registers and Extended Status Registers SEE NEW DESIGN RECOMMENDATIONS 7 E 28F016SA 2.1 Lead Descriptions Symbol Type Name and Function A0 INPUT BYTE-SELECT ADDRESS: Selects between high and low byte when the device is in x8 mode. This address is latched in x8 data programs. Not used in x16 mode (i.e., the A 0 input buffer is turned off when BYTE# is high). A1-A15 INPUT WORD-SELECT ADDRESSES: Select a word within one 64-Kbyte block. A6-15 selects 1 of 1024 rows, and A 1-5 selects 16 of 512 columns. These addresses are latched during data programs. A16-A20 INPUT BLOCK-SELECT ADDRESSES: Select 1 of 32 erase blocks. These addresses are latched during data programs, block erase and lock block operations. DQ0-DQ7 INPUT/OUTPUT LOW-BYTE DATA BUS: Inputs data and commands during CUI write cycles. Outputs array, buffer, identifier or status data in the appropriate read mode. Floated when the chip is deselected or the outputs are disabled. DQ8-DQ15 INPUT/OUTPUT HIGH-BYTE DATA BUS: Inputs data during x16 data program operations. Outputs array, buffer or identifier data in the appropriate read mode; not used for Status Register reads. Floated when the chip is deselected or the outputs are disabled. CE0#,CE1# INPUT CHIP ENABLE INPUTS: Activate the device's control logic, input buffers, decoders and sense amplifiers. With either CE0# or CE1# high, the device is deselected and power consumption reduces to standby levels upon completion of any current data program or block erase operations. Both CE0#, CE1# must be low to select the device. All timing specifications are the same for both signals. Device selection occurs with the latter falling edge of CE 0# or CE1#. The first rising edge of CE0# or CE1# disables the device. RP# INPUT RESET/POWER-DOWN: RP# low places the device in a deep powerdown state. All circuits that burn static power, even those circuits enabled in standby mode, are turned off. When returning from deep power-down, a recovery time is required to allow these circuits to power-up. When RP# goes low, any current or pending WSM operation(s) are terminated, and the device is reset. All Status Registers return to ready (with all status flags cleared). OE# INPUT OUTPUT ENABLE: Gates device data through the output buffers when low. The outputs float to tri-state off when OE# is high. NOTE: CEx# overrides OE#, and OE# overrides WE#. WE# INPUT WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue Registers and Address Queue Latches. WE# is active low, and latches both address and data (command or array) on its rising edge. Page Buffer addresses are latched on the falling edge of WE#. 8 SEE NEW DESIGN RECOMMENDATIONS E 28F016SA 2.1 Lead Descriptions (Continued) Symbol Type Name and Function OPEN DRAIN OUTPUT READY/BUSY: Indicates status of the internal WSM. When low, it indicates that the WSM is busy performing an operation. RY/BY# high indicates that the WSM is ready for new operations (or WSM has completed all pending operations), or block erase is suspended, or the device is in deep power-down mode. This output is always active (i.e., not floated to tri-state off when OE# or CE0#,CE1# are high), except if a RY/BY# Pin Disable command is issued. WP# INPUT WRITE PROTECT: Erase blocks can be locked by writing a nonvolatile lock-bit for each block. When WP# is low, those locked blocks as reflected by the Block-Lock Status bits (BSR.6), are protected from inadvertent data programs or block erases. When WP# is high, all blocks can be written or erased regardless of the state of the lock-bits. The WP# input buffer is disabled when RP# transitions low (deep power-down mode). BYTE# INPUT BYTE ENABLE: BYTE# low places device in x8 mode. All data is then input or output on DQ0-7, and DQ8-15 float. Address A 0 selects between the high and low byte. BYTE# high places the device in x16 mode, and turns off the A0 input buffer. Address A1 then becomes the lowest order address. 3/5# INPUT 3.3/5.0 VOLT SELECT: 3/5# high configures internal circuits for 3.3V operation. 3/5# low configures internal circuits for 5.0V operation. RY/BY# NOTES: Reading the array with 3/5# high in a 5.0V system could damage the device. There is a significant delay from 3/5# switching to valid data. VPP SUPPLY ERASE/PROGRAM POWER SUPPLY: For erasing memory array blocks or writing words/bytes/pages into the flash array. VCC SUPPLY DEVICE POWER SUPPLY (3.3V 10%, 5.0V 10%, 5.0V 5%): Do not leave any power pins floating. GND SUPPLY GROUND FOR ALL INTERNAL CIRCUITRY: Do not leave any ground pins floating. NC NO CONNECT: Lead may be driven or left floating. SEE NEW DESIGN RECOMMENDATIONS 9 E 28F016SA 28F032SA 28F016SV 3/5# CE1 # CE2 # A 20 A 19 A 18 A 17 A 16 VCC A 15 A 14 A 13 A 12 CE 0 # V PP RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1 3/5# CE1 # NC A 20 A 19 A 18 A 17 A 16 VCC A 15 A 14 A 13 A 12 CE0 # V PP RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1 3/5# CE1 # NC A 20 A 19 A 18 A 17 A 16 VCC A 15 A 14 A 13 A 12 CE 0 # V PP RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 E28F016SA 56-LEAD TSOP PINOUT 1.2 mm x 14 mm x 20 mm TOP VIEW 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 WP# WE# OE# RY/BY# DQ 15 DQ 7 DQ 14 DQ 6 GND DQ 13 DQ 5 DQ 12 DQ 4 V CC GND DQ 11 DQ 3 DQ 10 DQ 2 V CC DQ 9 DQ 1 DQ 8 DQ 0 A0 BYTE# NC NC 28F016SV 28F032SA WP# WE# OE# RY/BY# DQ 15 DQ 7 DQ 14 DQ 6 GND DQ 13 DQ 5 DQ 12 DQ 4 VCC GND DQ 11 DQ 3 DQ 10 DQ 2 VCC DQ 9 DQ 1 DQ 8 DQ 0 A0 BYTE# NC NC WP# WE# OE# RY/BY# DQ 15 DQ 7 DQ 14 DQ 6 GND DQ 13 DQ 5 DQ 12 DQ 4 V CC GND DQ 11 DQ 3 DQ 10 DQ 2 V CC DQ 9 DQ 1 DQ 8 DQ 0 A0 BYTE# NC NC 0489_02 NOTE: 56-Lead TSOP Mechanical Diagrams and Dimensions are shown at the end of this specification. Figure 2. TSOP Pinout Configuration 10 SEE NEW DESIGN RECOMMENDATIONS E 28F016SA 28F016SV CE 0# CE 0 # 1 A12 A12 2 A13 A14 A 15 3/5# A 13 A14 A15 3/5# 3 4 5 6 CE1 # CE1 # NC A20 NC A 20 28F016SV V PP RP# A 11 56 55 54 V PP RP# A 11 7 53 52 51 50 A 10 A9 A1 A2 A 10 A9 A1 A2 8 9 49 48 A3 A4 A3 A4 A19 A 19 10 47 A5 A5 A 18 A 18 11 46 A6 A6 A17 A 17 12 45 A7 A7 A16 A 16 13 44 GND GND V CC V CC 14 43 A8 A8 GND GND 15 42 VCC VCC DQ 6 DQ 6 16 41 DQ 9 DQ 9 DQ14 DQ14 17 DQ 7 DQ 7 18 40 39 DQ 1 DQ 8 DQ 1 DQ 8 DQ 0 DA28F016SA 56-LEAD SSOP STANDARD PINOUT 1.8 mm x 16 mm x 23.7 mm TOP VIEW DQ15 DQ15 19 38 DQ 0 RY/BY# RY/BY# 20 37 A0 A0 OE# OE# 21 36 BYTE# BYTE# WE# WE# 22 35 NC NC WP# WP# 23 34 NC NC DQ 13 DQ 13 24 33 DQ 5 DQ 5 25 32 DQ 2 DQ 10 DQ 2 DQ 10 DQ 12 DQ 12 26 31 DQ 3 DQ 3 DQ 4 DQ 4 27 30 DQ 11 DQ 11 V CC V CC 28 29 GND GND 0489_17 Figure 3. SSOP Pinout Configuration SEE NEW DESIGN RECOMMENDATIONS 11 E 28F016SA 3.0 MEMORY MAPS A[20-0] 1FFFFF 1F0000 1EFFFF 1E0000 1DFFFF 1D0000 1CFFFF 1C0000 1BFFFF 1B0000 1AFFFF 1A0000 19FFFF 190000 18FFFF 180000 17FFFF 170000 16FFFF 160000 15FFFF 150000 14FFFF 140000 13FFFF 130000 12FFFF 120000 11FFFF 110000 10FFFF 100000 0FFFFF 0F0000 0EFFFF 0E0000 0DFFFF 0D0000 0CFFFF 0C0000 0BFFFF 0B0000 0AFFFF 0A0000 09FFFF 090000 08FFFF 080000 07FFFF 070000 06FFFF 060000 05FFFF 050000 04FFFF 040000 03FFFF 030000 02FFFF 020000 01FFFF 010000 00FFFF 000000 64-Kbyte Block 31 64-Kbyte Block 30 64-Kbyte Block 29 64-Kbyte Block 28 64-Kbyte Block 27 64-Kbyte Block 26 64-Kbyte Block 25 64-Kbyte Block 24 64-Kbyte Block 23 64-Kbyte Block 22 64-Kbyte Block 21 64-Kbyte Block 20 64-Kbyte Block 19 64-Kbyte Block 18 64-Kbyte Block 17 64-Kbyte Block 16 64-Kbyte Block 15 64-Kbyte Block 14 64-Kbyte Block 13 64-Kbyte Block 12 64-Kbyte Block 11 64-Kbyte Block 10 64-Kbyte Block 9 64-Kbyte Block 8 64-Kbyte Block 7 64-Kbyte Block 6 64-Kbyte Block 5 64-Kbyte Block 4 64-Kbyte Block 3 64-Kbyte Block 2 64-Kbyte Block 1 64-Kbyte Block 0 0489_03 Figure 4. 28F016SA Memory Map (Byte-Wide Mode) 12 SEE NEW DESIGN RECOMMENDATIONS E 3.1 28F016SA Extended Status Register Memory Map x8 MODE A[20-0] RESERVED GSR RESERVED x16 MODE F8003H RESERVED 1F0005H GSR 1F0004H F8002H RESERVED 1F0003H BSR 31 RESERVED RESERVED . . . A[20-1] 1F0006H BSR 31 1F0002H F8001H 1F0001H RESERVED 1F0000H RESERVED . . . 010002H F8000H 08001H RESERVED RESERVED 000006H 00003H RESERVED RESERVED 000005H GSR GSR 000004H 00002H RESERVED RESERVED 000003H BSR 0 RESERVED BSR 0 000002H RESERVED 000001H RESERVED RESERVED 000000H 0489_04 Figure 5. Extended Status Register Memory Map (Byte-Wide Mode) 00001H 00000H 0489_05 Figure 6. Extended Status Register Memory Map (Word-Wide Mode) SEE NEW DESIGN RECOMMENDATIONS 13 E 28F016SA 4.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS 4.1 Bus Operations for Word-Wide Mode (BYTE# = VIH) Mode Notes RP# CE1# CE0# OE# WE# A1 DQ0-15 RY/BY# Read 1,2,7 VIH VIL VIL VIL VIH X DOUT X Output Disable 1,6,7 VIH VIL VIL VIH VIH X High Z X Standby 1,6,7 VIH VIL VIH VIH VIH VIL VIH X X X High Z X Deep Power-Down 1,3 VIL X X X X X High Z VOH Manufacturer ID 4 VIH VIL VIL VIL VIH VIL 0089H VOH Device ID 4 VIH VIL VIL VIL VIH VIH 66A0H VOH 1,5,6 VIH VIL VIL VIH VIL X DIN X Write 4.2 Bus Operations for Byte-Wide Mode (BYTE# = VIL) Mode Notes RP# CE1# CE0# OE# WE# A0 DQ0-7 RY/BY# Read 1,2,7 VIH VIL VIL VIL VIH X DOUT X Output Disable 1,6,7 VIH VIL VIL VIH VIH X High Z X Standby 1,6,7 VIH VIL VIH VIH VIH VIL VIH X X X High Z X Deep Power-Down Manufacturer ID Device ID Write 1,3 VIL X X X X X High Z VOH 4 VIH VIL VIL VIL VIH VIL 89H VOH 4 VIH VIL VIL VIL VIH VIH A0H VOH 1,5,6 VIH VIL VIL VIH VIL X DIN X NOTES: 1. X can be VIH or VIL for address or control pins except for RY/BY#, which is either VOL or VOH. 2. RY/BY# output is open drain. When the WSM is ready, block erase is suspended or the device is in deep power-down mode. RY/BY# will be at VOH if it is tied to VCC through a resistor. RY/BY# at VOH is independent of OE# while a WSM operation is in progress. 3. RP# at GND 0.2V ensures the lowest deep power-down current. 4. A0 and A1 at VIL provide manufacturer ID codes in x8 and x16 modes, respectively. A0 and A1 at VIH provide device ID codes in x8 and x16 modes, respectively. All other addresses are set to zero. 5. Commands for different block erase operations, data program operations or lock-block operations can only be successfully completed when VPP = VPPH. 6. While the WSM is running, RY/BY# in level-mode (default) stays at VOL until all operations are complete. RY/BY# goes to VOH when the WSM is not busy or in erase suspend mode. 7. RY/BY# may be at VOL while the WSM is busy performing various operations; for example, a Status Register read during a data program operation. 14 SEE NEW DESIGN RECOMMENDATIONS E 4.3 28F016SA 28F008SA-Compatible Mode Command Bus Definitions First Bus Cycle Command Notes Read Array Second Bus Cycle Oper Addr Data(4) Oper Addr Data Write X xxFFH Read AA AD Intelligent Identifier 1 Write X xx90H Read IA ID Read Compatible Status Register 2 Write X xx70H Read X CSRD Clear Status Register 3 Write X xx50H Word/Byte Program Write X xx40H Write PA PD Alternate Word/Byte Program Write X xx10H Write PA PD Block Erase/Confirm Write X xx20H Write BA xxD0H Erase Suspend/Resume Write X xxB0H Write X xxD0H ADDRESS A = Array Address BA = Block Address IA = Identifier Address PA = Program Address X = Don't Care DATA AD = Array Data CSRD = CSR Data ID = Identifier Data PD = Program Data NOTES: 1. Following the Intelligent Identifier command, two read operations access the manufacturer and device signature codes. 2. The CSR is automatically available after device enters data program, block erase, or suspend operations. 3. Clears CSR.3, CSR.4 and CSR.5. Also clears GSR.5 and all BSR.5 and BSR.2 bits. 4. The upper byte of the data bus (DQ8-15) during command writes is a "Don't Care" in x16 operation of the device. See Status Register definitions. SEE NEW DESIGN RECOMMENDATIONS 15 E 28F016SA 4.4 28F016SA-Performance Enhancement Command Bus Definitions First Bus Cycle Second Bus Cycle Notes Oper Addr Data(12) Oper Addr Data(12) Read Extended Status Register 1 Write X xx71H Read RA GSRD BSRD Page Buffer Swap 7 Command Mode Write X xx72H Read Page Buffer Write X xx75H Read PBA PD Single Load to Page Buffer Write X xx74H Write PBA PD Sequential Load to Page Buffer Third Bus Cycle Oper Addr Data x8 4,6,10 Write X xxE0H Write X BCL Write X BCH x16 4,5,6,10 Write X xxE0H Write X WCL Write X WCH x8 3,4,9,10 Write X xx0CH Write A0 BC(L,H) Write PA BC(H,L) x16 4,5,10 Write X xx0CH Write X WCL Write PA WCH x8 3 Write X xxFBH Write A0 WD(L,H) Write PA WD(H,L) Write X xx77H Write BA xxD0H Write X xx97H Write X xxD0H Upload Device Information Write X xx99H Write X xxD0H Erase All Unlocked Blocks/Confirm Write X xxA7H Write X xxD0H Page Buffer Write to Flash Two-Byte Program Lock Block/Confirm Upload Status Bits/Confirm 2 RY/BY# Enable to Level-Mode 8 Write X xx96H Write X xx01H RY/BY# Pulse-OnWrite 8 Write X xx96H Write X xx02H RY/BY# Pulse-OnErase 8 Write X xx96H Write X xx03H RY/BY# Disable 8 Write X xx96H Write X xx04H Sleep 11 Write X xxF0H Write X xx80H Abort ADDRESS BA = Block Address PBA = Page Buffer Address RA = Extended Register Address PA = Program Address X = Don't Care 16 DATA AD = Array Data PD = Page Buffer Data BSRD = BSR Data GSRD = GSR Data WC (L,H) = Word Count (Low, High) BC (L,H) = Byte Count (Low, High) WD (L,H) = Write Data (Low, High) SEE NEW DESIGN RECOMMENDATIONS E 28F016SA NOTES: 1. RA can be the GSR address or any BSR address. See Figures 5 and 6 for Extended Status Register Memory Maps. 2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the actual lock-bit status. 3. A0 is automatically complemented to load the second byte of data. BYTE# must be at VIL. The A0 value determines which WD/BC is supplied first: A0 = 0 looks at the WDL/BCL, A0 = 1 looks at the WDH/BCH. 4. BCH/WCH must be at 00H for this product because of the 256-byte (128-word) Page Buffer size and to avoid writing the Page Buffer contents into more than one 256-byte segment within an array block. They are simply shown for future Page Buffer expandability. 5. In x16 mode, only the lower byte DQ0-7 is used for WCL and WCH. The upper byte DQ8-15 is a don't care. 6. PBA and PD (whose count is given in cycles 2 and 3) are supplied starting in the fourth cycle, which is not shown. 7. This command allows the user to swap between available Page Buffers (0 or 1). 8. These commands reconfigure the RY/BY# output to one of two pulse-modes or enable and disable the RY/BY# function. 9. Program address, PA, is the destination address in the flash array which must match the source address in the Page Buffer. Refer to the 16-Mbit Flash Product Family User's Manual. 10. BCL = 00H corresponds to a byte count of 1. Similarly, WCL = 00H corresponds to a word count of 1. 11. To ensure that the 28F016SA's power consumption during sleep mode reaches the deep power-down current level, the system also needs to de-select the chip by taking either or both CE0# or CE1# high. 12. The upper byte of the data bus (DQ8-15) during command writes is a "Don't Care" in x16 operation of the device. SEE NEW DESIGN RECOMMENDATIONS 17 E 28F016SA 4.5 Compatible Status Register WSMS ESS ES DWS VPPS R R R 7 6 5 4 3 2 1 0 NOTES: CSR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy RY/BY# output or WSMS bit must be checked to determine completion of an operation (erase suspend, block erase or data program) before the appropriate Status bit (ESS, ES or DWS) is checked for success. CSR.6 = ERASE-SUSPEND STATUS 1 = Erase Suspended 0 = Erase In Progress/Completed If DWS and ES are set to "1" during a block erase attempt, an improper command sequence was entered. Clear the CSR and attempt the operation again. CSR.5 = ERASE STATUS 1 = Error In Block Erasure 0 = Successful Block Erase CSR.4 = DATA WRITE STATUS 1 = Error in Data Program 0 = Data Program Successful CSR.3 = VPP STATUS 1 = VPP Low Detect, Operation Abort 0 = VPP OK The VPPS bit, unlike an A/D converter, does not provide continuous indication of VPP level. The WSM interrogates VPP's level only after the Data Program or Block Erase command sequences have been entered, and informs the system if VPP has not been switched on. VPPS is not guaranteed to report accurate feedback between VPPL and VPPH. CSR.2-0 = RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use; mask them out when polling the CSR. 18 SEE NEW DESIGN RECOMMENDATIONS E 4.6 28F016SA Global Status Register WSMS OSS DOS DSS QS PBAS PBS PBSS 7 6 5 4 3 2 1 0 NOTES: GSR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy [1] RY/BY# output or WSMS bit must be checked to determine completion of an operation (block lock, erase suspend, any RY/BY# reconfiguration, Upload Status Bits, block erase or data program) before the appropriate Status bit (OSS or DOS) is checked for success. GSR.6 = OPERATION SUSPEND STATUS 1 = Operation Suspended 0 = Operation in Progress/Completed GSR.5 = DEVICE OPERATION STATUS 1 = Operation Unsuccessful 0 = Operation Successful or Currently Running GSR.4 = DEVICE SLEEP STATUS 1 = Device in Sleep 0 = Device Not in Sleep MATRIX 5/4 0 0 = Operation Successful or Currently Running 0 1 = Device in Sleep Mode or Pending Sleep 1 0 = Operation Unsuccessful 1 1 = Operation Unsuccessful or Aborted If operation currently running, then GSR.7 = 0. If device pending sleep, then GSR.7 = 0. Operation aborted: Unsuccessful due to Abort command. GSR.3 = QUEUE STATUS 1 = Queue Full 0 = Queue Available GSR.2 = PAGE BUFFER AVAILABLE STATUS 1 = One or Two Page Buffers Available 0 = No Page Buffer Available GSR.1 = PAGE BUFFER STATUS 1 = Selected Page Buffer Ready 0 = Selected Page Buffer Busy The device contains two Page Buffers. Selected Page Buffer is currently busy with WSM operation. GSR.0 = PAGE BUFFER SELECT STATUS 1 = Page Buffer 1 Selected 0 = Page Buffer 0 Selected NOTE: 1. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block. GSR.7 provides indication when all queued operations are completed. SEE NEW DESIGN RECOMMENDATIONS 19 E 28F016SA 4.7 Block Status Register BS BLS BOS BOAS QS VPPS R R 7 6 5 4 3 2 1 0 NOTES: [1] BSR.7 = BLOCK STATUS 1 = Ready 0 = Busy RY/BY# output or BS bit must be checked to determine completion of an operation (block lock, erase suspend, any RY/BY# reconfiguration, Upload Status Bits, block erase or data program) before the appropriate Status bits (BOS, BLS) is checked for success. BSR.6 = BLOCK-LOCK STATUS 1 = Block Unlocked for Program/Erase 0 = Block Locked for Program/Erase BSR.5 = BLOCK OPERATION STATUS 1 = Operation Unsuccessful 0 = Operation Successful or Currently Running The BOAS bit will not be set until BSR.7 = 1. BSR.4 = BLOCK OPERATION ABORT STATUS 1 = Operation Aborted 0 = Operation Not Aborted MATRIX 5/4 0 0 = Operation Successful or Currently Running 0 1 = Not a Valid Combination 1 0 = Operation Unsuccessful 1 1 = Operation Aborted Operation halted via Abort command. BSR.3 = QUEUE STATUS 1 = Queue Full 0 = Queue Available BSR.2 = VPP STATUS 1 = VPP Low Detect, Operation Abort 0 = VPP OK BSR.1-0 = RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use; mask them out when polling the BSRs. NOTE: 1. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block. GSR.7 provides indication when all queued operations are completed. 20 SEE NEW DESIGN RECOMMENDATIONS E 28F016SA 5.0 ELECTRICAL SPECIFICATIONS 5.1 Absolute Maximum Ratings* NOTICE: This is a production datasheet. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. * WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may effect device reliability. Temperature under Bias .................... 0C to +80C Storage Temperature................... -65C to +125C VCC = 3.3V 10% Systems Sym Parameter Notes Min Max Units Test Conditions Ambient Temperature TA Operating Temperature, Commercial 1 0 70 C VCC VCC with Respect to GND 2 -0.2 7.0 V 2,3 -0.2 14.0 V -0.5 VCC +0.5 V VPP VPP Supply Voltage with Respect to GND V Voltage on Any Pin (Except V CC, VPP) with Respect to GND 2 I Current into Any Non-Supply Pin 5 30 mA IOUT Output Short Circuit Current 4 100 mA VCC = 5.0V 10% , VCC = 5.0V 5% Systems(6) Sym Parameter Notes Min Max Units Test Conditions Ambient Temperature TA Operating Temperature, Commercial 1 0 70 C VCC VCC with Respect to GND 2 -0.2 7.0 V VPP VPP Supply Voltage with Respect to GND 2,3 -0.2 14.0 V V Voltage on Any Pin (Except V CC, VPP) with Respect to GND 2 -2.0 7.0 V I Current into Any Non-Supply Pin 5 30 mA IOUT Output Short Circuit Current 4 100 mA NOTES: 1. Operating temperature is for commercial product defined by this specification. 2. Minimum DC voltage is -10% on input/output pins. During transitions, this level may undershoot to -2.0V for periods <20 ns. Maximum DC voltage on input/output pins is VCC + 10% which, during transitions, may overshoot to VCC + 2.0V for periods <20 ns. 3. Maximum DC voltage on VPP may overshoot to +14.0V for periods <20 ns. 4. Output shorted for no more than one second. No more than one output shorted at a time. 5. This specification also applies to pins marked "NC." 6. 5% VCC specifications refer to the 28F016SA-070 in its High Speed Test configuration. SEE NEW DESIGN RECOMMENDATIONS 21 E 28F016SA 5.2 Capacitance For a 3.3V System: Symbol CIN COUT CLOAD Parameter Capacitance Looking into an Address/Control Pin Capacitance Looking into an Output Pin Load Capacitance Driven by Outputs for Timing Specifications Notes Typ Max Units Test Conditions 1 6 8 pF TA = +25C, f = 1.0 MHz 1 8 12 pF TA = +25C, f = 1.0 MHz 50 pF For VCC = 3.3V 10% 2.5 ns 50 Transmission Line Delay 1 Equivalent Testing Load Circuit For a 5.0V System: Symbol CIN COUT CLOAD Parameter Capacitance Looking into an Address/Control Pin Capacitance Looking into an Output Pin Load Capacitance Driven by Outputs for Timing Specifications Equivalent Testing Load Circuit for VCC 10% Equivalent Testing Load Circuit for VCC 5% Notes Typ Max Units Test Conditions 1 6 8 pF TA = +25C, f = 1.0 MHz 1 8 12 pF TA = +25C, f = 1.0 MHz 100 pF For VCC = 5.0V 10% 30 pF For VCC = 5.0V 5% 2.5 ns 2.5 ns 25 Transmission Line Delay 83 Transmission Line Delay 1 NOTE: 1. Sampled, not 100% tested. 22 SEE NEW DESIGN RECOMMENDATIONS E 5.3 28F016SA Timing Nomenclature All 3.3V system timings are measured from where signals cross 1.5V. For 5.0V systems use the standard JEDEC cross point definitions. Each timing parameter consists of five characters. Some common examples are defined below: tCE tELQV time(t) from CE# (E) going low (L) to the outputs (Q) becoming valid (V) tOE tGLQV time(t) from OE# (G) going low (L) to the outputs (Q) becoming valid (V) tACC tAVQV time(t) from address (A) valid (V) to the outputs (Q) becoming valid (V) tAS tAVWH time(t) from address (A) valid (V) to WE# (W) going high (H) tDH tWHDX time(t) from WE# (W) going high (H) to when the data (D) can become undefined (X) Pin Characters Pin States A Address Inputs H High D Data Inputs L Low Q Data Outputs V Valid E CE# (Chip Enable) X Driven, but not necessarily valid F BYTE# (Byte Enable) Z High Impedance G OE# (Output Enable) W WE# (Write Enable) P RP# (Deep Power-Down Pin) R RY/BY# (Ready Busy) V Any Voltage Level Y 3/5# Pin 5V VCC at 4.5V Minimum 3V VCC at 3.0V Minimum SEE NEW DESIGN RECOMMENDATIONS 23 E 28F016SA 2.4 2.0 INPUT 2.0 OUTPUT TEST POINTS 0.8 0.45 0.8 0489_06 AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0." Input timing begins at VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns. Figure 7. Transient Input/Output Reference Waveform (VCC = 5.0V 10%) for Standard Test Configuration(1) 3.0 INPUT 1.5 TEST POINTS 1.5 OUTPUT 0.0 0489_07 AC test inputs are driven at 3.0V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.5V. Input rise and fall times (10% to 90%) <10 ns. Figure 8. Transient Input/Output Reference Waveform (VCC = 3.3V 10%) High Speed Reference Waveform(2) (VCC = 5.0V 5%) NOTES: 1. Testing characteristics for 28F016SA-080/28F016SA-100. 2. Testing characteristics for 28F016SA-070/28F016SA-120/28F016SA-150. 24 SEE NEW DESIGN RECOMMENDATIONS E 28F016SA 2.5 ns of 25 Transmission Line From Output Test under Test Point Total Capacitance = 100 pF 0489_08 Figure 9. Transient Equivalent Testing Load Circuit (V CC = 5.0V 10%) 2.5 ns of 50 Transmission Line From Output Test under Test Point Total Capacitance = 50 pF 0489_09 Figure 10. Transient Equivalent Testing Load Circuit (V CC = 3.3V 10%) 2.5 ns of 83 Transmission Line From Output Test under Test Point Total Capacitance = 30 pF 0489_10 Figure 11. High Speed Transient Equivalent Testing Load Circuit (V CC = 5.0V 5%) SEE NEW DESIGN RECOMMENDATIONS 25 E 28F016SA 5.4 DC Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE Vcc = 3.3V 10%, TA = 0C to +70C, -40C to +85C 3/5# = Pin Set High for 3.3V Operations Temp Sym Parameter Notes Comm Typ Max Extended Typ Max Units IIL Input Load Current 1 1 1 A ILO Output Leakage Current 1 10 10 A ICCS VCC Standby Current 1,5,6 50 100 70 250 A 1 4 1 10 mA Test Conditions VCC = VCC Max VIN = VCC or GND VCC = VCC Max VIN = VCC or GND VCC = VCC Max CE0#, CE1#, RP#, = VCC 0.2V BYTE#, WP#, 3/5# = V CC 0.2V or GND 0.2V VCC = VCC Max CE0#, CE1#, RP# = VIH BYTE#, WP#, 3/5# = V IH or VIL RP# = GND 0.2V BYTE# = GND 0.2V or VCC 0.2V VCC = VCC Max CMOS: CE0#, CE1# = GND 0.2V, BYTE# = GND 0.2V or VCC 0.2V, Inputs = GND 0.2V or VCC 0.2V TTL: CE0#, CE1# = VIL, BYTE# = VIL or VIH, Inputs = VIL or VIH f = 8 MHz, I OUT = 0 mA VCC = VCC Max CMOS: CE0#, CE1# = GND 0.2V, BYTE# = GND 0.2V or VCC 0.2V, Inputs = GND 0.2V or VCC 0.2V TTL: CE0#, CE1# = VIL, BYTE# = VIL or VIH, Inputs = VIL or VIH f = 4 MHz, I OUT = 0 mA ICCD VCC Deep PowerDown Current 1 1 5 3 35 A ICCR1 VCC Read Current 1,4,5 30 35 30 40 mA ICCR2 VCC Read Current 1,4,5 15 20 15 25 mA ICCW VCC Program Current for Word or Byte VCC Block Erase Current VCC Erase Suspend Current 1 8 12 8 12 mA Program in Progress 1 6 12 6 12 mA Block Erase in Progress 1,2 3 6 3 6 mA CE0#, CE1# = VIH Block Erase Suspended ICCE ICCES 26 SEE NEW DESIGN RECOMMENDATIONS E 5.4 28F016SA DC Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE (Continued) Vcc = 3.3V 10%, TA = 0C to +70C, -40C to +85C 3/5# = Pin Set High for 3.3V Operations Temp Sym Parameter IPPS VPP Standby/ IPPR Read Current IPPD VPP Deep PowerDown Current Comm Extended Notes Typ Max Typ Max Units 1 1 10 1 10 A VPP VCC 65 200 65 200 A VPP > VCC 0.2 5 0.2 5 A RP# = GND 0.2V 1 SEE NEW DESIGN RECOMMENDATIONS Test Conditions 27 E 28F016SA 5.4 DC Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE (Continued) Vcc = 3.3V 10%, TA = 0C to +70C, -40C to +85C 3/5# = Pin Set High for 3.3V Operations Sym IPPW IPPE IPPES Parameter VPP Program Current for Word or Byte VPP Block Erase Current VPP Erase Suspend Current Temp Comm/Extended Notes Min Typ Max Units Test Conditions 1 10 15 mA VPP = VPPH Program in Progress 1 4 10 mA 1 65 200 A VPP = VPPH Block Erase in Progress VPP = VPPH Block Erase Suspended VIL Input Low Voltage -0.3 0.8 V VIH Input High Voltage 2.0 VCC + 0.3 V VOL Output Low Voltage 0.4 V VCC = VCC Min IOL = 4 mA VOH1 Output High Voltage 2.4 V VCC = VCC Min IOH = -2.0 mA VCC -0.2 V VCC = VCC Min IOH = -100 A VOH2 VPPL VPPH VLKO VPP during Normal Operations VPP during Program/ Erase Operations VCC Program/Erase Lock Voltage 3 0.0 3 11.4 2.0 12.0 6.5 V 12.6 V V NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 3.3V, VPP = 12.0V, T = 25C. These currents are valid for all product versions (package and speeds). 2. ICCES is specified with the device deselected. If the device is read while in erase suspend mode, current draw is the sum of ICCES and ICCR. 3. Block erases, word/byte programs and lock block operations are inhibited when VPP = VPPL and not guaranteed in the range between VPPH and VPPL. 4. Automatic Power Savings (APS) reduces ICCR to less than 1 mA in static operation. 5. CMOS Inputs are either VCC 0.2V or GND 0.2V. TTL Inputs are either VIL or VIH. 6. Standby current levels are not reached when putting the chip in standby mode immediately after reading the page buffer. Default the device into read array or read Status Register mode before entering standby to ensure standby current levels. 28 SEE NEW DESIGN RECOMMENDATIONS E 5.5 28F016SA DC Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE VCC = 5.0V 10%, 5.0V 5%, T A = 0C to +70C, -40C to +85C 3/5# Pin Set Low for 5V Operations Temp Sym Parameter Notes Comm Typ Max Extended Typ Max Units IIL Input Load Current 1 1 1 A ILO Output Leakage Current 1 10 10 A ICCS VCC Standby Current 1,5,6 50 100 70 250 A 2 4 2 10 mA Test Conditions VCC = VCC Max VIN = VCC or GND VCC = VCC Max VIN = VCC or GND VCC = VCC Max CE0#, CE1#, RP# = VCC 0.2V BYTE#, WP#, 3/5# = V CC 0.2V or GND 0.2V VCC = VCC Max CE0#, CE1#, RP# = VIH BYTE#, WP#, 3/5# = VIH or VIL RP# = GND 0.2V BYTE# = GND 0.2V or VCC 0.2V VCC = VCC Max CMOS: CE0#, CE1# = GND 0.2V, BYTE# = GND 0.2V or VCC 0.2V, Inputs = GND 0.2V or VCC 0.2V TTL: CE0#, CE1# = VIL, BYTE# = VIL or VIH, Inputs = VIL or VIH f = 10 MHz, I OUT = 0 mA VCC = VCC Max CMOS: CE0#, CE1# = GND 0.2V, BYTE# = GND 0.2V or VCC 0.2V, Inputs = GND 0.2V or VCC 0.2V TTL: CE0#, CE1# = VIL, BYTE# = VIL or VIH, Inputs = VIL or VIH f = 5 MHz, I OUT = 0 mA ICCD VCC Deep PowerDown Current 1 1 5 10 60 A ICCR1 VCC Read Current 1,4,5 50 60 55 70 mA ICCR2 VCC Read Current 1,4,5 30 35 30 35 mA ICCW VCC Program Current for Word or Byte VCC Block Erase Current VCC Erase Suspend Current 1 25 35 25 35 mA Program in Progress 1 18 25 18 25 mA Block Erase in Progress 1,2 5 10 5 10 mA CE0#, CE1# = VIH Block Erase Suspended ICCE ICCES SEE NEW DESIGN RECOMMENDATIONS 29 E 28F016SA 5.5 DC Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE (Continued) VCC = 5.0V 10%, 5.0V 5%, T A = 0C to +70C, -40C to +85C 3/5# Pin Set Low for 5V Operations Temp Sym Parameter IPPS VPP Standby/Read IPPR Current IPPD VPP Deep PowerDown Current 30 Comm Extended Notes Typ Max Typ Max Units 1 1 10 1 10 A VPP VCC 65 200 65 200 A VPP > VCC 0.2 5 0.2 5 A RP# = GND 0.2V 1 Test Conditions SEE NEW DESIGN RECOMMENDATIONS E 5.5 DC 28F016SA Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE (Continued) VCC = 5.0V 10%, 5.0V 5%,T A = 0C to +70C, -40C to +85C 3/5# Pin Set Low for 5V Operations Sym IPPW Parameter VIL VPP Program Current for Word or Byte VPP Block Erase Current VPP Erase Suspend Current Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH1 Output High Voltage IPPE IPPES Temp Comm/Extended Notes Min Typ Max Units 1 7 12 mA 1 5 10 mA 1 65 200 A -0.5 0.8 V 2.0 VCC +0.5 V 0.45 V 0.85 VCC V VOH2 VCC V VPPL -0.4 0.0 VPPH VLKO VPP during Normal Operations VPP during Program/ Erase Operations VCC Program/Erase Lock Voltage 3 11.4 12.0 6.5 V 12.6 V 2.0 Test Conditions VPP = VPPH Program in Progress VPP = VPPH Block Erase in Progress VPP = VPPH Block Erase Suspended VCC = VCC Min IOL = 5.8 mA VCC = VCC Min IOH = -2.5 mA VCC = VCC Min IOH = -100 A V NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0V, VPP = 12.0V, T = 25C. These currents are valid for all product versions (package and speeds). 2. ICCES is specified with the device deselected. If the device is read while in erase suspend mode, current draw is the sum of ICCES and ICCR. 3. Block erases, word/byte programs and lock block operations are inhibited when VPP = VPPL and not guaranteed in the range between VPPH and VPPL. 4. Automatic Power Saving (APS) reduces ICCR to less than 2 mA in static operation. 5. CMOS Inputs are either VCC 0.2V or GND 0.2V. TTL Inputs are either VIL or VIH. 6. Standby current levels are not reached when putting the chip in standby mode immediately after reading the page buffer. Default the device into read array or read Status Register mode before entering standby to ensure standby current levels. SEE NEW DESIGN RECOMMENDATIONS 31 E 28F016SA 5.6 AC Characteristics-Read Only Operations: COMMERCIAL AND EXTENDED TEMPERATURE(1) VCC = 3.3V 10%, T A = 0C to +70C, -40C to +85C Temp Commercial Speed Sym Parameter -120 Extended -150 -150 VCC 3.3V 10% Load 50 pF Notes Min Max 120 Min Units Max Min 150 Max tAVAV Read Cycle Time tAVQV Address to Output Delay tELQV CE# to Output Delay tPHQV RP# High to Output Delay tGLQV OE# to Output Delay 2 tELQX CE# to Output in Low Z 3 tEHQZ CE# to Output in High Z 3 tGLQX OE# to Output in Low Z 3 tGHQZ OE# to Output in High Z 3 tOH Output Hold from Address, CE# or OE# Change, Whichever Occurs First 3 tFLQV tFHQV BYTE# to Output Delay 3 120 150 150 ns tFLQZ BYTE# Low to Output in High Z 3 30 40 40 ns tELFL tELFH CE# Low to BYTE# High or Low 3 5 5 5 ns 2 150 ns 120 150 150 ns 120 150 150 ns 620 750 750 ns 45 50 50 ns 0 0 0 30 ns 35 0 35 0 0 15 ns 20 0 20 0 ns 0 ns ns For Extended Status Register Reads Symbol Parameter Temp Commercial Extended Speed -120 -150 VCC 3.3V 10% Load 50 pF Notes Min tAVEL Address Setup to CE# Going Low 3,4 0 0 ns tAVGL Address Setup to OE# Going Low 3,4 0 0 ns 32 Max Min Units Max SEE NEW DESIGN RECOMMENDATIONS E 5.6 28F016SA AC Characteristics-Read Only Operations: COMMERCIAL AND EXTENDED TEMPERATURE(1) (Continued) VCC = 5.0V 10%, 5.0V 5%, T A = 0C to +70C. -40C to +85C Temp Sym Parameter Commercial Comm/Ext Speed -70 -80 -100 VCC 5.0V 5%V 5.0V 10%V 5.0V 10%V Load 30 pF 50 pF 50% Notes Min Max Max Max Read Cycle Time tAVQV Address to Output Delay tELQV CE# to Output Delay tPHQV RP# to Output Delay tGLQV OE# to Output Delay 2 tELQX CE# to Output in Low Z 3 tEHQZ CE# to Output in High Z 3 tGLQX OE# to Output in Low Z 3 tGHQZ OE# to Output in High Z 3 tOH Output Hold from Address, CE# or OE# Change, Whichever Occurs First 3 tFLQV tFHQV BYTE# to Output Delay 3 70 80 100 ns tFLQZ BYTE# Low to Output in High Z CE# Low to BYTE# High or Low 3 25 30 30 ns 3 5 5 5 ns 2 80 Min tAVAV tELFL tELFH 70 Min Units 100 ns 70 80 100 ns 70 80 100 ns 400 480 550 ns 30 35 40 ns 0 0 25 0 0 30 0 15 0 30 0 15 0 SEE NEW DESIGN RECOMMENDATIONS ns ns ns 15 0 ns ns 33 E 28F016SA For Extended Status Register Reads Temp Versions(5) Commercial Commercial Comm/Ext Load 30 pF 50 pF 50 pF VCC 5% 28F016SA-070(6) 28F016SA-080(7) VCC 10% Sym Units Max Min Max 28F016SA-100(7) Parameter Notes Min Min Max tAVEL Address Setup to CE# Going Low 3,4 0 0 0 ns tAVGL Address Setup to OE# Going Low 3,4 0 0 0 ns NOTES: 1. See AC Input/Output Reference Waveforms for timing measurements, Figures 7 and 8. 2. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV. 3. Sampled, not 100% tested. 4. This timing parameter is used to latch the correct BSR data onto the outputs. 5. Device speeds are defined as: 70/80 ns at VCC = 5.0V equivalent to 120 ns at VCC = 3.3V 100 ns at VCC = 5.0V equivalent to 150 ns at VCC = 3.3V 6. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for High Speed Test Configuration. 7. See Standard AC Input/Output Reference Waveforms and AC Testing Load Circuit. 34 SEE NEW DESIGN RECOMMENDATIONS E 28F016SA V IH ADDRESSES STABLE ADDRESSES (A) VIL t AVAV V IH CEx# (E)(1) V IL t AVEL t EHQZ VIH t AVGL OE# (G) V IL t GHQZ VIH WE# (W) t GLQV V IL t ELQV VOH DATA (D/Q) t OH t GLQX tELQX HIGH Z HIGH Z VALID OUTPUT V OL t AVQV 5.0V V CC GND t PHQV VIH RP# (P) V IL 0489_11 NOTE: 1. CEX# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high. Figure 12. Read Timing Waveforms SEE NEW DESIGN RECOMMENDATIONS 35 E 28F016SA VIH ADDRESSES STABLE ADDRESSES (A) V IL t AVAV VIH CEx #(E) (1) V IL t AVFL = t ELFL t EHQZ VIH t AVEL OE# (G) t GHQZ V IL t ELFL t AVGL VIH t FLQV = t AVQV BYTE# (F) t GLQV V IL t t ELQV OH t GLQX VOH t ELQX HIGH Z DATA (DQ0-DQ7) VOL t AVQV VOH DATA (DQ8-DQ15) VOL DATA OUTPUT DATA OUTPUT HIGH Z HIGH Z t FLQZ DATA OUTPUT HIGH Z 0489_12 NOTE: 1. CEX# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high. Figure 13. BYTE# Timing Waveforms 36 SEE NEW DESIGN RECOMMENDATIONS E 5.7 28F016SA Power-Up and Reset Timings: COMMERCIAL/EXTENDED TEMPERATURE VCC Power-Up RP# (P) t YHPH t YLPH 3/5# 5.0V (Y) t PLYL 4.5V 3.3V VCC 0V (3V,5V) t PL5V CE X # t PHEL3 Address (A) t PHEL5 Valid Valid t AVQV t AVQV Data (Q) Valid 5.0V Outputs Valid 3.3V Outputs t PHQV t PHQV 0489_13 Figure 14. VCC Power-Up and RP# Reset Waveforms Symbol Parameter tPLYL tPLYH RP# Low to 3/5# Low (High) tYLPH tYHPH 3/5# Low (High) to RP# High tPL5V tPL3V Notes Min Max Unit 0 s 1 2 s RP# Low to VCC at 4.5V minimum (to VCC at 3.0V min or 3.6V max) 2 0 s tPHEL3 RP# High to CE# Low (3.3V VCC) 1 500 ns tPHEL5 RP# High to CE# Low (5V VCC) 1 330 ns tAVQV Address Valid to Data Valid for V CC = 5V 10% 3 80 ns tPHQV RP# High to Data Valid for VCC = 5V 10% 3 480 ns NOTES: CE0#, CE1# and OE# are switched low after Power-Up. 1. The tYLPH/tYHPH and tPHEL3/tPHEL5 times must be strictly followed to guarantee all other read and program specifications. 2. The power supply may start to switch concurrently with RP# going low. 3. The address access time and RP# high to data valid time are shown for 5V VCC operation of the 28F016SA-080. Refer to the AC Characteristics Read Only Operations for 3.3V VCC and all other speed options. SEE NEW DESIGN RECOMMENDATIONS 37 E 28F016SA 5.8 AC Characteristics for WE#-Controlled Command Write Operations: COMMERCIAL AND EXTENDED TEMPERATURE(1) VCC = 3.3V 10%, T A = 0C to +70C, -40C to +85C Temp Sym Parameter Notes tAVAV Write Cycle Time tVPWH VPP Setup to WE# Going High tPHEL Commercial Min Typ Comm/Extended Max Min Typ Max Units 120 150 ns 100 100 ns RP# Setup to CE# Going Low 480 480 ns tELWL CE# Setup to WE# Going Low 10 10 ns tAVWH Address Setup to WE# Going High 2,6 75 75 ns tDVWH Data Setup to WE# Going High 2,6 75 75 ns tWLWH WE# Pulse Width 75 75 ns tWHDX Data Hold from WE# High 2 10 10 ns tWHAX Address Hold from WE# High 2 10 10 ns tWHEH CE# Hold from WE# High 10 10 ns tWHWL WE# Pulse Width High 45 75 ns tGHWL Read Recovery before Write 0 0 ns tWHRL WE# High to RY/BY# Going Low tRHPL RP# Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High tPHWL 3 100 ns 0 0 ns RP# High Recovery to WE# Going Low 1 1 s tWHGL Write Recovery before Read 95 120 ns tQVVL VPP Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High 0 0 s tWHQV1 Duration of Word/Byte Program Operation tWHQV2 Duration of Block Erase Operation 38 3 100 4,5 5 4 0.3 9 Note 7 5 10 0.3 9 Note 7 s 10 sec SEE NEW DESIGN RECOMMENDATIONS E 5.8 28F016SA AC Characteristics for WE#-Controlled Command Write Operations: COMMERCIAL AND EXTENDED TEMPERATURE(1) (Continued) VCC = 5.0V 10%, 5.0V 5%, T A = 0C to +70C, -40C to +85C Versions Temp Commercial VCC 5% 28F016SA-070 VCC 10% Sym Parameter tAVAV Write Cycle Time tVPWH VPP Setup to WE# Going High tPHEL Notes Commercial Unit 28F016SA-080 Min Typ Max Comm/Ext Min Typ Max 28F016SA-100 Min Typ Max 70 80 100 ns 100 100 100 ns RP# Setup to CE# Going Low 480 480 480 ns tELWL CE# Setup to WE# Going Low 0 0 0 ns tAVWH Address Setup to WE# Going High 2,6 50 50 50 ns tDVWH Data Setup to WE# Going High 2,6 50 50 50 ns tWLWH WE# Pulse Width 40 50 50 ns tWHDX Data Hold from WE# High 2 0 0 0 ns tWHAX Address Hold from WE# High 2 10 10 10 ns tWHEH CE# Hold from WE# High 10 10 10 ns tWHWL WE# Pulse Width High 30 30 50 ns tGHWL Read Recovery before Write 0 0 0 ns 3 SEE NEW DESIGN RECOMMENDATIONS 39 E 28F016SA 5.8 AC Characteristics for WE#-Controlled Command Write Operations: COMMERCIAL AND EXTENDED TEMPERATURE(1) (Continued) VCC = 5.0V 10%, 5.0V 5%, T A = 0C to +70C, -40C to +85C Versions Temp Commercial VCC 5% 28F016SA-070 VCC 10% Sym Parameter tWHRL WE# High to RY/BY# Going Low tRHPL RP# Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High tPHWL Notes Commercial Unit 28F016SA-080 Min Typ Max Min Typ 100 3 Comm/Ext Max 28F016SA-100 Min Typ 100 Max 100 ns 0 0 0 ns RP# High Recovery to WE# Going Low 1 1 1 s tWHGL Write Recovery before Read 60 65 80 ns tQVVL VPP Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High 0 0 0 s tWHQV1 Duration of Word/Byte Program Operation 4,5 4.5 tWHQV2 Duration of Block Erase Operation 4 0.3 40 6 Note 7 4.5 10 0.3 6 Note 7 4.5 10 0.3 6 Note 7 s 10 sec SEE NEW DESIGN RECOMMENDATIONS E 28F016SA NOTES: CE# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high. 1. Read timings during data program and block erase are the same as for normal read. 2. Refer to command definition tables for valid address and data values. 3. Sampled, but not 100% tested. 4. Data program/block erase durations are measured to valid Status Register data. 5. Word/byte program operations are typically performed with 1 programming pulse. 6. Address and data are latched on the rising edge of WE# for all command write operations. 7. This information will be available in a technical paper. Please call Intel's Application Hotline or your local Intel sales office for more information. WRITE VALID ADDRESS & DATA (DATA-WRITE) OR ERASE CONFIRM COMMAND WRITE DATA-WRITE OR ERASE SETUP COMMAND DEEP POWER-DOWN AUTOMATED DATA-WRITE OR ERASE DELAY WRITE READ EXTENDED REGISTER COMMAND READ EXTENDED STATUS REGISTER DATA V IH ADDRESSES (A) V NOTE 1 IL A t t AVAV A=RA IN t AVWH WHAX READ COMPATIBLE STATUS REGISTER DATA V NOTE 3 IH ADDRESSES (A) V NOTE 2 IL A t V t AVAV IN t AVWH WHAX IH CEx # (E) V NOTE 4 IL t t ELWL WHEH t V OE# (G) V IL t V WHGL IH t WHWL t WHQV1,2 GHWL IH WE# (W) V IL t t V IH DATA (D/Q) V IL DVWH HIGH Z t D IN WLWH t WHDX D D IN t V D IN D OUT IN PHWL WHRL OH RY/BY# (R) V OL t V IH RHPL NOTE 5 RP# (P) V IL t V V V PP (V) VPWH t QVVL PPH PPL V IN V IL 0489_14 NOTES: 1. This address string depicts data program/block erase cycles with corresponding verification via ESRD. 2. This address string depicts data program/block erase cycles with corresponding verification via CSRD. 3. This cycle is invalid when using CSRD for verification during data program/block erase operations. 4. CEX# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high. 5. RP# low transition is only to show tRHPL; not valid for above read and program cycles. Figure 15. AC Waveforms for Command Write Operations SEE NEW DESIGN RECOMMENDATIONS 41 E 28F016SA 5.9 AC Characteristics for CE#-Controlled Command Write Operations: COMMERCIAL AND EXTENDED TEMPERATURE(1) VCC = 3.3V 10%, TA = 0C to +70C, -40C to +85C Sym Parameter Temp Commercial Comm/Ext Speed -120 -150 Notes tAVAV Write Cycle Time tVPEH VPP Setup to CE# Going High tPHWL Min Typ Max Min Typ Unit Max 120 150 ns 100 100 ns RP# Setup to WE# Going Low 480 480 ns tWLEL WE# Setup to CE# Going Low 0 0 ns tAVEH Address Setup to CE# Going High 2,6 75 75 ns tDVEH Data Setup to CE# Going High 2,6 75 75 ns tELEH CE# Pulse Width 75 75 ns tEHDX Data Hold from CE# High 2 10 10 ns tEHAX Address Hold from CE# High 2 10 10 ns tEHWH WE Hold from CE# High 10 10 ns tEHEL CE# Pulse Width High 45 75 ns tGHEL Read Recovery before Write 0 0 ns tEHRL CE# High to RY/BY# Going Low tRHPL RP# Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High tPHEL 3 100 ns 0 0 ns RP# High Recovery to CE# Going Low 1 1 s tEHGL Write Recovery before Read 95 120 ns tQVVL VPP Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High 0 0 s tEHQV1 Duration of Word/Byte Program Operation tEHQV2 Duration of Block Erase Operation 42 3 100 4,5 5 4 0.3 9 Note 7 5 10 0.3 9 Note 7 s 10 sec SEE NEW DESIGN RECOMMENDATIONS E 5.9 28F016SA AC Characteristics for CE#-Controlled Command Write Operations: COMMERCIAL AND EXTENDED TEMPERATURE(1) (Continued) VCC = 5.0 to 10% , 5.0 5%, T A = 0C to +70C, -40C to +85C Versions Temp Commercial VCC 5% 28F016SA-070 VCC 10% Sym Parameter tAVAV Write Cycle Time tVPEH VPP Setup to CE# Going High tPHWL RP# Setup to WE# Going Low tWLEL WE# Setup to CE# Going Low tAVEH Address Setup to CE# Going High tDVEH Data Setup to CE# Going High tELEH CE# Pulse Width tEHDX Data Hold from CE# High tEHAX Address Hold from CE# High tEHWH Notes Commercial Unit 28F016SA-080 Min Typ Max Comm/Ext Min Typ Max 28F016SA-100 Min Typ Max 70 80 100 ns 3 100 100 100 ns 3 480 480 480 ns 0 0 0 ns 2,6 50 50 50 ns 2,6 50 50 50 ns 40 50 50 ns 2 0 0 0 ns 2 10 10 10 ns WE# Hold from CE# High 10 10 10 ns tEHEL CE# Pulse Width High 30 30 50 ns tGHEL Read Recovery before Write 0 0 0 ns tEHRL CE# High to RY/BY# Going Low 100 SEE NEW DESIGN RECOMMENDATIONS 100 100 ns 43 E 28F016SA 5.9 AC Characteristics for CE#-Controlled Command Write Operations: COMMERCIAL AND EXTENDED TEMPERATURE(1) (Continued) VCC = 5.0 to 10%, 5.0V 5%, T A = 0C to +70C, -40C to +85C Versions Temp Commercial VCC 5% 28F016SA-070 VCC 10% Commercial Unit 28F016SA-080 Parameter Notes Min tRHPL RP# Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High 3 0 0 0 ns tPHEL RP# High Recovery to CE# Going Low 1 1 1 s tEHGL Write Recovery before Read 60 65 80 s tQVVL VPP Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High 0 0 0 s 4,5 4.5 tEHQV2 Duration of Block Erase Operation 4 0.3 6 Max Min Note 7 4.5 10 0.3 Typ 6 Max 28F016SA-100 Sym tEHQV1 Duration of Word/Byte Program Operation Typ Comm/Ext Min Note 7 4.5 10 0.3 Typ 6 Max Note 7 s 10 sec NOTES: CE# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high. 1. Read timings during data program and block erase are the same as for normal read. 2. Refer to command definition tables for valid address and data values. 3. Sampled, but not 100% tested. 4. Data program/block erase durations are measured to valid Status Register data. 5. Word/byte program operations are typically performed with 1 programming pulse. 6. Address and data are latched on the rising edge of CE# for all command write operations. 7. This information will be available in a technical paper. Please call Intel's Application Hotline or your local Intel sales office for more information. 44 SEE NEW DESIGN RECOMMENDATIONS E 28F016SA WRITE VALID ADDRESS & DATA (DATA-WRITE) OR ERASE CONFIRM COMMAND WRITE DATA-WRITE OR ERASE SETUP COMMAND DEEP POWER-DOWN AUTOMATED DATA-WRITE OR ERASE DELAY WRITE READ EXTENDED REGISTER COMMAND READ EXTENDED STATUS REGISTER DATA V IH ADDRESSES (A) V IL NOTE 1 A t t AVAV V IH ADDRESSES (A) V NOTE 2 IL t EHAX READ COMPATIBLE STATUS REGISTER DATA NOTE 3 A t V A=RA IN AVEH t AVAV IN t AVEH EHAX IH WE# (W) V IL t t WLEL EHWH t V OE# (G) V IL t V CEx#(E) V NOTE 4 IH DATA (D/Q) GHEL IL HIGH Z t ELEH t DVEH D IN EHDX D D IN D IN D OUT IN PHEL t V RY/BY# (R) V t EHQV1,2 IL t V t EHEL IH t V EHGL IH EHRL OH OL t V IH RHPL NOTE 5 RP# (P) V IL t V V (V) V PP V V VPEH t QVVL PPH PPL IH IL 0489_15 NOTES: 1. This address string depicts data program/block erase cycles with corresponding verification via ESRD. 2. This address string depicts data program/block erase cycles with corresponding verification via CSRD. 3. This cycle is invalid when using CSRD for verification during data program/block erase operations. 4. CEX# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high. 5. RP# low transition is only to show tRHPL; not valid for above read and program cycles. Figure 16. Alternate AC Waveforms for Command Write Operations SEE NEW DESIGN RECOMMENDATIONS 45 E 28F016SA 5.10 AC Characteristics for Page Buffer Write Operations: COMMERCIAL AND EXTENDED TEMPERATURE(1) VCC = 3.3V 10%, T A = 0C to +70C, -40C to +85C Sym Parameter Temp Commercial Speed -120 Notes Min Typ Comm/Ext -150 Max Min Typ Unit Max tAVAV Write Cycle Time 120 150 ns tELWL CE# Setup to WE# Going Low 10 10 ns tAVWL Address Setup to WE# Going Low 3 0 0 ns tDVWH Data Setup to WE# Going High 2 75 75 ns tWLWH WE# Pulse Width 75 75 ns tWHDX Data Hold from WE# High 2 10 10 ns tWHAX Address Hold from WE# High 2 10 10 ns tWHEH CE# Hold from WE# High 10 10 ns tWHWL WE# Pulse Width High 45 75 ns tGHWL Read Recovery before Write 0 0 ns tWHGL Write Recovery before Read 95 120 ns 46 SEE NEW DESIGN RECOMMENDATIONS E 28F016SA 5.10 AC Characteristics for Page Buffer Write Operations: COMMERCIAL AND EXTENDED TEMPERATURE(1) (Continued) VCC = 5.0V 10%, 5.0V 5%, T A = 0C to +70C, -40C to +85C Sym Parameter Temp Commercial Commercial Comm/Ext Speed -70 -80 -100 VCC Notes 5.0V 5% Min Typ Max 5.0V 10% Min Typ Max Unit 5.0V 10% Min Typ Max tAVAV Write Cycle Time 70 80 100 ns tELWL CE# Setup to WE# Going Low 0 0 0 ns tAVWL Address Setup to WE# Going Low 3 0 0 0 ns tDVWH Data Setup to WE# Going High 2 50 50 50 ns tWLWH WE# Pulse Width 40 50 50 ns tWHDX Data Hold from WE# High 2 0 0 0 ns tWHAX Address Hold from WE# High 2 10 10 10 ns tWHEH CE# Hold from WE# High 10 10 10 ns tWHWL WE# Pulse Width High 30 30 50 ns tGHWL Read Recovery before Write 0 0 0 ns tWHGL Write Recovery before Read 60 65 80 ns NOTES: CE# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high. 1. These are WE#-controlled write timings, equivalent CE#-controlled write timings apply. 2. Sampled, but not 100% tested. 3. Address must be valid during the entire WE# low pulse or the entire CE# low pulse for CE#-controlled writes. SEE NEW DESIGN RECOMMENDATIONS 47 E 28F016SA V t WHEH IH CEx#(E) V IL t ELWL V IH t WHWL WE# (W) t AVWL V IL t WLWH t WHAX V IH ADDRESSES (A) VALID V IL t t DVWH WHDX V IH DATA (D/Q) HIGH Z DIN V IL 0489_16 Figure 17. Page Buffer Write Timing Waveforms (Loading Data to the Page Buffer) 48 SEE NEW DESIGN RECOMMENDATIONS E 5.11 28F016SA Erase and Word/Byte Write Performance, Cycling Performance and Suspend Latency(3) VCC = 3.3V 10%, VPP = 12.0V 0.6V, T A = 0C to +70C Sym Typ(1) Max Units 2,4 3.26 Note 6 s 2,4 6.53 Note 6 s Parameter Notes Page Buffer Byte Write Time Page Buffer Word Write Time Min Test Conditions tWHRH1 Word/Byte Program Time 2 9 Note 6 s tWHRH2 Block Program Time 2 0.6 2.1 sec Byte Prog. Mode tWHRH3 Block Program Time 2 0.3 1.0 sec Word Prog. Mode Block Erase Time 2 0.8 10 sec Full Chip Erase Time 2 25.6 sec Erase Suspend Latency Time to Read 7.0 s Auto Erase Suspend Latency Time to Write 10.0 s Erase Cycles 5 100,000 1,000,000 Cycles VCC = 5.0V 10%, V PP = 12.0V 0.6V, T A = 0C to +70C Sym Typ(1) Max Units 2,4 2.76 Note 6 s 2,4 5.51 Note 6 s Parameter Notes Page Buffer Byte Write Time Page Buffer Word Write Time Min Test Conditions tWHRH1 Word/Byte Program Time 2 6 Note 6 s tWHRH2 Block Program Time 2 0.4 2.1 sec Byte Prog. Mode Word Prog. Mode tWHRH3 Block Program Time 2 0.2 1.0 sec Block Erase Time 2 0.6 10 sec Full Chip Erase Time 2 19.2 sec Erase Suspend Latency Time to Read 5.0 s Auto Erase Suspend Latency Time to Write 8.0 s Erase Cycles 5 100,000 1,000,000 Cycles NOTES: 1. +25C, VCC = 3.3V or 5.0V nominal, VPP = 12.0V nominal, 10K cycles. 2. Excludes system-level overhead. 3. These performance numbers are valid for all speed versions. 4. This assumes using the full Page Buffer to data program to the flash memory (256 bytes or 128 words). 5. Typical 1,000,000 cycle performance assumes the application uses block retirement techniques. 6. This information will be available in a technical paper. Please call Intel's Application Hotline or your local Intel Sales office for more information. SEE NEW DESIGN RECOMMENDATIONS 49 E 28F016SA 6.0 DERATING CURVES 290489-16.eps Figure 18. ICC vs. Frequency (VCC = 5.5V) for x8 or x16 Operation 290489-19.eps Figure 20. ICC vs. Frequency (VCC = 3.6V) for x8 or x16 Operation 290489-21.eps 290489-18.eps Figure 19. ICC during Block Erase 50 Figure 21. IPP during Block Erase SEE NEW DESIGN RECOMMENDATIONS E 28F016SA 290489-24.eps Figure 22. Access Time (tACC) vs. Output Loading 290489-25.eps Figure 23. IPP during Word Write Operation 290489-26 Figure 24. IPP during Page Buffer Write Operation SEE NEW DESIGN RECOMMENDATIONS 51 E 28F016SA 7.0 MECHANICAL SPECIFICATIONS FOR TSOP 290489-28.eps Figure 25. Mechanical Specifications of the 28F016SA 56-Lead TSOP Type 1 Package Family: Thin Small Outline Package Symbol Millimeters Minimum Nominal A A1 0.05 A2 0.965 0.995 1.025 b 0.100 0.150 0.200 c 0.115 0.125 0.135 D1 18.20 18.40 18.60 E 13.80 14.00 14.20 0.50 D 19.80 20.00 20.20 L 0.500 0.600 0.700 N 56 0 3 Y Z Notes 1.20 e 52 Maximum 5 0.100 0.150 0.250 0.350 SEE NEW DESIGN RECOMMENDATIONS E 8.0 28F016SA MECHANICAL SPECIFICATIONS FOR SSOP a E He R1 A2 b R2 L1 Detail A D A B e 1 Y C A1 See Detail A 0528_20 Figure 26. Mechanical Specifications of the 56-Lead SSOP Package Family: Shrink Small Outline Package Symbol Millimeters Minimum A Nominal Maximum 1.80 1.90 A1 0.47 0.52 0.57 A2 1.18 1.28 1.38 B 0.25 0.30 0.40 C 0.13 0.15 0.20 D 23.40 23.70 24.00 E 13.10 13.30 13.50 e1 He 0.80 15.70 N L1 Notes 16.00 16.30 56 0.45 0.50 a 2 3 4 b 3 3 5 R1 0.15 0.20 0.25 R2 0.15 0.20 0.25 Y 0.55 0.10 SEE NEW DESIGN RECOMMENDATIONS 53 E 28F016SA 9.0 DEVICE NOMENCLATURE AND ORDERING INFORMATION DA 2 8 F 0 1 6SA - 0 7 0 ACCESS SPEED DA = Commercial Temperature 56-Lead SSOP E = Commercial Temperature 56-Lead TSOP T = Extended Temperature 56-Lead SSOP 70 ns 100 ns 100 ns 0489_18 Valid Combinations Option Order Code VCC = 3.3V 10%, 50 pF Load VCC = 5.0V 10%, 100 pF Load VCC = 5.0V 5%, 30 pF Load 1 E28F016SA-070 E28F016SA-120 E28F016SA-080 E28F016SA-070 2 E28F016SA-100 E28F016SA-150 E28F016SA-100 3 DA28F016SA-070 DA28F016SA-120 DA28F016SA-080 4 DA28F016SA-100 DA28F016SA-150 DA28F016SA-100 5 DT28F016SA-100 DT28F016SA-150 DT28F016SA-150 54 DA28F016SA-070 DT28F016SA-150 SEE NEW DESIGN RECOMMENDATIONS E 28F016SA 10.0 ADDITIONAL INFORMATION Order Number Document/Tool 297372 16-Mbit Flash Product Family User's Manual 290608 Word-Wide FlashFileTM Memory Family 28F160S3, 28F320S3 datasheet 290609 Word-Wide FlashFileTM Memory Family 28F160S5, 28F320S5 datasheet 290598 Byte-Wide Smart 3 FlashFileTM Memory Family datasheet 290597 Byte-Wide Smart 5 FlashFileTM Memory Family datasheet 290429 28F008SA 8-Mbit FlashFileTM Memory Datasheet 292126 AP-377 16-Mbit Flash Product Family Software Drivers 28F016SA, 28F016SV, 28F016XS, 28F016XD 292144 AP-393 28F016SV Compatibility with 28F016SA 292159 AP-607 Multi-Site Layout Planning with Intel's Flash FileTM Components 297408 28F016SA/DD28F032SA Specification Update 297534 Small and Low-Cost Power Supply solution for Intel's Flash Memory Products (Technical Paper) 297508 FLASHBuilder Design Resource Tool NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel's World Wide Web home page at http://www.Intel.com for technical documentation and tools. SEE NEW DESIGN RECOMMENDATIONS 55