1.8V, 25-bit (1:1) or 14-bit (1:2) JEDEC-Compliant
Data Register with Parity
CY2SSTU32866
Rev 1.0, November 25, 2006 Page 1 of 24
2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 www.SpectraLinear.com
Features
• Operating frequency: DC to 500 MHz
• Supports DDRII SDRAM
• Two operations modes: 25 bit (1:1) and 14 bit (1:2)
• 1.8V operation
• Fully JEDEC-compliant (JESD 82-10)
• 96-ball FBGA
Functional Description
All clock and data inputs are compatible with the JEDEC
standard for SSTL_18. The control inputs are LVCMOS. All
outputs are 1.8-V CMOS drivers that have been optimized to
drive the DDR-II DIMM load. The CY2SSTU32866 operates
from a differential clock (CK and CK#). Data are registered at
the crossing of CK going high, and CK# going LOW.
The C0 input controls the pinout configuration of the 1:2 pinout
from A configuration (when LOW) to B configuration (when
HIGH). The C1 input controls the pinout configuration from
25-bit 1:1 (when LOW) to 14-bit 1:2 (when HIGH).
The device monitors both DCS# and CSR# inputs and will gate
the Qn outputs from changing states when both DCS# and
CSR# inputs are HIGH. If either DCS# or CSR# input is LOW,
the Qn outputs will function normally. The RESET# input has
priority over the DCS# and CSR# control and will force the
outputs LOW. If the DCS#-control functionality is not desired,
the CSR# input can be hardwired to ground, in which case the
set-up time requirement for DCS# would be the same as for
the other D data inputs.
The device supports low-power standby operation. When the
reset input (RESET#) is LOW, the differential input receivers
are disabled, and undriven (floating) data, clock, and reference
voltage (VREF) inputs are allowed. In addition, when RESET#
is LOW, all registers are reset and all outputs are forced LOW.
The LVCMOS RESET# and Cn inputs must always be held at
a valid logic HIGH or LOW level. To ensure defined outputs
from the register before a stable clock has been supplied,
RESET# must be held in the LOW state during power-up.
In the DDR-II RDIMM application, RESET# is specified to be
completely asynchronous with respect to CK and CK#.
Therefore, no timing relationship can be guaranteed between
the two. When entering reset, the register will be cleared and
the outputs will be driven low quickly, relative to the time to
disable the differential input receivers. However, when coming
out of reset, the register will become active quickly, relative to
the time to enable the differential input receivers.
Pin Configuration
1
2
34
5
6
A DCKE PP
O
VREF VDD QCKE NC
BD2D1
5
GND GND Q2 Q15
C
D3 D16 VDD VDD Q3 Q16
DDODTQERR
#
GND GND QODT NC
E D5 D17 VDD VDD Q5 Q17
F
D6 D1
8
GND GND Q6 Q18
G PAR
_
IN RST# VDD VDD C1 C0
H CK DCS# GND GND QCS# NC
J CK# CSR# VDD VDD ZOH ZOL
KD8D1
9
GND GND Q8 Q19
L D9 D20 VDD VDD Q9 Q20
M D10 D21 GND GND Q10 Q21
ND11D2
2
VDD VDD Q11 Q22
P
D12 D23 GND GND Q1
2
Q23
R
D13 D24 VDD VDD Q13 Q24
TD14D2
5
VREF VDD Q14 Q25
1
2
34
5
6
1
2
3
4
5
6
A
DCKE PP
O
VREF VDD QCKE
A
QCKEB
B
D2 N
C
GND GND Q2
A
Q2B
C
D3 N
C
VDD VDD Q3
A
Q3B
DDODTQERR
#
GND GND QODTA QODTB
ED
5
N
C
VDD VDD Q5
A
Q5B
F
D6 N
C
GND GND Q6
A
Q6B
G PAR_IN RST# VDD VDD C1 C0
H CK DCS# GND GND QCSA
#
QCSB#
J CK# CSR# VDD VDD ZOH ZOL
KD8N
C
GND GND Q8
A
Q8B
LD9N
C
VDD VDD Q9
A
Q9B
M
D10 N
C
GND GND Q10A Q10B
ND11N
C
VDD VDD Q11A Q11B
P
D12 N
C
GND GND Q12A Q12B
R
D13 N
C
VDD VDD Q13A Q13B
TD14N
C
VREF VDD Q14A Q14B
1
2
3
4
5
6
1
2
3
4
5
6
A
D1 PPO VREF VDD Q1
A
Q1B
BD
2
N
C
GND GND Q2
A
Q2B
C
D
3
N
C
VDD VDD Q3
A
Q3B
DD
4
QERR# GND GND Q4
A
Q4B
ED
5
N
C
VDD VDD Q5
A
Q5B
FD
6
N
C
GND GND Q6
A
Q6B
G PAR_IN RST# VDD VDD C1 C
0
H CK DCS# GND GND QCSA# QCSB#
J CK# CSR# VDD VDD ZOH ZOL
KD
8
N
C
GND GND Q8
A
Q8B
LD
9
N
C
VDD VDD Q9
A
Q9B
M
D1
0
N
C
GND GND Q10
A
Q10B
NDODTN
C
VDD VDD QODT
A
QODTB
P
D1
2
N
C
GND GND Q12
A
Q12B
R
D1
3
N
C
VDD VDD Q13
A
Q13B
TDCKEN
C
VREF VDD QCKEA QCKEB
1
2
3
4
5
6
1:1 Register C0 = 0, C1=0 1:2 Register A C0 = 0, C1=1 1:2 Register B C0 = 1, C1=1
CY2SSTU32866
Rev 1.0, November 25, 2006 Page 2 of 24
The CY2SSTV32866 accepts a parity bit from the memory
controller on its parity bit (PAR_IN) input, compares it with the
data received on the DIMM-independent D-inputs and
indicates whether a parity error has occurred on its open-drain
QERR# pin (active LOW). The convention is even parity, i.e.,
valid parity is defined as an even number of ones across the
DIMM-independent data inputs combined with the parity input
bit.
When used as a single device, the C0 and C1 inputs are tied
LOW. In this configuration, parity is checked on the PAR_IN
input which arrives one cycle after the input data to which it
applies. The partial-parity-out (PPO) and QERR# signals are
produced three cycles after the corresponding data inputs.
When used in pairs, the C0 input of the first register is tied
LOW and the C0 input of the second register is tied HIGH. The
C1 input of both registers are tied HIGH. Parity, which arrives
one cycle after the data input to which it applies, is checked on
the PAR_IN input of the first device. The PPO and QERR#
signals are produced on the second device three clock cycles
after the corresponding data inputs. The PPO output of the first
register is cascaded to the PAR_IN of the second register. The
QERR# output of the first register is left floating and the valid
error information is latched on the QERR# output of the
second register. If an error occurs and the QERR# output is
driven LOW, it stays latched LOW for two clock cycles or until
RESET# is driven LOW. The DIMM-dependent signals
(DCKE, DCS#, DODT, and CSR#) are not included in the
parity check computation.
Parity is calculated using Table 1.
Table 1. Parity Function Table
Inputs Outputs
RESET# DCS# CSR# CK CK#
Sum of inputs =
H (D1-25) PAR_IN PPO QERR#
HLXpn pn Even L L H
HLXpn pn Odd L H L
HLXpn pn Even H H L
HLXpn pn Odd H L H
HHLpn pn Even L L H
HHLpn pn Odd L H L
HHLpn pn Even H H L
HHLpn pn Odd H L H
HHHpn pn X X PPO0QERR#0
H X X L or H L or H X X PPO0QERR#0
LX or
Floating
X or
Floating
X or
Floating
X or
Floating
X or Floating X or
Floating
LH
Pin Definition
Pin Name
Pin Number
(C0 = 0, C1 = 0)
Pin Number
(C0 = 0, C1 = 1)
Pin Number
(C0 = 1, C1 = 1) Description
GND B3, B4, D3, D4, F3, F4,
H3, H4, K3, K4, M3, M4,
P3, P4
B3, B4, D3, D4, F3,
F4, H3, H4, K3, K4,
M3, M4, P3, P4
B3, B4, D3, D4, F3,
F4, H3, H4, K3, K4,
M3, M4, P3, P4
Ground
VDD A4, C3, C4, E3, E4, G3,
G4, J3, J4, L3, L4, N3,
N4, R3, R4, T4
A4, C3, C4, E3,
E4, G3, G4, J3, J4,
L3, L4, N3, N4, R3,
R4, T4
A4, C3, C4, E3,
E4, G3, G4, J3, J4,
L3, L4, N3, N4, R3,
R4, T4
Power Supply Voltage
VREF A3, T3 A3, T3 A3, T3 Input Reference Voltage
ZOH J5 J5 J5 Reserved
ZOL J6 J6 J6 Reserved
CK H1 H1 H1 Positive Master Clock
CK# J1 J1 J1 Negative Master Clock
C0 G6 G6 G6 Configuration control input
C1 G5 G5 G5 Configuration control input
CY2SSTU32866
Rev 1.0, November 25, 2006 Page 3 of 24
RESET# G2 G2 G2 Asynchronous reset – resets registers and
disables Vref data and clock differential input
receivers
CSR# J2 J2 J2 Chip Select – Disables D1-D24 when both CSR#
and DCS# are HIGH (VDD)
DCS# H2 H2 H2 Chip Select – Disables D1-D24 when both CSR#
and DCS# are HIGH (VDD)
D1 A1 Data input – clocked in on the crossing points of
CK and CK#
D2-3 B1, C1 B1, C1 B1, C1 Data input – clocked in on the crossing points of
CK and CK#
D4 D1 Data input – clocked in on the crossing points of
CK and CK#
D5, 6, 8, 9,
10
E1, F1, K1, L1, M1 E1, F1, K1, L1, M1 E1, F1, K1, L1, M1 Data input – clocked in on the crossing points of
CK and CK#
D11 N1 N1 Data input – clocked in on the crossing points of
CK and CK#
D12, 13 P1, R1 P1, R1 P1, R1 Data input – clocked in on the crossing points of
CK and CK#
D14 T1 T1 Data input – clocked in on the crossing points of
CK and CK#
D15-25 B2, C2, E2, F2, K2, L2,
M2, N2, P2, R2, T2
Data input – clocked in on the crossing points of
CK and CK#
DODT D1 D1 N1 The outputs of this register bit will not be
suspended by the DCS# and CSR# Control
DCKE A1 A1 T1 The outputs of this register bit will not be
suspended by the DCS# and CSR# Control
Q1A A5 Data Outputs that are suspended by the DCS#
and CSR# control
Q2A-3A B5, C5 B5, C5 B5, C5 Data Outputs that are suspended by the DCS#
and CSR# control
Q4A D5 Data Outputs that are suspended by the DCS#
and CSR# control
Q5A, 6A, 8A,
9A, 10A
E5, F5, K5, L5, M5 E5, F5, K5, L5, M5 E5, F5, K5, L5, M5 Data Outputs that are suspended by the DCS#
and CSR# control
Q11A N5 N5
Q12A, Q13A P5, R5 P5, R5 P5, R5
Q14A T5 T5 Data Outputs that are suspended by the DCS#
and CSR# control
Q1B A6 Data Outputs that are suspended by the DCS#
and CSR# control
Q2B-3B B6, C6 B6, C6 Data Outputs that are suspended by the DCS#
and CSR# control
Q4B D6 Data Outputs that are suspended by the DCS#
and CSR# control
Q5B, 6B, 8B,
9B, 10B,
E6, F6, K6, L6, M6 E6, F6, K6, L6, M6 Data Outputs that are suspended by the DCS#
and CSR# control
Q11B N6 Data Outputs that are suspended by the DCS#
and CSR# control
Pin Definition (continued)
Pin Name
Pin Number
(C0 = 0, C1 = 0)
Pin Number
(C0 = 0, C1 = 1)
Pin Number
(C0 = 1, C1 = 1) Description
CY2SSTU32866
Rev 1.0, November 25, 2006 Page 4 of 24
Q12B, 13B P6, R6 P6, R6 Data Outputs that are suspended by the DCS#
and CSR# control
Q14B T6 Data Outputs that are suspended by the DCS#
and CSR# control
Q15-25 B6, C6, E6, F6, K6, L6,
M6, N6, P6, R6, T6
Data Outputs that are suspended by the DCS#
and CSR# control
QCSA# H5 H5 H5 Data outputs that will not be suspended by the
DCS# and CSR# control
QCSB# H6 H6 Data outputs that will not be suspended by the
DCS# and CSR# control
QODTA D5 D5 N5 Data outputs that will not be suspended by the
DCS# and CSR# control
QODTB D6 N6 Data outputs that will not be suspended by the
DCS# and CSR# control
QCKEA A5 A5 T5 Data outputs that will not be suspended by the
DCS# and CSR# control
QCKEB A6 T6 Data outputs that will not be suspended by the
DCS# and CSR# control
PPO A2 A2 A2 Partial parity out – indicates odd parity of inputs
D1-D25
QERR# D2 D2 D2 Output error bit – generated one clock cycle after
the corresponding data output
PAR_IN G1 G1 G1 Parity input – arrives one clock cycle after the
corresponding data input
NC A6, D6, H6 B2, C2, E2, F2, K2,
L2, M2, N2, P2,
R2, T2
B2, C2, E2, F2, K2,
L2, M2, N2, P2,
R2, T2
No Connect Pins
Pin Definition (continued)
Pin Name
Pin Number
(C0 = 0, C1 = 0)
Pin Number
(C0 = 0, C1 = 1)
Pin Number
(C0 = 1, C1 = 1) Description
Table 2. Flip Flop Function Table
Inputs Outputs
RESET# DCS# CSR# CK CK# Dn, DODT, DCKE Qn QCS# QODT, QCKE
HL L pn pn LLLL
HL L pn pn HHLH
H L L L or H L or H X Q0 Q0 Q0
HL H pn pn LLLL
HL H pn pn HHLH
H L H L or H L or H X Q0 Q0 Q0
HH L pn pn LLHL
HH L pn pn HHHH
H H L L or H L or H X Q0 Q0 Q0
HH H pn pn LQ0HL
HH H pn pn HQ0HH
H H H L or H L or H X Q0 Q0 Q0
L X or Floating X or Floating X or Floating X or Floating X or Floating L L L
CY2SSTU32866
Rev 1.0, November 25, 2006 Page 5 of 24
DCLK
R
G2
RESET
Q2−Q3
,
Q5−Q6
,
Q8−Q2
5
J1
CLK
H1
CLK
Parity
Generator
22
22
D2
A2 PPO
QERR
D2−D3,
D5−D6,
D8−D25
D2−D3,
D5−D6,
D8−D25
LPS0
(internal node)
D2−D3,
D5−D6,
D8-D25 22
PAR_IN G1
1
0
22
R
CLK
2−Bit
Counter
A3, T3
VREF
0
1
C0 G6
C1 G5
LPS1
(internal node)
CE
DCLK
R
DCLK
R
DCLK
R
D
CLK
R
0
1
CE
Q
QQ
Q
Q
Figure 1. Parity logic Diagram for 1:1 register configuration (positive logic) C0=0, C1=0
CY2SSTU32866
Rev 1.0, November 25, 2006 Page 6 of 24
DCLK
R
G2
RESET
J1
CLK
H1
CLK
Parity
Generator
11
11
D2
A2 PPO
QERR
D2−D3,
D5−D6,
D8−D14
D2−D3,
D5−D6,
D8−D14
LPS0
(internal node)
D2−D3,
D5−D6,
D8-D14 11
PAR_IN G1
1
0
R
CLK
2−Bit
Counter
A3, T3
VREF
0
1
C0 G6
C1 G5
LPS1
(internal node)
CE
DCLK
R
DCLK
R
DCLK
R
D
CLK
R
0
1
CE
Q2A−Q3A
,
Q5A−Q6A
,
Q8A−Q14A
11
Q2B−Q3B
,
Q5B−Q6B
,
Q8B−Q14B
11
Q
QQQ
Q
Figure 2. Parity logic Diagram for 1:2 register-A configuration (positive logic) C0=0, C1=1
CY2SSTU32866
Rev 1.0, November 25, 2006 Page 7 of 24
DCLK
R
G2
RESET
J1
CLK
H1
CLK
Parity
Generator
11
11
D2
A2 PPO
QERR
D1−D6,
D8−D13
D1−D6,
D8−D13
LPS0
(internal node)
D1−D6,
D8-D13 11
PAR_IN G1
1
0
R
CLK
2−Bit
Counter
A3, T3
VREF
0
1
C0 G6
C1 G5
LPS1
(internal node)
CE
DCLK
R
DCLK
R
DCLK
R
D
CLK
R
0
1
CE
Q1A−Q6A
,
Q8A−Q13A
11
Q1B−Q6B
,
Q8B−Q13B
11
Q
QQQ
Q
Figure 3. Parity logic Diagram for 1:2 register-B configuration (positive logic) C0=1, C1=1
CY2SSTU32866
Rev 1.0, November 25, 2006 Page 8 of 24
(RESET switches from L to H)
CLK
D1−D25†
RESET
tsu
tpd
CLK to PPO
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
th
tsu th
tpdm, tpdmss
CLK to Q
DCS
CSR
CLK
Q1−Q25
PAR_IN†
n n + 1 n + 2
PPO
n + 3 n + 4
tPHL
CLK to QERR
QERR‡
tPHL, tPLH
CLK to QERR
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
tact
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
H, L, or X H or L
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
Data to QERR Latency
Figure 4. CY2SSTU32866 used as single device C0=0, C1=0, RST# Switchs L to H
CY2SSTU32866
Rev 1.0, November 25, 2006 Page 9 of 24
ÌÌÌÌÌ
Ì
ÌÌÌ
Ì
ÌÌÌÌÌ
ÌÌÌÌ
Ì
ÌÌ
Ì
ÌÌÌÌ
ÌÌÌ
Ì
Ì
Ì
ÌÌÌ
ÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇÇÇÇ
Ç
ÇÇÇÇÇÇÇÇÇÇÇÇ
Ç
ÇÇÇÇÇÇÇÇÇÇÇÇÇÇ
CLK
D1−D25
RESET
tsu
tpd
CLK to PPO
th
tsu th
tpdm, tpdmss
CLK to Q
DCS
CSR
CLK
Q1−Q25
PAR_IN
n n + 1 n + 2
PPO
n + 3 n + 4
QERR†
tPHL or tPLH
CLK to QERR
ÌÌÌ
Ì
Ì
Ì
ÌÌÌ
ÌÌÌÌ
Ì
ÌÌ
Ì
ÌÌÌÌ
Unknown input
event H or L
ÉÉÉÉ
ÉÉÉÉ
Output signal is dependent on
the prior unknown input event
Data to PPO Latency
Data to QERR Latency
ÇÇÇÇÇÇÇÇÇÇÇÇÇÇ
Ç
ÇÇÇÇÇÇÇÇÇÇÇÇ
Ç
ÇÇÇÇÇÇÇÇÇÇÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
Figure 5. CY2SSTU32866 used as single device, C0=0, C1=0, RST# being held high
CY2SSTU32866
Rev 1.0, November 25, 2006 Page 10 of 24
CLK†
D1−D25†
RESET
DCS†
CSR†
CLK†
Q1−Q25
PAR_IN†
PPO
QERR
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
tinact
tRPHL
RESET to Q
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
tRPHL
RESET to PPO
tRPLH
RESET to QERR
H, L, or X H or L
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Figure 6. CY2SSTU32866 used as single device, C0=0, C1=0, RST# switchs from H to L
CY2SSTU32866
Rev 1.0, November 25, 2006 Page 11 of 24
C0 = 0, C1 = 1 (RESET switches from L to H)
CLK
D1−D14†
RESET
tsu
tpd
CLK to PPO
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
th
tsu th
tpdm, tpdmss
CLK to Q
DCS
CSR
CLK
Q1−Q14
PAR_IN†
n n + 1 n + 2
PPO
n + 3 n + 4
tPHL
CLK to QERR
QERR‡
(not used)
tPHL, tPLH
CLK to QERR
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
tact
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
H, L, or X H or L
ÎÎÎÎÎ
ÎÎÎÎÎ
Data to QERR
Latency
Figure 7. CY2SSTU32866 used as pair, C0=0, C1=1, RST# switches from L to H
CY2SSTU32866
Rev 1.0, November 25, 2006 Page 12 of 24
ÉÉÉÉÉÉÉÉÉÉÉÉ
É
ÉÉÉÉÉÉÉÉÉÉ
É
ÉÉÉÉÉÉÉÉÉÉÉÉ
ÇÇÇÇ
Ç
ÇÇ
Ç
ÇÇÇÇ
ÇÇÇÇÇ
Ç
ÇÇÇ
Ç
ÇÇÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
Ç
Ç
Ç
ÇÇÇ
ÇÇÇÇ
Ç
ÇÇ
Ç
ÇÇÇÇ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇ
CLK
D1−D14
RESET
tsu
tpd
CLK to PPO
th
tsu th
tpdm, tpdmss
CLK to Q
DCS
CSR
CLK
Q1−Q14
PAR_IN
n n + 1 n + 2
PPO
n + 3 n + 4
QERR†
(not used)
tPHL or tPLH
CLK to QERR
ÉÉÉÉÉÉÉÉÉÉÉÉ
É
ÉÉÉÉÉÉÉÉÉÉ
É
ÉÉÉÉÉÉÉÉÉÉÉÉ
Unknown input
event H or L
ÇÇÇÇ
ÇÇÇÇ
ÉÉÉÉ
ÉÉÉÉ
Output signal is dependent on
the prior unknown input event
Data to QERR
Latency
Data to PPO
Latency
Figure 8. CY2SSTU32866 used as pair, C0=0, C1=1, RST# being held high
CY2SSTU32866
Rev 1.0, November 25, 2006 Page 13 of 24
CLK†
D1−D14†
RESET
DCS†
CSR†
CLK†
Q1−Q14
PAR_IN†
PPO
QERR
(not used)
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
tinact
tRPHL
RESET to Q
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
tRPHL
RESET to PPO
tRPLH
RESET to QERR
H, L, or X H or L
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Figure 9. CY2SSTU32866 used as pair, C0=0, C1=1, RST# switches from H to L
CY2SSTU32866
Rev 1.0, November 25, 2006 Page 14 of 24
CLK
D1−D14†
RESET
tsu
tpd
CLK to PPO
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
th
tsu th
tpdm, tpdmss
CLK to Q
DCS
CSR
CLK
Q1−Q14
PAR_IN†‡
n n + 1 n + 2
PPO
(not used)
n + 3 n + 4
tPHL
CLK to QERR
QERR§
tPHL, tPLH
CLK to QERR
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
tact
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
H, L, or X H or L
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Data to QERR Latency
Figure 10. CY2SSTU32866 used as pair, C0=1, C1=1, RST# switches from L to H
CY2SSTU32866
Rev 1.0, November 25, 2006 Page 15 of 24
ÉÉÉÉÉÉÉÉÉÉÉÉ
É
ÉÉÉÉÉÉÉÉÉÉ
É
ÉÉÉÉÉÉÉÉÉÉÉÉ
ÇÇÇÇ
Ç
ÇÇ
Ç
ÇÇÇÇ
ÇÇÇÇÇ
Ç
ÇÇÇ
Ç
ÇÇÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
Ç
Ç
Ç
ÇÇÇ
ÇÇÇÇ
Ç
ÇÇ
Ç
ÇÇÇÇ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇ
CLK
D1−D14
RESET
tsu
tpd
CLK to PPO
th
tsu th
tpdm, tpdmss
CLK to Q
DCS
CSR
CLK
Q1−Q14
PAR_IN
n n + 1 n + 2
PPO
n + 3 n + 4
QERR†
(not used)
tPHL or tPLH
CLK to QERR
ÉÉÉÉÉÉÉÉÉÉÉÉ
É
ÉÉÉÉÉÉÉÉÉÉ
É
ÉÉÉÉÉÉÉÉÉÉÉÉ
Unknown input
event H or L
ÇÇÇÇ
ÇÇÇÇ
ÉÉÉÉ
ÉÉÉÉ
Output signal is dependent on
the prior unknown input event
Data to QERR
Latency
Data to PPO
Latency
Figure 11. CY2SSTU32866 used as pair, C0=1, C1=1, RST# being held high
CY2SSTU32866
Rev 1.0, November 25, 2006 Page 16 of 24
C0 = 1, C1 = 1 (RESET switches from H to L)
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
CLK†
D1−D14†
RESET
DCS†
CSR†
CLK†
Q1−Q14
PAR_IN†
PPO
(not used)
QERR
tinact
tRPHL
RESET to Q
tRPHL
RESET to PPO
tRPLH
RESET to QERR
H, L, or X H or L
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
Figure 12. CY2SSTU32866 used as pair, C0=1, C1=1, RST# switches from H to L
CY2SSTU32866
Rev 1.0, November 25, 2006 Page 17 of 24
Absolute Maximum Conditions [1]
Parameter Description Condition Min. Max. Unit
TSStorage Temperature –65 150 C
VCC Supply Voltage Range –0.5 2.5 V
VIN Input Voltage Range[2, 3] –0.5 VDD + 0.5 V
VOUT Output Voltage Range[2, 3] –0.5 VDD + 0.5 V
IIK Input Clamp Current VO < 0 or VO > VDD –50 50 mA
IOK Output Clamp Current VO < 0 or VO > VDD –50 50 mA
IOContinuous Output Current VO = 0 to VDD –50 50 mA
ICCC Continuous Current through VDD/GND –100 100 mA
DC Electrical Specifications
Parameter Description Conditions Min. Max. Unit
TA(Com.) Ambient Operating Temp 0 70 C
VDD Operating Voltage 1.7 1.9 V
VREF Voltage Reference 0.49*VDD 0.51*VDD V
VTT Terminating Voltage VREF–40mV VREF+40mV V
VIInput Voltage 0 VDD V
IIInput Current VI = VDD or GND –5 5 PA
VIL AC Input Low Voltage Data, CSR#, and PAR_IN inputs – VREF – 250mV V
DC Input Low Voltage – VREF – 125mV V
VIH AC Input High Voltage VREF + 250mV – V
DC Input High Voltage VREF + 125mV – V
VIL Input Low Voltage RESET#, Cn 0.35 X VDD V
VIH Input High Voltage 0.65 X VDD V
VICR Input Low Voltage CK, CK# 0.675 1.125 V
VID Input Differential Voltage 600 – mV
VOL Output Low Voltage IOL = 100 PA, VCC = 1.7V to 1.9V – 0.2 V
IOL = 6 mA, VCC = 1.7V – 0.5 V
VOH Output High Voltage IOH = –100 PA, VCC = 1.7V to 1.9V VDD – 0.2 – V
IOH = –6 mA, VCC = 1.7V 1.2 – V
IOH Output High Current – –8 mA
IOL Output Low Current – 8 mA
IDD Static Standby Power
Supply Current
RESET# = GND, IO = 0, VDD = 1.9V 100 PA
Static Operating Power
Supply Current
RESET# = VDD, VI = VIH(AC) or VIL(AC),
IO = 0, VDD = 1.9V
40 mA
Notes:
1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. This value is limited to 2.5V (max.)
CY2SSTU32866
Rev 1.0, November 25, 2006 Page 18 of 24
IDDD Power Supply Current
Dynamic Operating Clock
Only
RESET# = VDD, VI = VIH(AC) or VIL(AC), CK,
CK# switching 50% duty cycle,
VDD = 1.8V
28 (typical) PA/MHz
Dynamic Operating per
each Data Input
RESET# = VDD, VI = VIH(AC) or VIL(AC), CK,
CK# switching 50% duty cycle,
VDD = 1.8V, 1 IO switching 1:1 configuration
18 (typical) PA/MHz
RESET# = VDD, VI = VIH(AC) or VIL(AC), CK,
CK# switching 50% duty cycle,
VDD = 1.8V, 1 IO switching 1:2 configuration
36 (typical) PA/MHz
Low Power Active Mode,
CLK only
RESET# = VDD, VI = VIH(AC) or VIL(AC), CK,
CK# switching 50% duty cycle,
VDD = 1.8V, CS Enabled
27 (typical) PA/MHz
Low Power Active Mode
per each Data Input
RESET# = VDD, VI = VIH(AC) or VIL(AC), CK,
CK# switching 50% duty cycle,
VDD = 1.8V, 1 IO switching 1:1 configuration,
CS Enabled
2 (typical) PA/MHz
RESET# = VDD, VI = VIH(AC) or VIL(AC), CK,
CK# switching 50% duty cycle,
VDD = 1.8V, 1 IO switching 1:2 configuration;
CS Enabled
2 (typical) PA/MHz
CIN Ci (Data and CSR#) VI = VREF ± 250mV 2.5 3.5 pF
Ci (CK and CK#) VIX = 0.9V, VID = 600 mV 2 3 pF
Ci (RESET#) VI= VDD or GND 2.5 pF
DC Electrical Specifications (continued)
Parameter Description Conditions Min. Max. Unit
AC Timing Specifications
Parameter Description Conditions Min. Max. Unit
FCLK Clock Frequency – 500 MHz
TWPulse Duration CK, CK# H or L 1 – ns
TACT[4] Differential Input Active time – 10 ns
TINACT[5] Differential Input Inactive time – 15 ns
TSU Set-up Time DSR# before crossing CK,CK#,
CSR = H
0.7 – ns
CSR# before crossing CK,CK#,
DCS = H
0.7 – ns
DCS# before crossing CK,CK#,
CSR = L
0.5 – ns
DODT, DCKE and data before
crossing CK,CK#, CK going
HIGH
0.5 – ns
PAR_IN after crossing CK,CK# 0.5 ns
THHold Time DCS#, DODT, DCKE and data
after crossing CK, CK#
0.5 – ns
PAR_IN after crossing CK, CK# 0.5 – ns
TPDM Propagation Delay single bit switching From CK, CK# crossing to Q 1.86 ns
TPDMSS Propagation Delay simultaneous
switching
From CK, CK# to Q -
simultaneous switching
1.87 ns
TPD Propagation Delay from Low to High From CK, CK# crossing to PPO 2.15 (typical) ns
Notes:
4. Data and VREF inputs must be low a minimum time of TACT max, after RESET# is taken HIGH.
5. Data, VREF and clock inputs must be held at valid levels (not floating) a minimum time of TINACT max after RESET# is taken LOW.
CY2SSTU32866
Rev 1.0, November 25, 2006 Page 19 of 24
TPLH Propagation Delay from Low to High From CK, CK# crossing to
QERR#
1.2 3 ns
TPHL Propagation Delay from Low to High 1 2.4 ns
TrPLH Propagation Delay from Low to High RESET# LOW to QERR# HIGH 3 (typical) ns
TrPHL Propagation Delay from High to Low RESET# LOW to Q, PPO LOW 3 ns
SLR Slew Rate Rising dv/dt_r (20 to 80%) 1 4 V/ns
Slew Rate Falling dv/dt_f (20 to 80%) 1 4 V/ns
dv/dt 'Delta between Rising/Falling Rates – 1 V/ns
AC Timing Specifications (continued)
Parameter Description Conditions Min. Max. Unit
Figure 13. Test Load for Timing Measurements #1
DUT VDD
CL= 30pF
TL= 350ps, 50:
RL= 1000:
RL= 1000:
Test Point
OUT
CK
CK
CK Inputs
RL= 100:
Test Point
Test Point
CL includes probe and jig capacitance
Figure 14. Active and Inactive Times
VDD/2 VDD/2
IDD
tact
tinact
90%
LVCMOS
RESET
VDD
0V
10%
IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA
Figure 15. Pulse Duration
tw
VICR VICR
Input VID
VIH
VIL
VID = 600mV
VIH = VREF + 250mV (AC Voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs.
VIL = VREF - 250mV ( AC voltage levels) for differential inputs. VIL = VDD for LVCMOS inputs
CY2SSTU32866
Rev 1.0, November 25, 2006 Page 20 of 24
Figure 16. Set-up and Hold Times
VICR VID
VREF VREF
Input
VIH
VIL
th
tsu
CK
CK
VID = 600mV
VREF = VDD/2
VIH = VREF + 250mV (AC Voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs.
VIL = VREF - 250mV ( AC voltage levels) for differential inputs. VIL = VDD for LVCMOS inputs
Figure 17. Propagation Delay
V
ICR V
ICR V
I(P-P)
V
TT V
TT V
OL
V
OH
tPHL
tPLH
CK
CK
Output
tPLH and tPHL are the same as tPD
Figure 18. Propagation Delay after RESET#
Output
tRPHL
VDD/2 VIH
VIL
VOH
VOL
VTT
LVCMOS RESET
Input
tPLH and tPHL are the same as tPD
VIH = VREF + 250mV (AC Voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs.
VIL = VREF - 250mV ( AC voltage levels) for differential inputs. VIL = VDD for LVCMOS inputs
DUT
VDD
CL= 10pF
RL= 50:
Test Point
OUT
Figure 19. Load Circuit - High to Low Slew Measurement
CL includes probe and jig capacitance
CY2SSTU32866
Rev 1.0, November 25, 2006 Page 21 of 24
Figure 20. High to Low Slew Rate Measurement
OUTPUT
dv_f
80%
20%
VOH
VOL
dt_f
CL includes probe and jig capacitance
Figure 21. Load Circuit, Low to High slew measurement
DUT
CL= 10pF RL= 50:
Test Point
OUT
Figure 22. Low to High Slew Rate Measurement
OUTPUT
VOH
VOL
80%
20%
dt_r
dv_r
Figure 23. Load Circuit - High to Low Slew Rate Measurement
DUT
VDD
CL= 10pF
RL= 1k:
Test Point
OUT
CL includes probe and jig capacitance
CY2SSTU32866
Rev 1.0, November 25, 2006 Page 22 of 24
Figure 24. Open drain output - Low to High transition with respect to reset inputs
Figure 25. Open drain output - High to Low transition with respect to clock inputs
VICR VICR
Inputs VI(P-P)
tPLH
VCC/2
VCC
VOL
Output
Timing
VICR VICR
Inputs VI(P-P)
tPLH
Output
Timing
0.15V 0V
VOH
Figure 26. Open drain output - High to Low transition with respect to clock inputs
DUT
CL= 5pF RL= 1K:
Test Point
OUT
CL includes probe and jig capacitance
Figure 27. Partial-parity-out Load Circuit
CY2SSTU32866
Rev 1.0, November 25, 2006 Page 23 of 24
VTT = VDD/2
tPLH and tPHL are the same as tPD
VI(P-P) = 600mV
Figure 28. Partial-parity-out ; propagation delay times with respect to clock
inputs
VICR VICR VI(P-P)
VTT VTT VOL
VOH
tPHL
tPLH
CK
CK
Output
VTT = VDD/2
tPLH and tPHL are the same as tPD
VIH = VREF + 250mV (AC Voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs.
VIL = VREF - 250mV ( AC voltage levels) for differential inputs. VIL = VDD for LVCMOS inputs
Figure 29. Partial-parity-out ; propagation delay times with respect to clock inputs
LVCMOS
Output
tPHL
VDD/2 VIH
VIL
VOH
VOL
VTT
RESET
INPUT
Rev 1.0, November 25, 2006 Page 24 of 24
CY2SSTU32866
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir-
cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in
normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other applica-
tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional
processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any
circuitry or specification without notice.
Package Drawing and Dimensions
Ordering Information
Part Number Package Type Product Flow
Lead Free
CY2SSTU32866BFXC 96-pin FBGA Commercial, 0q to 70qC
CY2SSTU32866BFXCT 96-pin FBGA – Tape and Reel Commercial, 0q to 70qC
A
1
A1 CORNER
0.80
0.80
Ø0.50±0.05(96X)
Ø0.25 M C A B
Ø0.05 M C
B
A
0.15(4X)
0.40±0.05
1.20 MAX
C
SEATING PLANE
0.53±0.05
0.25 C
0.15 C
A1 CORNER
TOP VIEW BOTTOM VIEW
234
4.00
12.00
B
C
D
E
F
65
465231
5.50±0.10
13.50±0.10
A
B
2.00
6.00
G
H
0.26
L
R
N
T
P
M
J
K
M
T
R
N
P
C
G
E
K
L
J
H
F
D
A
B
REFERENCE JEDEC MO-205
PKG. WEIGHT: 0.23 gms
13.50±0.10
5.50±0.10
DIMENSIONS IN MILLIMETERS
PART #
BF96A STANDARD PKG.
BP96A LEAD FREE PKG.
96-Ball FBGA (5.5 x 13.5 x 1.2 MM) BF96A
