Chip Card & Security ICs SLE 5532 SLE 5542 Intelligent 256-Byte EEPROM Preliminary Short Product Information June 2005 SLE 5532/42 Preliminary Short Product Information Ref.: SPI_SLE5532_0605.doc This document contains preliminary information on a new product under development. Details are subject to change without notice. Revision History: Current Version 2005-06-16 Previous Releases: Page Subjects (changes since last revision) Important: Further information is confidential and on request. Please contact: Infineon Technologies AG in Munich, Germany, Chip Card & Security ICs, Tel +49 (0)89 / 234-80000 Fax +49 (0)89 / 234-81000 E-Mail: security.chipcard.ics@infineon.com Published by Infineon Technologies AG, AIM CC Applications Group St.-Martin-Strasse, D-81541 Munchen (c) Infineon Technologies AG 2005 All Rights Reserved. To our valued customers We constantly strive to improve the quality of all our products and documentation. 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Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Preliminary SLE 5532 SLE 5542 Intelligent 256-Byte EEPROM with Write Protect Function SLE 5532 Intelligent 256-Byte EEPROM with Write Protect Function and Programmable Security Code (PSC) SLE 5542 Features M3 * 100% functional compatibility to SLE 4432/42 * 256 x 8-bit EEPROM organization - Irreversible byte-wise protection of lowest 32 addresses (Byte 0...31) - 32 x 1 bit organization of protection memory * Two-wire link protocol - Byte-wise addressing - End of processing indicated at data output * Contact configuration and Answer-to-Reset (synchronous transmission) in accordance to standard ISO/IEC 7816 * Sophisticated electrical characteristics - Ambient temperature TA -40 ... +80C for chip - Supply voltage 5 V 10 % - Supply current < 3 mA (typical 600 A) - EEPROM erase / write time 5 ms - ESD protection typical 4,000 V - EEPROM Endurance minimum 100,000 erase / write cycles1) - Data retention for minimum of 10 years1) * Advanced 1.2 m CMOS-technology optimised for security layout - EEPROM-cells protected by shield - Secure wiring for all security relevant signals - Shielding of deeper layers via metal - Sensory and logical security functions - No isolation on backside necessary Additional Feature of SLE 5542 * 1) Data can only be changed after entry of the correct 3-byte programmable security code Values are temperature dependent. Short Product Information 3/6 2005-06-16 Preliminary 1 SLE 5532 SLE 5542 Ordering and Packaging information Table 1 Ordering Information Type Package1) Remark Ordering Code SLE 5532 C Die (on Wafer) unsawn on request SLE 5532 D Die (on Wafer) sawn on request SLE 5532 M3 T-M3.2-6 SLE 5532 MFC3 S-MFC3.1-6-1 FCoSTM on request SLE 5542 C Die (on Wafer) unsawn on request SLE 5542 D Die (on Wafer) sawn on request SLE 5542 M3 T-M3.2-6 SLE 5542 MFC3 S-MFC3.1-6-1 on request on request FCoSTM on request Pin Description Figure 1 Pin Configuration Wire-bonded Module M3.2 (top view) Figure 2 Pin Configuration Module Flip Chip MFC3.1 (top view) 1) Available as a Module Flip Chip (MFC3), wire-bonded module (M3) for embedding in plastic cards or as a die on unsawn (C) / sawn wafer (D) for customer packaging Short Product Information 4/6 2005-06-16 Preliminary VCC GND SLE 5532 SLE 5542 RST CLK I/O Figure 3 Pad Configuration Die Table 2 Pin Definitions and Functions Card Contact Symbol Function C1 VCC Supply voltage C2 RST Control input (Reset Signal) C3 CLK Clock input C5 GND Ground C6 N.C. Not connected C7 I/O Bi-directional data line (open drain) Short Product Information SLE 5532 SLE 5542 5/6 2005-06-16 Preliminary 2 SLE 5532 SLE 5542 Circuit Description The memory is organized in a Main Memory of 256 byte. Each of the first 32 bytes of the Main Memory can be irreversibly protected against data change by writing the corresponding bit in the Protection Memory (32 bit). Dependent on the state of the protection bit the memory is read only (ROM) or may be erased and written again (EEPROM). Change of the manufacturer code is only possible by the chip manufacturer. SLE 5542 Change of data of the Main Memory and write a bit of the Protection Memory is only possible after a correct verification of the Programmable Security Code (PSC). I/O 224 byte Read Main Memory Update Main Memory Memory Write Protection Unprotected Data Memory 32 bit Protection Memory (PROM) Read Protection Memory Figure 4 32 byte Protectable Data memory Application ID Chip Coding Memory Overview SLE 5532 I/O 224 byte Read Main Memory Memory Write Protection Unprotected Data Memory Security Logic Programmable Security Code Error Counter Read Protection Memory Figure 5 Update Main Memory 32 bit Protection Memory (PROM) 32 byte Protectable Data memory Application ID Chip Coding Memory Overview SLE 5542 Short Product Information 6/6 2005-06-16