NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM * * * * * * * * * * * * Features * High Performance: Maximum Operating Speed CAS Latency PC166 (6K) PC133 (75B) 2 10 10 ns 3 6 7.5 ns * * * * * Single Pulsed RAS Interface Fully Synchronous to Positive Clock Edge Four Banks controlled by BA0/BA1 (Bank Select) Programmable CAS Latency: 2, 3 Programmable Burst Length: 1, 2, 4, 8 or full page Programmable Wrap: Sequential or Interleave Multiple Burst Read with Single Write Option Automatic and Controlled Precharge Command Dual Data Mask for byte control (x16) Auto Refresh (CBR) and Self Refresh Suspend Mode and Power Down Mode Standard Power operation Random Column Address every CK (1-N Rule) Single Power Supply, either 3.3V or 2.5V LVTTL compatible Packages: TSOP-Type II Lead-free & Halogen-free product available Description The NT5SV8M16DS, NT5SV8M16DT, NT5SE8M16DS and NT5EV8M16DT are four-bank Synchronous DRAMs organized as 2Mbit x 16 I/O x 4 Bank. These synchronous devices achieve high-speed data transfer rates of up to 166MHz by employing a pipeline chip architecture that synchronizes the output data to a system clock. operation. Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 166MHz is possible depending on burst length, CAS latency, and speed grade of the device. Auto Refresh (CBR) and Self Refresh operation are supported. The device is designed to comply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, and data input/output (I/O or DQ) circuits are synchronized with the positive edge of an externally supplied clock. RAS, CAS, WE, and CS are pulsed signals which are examined at the positive edge of each externally applied clock (CK). Internal chip operating modes are defined by combinations of these signals and a command decoder initiates the necessary timings for each operation. A fifteen bit address bus accepts address data in the conventional RAS/CAS multiplexing style. Twelve addresses (A0-A11) and two bank select addresses (BA0, BA1) are strobed with RAS. Nine column addresses (A0-A8) plus bank select addresses and A10 are strobed with CAS. Prior to any access operation, the CAS latency, burst length, and burst sequence must be programmed into the device by address inputs A0-A11, BA0, BA1 during a mode register set cycle. In addition, it is possible to program a multiple burst sequence with single write cycle for write through cache REV 1.0 May 9, 2005 1 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Ordering Information Organization Part Number Package NT5SV8M16DS-6K 400mil 54-PIN TSOP II Lead-Free NT5SV8M16DT-6K 400mil 54-PIN TSOP II NT5SV8M16DS-75B 400mil 54-PIN TSOP II Lead-Free 8M x 16 NT5SV8M16DT-75B 400mil 54-PIN TSOP II NT5SE8M16DS-6K 400mil 54-PIN TSOP II Lead-Free NT5SE8M16DT-6K 400mil 54-PIN TSOP II NT5SE8M16DS-75B 400mil 54-PIN TSOP II Lead-Free 8M x 16 NT5SE8M16DT-75B Speed Grade Clock Frequency CL-tRCD-tRP Power Notes Lead free packaging 166MHz-3-3-3 3.3V Lead free packaging 133MHz-3-3-3 Lead free packaging 166MHz-3-3-3 2.5V Lead free packaging 133MHz-3-3-3 400mil 54 PIN TSOP II CL = CAS Latency Lead-free products are also halogen-free Nanya Technology Corporation Hwa Ya Technology Park 669 Fu Hsing 3rd Rd., Kueishan, Taoyuan, 333, Taiwan, R.O.C. Tel: +886-3-328-1688 Please visit our home page for more information: www.nanya.com REV 1.0 May 9, 2005 2 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Pin Configuration - 54 pins 400 mill TSOPII Package <Top View > VDD 1 54 VSS DQ0 VDDQ DQ1 DQ2 2 3 4 5 53 52 51 50 DQ15 VSSQ DQ14 DQ13 VSSQ DQ3 DQ4 VDDQ DQ5 6 7 8 9 10 49 48 47 46 45 VDDQ DQ12 DQ11 VSSQ DQ10 DQ6 11 44 DQ9 VSSQ 12 43 VDDQ DQ7 VDD LDQM WE CAS RAS CS BA0 13 14 15 16 17 18 19 20 42 41 40 39 38 37 36 35 DQ8 VSS NC UDQM CK CKE NC A11 BA1 A10/AP A0 21 22 23 34 33 32 A9 A8 A7 A1 A2 24 25 31 30 A6 A5 A3 VDD 26 27 29 28 A4 VSS 54-pin Plastic TSOP(II) 400 mil REV 1.0 May 9, 2005 3 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Pin Description CK Clock Input DQ0-DQ15 Data Input/Output CKE (CKE0, CKE1) Clock Enable DQM, LDQM, UDQM Data Mask CS Chip Select VDD Power (+3.3V) RAS Row Address Strobe VSS Ground CAS Column Address Strobe VDDQ Power for DQs (+3.3V) WE Write Enable VSSQ Ground for DQs BA1, BA0 Bank Select NC No Connection A0 - A11 Address Inputs -- -- Input/Output Functional Description Symbol Type Polarity Function CK Input Positive Edge CKE, CKE0, CKE1 Input Active High Activates the CK signal when high and deactivates the CK signal when low. By deactivating the clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode. CS Input Active Low CS enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS, CAS, WE Input Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM. BA1, BA0 Input -- Selects which bank is to be active. The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. A0 - A11 Input -- During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A8 defines the column address (CA0-CA8), when sampled at the rising clock edge. A10 is used to invoke auto-precharge operation at the end of the burst read or write cycle. If A10 is high, auto-precharge is selected and BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled. During a Precharge command cycle, A10 is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If A10 is high, all banks will be precharged regardless of the state of BS. If A10 is low, then BA0 and BA1 are used to define which bank to precharge. DQ0 - DQ15 InputOutput -- Data Input/Output pins operate in the same manner as on conventional DRAMs. The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In x16 products, the LDQM and UDQM control the lower and upper byte I/O buffers, respectively. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output Active High enable. DQM low turns the output buffers on and DQM high turns them off. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if DQM is high. DQM LDQM UDQM Input VDD, VSS Supply -- Power and ground for the input buffers and the core logic. VDDQ VSSQ Supply -- Isolated power supply and ground for the output buffers to provide improved noise immunity. REV 1.0 May 9, 2005 4 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Block Diagram Column Decoder Row Decoder CKE Buffer CK Column Decoder Row Decoder CKE Cell Array Memory Bank 0 Cell Array Memory Bank 1 CK Buffer Sense Amplifiers WE DQX Column Decoder Row Decoder Row Decoder CAS Command Decoder CS DQ0 DQM Column Decoder RAS Data Input/Output Buffers Data Control Circuitry Mode Register Column Address Counter Refresh Counter BA1 BA0 A10 Sense Amplifiers Control Signal Generator Address Buffers (15) A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A11 Cell Array Memory Bank 2 Sense Amplifiers Cell Array Memory Bank 3 Sense Amplifiers Cell Array, per bank, for 4Mb x 16 DQ: 4096 Row x 512 Col x 16 DQ (DQ0-DQ15). REV 1.0 May 9, 2005 5 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Power On and Initialization The default power on state of the mode register is supplier specific and may be undefined. The following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. Like a conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined manner. During power on, all VDD and VDDQ pins must be built up simultaneously to the specified voltage when the input signals are held in the "NOP" state. The power on voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies. The CK signal must be started at the same time. After power on, an initial pause of 200s is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A minimum of two Auto Refresh cycles (CBR) are also required. These may be done before or after programming the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes. Programming the Mode Register For application flexibility, CAS latency, burst length, burst sequence, and operation type are user defined variables and must be programmed into the SDRAM Mode Register with a single Mode Register Set Command. Any content of the Mode Register can be altered by re-executing the Mode Register Set Command. If the user chooses to modify only a subset of the Mode Register variables, all four variables must be redefined when the Mode Register Set Command is issued. After initial power up, the Mode Register Set Command must be issued before read or write cycles may begin. All banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The Mode Register Set Command is activated by the low signals of RAS, CAS, CS, and WE at the positive edge of the clock. The address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command may be issued following the mode register set command once a delay equal to tRSC has elapsed. CAS Latency The CAS latency is a parameter that is used to define the delay from when a Read Command is registered on a rising clock edge to when the data from that Read Command becomes available at the outputs. The CAS latency is expressed in terms of clock cycles and can have a value of 2 or 3 cycles. The value of the CAS latency is determined by the speed grade of the device and the clock frequency that is used in the application. A table showing the relationship between the CAS latency, speed grade, and clock frequency appears in the Electrical Characteristics section of this document. Once the appropriate CAS latency has been selected it must be programmed into the mode register after power up, for an explanation of this procedure see Programming the Mode Register in the previous section. REV 1.0 May 9, 2005 6 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Mode Register Operation (Address Input For Mode Set) BA1 BA0 A11 A10 A9 A8 A7 A6 Operation Mode A5 A4 CAS Latency A3 A2 BT A1 Address Bus (Ax) A0 Burst Length Mode Register(Mx) Burst Type M3 Type 0 Sequential 1 Interleave Operation Mode M14 M13 M12 M11 M10 M9 M8 M7 Mode Burst Length 0 0 0 0 0 0 0 0 Normal 0 0 0 0 0 1 0 0 Multiple Burst with Single Write CAS Latency REV 1.0 May 9, 2005 Length M2 M1 M0 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 8 8 Sequential Interleave 0 1 1 M6 M5 M4 Latency 1 0 0 Reserved Reserved 0 0 0 Reserved 1 0 1 Reserved Reserved 0 0 1 Reserved 1 1 0 Reserved Reserved 0 1 0 2 1 1 1 Full Page 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved Reserved 7 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Burst Mode Operation Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). There are three parameters that define how the burst mode will operate. These parameters include burst sequence, burst length, and operation mode. The burst sequence and burst length are programmable, and are determined by address bits A0 - A3 during the Mode Register Set command. Operation mode is also programmable and is set by address bits A7 - A11, BA0, and BA1. The burst type is used to define the order in which the burst data will be delivered or stored to the SDRAM. Two types of burst sequences are supported, sequential and interleaved. See the table below. The burst length controls the number of bits that will be output after a Read Command, or the number of bits to be input after a Write Command. The burst length can be programmed to have values of 1, 2, 4, 8 and full page sequential burst. Burst operation mode can be normal operation or multiple burst with single write operation. Normal operation implies that the device will perform burst operations on both read and write cycles until the desired burst length is satisfied. Multiple burst with single write operation was added to support Write Through Cache operation. Here, the programmed burst length only applies to read cycles. All write cycles are single write operations when this mode is selected. Burst Length and Sequence Burst Length 2 4 8 256 (Full Page) Starting Address (A2 A1 A0) Sequential Addressing (decimal) Interleave Addressing (decimal) xx0 0, 1 0, 1 xx1 1, 0 1, 0 x00 0, 1, 2, 3 0, 1, 2, 3 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 x11 3, 0, 1, 2 3, 2, 1, 0 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 n= A0-A7 Cn, Cn1+2, Cn+3, C+4, ... Not supported Note: Page length is a function of I/O organization and column addressing. x16 organization (CA0-CA8); Page Length = 512 bits REV 1.0 May 9, 2005 8 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Bank Activate Command In relation to the operation of a fast page mode DRAM, the Bank Activate command correlates to a falling RAS signal. The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock. The Bank Select address BA0 - BA1 is used to select the desired bank. The row address A0 - A11 is used to determine which row to activate in the selected bank. The Bank Activate command must be applied before any Read or Write operation can be executed. The delay from when the Bank Activate command is applied to when the first read or write operation can begin must meet or exceed the RAS to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank Activate command can be applied to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active is specified as tRAS(max). Bank Activate Command Cycle (CAS Latency = 3, tRCD = 3) T0 CK T1 T2 T3 Tn Tn+1 Tn+2 Tn+3 .......... Bank A Col. Addr. Bank A Row Addr. ADDRESS .......... RAS-CAS delay (tRCD) COMMAND Bank A Activate NOP Bank B Row Addr. Bank A Row Addr. RAS - RAS delay time (tRRD) Write A with Auto Precharge NOP : "H" or "L" .......... Bank B Activate Bank A Activate NOP NOP RAS Cycle time (tRC) Bank Select The Bank Select inputs, BA0 and BA1, determine the bank to be used during a Bank Activate, Precharge, Read, or Write operation. Bank Selection Bits REV 1.0 May 9, 2005 BA0 BA1 Bank 0 0 Bank 0 1 0 Bank 1 0 1 Bank 2 1 1 Bank 3 9 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Read and Write Access Modes After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS high and CAS low at the clock's rising edge after the necessary RAS to CAS delay (tRCD). WE must also be defined at this time to determine whether the access cycle is a read operation (WE high), or a write operation (WE low). The address inputs determine the starting column address. The SDRAM provides a wide variety of fast access modes. A single Read or Write Command will initiate a serial read or write operation on successive clock cycles up to 133 MHz for PC133 or upto 166MHz for PC166 devices. The number of serial data bits for each access is equal to the burst length, which is programmed into the Mode Register. Similar to Page Mode of conventional DRAMs, a read or write cycle can not begin until the sense amplifiers latch the selected row address information. The refresh period (tREF) is what limits the number of random column accesses to an activated bank. A new burst access can be done even before the previous burst ends. The ability to interrupt a burst operation at every clock cycle is supported; this is referred to as the 1-N rule. When the previous burst is interrupted by another Read or Write Command, the remaining addresses are overridden by the new address. Precharging an active bank after each read or write operation is not necessary providing the same row is to be accessed again. To perform a read or write cycle to a different row within an activated bank, the bank must be precharged and a new Bank Activate command must be issued. When more than one bank is activated, interleaved (ping pong) bank Read or Write operations are possible. By using the programmed burst length and alternating the access and precharge operations between multiple banks, fast and seamless data access operation among many different pages can be realized. When multiple banks are activated, column to column interleave operation can be done between different pages. Finally, Read or Write Commands can be issued to the same bank or between active banks on every clock cycle. REV 1.0 May 9, 2005 10 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Burst Read Command The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst, the Mode Register sets the type of burst (sequential or interleave) and the burst length (1, 2, 4, 8). The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the CAS latency that is set in the Mode Register. Burst Read Operation (Burst Length = 4, CAS latency = 2, 3) CK COMMAND T0 READ A T1 NOP CAS latency = 2 tCK2, DQs T2 T3 T4 T5 T6 NOP NOP NOP NOP DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 CAS latency = 3 tCK3, DQs NOP T7 NOP T8 NOP DOUT A3 Read Interrupted by a Read A Burst Read may be interrupted before completion of the burst by another Read Command, with the only restriction being that the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the burst length. The data from the first Read Command continues to appear on the outputs until the CAS latency from the interrupting Read Command is satisfied, at this point the data from the interrupting Read Command appears. Read Interrupted by a Read (Burst Length = 4, CAS latency = 2, 3) CK COMMAND CAS latency = 2 tCK2, DQs CAS latency = 3 tCK3, DQs REV 1.0 May 9, 2005 T0 T1 READ A READ B T2 T3 T4 T5 T6 NOP NOP NOP NOP NOP DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3 DOUT A0 DOUT B0 DOUT B1 DOUT B2 T7 NOP T8 NOP DOUT B3 11 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Read Interrupted by a Write To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first or second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ bus. Minimum Read to Write Interval (Burst Length = 4, CAS latency = 2, 3) T0 CK CAS latency = 2 tCK2, DQs CAS latency = 3 tCK3, DQs T2 T3 T4 T5 T6 T7 T8 DQM high for CAS latency = 2 only. Required to mask first bit of READ data. DQM COMMAND T1 NOP READ A WRITE A NOP NOP NOP DIN A0 DIN A1 DIN A2 DIN A3 DIN A0 DIN A1 DIN A2 DIN A3 NOP NOP NOP : "H" or "L" REV 1.0 May 9, 2005 12 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Non-Minimum Read to Write Interval (Burst Length = 4, CAS latency = 2, 3) CK T0 T1 T2 T3 T4 T5 T6 T7 T8 DQM COMMAND READ A NOP WRITE A NOP NOP NOP NOP NOP NOP CL = 2: DQM needed to mask first, second bit of READ data. CAS latency = 2 tCK2, DQs DIN A0 DIN A1 DIN A2 DIN A3 CL = 3: DQM needed to mask first bit of READ data. CAS latency = 3 tCK3, DQs DIN A0 DIN A1 DIN A2 DIN A3 : DQM high for CAS latency = 2 : DQM high for CAS latency = 3 REV 1.0 May 9, 2005 13 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Burst Write Command The Burst Write command is initiated by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. There is no CAS latency required for burst write cycles. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored. Burst Write Operation (Burst Length = 4, CAS latency = 2, 3) T0 CK COMMAND NOP DQs T1 T2 WRITE A DIN A0 T3 T4 T5 NOP NOP NOP DIN A1 DIN A2 DIN A3 T6 NOP NOP T7 NOP T8 NOP : "H" or "L" The first data element and the Write are registered on the same clock edge. Extra data is masked. Write Interrupted by a Write A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. Write Interrupted by a Write (Burst Length = 4, CAS latency = 2, 3) CK COMMAND T0 NOP T1 T2 WRITE A WRITE B T3 T4 T5 T6 NOP NOP NOP DIN B1 DIN B2 DIN B3 NOP T7 NOP T8 NOP 1 CK Interval DQs REV 1.0 May 9, 2005 DIN A0 DIN B0 14 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Write Interrupted by a Read A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is registered. The DQs must be in the high impedance state at least one cycle before the interrupting read data appears on the outputs to avoid data contention. When the Read Command is registered, any residual data from the burst write cycle will be ignored. Data that is presented on the DQ pins before the Read Command is initiated will actually be written to the memory. Minimum Write to Read Interval (Burst Length = 4, CAS latency = 2, 3) T0 CK COMMAND CAS latency = 2 tCK2, DQs CAS latency = 3 tCK3, DQs : "H" or "L" REV 1.0 May 9, 2005 WRITE A DIN A0 T1 READ B T2 NOP T3 T4 T5 T6 NOP NOP NOP DOUT B0 DOUT B1 DOUT B2 DOUT B3 DOUT B0 DOUT B1 DOUT B2 DIN A0 Input data for the Write is masked. NOP T7 NOP T8 NOP DOUT B3 Input data must be removed from the DQs at least one clock cycle before the Read data appears on the outputs to avoid data contention. 15 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Non-Minimum Write to Read Interval (Burst Length = 4, CAS latency = 2, 3) T0 CK COMMAND CAS latency = 2 tCK2, DQs CAS latency = 3 tCK3, DQs : "H" or "L" REV 1.0 May 9, 2005 T1 WRITE A NOP DIN A0 DIN A1 DIN A0 DIN A1 T2 READ B T3 T4 NOP NOP DOUT B0 Input data for the Write is masked. T5 T6 NOP NOP T7 NOP DOUT B1 DOUT B2 DOUT B3 DOUT B0 DOUT B1 DOUT B2 T8 NOP DOUT B3 Input data must be removed from the DQs at least one clock cycle before the Read data appears on the outputs to avoid data contention. 16 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Auto-Precharge Operation Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge Command or the auto-precharge function. When a Read or a Write Command is given to the SDRAM, the CAS timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the Read or Write Command is issued, then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence. If A10 is high when the Read or Write Command is issued, then the auto-precharge function is engaged. During auto-precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge before all burst read cycles have been completed. Regardless of burst length, the precharge will begin (CAS latency - 1) clocks prior to the last data output. Auto-precharge can also be implemented during Write commands. A Read or Write Command without auto-precharge can be terminated in the midst of a burst operation. However, a Read or Write Command with auto-precharge cannot be interrupted by a command to the same bank. Therefore use of a Read, Write, or Precharge Command to the same bank is prohibited during a read or write cycle with auto-precharge until the entire burst operation is completed. Once the precharge operation has started the bank cannot be reactivated until the Precharge time (tRP) has been satisfied. When using the Auto-precharge Command, the interval between the Bank Activate Command and the beginning of the internal precharge operation must satisfy tRAS(min). If this interval does not satisfy tRAS(min) then tRCD must be extended. Burst Read with Auto-Precharge (Burst Length = 1, CAS Latency = 2, 3) T0 CK COMMAND READ A Auto-Precharge CAS latency = 2 tCK2, DQs CAS latency = 3 tCK3, DQs T1 NOP T2 T3 NOP T4 NOP NOP T5 T6 NOP NOP T7 NOP T8 NOP * tRP DOUT A0 * tRP DOUT A0 *Bank can be reactivated at completion of t RP. tRP is a function of clock cycle time and speed sort. Begin Auto-precharge See the Clock Frequency and Latency table. REV 1.0 May 9, 2005 17 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Burst Read with Auto-Precharge (Burst Length = 2, CAS Latency = 2, 3) CK COMMAND T0 T1 READ A Auto-Precharge NOP T2 NOP T3 T4 tCK2, DQs DOUT A0 NOP NOP NOP NOP T7 NOP T8 NOP DOUT A1 * tRP CAS latency = 3 tCK3, DQs T6 * tRP CAS latency = 2 T5 DOUT A0 DOUT A1 * Begin Auto-precharge Bank can be reactivated at completion of tRP. tRP is a function of clock cycle time and speed sort. See the Clock Frequency and Latency table. Burst Read with Auto-Precharge (Burst Length = 4, CAS Latency = 2, 3) CK COMMAND T0 READ A Auto-Precharge T1 NOP T2 NOP T3 T4 NOP NOP DOUT A0 DOUT A1 DOUT A2 NOP NOP DOUT A0 DOUT A1 T7 NOP T8 NOP * DOUT A3 * tRP CAS latency = 3 tCK3, DQs T6 tRP CAS latency = 2 tCK2, DQs T5 DOUT A2 DOUT A3 *Bank can be reactivated at completion of t RP. tRP is a function of clock cycle time and speed sort. Begin Auto-precharge See the Clock Frequency and Latency table. REV 1.0 May 9, 2005 18 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Although a Read Command with auto-precharge can not be interrupted by a command to the same bank, it can be interrupted by a Read or Write Command to a different bank. If the command is issued before auto-precharge begins then the precharge function will begin with the new command. The bank being auto-precharged may be reactivated after the delay tRP. Burst Read with Auto-Precharge Interrupted by Read (Burst Length = 4, CAS Latency = 2, 3) CK COMMAND T0 READ A Auto-Precharge T1 NOP T2 READ B T3 T4 NOP NOP tCK2, DQs DOUT A0 DOUT A1 tCK3, DQs T7 NOP NOP NOP DOUT B0 DOUT B1 DOUT B2 DOUT B3 DOUT B1 DOUT B2 T8 NOP * tRP CAS latency = 3 T6 * tRP CAS latency = 2 T5 DOUT A0 DOUT A1 DOUT B0 DOUT B3 can be reactivated at completion of t . * Bank t is a function of clock cycle time and speed sort. RP RP See the Clock Frequency and Latency table. If interrupting a Read Command with auto-precharge with a Write Command, DQM must be used to avoid DQ contention. Burst Read with Auto-Precharge Interrupted by Write (Burst Length = 8, CAS Latency = 2) CK COMMAND T0 READ A Auto-Precharge T1 NOP T2 NOP T3 NOP T4 WRITE B T6 NOP DOUT A0 DIN B0 NOP T7 T8 NOP NOP DIN B3 DIN B4 * tRP CAS latency = 2 tCK2, DQs T5 DIN B1 DIN B2 DQM can be reactivated at completion of t . * Bank t is a function of clock cycle time and speed sort. RP RP . See the Clock Frequency and Latency table. REV 1.0 May 9, 2005 19 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The bank undergoing autoprecharge cannot be reactivated until tDAL, Data-in to Active delay, is satisfied. Burst Write with Auto-Precharge T0 CK COMMAND T1 WRITE A Auto-Precharge T2 NOP T3 NOP tCK2, DQs DIN A0 (Burst Length = 2, CAS Latency = 2, 3) T5 T6 T7 T8 NOP NOP NOP NOP * * tDAL DIN A0 NOP DIN A1 CAS latency = 3 tCK3, DQs NOP tDAL CAS latency = 2 T4 DIN A1 can be reactivated at completion of t . *Bank t is a function of clock cycle time and speed sort. DAL DAL See the Clock Frequency and Latency table. Similar to the Read Command, a Write Command with auto-precharge can not be interrupted by a command to the same bank. It can be interrupted by a Read or Write Command to a different bank, however. The interrupting command will terminate the write. The bank undergoing auto-precharge can not be reactivated until tDAL is satisfied. Burst Write with Auto-Precharge Interrupted by Write T0 T1 T2 T3 T4 (Burst Length = 4, CAS Latency = 3) T6 T7 T8 T5 CK COMMAND WRITE A Auto-Precharge NOP WRITE B NOP DIN A0 DIN A1 DIN B0 NOP NOP NOP NOP * tDAL CAS latency = 3 tCK3, DQs NOP DIN B1 DIN B2 DIN B3 can be reactivated at completion of t . * Bank t is a function of clock cycle time and speed sort. DAL DAL See the Clock Frequency and Latency table. REV 1.0 May 9, 2005 20 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Burst Write with Auto-Precharge Interrupted by Read T0 CK COMMAND T1 WRITE A NOP Auto-Precharge T2 T3 NOP T4 READ B NOP NOP NOP DIN A0 DIN A1 DIN A2 NOP NOP * tDAL CAS latency = 3 tCK3, DQs (Burst Length = 4, CAS Latency = 3) T6 T7 T8 T5 DOUT B0 DOUT B1 DOUT B2 * Bank A can be reactivated at completion of tDAL. tDAL is a function of clock cycle time and speed sort. See the Clock Frequency and Latency table. Precharge Command The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered when CS, RAS, and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank separately or all banks simultaneously. Three address bits, A10, BA0, and BA1, are used to define which bank(s) is to be precharged when the command is issued. Bank Selection for Precharge by Address Bits A10 Bank Select Precharged Bank(s) LOW BA0, BA1 Single bank defined by BA0, BA1 HIGH DON'T CARE All Banks For read cycles, the Precharge Command may be applied (CAS latency - 1) prior to the last data output. For write cycles, a delay must be satisfied from the start of the last burst write cycle until the Precharge Command can be issued. This delay is known as tDPL, Data-in to Precharge delay. After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Precharge time (tRP). REV 1.0 May 9, 2005 21 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Burst Read Followed by the Precharge Command (Burst Length = 4, CAS Latency = 3) CK COMMAND T0 READ Ax0 T1 NOP T2 NOP T3 T4 NOP T5 NOP T6 Precharge A NOP tRP CAS latency = 3 DOUT Ax0 tCK2, DQs DOUT Ax1 DOUT Ax2 * T7 NOP T8 NOP * DOUT Ax3 Bank A can be reactivated at completion of tRP. tRP is a function of clock cycle and speed sort. Burst Write Followed by the Precharge Command (Burst Length = 2, CAS Latency = 2) CK COMMAND T0 NOP T1 Activate Bank Ax T2 NOP T3 T4 T5 NOP WRITE Ax0 T6 NOP Precharge A T7 NOP tRP tDPL T8 NOP * CAS latency = 2 tCK2, DQs DIN Ax0 DIN Ax1 can be reactivated at completion of t . * Bank t and t are functions of clock cycle and speed sort. RP DPL RP See the Clock Frequency and Latency table. REV 1.0 May 9, 2005 22 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Precharge Termination The Precharge Command may be used to terminate either a burst read or burst write operation. When the Precharge command is issued, the burst operation is terminated and bank precharge begins. For burst read operations, valid data will continue to appear on the data bus as a function of CAS Latency. Burst Read Interrupted by Precharge (Burst Length = 8, CAS Latency = 2, 3) CK COMMAND T0 READ Ax0 T1 NOP T2 NOP T3 NOP T4 T5 T6 NOP Precharge A NOP tCK2, DQs DOUT Ax0 DOUT Ax1 DOUT Ax2 tCK3, DQs DOUT Ax0 DOUT Ax1 * REV 1.0 May 9, 2005 NOP DOUT Ax3 * tRP CAS latency = 3 NOP T8 * tRP CAS latency = 2 T7 DOUT Ax2 DOUT Ax3 Bank A can be reactivated at completion of tRP. tRP is a function of clock cycle time and speed sort. See the Clock Frequency and Latency table. 23 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Burst write operations will be terminated by the Precharge command. The last write data that will be properly stored in the device is that write data that is presented to the device a number of clock cycles prior to the Precharge command equal to the Data-in to Precharge delay, tDPL. Precharge Termination of a Burst Write (Burst Length = 8, CAS Latency = 2, 3) CK COMMAND T0 NOP T1 NOP T2 WRITE Ax0 T3 T4 NOP NOP T5 T6 NOP Precharge A T7 NOP T8 NOP DQM tDPL CAS latency = 2 tCK2, DQs DIN Ax0 DIN Ax1 DIN Ax2 tDPL CAS latency = 3 tCK3, DQs DIN Ax0 DIN Ax1 DIN Ax2 tDPL is an asynchronous timing and may be completed in one or two clock cycles depending on clock cycle time. REV 1.0 May 9, 2005 24 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Automatic Refresh Command (CAS before RAS Refresh) When CS, RAS, and CAS are held low with CKE and WE high at the rising edge of the clock, the chip enters the Automatic Refresh mode (CBR). All banks of the SDRAM must be precharged and idle for a minimum of the Precharge time (tRP) before the Auto Refresh Command (CBR) can be applied. An address counter, internal to the device provides the address during the refresh cycle. No control of the external address pins is required once this cycle has started. When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the Auto Refresh Command (CBR) and the next Activate Command or subsequent Auto Refresh Command must be greater than or equal to the RAS cycle time (tRC). Self Refresh Command The SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command is defined by having CS, RAS, CAS, and CKE held low with WE high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The user may halt the external clock while the device is in Self Refresh mode, however, the clock must be restarted before the device can exit Self Refresh operation. Once the clock is cycling, the device will exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the device exits Self Refresh Operation and before the next command can be issued. This delay is equal to the RAS cycle time (tRC) plus the Self Refresh exit time (tSREX). REV 1.0 May 9, 2005 25 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Power Down Mode In order to reduce standby power consumption, two power down modes are available: Precharge and Active Power Down mode. To enter Precharge Power Down mode, all banks must be precharged and the necessary precharge delay (tRP) must occur before the SDRAM can enter the power down mode. If a bank is activated but not performing a Read or Write operation, Active Power Down mode will be entered. (Issuing a Power Down Mode Command when the device is performing a Read or Write operation causes the device to enter Clock Suspend mode. See the following Clock Suspend section.) Once the Power Down mode is initiated by holding CKE low, all of the receiver circuits except CKE are gated off. The Power Down mode does not perform any refresh operations, therefore the device can't remain in Power Down mode longer than the Refresh period (tREF) of the device. The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command (or Device Deselect Command) is required on the next rising clock edge. Power Down Mode Exit Timing Tm Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tm+6 Tm+7 Tm+ 8 COMMAND NOP NOP NOP NOP NOP CK tCK CKE tCES(min) COMMAND NOP : "H" or "L" REV 1.0 May 9, 2005 26 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Data Mask The SDRAM has a Data Mask function that can be used in conjunction with data read and write cycles. When the Data Mask is activated (DQM high) during a write cycle, the write operation is prohibited immediately (zero clock latency). If the Data Mask is activated during a read cycle, the data outputs are disabled and become high impedance after a two-clock delay, independent of CAS latency. Data Mask Activated during a Read Cycle (Burst Length = 4, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK DQM COMMAND NOP READ A DQs NOP NOP DOUT A0 NOP DOUT A1 NOP NOP NOP NOP A two-clock delay before the DQs become Hi-Z : "H" or "L" No Operation Command The No Operation Command should be used in cases when the SDRAM is in an idle or a wait state. The purpose of the No Operation Command is to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle. Deselect Command The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought high, the RAS, CAS, and WE signals become don't cares. REV 1.0 May 9, 2005 27 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Clock Suspend Mode During normal access mode, CKE is held high, enabling the clock. When CKE is registered low while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends or "freezes" any clocked operation that was currently being executed. There is a one-clock delay between the registration of CKE low and the time at which the SDRAM's operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when Clock Suspend mode is exited. When the operation of the SDRAM is suspended during the execution of a Burst Read operation, the last valid data output onto the DQ pins will be actively held valid until Clock Suspend mode is exited. Clock Suspend during a Read Cycle T0 CK T1 T2 T3 T4 T5 (Burst Length = 4, CAS Latency = 2) T6 T7 T8 CKE A one clock delay to exit the Suspend command A one clock delay before suspend operation starts COMMAND NOP READ A NOP DQs NOP NOP DOUT A0 DOUT A2 DOUT A1 : "H" or "L" NOP DOUT element at the DQs when the suspend operation starts is held valid If Clock Suspend mode is initiated during a burst write operation, the input data is masked and is ignored until the Clock Suspend mode is exited. Clock Suspend during a Write Cycle (Burst Length = 4, CAS Latency = 2) T0 CK T1 T2 T3 T4 T5 T6 CKE T7 T8 A one clock delay to exit the Suspend command A one clock delay before suspend operation starts COMMAND DQs : "H" or "L" REV 1.0 May 9, 2005 NOP WRITE A DIN A0 NOP NOP NOP DIN A1 DIN A2 DIN A3 NOP DIN is masked during the Clock Suspend Period 28 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Command Truth Table (See note 1) CKE Function Device State Previous Cycle Current Cycle CS RAS CAS WE DQM BA0, BA1 , A11, A9-A0 A10 Notes Mode Register Set Idle H X L L L L X Auto (CBR) Refresh Idle H H L L L H X X X X Entry Self Refresh Idle H L L L L H X X X X Exit Self Refresh Idle (SelfRefresh) L H X X X X Single Bank Precharge See Current State Table H Precharge all Banks See Current State Table Bank Activate Idle Write Active H X L H L L X BS L Column 2 Write with Auto-Precharge Active H X L H L L X BS H Column 2 Read Active H X L H L H X BS L Column 2 Read with Auto-Precharge Active H X L H L H X BS H Column 2 Reserved OP Code H X X X L H H H X L L H L X BS L X H X L L H L X X H X H X L L H H X BS Row Address 2 2 H X L H H L X X X X No Operation Any H X L H H H X X X X Device Deselect Any H X H X X X X X X X Clock Suspend Mode Entry Active H L X X X X X X X X Clock Suspend Mode Exit Active L H X X X X X X X X Data Write/Output Enable Active H X X X X X L X X X Data Mask/Output Disable Active H X X X X X H X X X Power Down Mode Entry Idle/Active H L H X X X L H H H X X X X 6, 7 Power Down Mode Exit Any (Power Down) L H H X X X L H H H X X X X 6, 7 4 5 1. All of the SDRAM operations are defined by states of CS, WE, RAS, CAS, and DQM at the positive rising edge of the clock. Refer to the Current State Truth Table. 2. Bank Select (BA0, BA1): BA0, BA1 = 0,0 selects bank 0; BA0, BA1 = 1,0 selects bank 1; BA0, BA1 = 0,1 selects bank 2; BA0, BA1 = 1,1 selects bank 3. 3. Not applicable. 4. During normal access mode, CKE is held high and CK is enabled. When it is low, it freezes the internal clock and extends data Read and Write operations. One clock delay is required for mode entry and exit. 5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the data outputs are disabled and become high impedance after a two-clock delay. DQM also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency). 6. All banks must be precharged before entering the Power Down Mode. (If this command is issued during a burst operation, the device state will be Clock Suspend Mode.) The Power Down Mode does not perform any refresh operations; therefore the device can't remain in this mode longer than the Refresh period (tREF) of the device. One clock delay is required for mode entry and exit. 7. A No Operation or Device Deselect Command is required on the next clock edge following CKE going high. REV 1.0 May 9, 2005 29 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Clock Enable (CKE) Truth Table CKE Current State Self Refresh Power Down All Banks Idle Any State other than listed above Command Action Notes Previous Cycle Current Cycle CS RAS CAS WE BA0, BA1 A11 - A0 H X X X X X X X INVALID 1 L H H X X X X X Exit Self Refresh with Device Deselect 2 L H L H H H X X Exit Self Refresh with No Operation 2 L H L H H L X X ILLEGAL 2 L H L H L X X X ILLEGAL 2 L H L L X X X X ILLEGAL 2 L L X X X X X X Maintain Self Refresh H X X X X X X X INVALID 1 L H H X X X X X Power Down mode exit, all banks idle 2 L H L X X X X X ILLEGAL 2 L L X X X X X X Maintain Power Down Mode H H H X X X H H L H X X H H L L H X H H L L L H H H L L L L H L H X X X 3 Refer to the Idle State section of the Current State Truth Table 3 3 X X OP Code CBR Refresh Mode Register Set 4 3 Refer to the Idle State section of the Current State Truth Table H L L H X X H L L L H X H L L L L H H L L L L L L X X X X X X X Power Down H H X X X X X X Refer to operations in the Current State Truth Table H L X X X X X X Begin Clock Suspend next cycle L H X X X X X X Exit Clock Suspend next cycle L L X X X X X X Maintain Clock Suspend 3 3 X X OP Code Entry Self Refresh 4 Mode Register Set 4 5 1. For the given Current State CKE must be low in the previous cycle. 2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE (tCES) must be satisfied. When exiting power down mode, a NOP command (or Device Deselect Command) is required on the first rising clock after CKE goes high (see page 26). 3. The address inputs depend on the command that is issued. See the Idle State section of the Current State Truth Table for more information. 4. The Precharge Power Down Mode, the Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state. 5. Must be a legal command as defined in the Current State Truth Table. REV 1.0 May 9, 2005 30 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Current State Truth Table Current State Idle Row Active Read Write (Part 1 of 3)(See note 1) Command CS RAS CAS WE BA0,BA1 A11 - A0 OP Code Action Description Mode Register Set Set the Mode Register X Auto or Self Refresh Start Auto or Self Refresh X Precharge Notes L L L L L L L H X L L H L BS L L H H BS L H L L BS Column Write w/o Precharge ILLEGAL 4 L H L H BS Column Read w/o Precharge ILLEGAL 4 No Operation Row Address Bank Activate 2 2, 3 No Operation Activate the specified bank and row L H H H X X No Operation H X X X X X Device Deselect No Operation or Power Down L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge Precharge 6 L L H H BS ILLEGAL 4 L H L L BS Column Write Start Write; Determine if Auto Precharge 7, 8 L H L H BS Column Read Start Read; Determine if Auto Precharge 7, 8 OP Code Row Address Bank Activate L H H H X X No Operation No Operation H X X X X X Device Deselect No Operation L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge L L H H BS L H L L BS Column L H L H BS Column L H H H X X H X X X X L L L L L L L H X L L H L BS L L H H BS L H L L BS Column L H L H BS Column L H H H X X H X X X X X Device Deselect Continue the Burst OP Code Row Address Bank Activate X Write Terminate Burst; Start the Precharge ILLEGAL 8, 9 8, 9 Read Terminate Burst; Start a new Read cycle No Operation Continue the Burst Device Deselect Continue the Burst ILLEGAL X Auto or Self Refresh ILLEGAL X Precharge Row Address Bank Activate Write 4 Terminate Burst; Start the Write cycle Mode Register Set OP Code 5 Terminate Burst; Start the Precharge ILLEGAL 4 Terminate Burst; Start a new Write cycle 8, 9 Read Terminate Burst; Start the Read cycle 8, 9 No Operation Continue the Burst 1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is being applied to. 2. All Banks must be idle; otherwise, it is an illegal action. 3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is entered. 4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation. 6. The minimum and maximum Active time (tRAS) must be satisfied. 7. The RAS to CAS Delay (tRCD) must occur before the command is given. 8. Column address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied. REV 1.0 May 9, 2005 31 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Current State Truth Table Current State Read with Auto Precharge Write with Auto Precharge Precharging Row Activating (Part 2 of 3)(See note 1) Command CS RAS CAS WE BA0,BA1 A11 - A0 OP Code Action Description Notes L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge L L H H BS L H L L BS Column Write ILLEGAL 4 L H L H BS Column Read ILLEGAL 4 Row Address Bank Activate ILLEGAL 4 ILLEGAL 4 L H H H X X No Operation Continue the Burst H X X X X X Device Deselect Continue the Burst L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge L L H H BS L H L L BS Column Write ILLEGAL 4 L H L H BS Column Read ILLEGAL 4 OP Code Row Address Bank Activate ILLEGAL 4 ILLEGAL 4 L H H H X X No Operation Continue the Burst H X X X X X Device Deselect Continue the Burst L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge No Operation; Bank(s) idle after tRP L L H H BS L H L L BS Column Write ILLEGAL 4 L H L H BS Column Read ILLEGAL 4 OP Code Row Address Bank Activate ILLEGAL 4 L H H H X X No Operation No Operation; Bank(s) idle after tRP H X X X X X Device Deselect No Operation; Bank(s) idle after tRP L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge L L H H BS L H L L BS Column Write ILLEGAL 4 L H L H BS Column Read ILLEGAL 4 L H H H X X No Operation No Operation; Row Active after tRCD H X X X X X Device Deselect No Operation; Row Active after tRCD OP Code Row Address Bank Activate ILLEGAL 4 ILLEGAL 4, 10 1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is being applied to. 2. All Banks must be idle; otherwise, it is an illegal action. 3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is entered. 4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation. 6. The minimum and maximum Active time (tRAS) must be satisfied. 7. The RAS to CAS Delay (tRCD) must occur before the command is given. 8. Column address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied. REV 1.0 May 9, 2005 32 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Current State Truth Table Current State Write Recovering Write Recovering with Auto Precharge Refreshing Mode Register Accessing (Part 3 of 3)(See note 1) Command CS RAS CAS WE BA0,BA1 A11 - A0 OP Code Action Description Notes L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge L L H H BS L H L L BS Column Write Start Write; Determine if Auto Precharge 9 L H L H BS Column Read Start Read; Determine if Auto Precharge 9 Row Address Bank Activate ILLEGAL 4 ILLEGAL 4 L H H H X X No Operation No Operation; Row Active after tDPL H X X X X X Device Deselect No Operation; Row Active after tDPL L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge L L H H BS L H L L BS Column L H L H BS Column L H H H X X H X X X X L L L L L L L H X L L H L BS L L H H BS L H L L BS Column Write ILLEGAL L H L H BS Column Read ILLEGAL No Operation; Idle after tRC OP Code ILLEGAL 4 ILLEGAL 4 Write ILLEGAL 4, 9 Read ILLEGAL 4, 9 No Operation No Operation; Precharge after tDPL Row Address Bank Activate X Device Deselect No Operation; Precharge after tDPL Mode Register Set ILLEGAL X Auto or Self Refresh ILLEGAL X Precharge OP Code Row Address Bank Activate ILLEGAL ILLEGAL L H H H X X No Operation H X X X X X Device Deselect No Operation; Idle after tRC L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge L L H H BS L H L L BS Column Write ILLEGAL L H L H BS Column Read ILLEGAL L H H H X X No Operation No Operation; Idle after two clock cycles H X X X X X Device Deselect No Operation; Idle after two clock cycles OP Code Row Address Bank Activate ILLEGAL ILLEGAL 1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is being applied to. 2. All Banks must be idle; otherwise, it is an illegal action. 3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is entered. 4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation. 6. The minimum and maximum Active time (tRAS) must be satisfied. 7. The RAS to CAS Delay (tRCD) must occur before the command is given. 8. Column address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied. REV 1.0 May 9, 2005 33 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Absolute Maximum Ratings Symbol VDD VDDQ VIN VOUT TA TSTG PD IOUT Parameter Rating Units Notes Power Supply Voltage -0.3 to +4.6 V 1 Power Supply Voltage for Output -0.3 to +4.6 V 1 Input Voltage -0.3 to VDD+0.3 V 1 Output Voltage -0.3 to VDD+0.3 V 1 0 to +70 C 1 -55 to +125 C 1 Power Dissipation 1.0 W 1 Short Circuit Output Current 50 mA 1 Operating Temperature (ambient) Storage Temperature 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended DC Operating Conditions (TA = 0C to 70C) Symbol Rating Parameter Units Notes 3.6 V 1 3.3 3.6 V 1 2.0 -- VDD + 0.3 V 1, 2 -0.3 -- 0.8 V 1, 3 Min. Typ. Max. Supply Voltage 3.0 3.3 Supply Voltage for Output 3.0 VIH Input High Voltage VIL Input Low Voltage VDD VDDQ 1. All voltages referenced to VSS and VSSQ. 2. VIH (max) = VDD + 2.3V for pulse width 3ns. 3. VIL (min) = VSS - 2.0V for pulse width 3ns. Capacitance (TA = 25C, f = 1MHz, VDD = 3.3V 0.3V) Symbol CI CO REV 1.0 May 9, 2005 Parameter Min. Typ Max. Units Input Capacitance (A0-A11, BA0, BA1, CS, RAS, CAS, WE, CKE, DQM) 2.5 3.0 3.8 pF Input Capacitance (CK) 2.5 2.8 3.5 pF Output Capacitance (DQ0 - DQ15) 4.0 4.5 6.5 pF Notes 34 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM DC Electrical Characteristics (TA = 0 to +70C, VDD = 3.3V 0.3V) Symbol Parameter Min. Max. Units II(L) Input Leakage Current, any input (0.0V VIN VDD), All Other Pins Not Under Test = 0V -1 +1 A IO(L) Output Leakage Current (DOUT is disabled, 0.0V VOUT VDDQ) -1 +1 A VOH Output Level (LVTTL) Output "H" Level Voltage (IOUT = -2.0mA) 2.4 -- V VOL Output Level (LVTTL) Output "L" Level Voltage (IOUT = +2.0mA) -- 0.4 V DC Output Load Circuit 3.3 V 1200 VOH (DC) = 2.4V, IOH = -2mA Output VOL (DC) = 0.4V, IOL = 2mA 50pF REV 1.0 May 9, 2005 870 35 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM DC Electrical Characteristics Operating, Standby, and Refresh Currents (TA = 0 to +70C) Parameter Notes 85 mA 1, 2, 3 2 2 mA 1 2 2 2 mA 1 18 15 18 15 mA 1, 5 CKE VIH(min), tCK = Infinity, 8 6 8 6 mA 1, 7 ICC3N CKE VIH(min), tCK = min, CS = VIH (min) 30 30 30 30 mA 1, 5 ICC3P CKE VIL(max), tCK = min, 3 3 3 3 mA 1, 6 Operating Current (Burst Mode) ICC4 tCK = min, Read/ Write command cycling, Multiple banks active, gapless data, BL = 4 100 100 100 100 mA 1, 3, 4 Auto (CBR) Refresh Current ICC5 tCK = min, tRC = tRC(min) CBR command cycling 210 180 210 180 mA 1 Self Refresh Current ICC6 CKE 0.2V 2 2 2 2 mA 1 Precharge Standby Current in Power Down Mode Precharge Standby Current in Non-Power Down Mode No Operating Current (Active state: 4 bank) Test Condition ICC1 Speed (2.5V) Speed (3.3V) Units Operating Current Symbol 6K 75B 6K 75B 1 bank operation tRC = tRC(min), tCK = min Active-Precharge command cycling without burst operation 90 85 90 ICC2P CKE VIL(max), tCK = min, CS = VIH(min) 2 2 ICC2PS CKE VIL(max), tCK = Infinity, CS = VIH(min) 2 ICC2N CKE VIH(min), tCK = min, CS = VIH (min) ICC2NS 1. Currents given are valid for a single device. . 2. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of tCK and tRC. Input signals are changed up to three times during tRC(min). 3. The specified values are obtained with the output open. 4. Input signals are changed once during tCK(min). 5. Input signals are changed once during three clock cycles. 6. Active Standby Current will be higher if Clock Suspend is entered during a burst read cycle (add 1mA per DQ). 7. Input signals are stable. REV 1.0 May 9, 2005 36 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM AC Characteristics (TA = 0 to +70C, VDD = 3.3V 0.3V) 1. An initial pause of 200s, with DQM and CKE held high, is required after power-up. A Precharge All Banks command must be given followed by a minimum of two Auto (CBR) Refresh cycles before or after the Mode Register Set operation. 2. The Transition time is measured between VIH and VIL (or between VIL and VIH) 3. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 4. Load Circuit A: AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.40V crossover point 5. Load Circuit A: AC measurements assume tT = 1.0ns. 6. Load Circuit B: AC timing tests have VIL = 0.8 V and VIH = 2.0 V with the timing referenced to the 1.40V crossover point 7. Load Circuit B: AC measurements assume tT = 1.2ns. . AC Characteristics Diagrams tT tCKL Clock tSETUP tCKH Vtt = 1.4V VIH 1.4V VIL Output 1.4V Output tAC tOH tLZ REV 1.0 May 9, 2005 50pF AC Output Load Circuit (A) tHOLD Input Output 50 Zo = 50 Zo = 50 50pF AC Output Load Circuit (B) 1.4V 37 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Clock and Clock Enable Parameters Symbol Parameter -6K -75B Min. Max. Min. Max. Units Notes tCK3 Clock Cycle Time, CAS Latency = 3 6.0 1000 7.5 1000 ns tCK2 Clock Cycle Time, CAS Latency = 2 7.5 -- 10 -- ns tAC3 (A) Clock Access Time, CAS Latency = 3 -- -- -- -- ns 1 tAC2 (A) Clock Access Time, CAS Latency = 2 -- -- -- -- ns 1 tAC3 (B) Clock Access Time, CAS Latency = 3 -- 5 -- 5.4 ns 2 tAC2 (B) Clock Access Time, CAS Latency = 2 -- 5.4 -- 6 ns 2 tCKH Clock High Pulse Width 2 -- 2.5 -- ns tCKL Clock Low Pulse Width 2 -- 2.5 -- ns tCES Clock Enable Set-up Time 1.5 -- 1.5 -- ns tCEH Clock Enable Hold Time 0.8 -- 0.8 -- ns tSB Power down mode Entry Time 0 6 0 7.5 ns tT Transition Time (Rise and Fall) 0.3 8 0.5 10 ns 1. Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 4, 5 and load circuit A. 2. Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 6, 7 and load circuit B. Common Parameters Symbol Parameter -6K -75B Min. Max. Min. Max. Units Notes tCS Command Setup Time 1.5 -- 1.5 -- ns tCH Command Hold Time 0.8 -- 0.8 -- ns tAS Address and Bank Select Set-up Time 1.5 -- 1.5 -- ns tAH Address and Bank Select Hold Time 0.8 -- 0.8 -- ns tRCD RAS to CAS Delay 16 -- 20 -- ns 1 tRC Bank Cycle Time 54 -- 67.5 -- ns 1 tRAS Active Command Period 36 100K 45 100K ns 1 tRP Precharge Time 16 -- 20 -- ns 1 tRRD Bank to Bank Delay Time 12 -- 15 -- ns 1 tCCD CAS to CAS Delay Time 1 -- 1 -- CK 1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number). Mode Register Set Cycle Symbol tRSC REV 1.0 May 9, 2005 Parameter Mode Register Set Cycle Time -6K -75B Min. Max. Min. Max. 12 -- 15 -- Units ns 38 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Read Cycle Symbol -75B Units Notes Min. Max. Min. Max. -- -- -- -- ns 1 2.5 -- 2.7 -- ns 2, 4 tOH Data Out Hold Time tLZ Data Out to Low Impedance Time 0 -- 0 -- ns tHZ Data Out to High Impedance Time 3 6 3 7 ns DQM Data Out Disable Latency 2 -- 2 -- CK tDQZ 1. 2. 3. 4. -6K Parameter 3 AC Output Load Circuit A. AC Output Load Circuit B. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. Data Out Hold Time with no load must meet 1.8ns (-75H, -75D, -75A). Refresh Cycle Symbol tREF tSREX -6K Parameter -75B Units Notes Min. Max. Min. Max. Refresh Period -- 64 -- 64 ms Self Refresh Exit Time 1 -- 1 -- CK 1 1. 4096 auto refresh cycles. Write Cycle Symbol -6K Parameter -75B Min. Max. Min. Max. Units tDS Data In Set-up Time 1.5 -- 1.5 -- ns tDH Data In Hold Time 0.8 -- 0.8 -- ns tDPL Data input to Precharge 12 -- 15 -- ns tWR Write Recovery Time 12 -- 15 -- ns tDAL3 Data In to Active Delay CAS Latency = 3 5 -- 5 -- CK tDAL2 Data In to Active Delay CAS Latency = 2 4 -- 4 -- CK tDQW DQM Write Mask Latency 0 -- 0 -- CK REV 1.0 May 9, 2005 39 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Clock Frequency and Latency Symbol Parameter -6K -75B Units fCK Clock Frequency 166 133 MHz tCK Clock Cycle Time 6.0 7.5 ns tAA CAS Latency 3 3 CK tRP Precharge Time 3 3 CK tRCD RAS to CAS Delay 3 3 CK tRC Bank Cycle Time 9 9 CK tRAS Minimum Bank Active Time 6 6 CK tDPL Data In to Precharge 2 2 CK tDAL Data In to Active/Refresh 5 5 CK tRRD Bank to Bank Delay Time 2 2 CK tCCD CAS to CAS Delay Time 1 1 CK tWL Write Latency 0 0 CK tDQW DQM Write Mask Latency 0 0 CK tDQZ DQM Data Disable Latency 2 2 CK tCSL Clock Suspend Latency 1 1 CK REV 1.0 May 9, 2005 40 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. REV 1.0 May 9, 2005 Bank2,3 = Idle Hi-Z tCKH *BA0 = "L" DQ DQM A0-A9, A11 A10 * BA1 WE CAS RAS CS CKE CK RAx RAx tCKL T1 T3 tRCD tAH Ax0 CAx tCK2 tCH tCS T2 T4 Ax1 T5 Ax2 tRC RBx RBx T6 Ax3 T7 Bx0 CBx T9 Bx1 Bx2 tDS T11 Activate Command Bank 0 Bx3 RAy RAy T10 Ay0 CAy Ay2 T14 tDH Ay1 T13 Write Command Bank 0 T12 T15 Ay3 T17 T18 Precharge Command Bank 0 tDPL T16 tDPL and tDAL depend on clock cycle time and speed sort. See the Clock Frequency and Latency Table. tDAL T8 Activate Write with Activate Write with Command Auto Precharge Command Auto Precharge Bank 0 Command Bank 1 Command Bank 0 Bank 1 tAS tCES T0 RAz T22 Activate Command Bank 1 RBy RBy tCEH T21 tRRD Activate Command Bank 0 tRP T20 RAz T19 (Burst length = 4, CAS latency = 2) NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM AC Parameters for Write Timing \ 41 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. REV 1.0 May 9, 2005 Hi-Z Bank2,3 = Idle * BA0 = "L" DQ DQM A0-A9, A11 A10 * BA1 WE CAS RAS CS CKE CK RAx RAx T1 Activate Command Bank 0 T0 tRCD tCK3 T2 CAx tRAS T4 Read with Auto Precharge Command Bank 0 tRRD T3 T6 Activate Command Bank 1 tAC3 RBx RBx tRC T5 Ax0 tOH Ax1 Begin Auto Precharge Bank 0 T7 tRP Ax2 CBx T9 Read with Auto Precharge Command Bank 1 T8 Ax3 T10 Bx0 RAy RAy Bx1 Begin Auto Precharge Bank 1 T12 Activate Command Bank 0 T11 T13 Bx2 (Burst length = 4, CAS latency = 3; tRCD, tRP = 3) NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM AC Parameters for Read Timing (3/3/3) \ 42 NANYA reserves the right to change products and specifications without notice. (c) NANYA TECHNOLOGY CORPORATION REV 1.0 May 9, 2005 tAS tCES tCKH tCKL T1 Hi-Z Bank2,3 = Idle RAx RAx T2 tRCD tAH tCH tCS tCK2 Activate Command Bank 0 Note: Must satisfy tRAS(min) For -260: extend tRCD1 clock * BA0 = "L" DQ DQM A0-A9, A11 A10 * BA1 WE CAS RAS CS CKE CK T0 tRRD T5 tLZ Ax0 tOH T6 Activate Command Bank 1 tAC2 tRC RBx RBx Begin Auto Precharge Bank 0 tRAS(min) CAx T4 Read with Auto Precharge Command Bank 0 T3 CBx T8 Read with Auto Precharge Command Bank 1 Ax1 tHZ tRP T7 Bx0 Begin Auto Precharge Bank 1 T9 T10 tHZ Bx1 tRP RAy RAy T12 Activate Command Bank 0 tCEH T11 T13 (Burst length = 2, CAS latency = 2; tRCD, tRP = 2) NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM AC Parameters for Read Timing (2/2/2) \ 43 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. REV 1.0 May 9, 2005 tAS tCES Hi-Z Bank2,3=Idle * BA0=" L" DQ tAH tCH tCS T1 Activate Command Bank 0 RAx RAx tCKH tCKL Note: Must satisfy tRAS(min). Extended tRCD 1 clock. Not required for BL 4. DQM A0-A9, A11 A10 * BA1 WE CAS RAS CS CKE CK T0 tRCD tCK3 T2 tRAS CAx T4 RBx RBx tRC Begin Auto Precharge Bank 0 T5 Read with Activate Auto Precharge Command Command Bank 1 Bank 0 tRRD T3 tLZ tAC3 T6 Ax0 Ax1 tHZ CBx T8 Read with Auto Precharge Command Bank 1 tOH tRP T7 Begin Auto Precharge Bank 1 T9 T10 Bx0 tRP Bx1 tHZ RAy RAy tCEH T12 Activate Command Bank 0 T11 T13 (Burst length = 2, CAS latency = 3; tRCD, tRP = 2) NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM AC Parameters for Read Timing (3/2/2) \ 44 NANYA reserves the right to change products and specifications without notice. (c) NANYA TECHNOLOGY CORPORATION REV 1.0 May 9, 2005 Hi-Z *BA0=" L" Bank 2,3=Idle DQ DQM A0-A9, A11 A10 * BA1 WE CAS RAS CS CKE CK Activate Command Bank 0 RAx RAx T0 tRCD tCK3 T2 CAx tRRD tRAS (mIn) T3 tRC T4 Note: Must satisfy tRAS(min). Read with Extended tRCD not required Auto Precharge for BL4. Command Bank 0 T1 T6 Activate Command Bank 1 tAC3 RBx RBx Begin Auto Precharge Bank 0 T5 Ax0 tOH tRP T7 Ax1 T8 CBx T10 Read with Auto Precharge Command Bank 1 T9 T12 Activate Command Bank 0 RAy RAy Begin Auto Precharge Bank 1 T11 Bx0 tRP tCEH T13 Bx1 T14 (Burst length = 2, CAS latency = 3; tRCD, tRP = 3) NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM AC Parameters for Read Timing (3/3/3) \ 45 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Mode Register Set T22 T21 T20 T19 Mode Register Set Command tRP REV 1.0 May 9, 2005 DQ DQM A0-A9 A10,A11, BA0,BA1 WE CAS RAS CS CKE CK Hi-Z T0 T1 tCK2 Precharge Command All Banks T2 T3 T4 Address Key tRSC T5 T6 Any Command T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 (CAS latency = 2) \ 46 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. REV 1.0 May 9, 2005 DQ DQM A0-A9, A11 A10 BS WE CAS RAS CS CKE CK tCK T2 T3 T4 Precharge 1st Auto Refresh Command Command All Banks tRP High level is required T1 Inputs must be stable for 200s Hi-Z T0 T5 T7 T8 T9 T10 T11 T12 8th Auto Refresh Command T14 tRC T13 Minimum of 8 Refresh Cycles are required T6 T15 T18 Mode Register Set Command T19 Any Command 2 Clock min. T17 Address Key T16 T20 T21 T22 NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Power-On Sequence and Auto Refresh (CBR) \ 47 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. REV 1.0 May 9, 2005 Hi-Z * BA0=" L" Bank2,3=Idle DQ DQM A0-A9, A11 A10 * BA1 WE CAS RAS CS CKE CK RAx RAx tCK3 T1 Activate Command Bank 0 T0 T2 CAx T4 Read Command Bank 0 T3 tCES T5 T6 Ax0 Ax1 tCEH T8 T9 Clock Suspend 1 Cycle T7 T11 Clock Suspend 2 Cycles Ax2 T10 T12 Ax3 T14 T15 Clock Suspend 3 Cycles T13 T16 Ax4 T17 T18 T19 Ax6 tHZ T20 Ax7 T21 T22 (Burst length = 8, CAS latency = 3; tRCD = 3) NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Clock Suspension / DQM During Burst Read \ 48 NANYA reserves the right to change products and specifications without notice. (c) NANYA TECHNOLOGY CORPORATION REV 1.0 May 9, 2005 Hi-Z Bank2,3=Idle * BA0=" L" DQ DQM A0-A9, A11 A10 * BA1 WE CAS RAS CS CKE CK RAx RAx tCK3 T1 Activate Command Bank 0 T0 T2 CAx T4 DAx1 T5 Write Command Bank 0 Clock Suspend 1 Cycle DAx0 T3 T7 T8 T9 DAx2 Clock Suspend 2 Cycles T6 T11 T13 DAx3 T12 Clock Suspend 3 Cycles T10 T14 T16 DAx5 T15 T19 DAx7 T18 DAx6 T17 T20 T21 T22 (Burst length = 8, CAS latency = 3; tRCD = 3) NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Clock Suspension / DQM During Burst Write \ 49 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. REV 1.0 May 9, 2005 Hi-Z Bank2,3=Idle * BA0=" L" DQ DQM A0 -A9, A11 A10 * BA1 WE CAS RAS CS CKE CK T1 Activate Command Bank 0 RAx RAx tCES T0 tSB T2 T4 NOP ACTIVE STANDBY tCES T3 CAx T6 Read Command Bank 0 T5 tCK2 T7 Ax1 T9 T10 Clock Suspension Start Ax0 T8 T12 tHZ T13 Clock Suspension End Ax2 T11 T15 Precharge Command Bank 0 Ax3 VALID T14 T16 T17 tSB T18 T20 T21 T22 NOP Any Command PRECHARGE STANDBY tCES T19 (Burst length = 4, CAS latency = 2) NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Power Down Mode and Clock Suspend \ 50 NANYA reserves the right to change products and specifications without notice. (c) NANYA TECHNOLOGY CORPORATION NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Auto Refresh (CBR) T22 T21 T20 T19 REV 1.0 May 9, 2005 Precharge Command All Banks DQ DQM A0-A9, A11 A10 BS WE CAS RAS CS CKE CK Hi-Z T0 T1 tCK2 tRP T2 T3 Auto Refresh Command T4 T5 T6 tRC T7 T8 T9 T10 Auto Refresh Command T11 T12 T13 tRC T14 T15 T16 T17 T18 (CAS latency = 2) \ 51 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. REV 1.0 May 9, 2005 DQ DQM A0-A9, A11 A10 BS WE CAS RAS CS CKE CK All Banks must be idle Hi-Z T0 T2 tSB T3 T4 Power Down Entry Self Refresh Entry tCES T1 tCES Tm Power Down Exit Self Refresh Exit tSREX tRC Any Command Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tm+6 Tm+7 Tm+8 Tm+9 Tm+10 Tm+11 Tm+12 Tm+13 Tm+14 Tm+15 (Note: The CK signal must be reestablished prior to CKE returning high.) NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Self Refresh (Entry and Exit) \ 52 NANYA reserves the right to change products and specifications without notice. (c) NANYA TECHNOLOGY CORPORATION REV 1.0 May 9, 2005 Activate Command Bank 1 Hi-Z RBx RBx High Bank2,3=Idle * BA0=" L" DQ DQM A0-A9, A11 A10 * BA1 WE CAS RAS CS CKE CK T0 tRCD tCK3 T1 CBx T3 Read Command Bank 1 T2 T4 tAC3 T5 Bx0 Bx1 RAx RAx T7 Activate Command Bank 0 T6 Bx2 T8 Bx3 Bx4 CAx Bx5 T10 Read Command Bank 0 T9 T12 Precharge Command Bank 1 Bx6 T11 Ax0 T13 Ax1 RBy RBy T15 Activate Command Bank 1 T14 Ax4 T16 Ax6 T18 Read Command Bank 1 Ax5 CBy T17 Ax7 T19 By0 T21 Precharge Command Bank 0 T20 T22 (Burst length = 8, CAS latency = 3; tRCD, tRP = 3) NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Random Row Read (Interleaving Banks) with Precharge \ 53 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. REV 1.0 May 9, 2005 Activate Command Bank 1 Hi-Z RBx RBx High * BA0=" L" Bank2,3=Idle DQ DQM A0-A9, A11 A10 * BA1 WE CAS RAS CS CKE CK T0 T2 CBx T3 Read with Auto Precharge Command Bank 1 tRCD tCK3 T1 T4 tAC3 T5 Bx0 T6 Bx1 Bx2 RAx RAx RAx RAx T8 Activate Command Bank 0 T7 Bx3 T9 Bx5 T12 Bx6 Read with Auto Precharge Command Bank 0 Bx4 T11 T13 Bx7 Ax0 Start Auto Precharge Bank 1 CAx T10 T14 Ax1 T17 T18 RBy RBy Ax5 Ax6 Read with Auto Precharge Command Bank 1 Ax4 T19 CBy Start Auto Precharge Bank 0 T16 Activate Command Bank 1 T15 Ax7 T20 T21 By0 T22 (Burst length = 8,CAS latency = 3; tRCD, tRP = 3) NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Random Row Read (Interleaving Banks) with Auto-Precharge \ 54 NANYA reserves the right to change products and specifications without notice. (c) NANYA TECHNOLOGY CORPORATION REV 1.0 May 9, 2005 Activate Command Bank 0 Hi-Z RAx RAx High * BA0=" L" Bank2,3=Idle DQ DQM A0-A9, A11 A10 * BA1 WE CAS RAS CS CKE CK T0 tRCD tCK3 T1 CAX DAx1 T3 Write with Auto Precharge Command Bank 0 DAx0 T2 T4 T5 DAx4 T6 RBx RBx DAx6 T8 Activate Command Bank 1 DAx5 T7 DBx0 CBx T10 DBx4 T14 T16 RAy RAy Activate Command Bank 0 DBx5 T15 T17 DBx6 T18 DAy0 Bank may be reactivated at the completion of tDAL. DAy1 DAy2 T22 tDAL T21 CAy T20 Write with Auto Precharge Command Bank 0 DBx7 T19 Number of clocks depends on clock cycle time and speed sort. See the Clock Frequency and Latency table. DBx2 DBx3 T13 tDAL T12 DBx1 T11 Write with Auto Precharge Command Bank 1 DAx7 T9 (Burst length = 8, CAS latency = 3; tRCD, tRP = 3) NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Random Row Write (Interleaving Banks) with Auto-Precharge \ 55 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. REV 1.0 May 9, 2005 Hi-Z RAx RAx High Activate Command * BA0=" L" Bank 0 Bank2,3=Idle DQ DQM A0-A9, A11 A10 * BA1 WE CAS RAS CS CKE CK T0 tRCD tCK3 T1 CAX DAx1 T3 Write Command Bank 0 DAx0 T2 T4 T5 DAx4 T6 RBx RBx DAx6 T8 Activate Command Bank 1 DAx5 T7 DAx7 T9 T14 DBx4 tRP DBx3 T13 Precharge Command Bank 0 DBx2 T12 DBx1 T11 Write Command Bank 1 DBx0 CBx T10 T16 RAy RAy Activate Command Bank 0 DBx5 T15 T17 DBx6 T18 DBx7 T19 DAy2 Write Command Bank 0 Precharge Command Bank 1 DAy0 tDPL T22 DAy1 T21 CAy T20 (Burst length = 8,CAS latency = 3; tRCD, tRP = 3) NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Random Row Write (Interleaving Banks) with Precharge \ 56 NANYA reserves the right to change products and specifications without notice. (c) NANYA TECHNOLOGY CORPORATION REV 1.0 May 9, 2005 Hi-Z * BA0=" L" Bank2,3=Idle DQ DQM A0-A9, A11 A10 * BA1 WE CAS RAS CS CKE CK RAx RAx tCK3 T1 Activate Command Bank0 T0 T2 CAx T4 Read Command Bank 0 T3 T5 T6 Ax0 T7 Ax1 T8 Ax3 T10 DAy0 T13 DAy1 T12 CAy T11 DAy3 T14 The Read Data Write The Write Data is Masked with a Command is Masked with a Two Clock Bank 0 Zero Clock Latency Latency Ax2 T9 DAy4 T15 T16 T18 Precharge Command Bank 0 T17 T19 T20 T21 T22 (Burst length = 8, CAS latency = 3; tRCD, tRP = 3) NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Read / Write Cycle \ 57 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. REV 1.0 May 9, 2005 Hi-Z Bank2,3=Idle * BA0=" L" DQ DQM A0-A9, A11 A10 * BA1 WE CAS RAS CS CKE CK RAx RAx tCK3 T1 Activate Command Bank 0 T0 tRCD T2 CAx T4 RBx RBx T5 Activate Command Bank 1 Read Command Bank 0 T3 Ax0 tAC3 T6 Ax1 CBx T8 Read Command Bank 1 T7 Ax2 Ax3 CBy Bx0 T10 Read Command Bank 1 T9 T12 By0 T13 By1 CAy T14 Bz0 T15 Bz1 T16 Read with Read Precharge Command Auto Precharge Command Command Bank 1 Bank 1 Bank 0 Bx1 CBz T11 Ay0 T17 T19 T20 Ay1 Ay2 Ay3 Start Auto Precharge Bank 0 T18 T21 T22 (Burst length = 4, CAS latency = 3; tRCD, tRP = 3) NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Interleaved Column Read Cycle \ 58 NANYA reserves the right to change products and specifications without notice. (c) NANYA TECHNOLOGY CORPORATION REV 1.0 May 9, 2005 Hi-Z RAx RAx Activate Command * BA0=" L" Bank 0 Bank2,3=Idle DQ DQM A0-A9, A11 A10 * BA1 WE CAS RAS CS CKE High CK T0 tCK3 T1 CAx RBx RBx T4 Activate Command Bank 1 T3 Read Command Bank 0 T2 T5 Ax1 CBx T7 Ax2 Read with Auto Precharge Command Bank 1 Ax0 T6 T8 Ax3 T9 Bx1 T12 Bx2 Read with Auto Precharge Command Bank 0 Bx0 T11 T13 Bx3 T14 RBy RBy Activate Command Bank 1 Ay0 Start Auto Precharge Bank 1 CAy T10 T16 CBy T17 Ay1 Ay3 Read with Auto Precharge Command Bank 1 Ay2 Start Auto Precharge Bank 0 T15 T18 T20 T21 By0 By1 Start Auto Precharge Bank 1 T19 (Burst length = 4, CAS latency = 3; tRCD, tRP = 3) T22 NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Auto Precharge after Read Burst \ 59 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. REV 1.0 May 9, 2005 Activate Command Bank 0 Bank2,3=Idle * BA0=" L" DQ Hi-Z RAx A0-A9, A11 DQM RAx High A10 * BA1 WE CAS RAS CS CKE CK T0 DAx1 T2 Write Command Bank 0 DAx0 CAx tCK2 T1 RBx RBx T4 DAx3 CBx DBx0 T5 T6 DBx1 Write with Activate Command Auto Precharge Command Bank 1 Bank 1 DAx2 T3 T7 DBx2 T8 DAy0 DAy1 tDAL CAy T10 DAy2 RBy RAz RAz DAz0 CAz T17 DBy3 T16 DBy2 T15 DBy1 tDAL CBy T14 DBy0 T13 DAy3 T12 RBy T11 DAz1 T18 Number of clocks depends on clock cycle and speed sort. See the Clock Frequency and Latency table. Bank may be reactivated at the completion of tDAL. Write with Write with Write with Activate Activate Auto Precharge Command Auto Precharge Command Auto Precharge Command Command Command Bank 1 Bank 0 Bank 0 Bank 0 Bank 1 DBx3 T9 DAz2 T19 DAz3 T20 T22 tDAL T21 (Burst length = 4, CAS latency = 2) NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Auto Precharge after Write Burst \ 60 NANYA reserves the right to change products and specifications without notice. (c) NANYA TECHNOLOGY CORPORATION REV 1.0 May 9, 2005 Activate Command Bank 0 Hi-Z Hi-Z RAv RAv High Bank2,3=Idle * BA0=" L" DQ8 - DQ15 DQ0 - DQ7 UDQM LDQM A0-A9, A11 A10 * BA1 WE CAS RAS CS CKE CK T0 T2 Read Command Bank 0 CAv tCK2 T1 T3 Av0 Av0 T4 Av1 Av1 T5 Av2 Av2 T6 Av3 Av3 T7 T9 DAw0 CAw Single Write Command Bank 0 DAw0 T8 T11 Single Write Command Bank 0 DAx0 CAx T10 CAy T13 T14 Ay0 Ay0 T15 Ay1 T16 Lower Byte Read is masked Command Upper Byte Bank 0 is masked T12 Ay2 T17 Ay3 Ay3 T18 T20 Single Write Command Bank 0 DAz0 DAz0 CAz T19 T22 Lower Byte is masked T21 (Burst length = 4, CAS latency = 2) NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Burst Read and Single Write Operation \ 61 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. REV 1.0 May 9, 2005 DQ Hi-Z T2 Activate Command Bank A RAx A0-A9, A11 DQM Low RAx tCK3 T1 A10 BA0,BA1 WE CAS RAS CS CKE CK T0 tRCD T3 T5 Read Command Bank A T4 CAx T6 T7 Ax0 T8 Ax1 T9 Ax2 Ax3 T10 T11 Write Command Bank A T17 T18 Precharge Command Bank A tDPL T16 DAy3 T15 DAy2 T14 DAy1 T13 DAy0 CAy T12 T19 T20 T21 T22 (at 100MHz Burst Length = 4, CAS Latency = 3, tRCD, tRP = 3) NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM CS Function (Only CS signal needs to be asserted at minimum rate) \ 62 NANYA reserves the right to change products and specifications without notice. (c) NANYA TECHNOLOGY CORPORATION NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Package Dimensions (400mil; 54 lead; Thin Small Outline Package) 22.22 0.13 11.76 0.20 10.16 0.13 Detail A Lead #1 Seating Plane 0.10 0.80 Basic + 0.10 0.35 - 0.05 0.71REF 1.20 Max Detail A 0.25 Basic Gage Plane 0.5 0.1 0.05 Min REV 1.0 May 9, 2005 63 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT5SV8M16DS / NT5SV8M16DT NT5SE8M16DS / NT5SE8M16DT 128Mb Synchronous DRAM Revision Log Revision Date Modification 0.1 Jun 9, 2004 Draft release. 0.2 Aug 3, 2004 2.5V part added, full page burst support 1.0 May 9, 2005 P2; ordering infromation. Remove BGA portion & update currents specs. P37; DC characteristics, added all parameters spec. Please visit our home page for more information: www.nanya.com Nanya Technology Corporation Hwa Ya Technology Park 669 Fu Hsing 3rd Rd., Kueishan, Taoyuan, 333, Taiwan, R.O.C. Tel: +886-3-328-1688 Nanya reserves the right to make changes or deletions without any notice to any of its products. Nanya makes no guarantee, warranty or representation regarding the suitability of its products for any particular purpose. Nanya assumes no liability arising out of the application or use of its products. All parameters can and do vary in its application and must be validated for each customer application by the customeris technician. By purchasing Nanya products, Nanya does not convey any license under its patent rights not the rights of others. Nanya products are not designed or intended or authorized for use in systems intended for the military or surgical implants or any other applications where life is involved or where injury or death may occur or the loss/corruption of data or the loss of system reliability or mission critical applications. Should the buyer purchase or use Nanya products in such unintended or unauthorized application, the Buyer and user shall indemnify and hold Nanya and its officers, employees, subsidiaries, affiliates and distributors harmless against all claims, costs, damages, all fees and expenses directly or indirectly arising from any claim of loss, injury or death associated with unintended or unauthorized use even if such claims alleges Nanya was negligent regarding design or manufacture of the part. Nanya and the Nanya logo are trademarks of the Nanya Technology Corporation. (c)2004 Nanya Technology Corporation All rights reserved. Printed in Taiwan REV 1.0 May 9, 2005 64 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice.