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Februa ry 199 4

Revised October 2003

74LVXC4245 8-Bit Dual Supply Configurable Voltage Interface Transceiver with 3-STATE Outputs

74LVXC4245

8-Bit Dual Supply Configurable Voltage Interface

Transceiver with 3-STATE Outputs

General Description

The LVXC4245 is a 24-pin dual-supply, 8-bit configurable

voltage interface transceiver suited for PCMCIA and other

real time configurable I/O applications. The VCCA pin

accepts a 5V supply l evel. The “ A” Port is a dedicated 5V

port. The VCCB pin accepts a 3V-to-5V supply level. The

“B” Port is configured to track the VCCB supply level

respectively. A 5V level on the VCC pin will configure the

I/O pins at a 5V level and a 3V VCC will configure the I/O

pins at a 3V level. This device w ill allow the VCCB voltage

source pin and I/O pins on the “B” Port to float when OE is

HIGH. This feature is necessary to buffer data to and from

a PCMCIA socket that permits PCMCIA cards to be

inserted and removed during normal operation.

Features

■Bidirectional interface between 5V and 3V-to-5V buses

■Control inputs compatible with TTL level

■Outputs source/sink up to 24 mA

■Guaranteed simultaneous switching noise level and

dynamic thresh ol d per for man ce

■Implements patented EMI reduction circuitry

■Flexible VCCB operating range

■Allows B Port an d VCCB to float simultaneously when OE

is HIGH

■Functionally compatible with the 74 series 245

Ordering Code:

Devices also available in Tape and R eel. Specify by appending the suffix lett er “X” to the ordering code.

Logic Symbol

Pin Descriptions

Connection Diagram

Order Number Package Number Package Description

74LVXC4245WM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74LVXC4245QSC MQA24 24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide

74LVXC4245MTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Pin Names Description

OE Output Enable Input

T/R Tr ansmit/Receive Input

A0–A7Side A Inputs or 3-STATE Outputs

B0–B7Side B Inputs or 3-STATE Outputs

www.fairchildsemi.com 2

74LVXC4245

Truth Table

H = HIGH Voltage Le ve l

L = LOW Voltage Level

X = Immaterial

Logic Diagram

Inputs Outputs

OE T/R

L L Bus B Data to Bus A

L H Bus A Data to Bus B

H X HIGH-Z State

3 www.fairchildsemi.com

74LVXC4245

Absolute Maxim um Ratings(Note 1) Recommended Operating

Conditions (Note 2)

Note 1: The “Absolute Maximum Ratings” are those value s beyond whic h

the saf ety of the device cannot b e guaranteed . The device should not be

operated at these limits. The parametric values defined in the Electrical

Char ac teristics tables are not guaranteed at t he absolute maxim um ratings .

The “R ecomm ended Ope rating Co ndition s” table will define the condit ions

for actu al device operation.

Note 2: The A Port unused pins (inputs and I/O's) mu st be held HIGH or

LOW. They may not float.

DC Electrical Characteristics

Supply Voltage (VCCA,VCCB)−0.5V to +7.0V

DC Input Voltage (VI) @ OE, T/R −0.5V to VCCA +0.5V

DC Input/Output Voltage (VI/O)

@ An−0.5V to VCCA +0.5V

@ Bn−0.5V to VCCB +0.5V

DC Input Diode Current (IIK)

@ OE, T/R ±20 mA

DC Output Diode Current (IOK)±50 mA

DC Output Source or

Sink Current (IO)±50 mA

DC VCC or Ground Current

Per Output Pin (ICC or IGND)±50 mA

and Max Current ±200 mA

Storag e Temperature Range (TSTG)−65°C to +150°C

DC Latch-Up Source or

Sink Current ±300 mA

Supply Voltage VCCA 4.5V to 5.5V

VCCB 2.7V to 5.5V

Input Voltage (VI) @ OE, T/R 0V to VCCA

Input/Output Voltage (VI/O)

@An0V to VCCA

@Bn0V to VCCB

Free Air Operating Temperature (TA)−40°C to +85°C

Minimum Input Edge Rate (∆V/∆t) 8 ns/V

VIN from 30% to 70% of VCC

VCC @ 3V, 4.5V, 5.5V

Symbol Parameter VCCA VCCB TA = +25°CT

A = −40°C to +85°CUnits Conditions

(V) (V) Typ Guaranteed Limits

VIHA Minimum HIGH Level An4.5 2.7 2.0 2.0

VOUT ≤ 0.1V

Input Voltage OE 4.5 3.6 2.0 2.0 or

T/R 5.5 5.5 2.0 2.0 ≥ VCC − 0.1V

VIHB Bn4.5 2.7 2.0 2.0

4.5 3.6 2.0 2.0

4.5 5.5 3.85 3.85

VILA Maximum LOW Level An4.5 2.7 0.8 0.8

VOUT ≤ 0.1V

Input Voltage OE 4.5 3.6 0.8 0.8 or

T/R 5.5 5.5 0.8 0.8 ≥ VCC − 0.1V

VILB Bn4.5 2.7 0.8 0.8

4.5 3.6 0.8 0.8

4.5 5.5 1.65 1.65

VOHA Minimum HIGH Level 4.5 3.0 4.49 4.4 4.4 VIOUT = −100 µA

Output Voltage 4.5 3.0 4.25 3.86 3.76 IOH = −24 mA

VOHB 4.5 3.0 2.99 2.9 2.9

IOUT = −100 µA

4.5 3.0 2.85 2.56 2.46 IOH = −12 mA

4.5 3.0 2.65 2.35 2.25 IOH = −24 mA

4.5 2.7 2.5 2.3 2.2 IOH = −12 mA

4.5 2.7 2.3 2.1 2.0 IOH = −24 mA

4.5 4.5 4.25 3.86 3.76 IOH = −24 mA

VOLA Maximum LOW Level 4.5 3.0 0.002 0.1 0.1 VIOUT = 100 µA

Output Voltage 4.5 3.0 0.21 0.36 0.44 IOL = 24 mA

VOLB 4.5 3.0 0.002 0.1 0.1

IOUT = 100 µA

4.5 3.0 0.21 0.36 0.44 IOL = 24 mA

4.5 2.7 0.11 0.36 0.44 IOL = 12 mA

4.5 2.7 0.22 0.42 0.5 IOL = 24 mA

4.5 4.5 0.18 0.36 0.44 IOL = 24 mA

IIN Maximum Input VI = VCCA, GND

Leakage Current @ 5.5 3.6 ±0.1 ±1.0 µA

OE, T/R 5.5 5.5 ±0.1 ±1.0

www.fairchildsemi.com 4

74LVXC4245

DC Electrical Characteristics (Continued)

Note 3: Worst case package.

Note 4: Max num ber of output s d ef ined as (n). D at a inputs are driven 0V to VCC level; one output at GN D .

Note 5: Max num ber of Data Inputs (n) swit c hing. (n−1) inputs switch ing 0V to VCC level. I nput-unde r-t es t s w it c hing:

VCC level to threshold (VIHD), 0V to thresh old (VILD), f = 1 MHz.

Symbol Parameter VCCA VCCB TA = +25°CT

A = −40°C to +85°CUnits Conditions

(V) (V) Typ Guaranteed Limits

IOZA Maxi mum 3-STATE 5.5 3.6 ±0.5 ±5.0 µAVI = VIL, VIH, OE = VCCA

Output Leakage @ An5.5 5.5 ±0.5 ±5.0 VO = VCCA, GND

IOZB Maxi mum 3-STATE 5.5 3.6 ±0.5 ±5.0 µAVI = VIL, VIH, OE = VCCA

Output Leakage @ Bn5.5 5.5 ±0.5 ±5.0 VO = VCCB, GND

∆ICC Maximum All Inputs 5.5 5.5 1.0 1.35 1.5 mA VI = VCC − 2.1V

ICC/Input Bn5.5 3.6 0.35 0.5 mA VI = VCCB − 0.6V

ICCA1 Quiescent VCCA An = VCCA or GND

Supply Current as B 5.5 Open 8 80 µAB

n = Open, OE = VCCA

Port Floats T/R = VCCA, VCCB =

Open

ICCA2 Quiescent VCCA An = VCCA or GND

Supply Current 5.5 3.6 8 80 µAB

n = VCCB or GND

5.5 5.5 8 80 OE = GND, T/R = GND

ICCB Quiescent VCCB An = VCCA or GND

Supply Current 5.5 3.6 5 50 µAB

n = VCCB or GND

5.5 5.5 8 80 OE = GND, T/R = VCCA

VOLPA Quiet Output 5.0 3.3 1.5 V(Note 3) (Note 4)

Maximum Dynamic 5.0 5.0 1.5

VOLPB VOL 5.0 3.3 0.8 V(Note 3) (Note 4)

5.0 5.0 1.5

VOLVA Quiet Output Minimum 5.0 3.3 −1.2 V(Note 3) (Note 4)

Dynamic VOL 5.0 5.0 −1.2

VOLVB 5.0 3.3 −0.8 V(Note 3) (Note 4)

5.0 5.0 −1.2

VIHDA Minimum HIGH Level 5.0 3.3 2.0 V(Note 3) (Note 5)

Dynamic Input 5.0 5.0 2.0

VIHDB Voltage 5.0 3.3 2.0 V(Note 3) (Note 5)

5.0 5.0 3.5

VILDA Maximum LOW Level 5.0 3.3 0.8 V(Note 3) (Note 5)

Dynamic Input 5.0 5.0 0.8

VILDB Voltage 5.0 3.3 0.8 V(Note 3) (Note 5)

5.0 5.0 1.5

5 www.fairchildsemi.com

74LVXC4245

AC Electrical Characteristics

Note 6: Typical values at VCCA = 5V, VCCB = 5V @25°C.

Note 7: Typical values at VCCA = 5V, VCCB = 3.3V @ 25°C.

Note 8: Skew is def ined as the absol ut e v alue of the difference between the actu al propaga tio n delay for any two s eparate out puts of the sam e device. The

specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (t OSLH). Par am eter guaranteed by design.

Capacitance

Note 9: CPD is measured at 10 MHz.

Power Up Considerations

To insure the system does not experience unnecessary ICC

current draw, bus contention, or oscillations during power

up, the f ollowing guidel ines should be a dhered to (re fer to

Table 1):

•Power up the control side of t he device first. This is the

VCCA.

•OE should ramp with or ahead of VCCA. This will help

guar d against bus contention.

•The Transmit/Receive control pin (T/R) should ramp with

VCCA, this will ensure that the A Port data pins are con-

figured as inpu ts. Wit h VCCA receiving powe r first, the A

I/O Port should be configured as inputs to help guard

against bus conten tion and oscilla ti on s.

•A side data inp uts sh ould be dr iven to a val id logic l eve l.

This will prevent excessive current draw.

The above steps will ensure that no bus contention or oscil-

lations, and therefore no excessive current draw occurs

during the power up cycli ng of these devices. These steps

will help prevent possible damage t o the t ranslator device s

and potential damage to other system components.

TABLE 1. Low Voltage T ranslator Power Up Sequencing Table

Please reference Application Note AN-5001 for more detailed information on using Fairchild’s LVX Low Voltage Dual

Supply CMOS Translating Transceivers.

Symbol Parameter

CL = 50 pF CL = 50 pF

Units

VCCA = 4.5V to 5.5V VCCA = 4.5V to 5.5V

VCCB = 4.5V to 5.5V VCCB = 2.7V to 3.6V

TA = +25°CT

A = −40°C to +85°CT

A = +25°CT

A = −40°C to +85°C

Min Typ Max Min Max Min Typ Max Min Max

(Note 6) (Note 7)

tPHL Propagation 1.0 4.9 6.5 1.0 7.0 1.0 5.5 7.5 1.0 8.0 ns

tPLH Delay A to B 1.0 4.0 5.5 1.0 6.0 1.0 5.0 7.0 1.0 7.5

tPHL Propagation 1.0 4.7 6.5 1.0 7.0 1.0 5.6 7.5 1.0 8.0 ns

tPLH Delay B to A 1.0 3.9 5.0 1.0 5.5 1.0 4.3 6.0 1.0 6.5

tPZL Output Enable 1.0 5.6 7.5 1.0 8.0 1.0 6.7 9.0 1.0 10.0 ns

tPZH Time OE to B 1.0 5.7 7.5 1.0 8.0 1.0 6.9 9.5 1.0 10.0

tPZL Output Enable 1.0 7.4 9.0 1.0 10.0 1.0 8.0 10.0 1.0 11.0 ns

tPZH Time OE to A 1.0 6.1 7.5 1.0 8.5 1.0 6.3 8.0 1.0 8.5

tPHZ Output Disable 1.0 4.8 7.0 1.0 7.5 1.0 6.0 9.0 1.0 9.5 ns

tPLZ Time OE to B 1.0 3.8 5.5 1.0 6.0 1.0 4.2 6.5 1.0 7.0

tPHZ Output Disable 1.0 3.4 5.5 1.0 6.0 1.0 3.4 5.5 1.0 6.0 ns

tPLZ Time OE to A 1.0 2.9 4.5 1.0 5.0 1.0 2.9 5.0 1.0 5.5

tOSHL Output to Output

tOSLH Skew (Note 8) 1.0 1.5 1.5 1.0 1.5 1.5 ns

Data to Output

Symbol Parameter Typ Units Conditions

CIN Input Capacitance 4.5 pF VCC = Open

CI/O Input/Output Capacitance 10 pF VCCA = 5V, VCCB = 3.3V

CPD Power Dissipation Capacitance A→B45pFV

CCA = 5V

(Note 9) B→A50pFV

CCB = 3.3V

Device Type VCCA VCCB T/R OE A Side I/O B Side I/O Floata ble Pin

Allowed

74LVXC4245 5V 2.7V to 5.5V ramp ramp logic outputs yes, VCCB and B

(power up 1st) configurable with VCCA with VCCA 0V or VCCA I/O’s w/ OE HIGH

www.fairchildsemi.com 6

74LVXC4245

Configurable I/ O Application for PCMCIA Cards

Block Diagram

The LVXC4245 is a 24-pin dual supply device well suited

for PCMCIA configurable I/O applications. Ideal for low

power notebook designs, the LVXC4245 consumes less

than 1 mW of quiescent power in all modes of operation.

The LVXC4245 meets all PCMCIA I/O voltage require-

ments at 5V and 3.3V operation. By tying VCCB of the

LVXC4245 to the card voltage supply, the PCMCIA card

will always experience rail to rail output swings, maximizing

the reliability of the interface.

The VCCA pin on the LVXC4245 must always be tied to a

5V power sup ply. This voltage connection provide s inter na l

references needed to account for variations in VCCB. When

connected as in the block diagram above, the LVXC4245

meets all the voltage and current requirements of the ISA

bus standar d ( IEEE P996).

7 www.fairchildsemi.com

74LVXC4245

Physical Dim ensions inches (millimeters) unless otherwise noted

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Package Number M24B

24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide

Package Number MQA24

www.fairchildsemi.com 8

74LVXC4245 8-Bit Dual Supply Configurable Voltage Interface Transceiver with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC24

Fairchild does not assu me any responsibility for use of any circuitry de scribed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syste ms are devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical compon ent i n any compon ent of a lif e supp ort

device or system whose failure to perform can be rea-

sonabl y ex pect ed to ca use the failu re of the life support

device or system, or to affect its safety or effectiveness.

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specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer

application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not

designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification

in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized

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