AT93C46B-10PC-2.5 - Atmel Corporation

AT93C46B

Features

•x16 Organization Utilizing “No Connects” for Pins 6 and 7

•Low Voltage and Standard Voltage Operation

– 5.0 (VCC = 4.5V to 5.5V)

– 2.7 (VCC = 2.7V to 5.5V)

– 2.5 (VCC = 2.5V to 5.5V)

•3-Wire Serial Interface

•2 MHz Clock Rate (5V) Compatibility

•Self-Timed Write Cycle (10 ms max)

•High Reliability

– Endurance: 1 Million Cycles

– Data Retention: 100 Years

•Automotive Grade and Extended Temperature Devices Available

•8-Pin PDIP and JEDEC SOIC Packages

Description

The AT93C46B provides 1024 bits of serial electrically erasable programmable read

only memory (EEPROM) organized as 64 words of 16 bits each. The device is opti-

mized for use in many industrial and commerc ial applications where low power and

low voltag e operation ar e es sen tia l. The AT 93C4 6B is avai lable in spac e sa vi ng 8- pi n

PDIP and 8-pin JEDEC packages.

The AT93C46B is enabled through the Chip Select pin (CS), and access ed via a 3-

wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock

(SK). Upon receiving a READ instruction at DI, the address is decoded and the data is

clocked out serially on the data output pi n DO. The WRITE cycle is compl etely self-

timed and no separate ERASE cycle is required before WRITE. The WRITE cycle is

only enabled when the part is in the ERASE/WRITE ENABLE state. When CS is

brought “high” following the initiation of a WRITE cycle, the DO pin outputs the

READY/BUSY status of the part.

The AT93C46B is available in 4.5V to 5.5V, 2.7V to 5.5V, and 2.5V to 5.5V versions.

0917A-A–11/97

3-Wire

Serial

E2PROMs

1K (64 x 16)

AT93C46B

8-Pin PDIP

VCC

GND

8-Pin SOIC

VCC

GND

Pin Configuration

Pin Name Function

CS Chip Select

SK Serial Data Cloc k

DI Serial Data Input

DO Serial Data Output

GND Ground

VCC Power Supply

NC No Connect

AT93C46B

Absolute Maximum Ratings*

Bloc k Diagram

Operating Temperature.........................-55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device . This is a stress ra ting onl y and

funct ion al ope ration of the device at these or an y

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditi ons f or e xtended p eriods ma y af fect dev ice

reliability.

Storage Temperature............................-65°C to +150°C

Voltage on Any Pin

with Respect to Ground...........................-1.0V to +7.0V

Maximum Operating Voltage.................................6.25V

DC Output Current ..............................................5.0 mA

AT93C46B

Pin Capacitance(1)

Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).

Note: 1. This parameter is characterized and is not 100% tested.

DC Characteristics

Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +2.5V to +5.5V,

TAC = 0°C to +70°C, VCC = +2.5V to +5.5V (unless otherwise noted).

Note: 1. VIL and VIH max are reference only and are not tested.

Test Conditions Max Units Conditions

COUT Out put Ca pa cit anc e ( DO) 5 pF VOUT = 0V

CIN Input Capacitance (CS, SK, DI) 5 pF VIN = 0V

Symbol Parameter Test Conditi on Min Typ Max Units

VCC2 Supply Voltage 2.5 5.5 V

VCC3 Supply Voltage 2.7 5.5 V

VCC4 Supply Voltage 4.5 5.5 V

ICC Supply Current VCC = 5.0V READ at 1.0 MHz 0.5 2.0 mA

WRITE at 1.0 MHz 0.5 2.0 mA

ISB1 Standby Current VCC = 2.5V CS = 0V 14.0 20.0 µA

ISB2 Standby Current VCC = 2.7V CS = 0V 14.0 20.0 µA

ISB3 Standby Current VCC = 5.0V CS = 0V 35.0 50.0 µA

IIL Input Leakage VIN = 0V to VCC 0.1 1.0 µA

IOL Output Leakage VIN = 0V to VCC 0.1 1.0 µA

VIL1(1)

VIH1(1) Input Low Voltage

Input High Voltage 4.5V ≤ VCC ≤ 5.5V -0.1

2.0 0.8

VCC + 1 V

VIL2(1)

VIH2(1) Input Low Voltage

Input High Voltage 1.8V ≤ VCC ≤ 2.7V 0.0

VCC x 0.7 VCC x 0.3

VCC + 1 V

VOL1

VOH1

Output Low Voltage

Output High Voltage 4.5V ≤ VCC ≤ 5.5V IOL = 2.1 mA 0.4 V

IOH = -0.4 mA 2.4 V

VOL2

VOH2

Output Low Voltage

Output High Voltage 1.8V ≤ VCC ≤ 2.7V IOL = 0.15 mA 0.2 V

IOH = -100 µAV

CC - 0.2 V

AT93C46B

AC Characteristics

Applicable over recommended operating range from TA = -40°C to + 85°C, VCC = +2.5V to + 5.5V,

CL = 1 TTL Gate and 100 pF (unless otherwise noted).

Symbol Parameter Test Condition Min Typ Max Units

fSK SK Clock Frequency 4.5V ≤ VCC ≤ 5.5V

2.7V ≤ VCC ≤ 5.5V

2.5V ≤ VCC ≤ 5.5V

0.5 MHz

tSKH SK High Time 4.5V ≤ VCC ≤ 5.5V

2.7V ≤ VCC ≤ 5.5V

2.5V ≤ VCC ≤ 5.5V

250

500 ns

tSKL SK Low Time 4.5V ≤ VCC ≤ 5.5V

2.7V ≤ VCC ≤ 5.5V

2.5V ≤ VCC ≤ 5.5V

250

500 ns

tCS Minimum CS Low Time 4.5V ≤ VCC ≤ 5.5V

2.7V ≤ VCC ≤ 5.5V

2.5V ≤ VCC ≤ 5.5V

250

500 ns

tCSS CS Setup Time Relative to SK 4.5V ≤ VCC ≤ 5.5V

2.7V ≤ VCC ≤ 5.5V

2.5V ≤ VCC ≤ 5.5V

100 ns

tDIS DI Setup Time Relative to SK 4.5V ≤ VCC ≤ 5.5 V

2.7V ≤ VCC ≤ 5.5V

2.5V ≤ VCC ≤ 5.5V

100

200 ns

tCSH CS Hold Time Relative to SK 0 ns

tDIH DI Hold Time Relative to SK 4.5V ≤ VCC ≤ 5.5V

2.7V ≤ VCC ≤ 5.5V

2.5V ≤ VCC ≤ 5.5V

100

200 ns

tPD1 Output Delay to ‘1’ AC Test 4.5V ≤ VCC ≤ 5.5V

2.7V ≤ VCC ≤ 5.5V

2.5V ≤ VCC ≤ 5.5V

250

500 ns

tPD0 Output Delay to ‘0’ AC Test 4.5V ≤ VCC ≤ 5.5V

2.7V ≤ VCC ≤ 5.5V

2.5V ≤ VCC ≤ 5.5V

250

500 ns

tSV CS to Status Valid AC Test 4.5V ≤ VCC ≤ 5.5V

2.7V ≤ VCC ≤ 5.5V

2.5V ≤ VCC ≤ 5.5V

250

500 ns

tDF CS to DO in High Impedance AC Test

CS = VIL

4.5V ≤ VCC ≤ 5.5V

2.7V ≤ VCC ≤ 5.5V

2.5V ≤ VCC ≤ 5.5V

100

200 ns

tWP Write Cycle Time 0.1 10 ms

4.5V ≤ VCC ≤ 5.5 V 1 ms

Endurance 25°C, VCC = 5.0V, Page Mode 1M Cycles

AT93C46B

Instruction Set for the AT93C46B

Instruction SB Op Code Address

(x16) Comments

READ 1 10 A5 - A0Reads data stored in memory, at specified address.

EWEN 1 00 11XXXX Write enable must precede all programming modes.

ERASE 1 11 A5 - A0Erase memory location An - A0.

WRITE 1 01 A5 - A0Writes memory location An - A0.

ERAL 1 00 10XXXX Erases all memory locations. Valid only at VCC = 4.5V to 5.5V.

WRAL 1 00 01XXXX Writes all memory locations. Valid only at VCC = 4.5V to 5.5V.

EWDS 1 00 00XXXX Disables all programming instr uctions.

AT93C46B

Functional Description

The AT93C46B is accessed via a simple and versatile

three-wire serial communication interface. Device opera-

tion is contro lled by seven in structi ons issu ed by the host

processor. A valid instruction starts with a rising edge of CS

and cons ists of a Sta rt Bit (log ic ‘1’) fo llowed by the appro-

priate Op Code and the desired memory Address location.

READ (READ): The Read (READ) instruction contains

the Addr ess c ode fo r th e m emo ry loc at ion to b e r ea d. Aft er

the instruction and address are decoded, data from the

selected memory location is available at the serial output

pin DO. Output data changes are synchronized with the ris-

ing edges of serial clock SK. It should be noted that a

dummy bit (logic ‘0’) precedes the 16 bit data output string.

ERASE/WRITE (EWEN): To assure data integrity, the

part automatically goes into the Erase/Write Disable

(EWDS) state when power is first applied. An Erase/Write

Enable (EWEN) instruction must be executed first before

any programming instructions can be carried out. Please

note that once in the Erase/Write Enable state, program-

ming remains enabled until an Erase/Write Disable

(EWDS) instruc tion is execute d or VCC power is removed

from the part.

ERASE (ERASE): The Erase (ERASE) instruction pro-

grams all bits in the specified memory location to the logical

‘1’ state. The self-timed erase cycle starts once the ERASE

instruction and address a re decoded. The DO pi n outputs

the READ Y / BUSY status of the part if CS is brough t high

after being kept low for a minimum of 250 ns (tCS). A lo gic

‘1’ at pin DO indicates that the selected memory location

has been er ased, an d the part is ready for anothe r instruc-

tion.

WRITE (WRITE): The Write (WRITE ) instr uctio n c on tai ns

the 16 bits of data to be written into the specified memory

location. The self-timed programming cycle starts after the

last bit of data is received at serial data input pin DI. The

DO pin outputs the READY/BUSY status of the part if CS is

brought high after being kept low for a minimum of 250 ns

(tCS). A l ogic ‘0’ at DO in dicate s th at progr amming is sti ll in

progress. A logic ‘1’ indicates that the memory l ocation at

the specified address has been written with the data pat-

tern contained in the instruction and the part is ready for

further instructions.

ERASE ALL (ERAL): The Erase All (ERAL) instruction

programs every bit in the memory array to the logic ‘1’ state

and is pr imar ily u sed for te sting purpo ses. Th e DO pi n out-

puts th e READ Y/BU SY statu s of t he par t if CS is br ought

high after being kept low for a minimum of 250 ns (tCS). The

ERAL instruction is valid only at VCC = 5.0V ± 10%.

WRITE ALL (WRAL): T he Write All (WRAL) instruction

programs all memory locations with the data patterns spec-

ified in the instruction. The DO pin outputs the

READY/ BU SY stat us of the p art i f CS is brou ght h igh afte r

being k ept low fo r a mini mum of 25 0 ns (t CS). The WRAL

instruction is valid only at VCC = 5.0V ± 10%.

ERASE/W RITE DISABLE (EWDS): To protect against

accidental data disturb, the Erase/Write Disable (EWDS)

instruction disables all programming modes and should be

executed after all p rogramming operations. The operation

of the READ instruction is independent of both the EWEN

and EWDS instructions and can be executed at any time.

Synchronous Data Timing

Note: 1. This is the minimum SK period.

AT93C46B

Organization Key for Timing Diagrams

READ Timing

EWEN Timing

EWDS Timing(1)

Note: 1. Requires a minimum of nine clock cycles.

I/O AT93C46B

(x16)

ANA5

DND15

AT93C46B

WRITE Timing

WRAL Timing(1)(2)

Notes: 1. Valid only at VCC = 4.5V to 5.5V.

2. Requires a minimum of nine clock cycles.

ERASE Timing

AT93C46B

TERAL Timing(1)

Note: 1. Valid only at VCC = 4.5V to 5.5V.

AT93C46B

Order ing In formation

tWP (max)

(ms) ICC (max)

(µA) ISB (max)

(µA) fMAX

(kHz) Ordering Code Package Operation Range

10 2000 50.0 2000 AT93C46B-10PC

AT93C46B-10SC 8P3

8S1 Commercial

(0°C to 70°C)

10 800 20.0 1000 AT93C46B-10PC-2.7

AT93C46B-10SC-2.7 8P3

8S1 Commercial

(0°C to 70°C)

10 600 20.0 500 AT93C46B-10PC-2.5

AT93C46B-10SC-2.5 8P3

8S1 Commercial

(0°C to 70°C)

10 2000 50.0 2000 AT93C46B-10PI

AT93C46B-10SI 8P3

8S1 Industrial

(-40°C to 85°C)

10 800 20.0 1000 AT93C46B-10PI-2.7

AT93C46B-10SI-2.7 8P3

8S1 Industrial

(-40°C to 85°C)

10 600 20.0 500 AT93C46B-10PI-2.5

AT93C46B-10SI-2.5 8P3

8S1 Industrial

(-40°C to 85°C)

Package Type

8P3 8 Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

8S1 8 Lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

Options

Blank Standard Device (4.5V to 5.5V)

-2.7 Low Voltage (2.7V to 5.5V)

-2.5 Low Voltage (2.5V to 5.5V)