M1A3P1000L-1FGG144YC - Microsemi Corp.

May 2012 I

ProASIC3L Low Power Flash FPGAs

with Flash*Freeze Technology

Features and Benefits

Low Power

• Dramatic Reduction in Dynamic and Static Power Savings

• 1.2 V to 1.5 V Core and I/O V oltage Support for Low Power

• Low Power Consumption in Flash*Freeze Mode Allows for

Instantaneous Entry to / Exit from Low-Power Flash*Freeze

Mode

• Supports Single-Voltage System Operation

• Low-Impedance Switches

High Capacity

• 250,0 00 to 3,000,000 Sy s tem Ga t es

• Up to 50 4 kb i ts of True Dual- P ort SR AM

• Up to 620 User I/Os

Reprogrammable Flash Technology

• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS

Process

• Live-at-Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

• Retains Programmed Design when Powered Off

High Performance

• 350 MHz (1.5 V systems) and 250 MHz (1.2 V systems) System

Performance

• 3.3 V, 66 MHz, 66-Bit PCI (1.5 V system s) and 66 MHz, 32-Bit

PCI (1.2 V systems)

In-System Programming (ISP) and Security

• ISP Using On-Chip 128-Bit Advanced Encryption Standard

(AES) Decryption via JTAG (IEEE 1532–compliant)

• FlashLock® to Secure FPGA Contents

High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

• High-Per f or ma nce , Lo w-Sk ew Gl oba l Net wor k

• Architecture Supports Ultra-High Utilization

Advanced and Pro (Professional) I/Os

• 700 Mbps DDR, LVDS-Capable I/Os

• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—up to 8 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and

LVCMOS 2.5 V / 5.0 V Input

• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and

M-LVDS

• Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL

2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3

Class I and II (A3PE3000L only)

• Wide Range Power Supply Voltage Support per JESD8-B,

Allowing I/Os to Operate from 2.7 V to 3.6 V

• Wide Range Power Supply Voltage Support per JESD8-12,

Allowing I/Os to Operate from 1.14 V to 1.575 V

• I/O Registers on Input, Output, and Enable Paths

• Hot-Swappable and Cold-Sparing I/Os Programmable Output

Slew Rate and Drive Strength

• Programmable Input Delay (A3PE3000L only)

• Schmitt Trigger Option on Single-Ended Inputs (A3PE3000L)

• Weak Pull-Up/- Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the ProASIC®3L Family

(except PQ208)

Clock Conditioning Circuit (CCC) and PLL

• Six CCC Blocks, One with Integrate d PLL (ProASIC3L) and All

with Integrated PLL (ProASIC3EL)

• Configurable Phase Shift, Multiply/Divide, Delay Capabilities,

and External Feedback

• Wide Input Frequency Range 1.5 MHz to 250 MHz (1.2 V

systems) and 350 MHz (1.5 V systems))

SRAMs and FIFOs

• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,

and ×18 organizati on s ava i la b l e)

• T rue Dual-Port SRAM (except ×18)

• 24 SRAM and FIFO Configurations with Synchronous

Operation:

– 250 MHz: For 1.2 V systems

– 350 MHz: For 1.5 V systems

ARM® Processor Support in ProASIC3L FPGAs

• ARM Cortex™-M1 Soft Processor Available with or without

Debug

Table 1 • ProASIC3 Low-Power Product Family

ProASIC3L Devices A3P250L A3P600L A3P1000L A3PE3000L

ARM Cortex-M1

Devices 1M1A3P600L M1A3P1000L M1A3PE3000L

System Gates 250,000 600,000 1,000,000 3,000,000

VersaTiles (D-flip-flops) 6,144 13,824 24,576 75,264

RAM Kbits (1,024 bits) 36 108 144 504

4,608-Bit Blocks 82432112

FlashROM Kbits 1111

Secure (AES) ISP 2Yes Yes Yes Yes

Integrated PLL in CCCs 31116

VersaNet Globals 18 18 18 18

I/O Banks 4448

Maximum User I/Os 157 235 300 620

Package Pins

VQFP

PQFP

FBGA

VQ100

PQ208

FG144, FG256 PQ208

FG144, FG256, FG484 PQ208

FG144, FG256, FG484 PQ208 3

FG324, FG484, FG896

Notes:

1. Refer to the Cortex-M1 product brief for more information.

2. AES is not available for ARM Cortex-M1 ProASIC3L devices.

3. For the A3PE3000L, the PQ208 package has six CCCs and two PLLs.

Revision 10

ProASIC3L Low Power Flash FPGAs

II Revision 10

I/Os Per Package 1

ProASIC3L

Low-Power

Devices A3P250L 2A3P600L A3P1000L A3PE3000L

ARM

Cortex-M1

Devices M1A3P600L M1A3P1000L M1A3PE3000L 3

Package

I/O Type

Single-

Ended I/O 4Differential

I/O Pairs Single-

Ended I/O 4Differential

I/O Pairs Single-

Ended I/O 4Differential

I/O Pairs Single-

Ended I/O 4Differential

I/O Pairs

VQ1006813 –––––

PQ208 151 34 154 35 154 35 147 65

FG144 972497259725

FG256 157 38 177 43 177 44 – –

FG324 – – – – – – 221 110

FG484 – – 235 60 300 74 341 168

FG896 – – – – – – 620 310

Notes:

1. When considering migrating your design to a lower- or higher-density device, refer to the packaging section of the datasheet to ensure

you are complying with design and board migration requirements.

2. For A3P250L devices, the maximum number of LVPECL pairs in east and west banks cannot exceed 15.

3. ARM Cortex-M1 support is TBD on this device.

4. Each used differential I/O pair reduces the number of single-ended I/Os available by two.

5. FG256 and FG484 are footprint-compatible packages.

6. "G" indicates RoHS-compliant packages. Refer to "ProASIC3L Ordering Information" on page III for the location of the "G" in the part

number.

7. For A3PE3000L devices, the usage of certain I/O standards is limited as follows:

– SSTL3(I) and (II): up to 40 I/Os per north or south bank

– LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank

– SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank

8. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular I/O, the number of single-ended user

I/Os available is reduced by one.

Table 2 • ProASIC3L FPGAs Package Sizes Dimensions

Package VQ100 PQ208 FG144 FG256 FG324 FG484 FG896

Length × Width

(mm\mm) 14 × 14 28 × 28 13 × 13 17 × 17 19 × 19 23 × 23 31 × 31

Nominal Area

(mm2)196 784 169 289 361 529 961

Pitch (mm) 0.5 0.5 1.0 1.0 1.0 1.0 1.0

Height (mm) 1.00 3.40 1.45 1.60 1.63 2.23 2.23

ProASIC3L Low Power Flash FPGAs

Revision 10 III

ProASIC3L Ordering Information

Speed Grade

Blank = Standard

1 = 15% Faster than Standard

A3P1000L FG

Part Number

ProASIC3L Devices

Package Type

VQ =Very Thin Quad Flat Pack (0.5 mm pitch)

144 I

Package Lead Count

Lead-Free Packaging

Application (Temperature Range)

Blank = Commercial (0°C to +70°C Ambient Temperature)

I = Industrial (–40°C to +85°C Ambient Temperature)

Blank = Standard Packaging

G= RoHS-Compliant (Green) Packaging

250,000 System Gates

A3P250L =

600,000 System Gates

A3P600L =

1,000,000 System Gates

A3P1000L =

3,000,000 System Gates

A3PE3000L=

ProASIC3L Devices with Cortex-M1

600,000 System Gates

M1A3P600L =

1,000,000 System Gates

M1A3P1000L =

3,000,000 System Gates

M1A3PE3000L =

PQ =Plastic Quad Flat Pack (0.5 mm pitch)

FG =Fine Pitch Ball Grid Array (1.0 mm pitch)

Security Feature

Y = Device Includes License to Implement IP Based on the

Cryptography Research, Inc. (CRI) Patent Portfolio

ProASIC3L Low Power Flash FPGAs

IV Revision 10

Temperature Grade Offerings

Speed Grade and Temperature Grade Matrix

ProASIC3L Device Status

Contact your local Microsemi SoC Products Group representative for devi c e availability:

http://www.microsemi.com/soc/contact/default.aspx.

Package A3P250L A3P600L A3P1000L A3PE3000L

ARM Cortex-M1 Devices M1A3P600L M1A3P1000L M1A3PE3000L

VQ100 C, I – –

PQ208 C, IC, IC, IC, I

FG144 C, IC, IC, I

FG256 C, IC, IC, I

FG324 – – – C, I

FG484 – C, IC, IC, I

FG896 – – – C, I

Notes:

1. C = Commercial temperature range: 0°C to 70°C ambient temperature.

2. I = Industrial temperature range: –40°C to 85°C ambient temperature.

Temperature Grade Std. –1

C 1✓✓

I 2✓✓

Notes:

1. C = Commercial temperature range: 0°C to 70°C ambient temperature.

2. I = Industrial temperature range: –40°C to 85°C ambient temperature.

ProASIC3L Devices Status M1 ProASIC3L Devices Status

A3P250L Production

A3P600L Production M1A3P600L Production

A3P1000L Production M1A3P1000L Production

A3P3000L Production M1A3P3000L Production

ProASIC3L Low Power Flash FPGAs

Revision 10 V

Table of Content s

ProASIC3L Device Family Overview

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

ProASIC3L DC and Switching Characteristics

General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-120

Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-126

Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-131

Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-133

Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-147

JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-148

Pin Descriptions and Packaging

Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

Package Pin Assignments

VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

PQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

FG144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

FG256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19

FG324 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29

FG484 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34

FG896 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-50

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

Safety Critical, Life Support, and High -R eliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

Revision 10 1-1

1 – ProASIC3L Device Family Overview

General Description

The ProASIC3L family of Microsem i flash FPGAs dramatically re duces dynamic power consumption by

40% and static power by 50% compared to the equivalent ProASIC3 device. These power savings are

coupled with performance, density, true single-chip, 1.2 V to 1.5 V core and I/O operation as low as

1.2 V, reprogrammability, and advanced features.

Using Microsemi's proven Flash*Freeze technology enables users to shut off dynamic power

instantaneously and switch the device to static mode without the need to switch off clocks or power

supplies while retaining internal states of the device. This greatly simplifies power management on a

board done through I/Os and clocks. In addition, optimized software tools using power-driven layout

provide instant push-button power reduction.

Nonvolatile flash technology gives ProASIC3L devices the advantage of being a secure, low-power,

single-chip solution tha t is live at power-up (LAPU). ProASIC3L offers dramatic dynamic power savings

giving the FPGA users flexibility to combine low power with high performance.

These features enable designers to create high-density systems using existing ASIC or FPGA design

flows and tools.

ProASIC3L devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as

clock conditioning circuitry (CCC) based on an in tegrated phase-locked loop (PL L). ProASIC3L devices

support devices from 250 k system gates to 3 million system gates with up to 504 kbits of true dual-port

SRAM and 620 user I/Os.

M1 ProASIC3L devices support the high-performance, 32-bit Cortex-M1 processor developed by ARM

for implementation in FPGAs. ARM Cortex-M1 is a soft processor th at is fully impl emented in the FPGA

fabric. It has a three-stage pipeline that offers a good balance between low-power consumption and

speed when implemented in an M1 ProASIC3L device. The processor runs the ARMv6-M instruction set,

has a configurable nested interrupt controll er, a nd can be implemented with or without the debug block.

ARM Cortex-M1 is available for free from Microsemi for use in M1 ProASIC3L FPGAs.

The ARM-enabled devices have Microsemi SoC Products Group ordering numbers that begin with M1

and do not support AES decryption.

Flash*Freeze Technology

The ProASIC3L devices offer Micros emi's proven Flash*Freeze techn ology, which allows instantaneous

switching from an active state to a static state. ProASIC3 L devices do not need additional components to

turn off I/Os or clocks while retaining the design information, SRAM content, and registers. Flash*Freeze

technology is combined with in-system programmability, which enables users to quickly and easily

upgrade and update their designs in the final stages of manufacturing or in the field. The ability of

ProASIC3L devices to support a wide range core voltage (1.2 V to 1.5 V) allows for an even greater

reduction in power consumption, which enables low total system power.

When the ProASIC3L device enters Flash*Freeze mode, the device automatically shuts off the clocks

and inputs to the FPGA core; when the device exits Flash*Freeze mod e, all activity resu me s and da ta is

retained.

The availability of low-power modes, combined with a reprogrammable, single-chip, single-voltage

solution, make ProASIC3L devices suitable for low-power data transfer and manipulation in portable

media, secure communications, rad io applications as wel l as high performance portable, industrial, test,

scientific, and medical applications.

ProASIC3L Device Family Overview

1-2 Revision 10

Flash Advantages

Low Power

The ProASIC3L family of Microsemi flash-based FPGAs provide a low-power advantage, and when

coupled with high performance, enables designers to make power-smart choices using a single-chip,

reprogrammable, and live-at-pow er-up device.

ProASIC3L devices offer 40% dynamic power and 5 0% static power savings compared to the equiva lent

ProASIC3 device by reducing the core operating voltage to 1.2 V. In additi on, the Power Driven Layout

(PDL) feature in Libero® Integrated Design Environment (IDE) offers up to 30% additional power

reduction over the standard timing-driven place-and-route (TDPR). With Flash*Freeze technology,

ProASIC3L devices are able to retain device SRAM and logic while dynamic power is reduced to a

minimum, without the need to stop clock or power supplies. Combining these features provides a low-

power, feature-rich and high-performance solution.

Security

Nonvolatile, flash-based ProASIC3L devices do not require a boot PROM, so there is no vulnerable

external bitstream that can be easily copied. ProASIC3L devices incorporate FlashLock, which provi des

a unique combination of reprogrammability and design security without external overhead, advantages

that only an FPGA with nonvolatile flash programming can offer.

ProASIC3L devices utilize a 128-bit flash-based lock and a sep arate AES key to provide the highest level

of protection in the FPGA industry for programmed intellectual property and configuration data. In

addition, all FlashROM data in ProASIC3L devi ces c an be encrypted prior to loading, using the industry-

leading AES-128 (FIPS192) bit block cipher encryption standard. AES was adopted by the National

Institute of Standards and Technology (NIST) in 2000 and replaces the 197 7 DES standard. ProASIC3L

devices have a built-in AES decryption engine and a flash-based AES key that make them the most

comprehensive programmable logic device security solution available today. ProASIC3L devices with

AES-based security provide a high level of protection for remote field updates over public networks such

as the Internet, and are designed to ensure that valuable IP remains out of the hands of system

overbuilders, system cloners, and IP thieves. The contents of a programmed device cannot be read

back, although secure design verification is possible .

Security, built into the FPGA fabric, is an inherent component of the ProASIC3L family. The flash cells

are located beneath seven metal layers, and many device design and layout techniques have been used

to make invasive attacks extremely difficult. The ProASIC3L family, w ith FlashLock and AES security, is

unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected

with industry-standard security, making remote ISP possible. A ProASIC3L device provides the best

available security for programmable logic designs.

Single Chip

Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the

configuration data is an inherent part of the FPGA structu re, a nd no exte rnal configuratio n data needs to

be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based ProASIC3L FPGAs

do not require system configuration components such as EEPROMs or microcontrollers to load device

configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system

reliability.

Live at Power-Up

Flash-based ProASIC3L devices sup port Level 0 of the L APU classification standard. This featu re helps

in system component initialization, execution of critical tasks before the processor wakes up, setup and

configuration of memory blocks, clock generation, and bus activity management. The LAPU feature of

flash-based ProASIC3L devices greatly simplifies total system design and reduces total system cost,

often eliminating the n eed for CPLDs and clock generation PLL s. In addition, glitche s and brownouts in

system power will not corrupt the ProASIC3L device's flash configuration, and unlike SRAM-based

FPGAs, the device will not have to be reloaded when system power is restored. This enables the

reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout

detection, and clock generator devices from the PCB design. Flash-based ProASIC3L devices simplify

total system design and reduce cost and design risk while increasing system reliability and improving

system initialization time.

ProASIC3L Low Power Flash FPGAs

Revision 10 1-3

Reduced Cost of Ownership

Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-

based FPGAs, flash-based ProASIC3L devi ces allow all functionality to be live at power-up; no external

boot PROM is required. On-board security mechanisms prevent access to all the programming

information and enable secure remote updates of the FPGA logic. Designers can perform secure remote

in-system reprogramming to support future design iterations and field upgrades with confidence that

valuable intellectual property cannot be compromised or copied. Secure ISP can be performed using the

industry-standard AES algorithm. The ProASIC3L family device architecture mitigates the need for ASIC

migration at higher user vol umes. This makes the ProASIC3L family a cost-effective ASIC replacement

solution, manipulation in portable media and secure communications, radio appl ications as well as high

performance portable Industrial, test, scientific and medical applications.

Firm-Error Immunity

Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike

a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the

configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These

errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a

complete system failure. Firm errors do not exist in the configuration memory of ProASIC3L flash-based

FPGAs. Once it is programmed, the flash cell configuration element of ProASIC3L FPGAs cannot be

altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in

the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and

correction (EDAC) circuitry built into the FPGA fabric.

Advanced Flash Technology

The ProASIC3L family offers many benefits, including nonvolatility and reprogrammability, through an

advanced flash-based, 130-nm LVCMOS process with 7 layers of metal. Standard CMOS design

techniques are used to implement logic and control functions. The combination of fine granularity,

enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization

without compromising device routability or performance. Logic functions within the device are

interconnected through a four-level routing hierarchy.

Advanced Architecture

The proprietary ProASIC3L architecture provides granularity comparable to standard-cell ASICs. The

ProASIC3L device consists of five distinct and programmable architectural features (Figure 1-1 on

page 1-4 and Figure 1-2 on page 1-4):

• FPGA VersaTiles

• Dedicated FlashROM

• Dedicated SRAM/FIFO memory

• Extensive CCCs and PLLs

• I/O structure

The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic

function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch

interconnections. The versatility of the ProASIC3L core tile, as either a three-input lookup table (LUT)

equivalent or a D-flip-flop/latch with enable, allo ws for efficient use of the FPGA fabric.

The VersaTile capability is unique to the ProASIC family of third-generation-architecture flash FPGAs.

VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed

throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core

utilization is possible for virtually any design.

ProASIC3L Device Family Overview

1-4 Revision 10

Figure 1- 1 • ProASIC3L Device Ar c hitecture Overvie w with Four I/O Banks (A3P250L, A3P600L,

and A3P1000L)

Figure 1- 2 • ProASIC3EL Device Architecture Overview

ISP AES

Decryption* User Nonvolatile

FlashRom Flash*Freeze

Technology Charge

Pumps

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block

(A3P600L and A3P1000L)

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block

VersaTile

CCC

I/Os

Bank 0

Bank 3Bank 3

Bank 1Bank 1

Bank 2

4,608-Bit Dual-Port SRAM

or FIFO Block

VersaTile

RAM Block

CCC

Pro I/Os

4,608-Bit Dual-Port SRAM

or FIFO Block

RAM Block

ISP AES

Decryption* User Nonvolatile

FlashRom Flash*Freeze

Technology Charge

Pumps

ProASIC3L Low Power Flash FPGAs

Revision 10 1-5

Flash*Freeze Technology

The ProASIC3L devices offer Microsemi's proven Flash*Freeze tech nology, which enables designers to

instantaneously shut off dynamic power consumption while retaining all SRAM and register information.

Flash*Freeze technology enables the u ser to quickly (within 1 µs) enter and exit Fl ash*Freeze mode by

activating the Flash*Freeze (FF) pin while all power suppl ies are kept at their original values. In addition,

I/Os and global I/Os can still be driven and can be toggling without impact on power consumption; clocks

can still be driven or can be toggling without impact on power consumption; and the device retains all

core registers, SRAM information, an d states. I/O states are tristated during Flash*F reeze mode or can

be set to a certain state using weak pull-up or pull-down I/O attribute configuration. No power is

consumed by the I/O banks, clocks, JTAG pins, or PLL. Flash*Freeze technology allows the user to

switch to active mode on demand, thus simplifying the power management of the device.

The FF pin (active low) can be routed internall y to the core to allow the user's logic to decid e when it is

safe to transition to this mode. It is also possible to use the FF pin as a regular I/O if Flash*Fre eze mode

usage is not planned, which is advantageous because of the inherent low-power static and dynamic

capabilities of the ProASIC3L device. Refer to Figure 1-3 for an illustration of entering/exiting

Flash*Freeze mode.

VersaTiles

The ProASIC3L core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS® core

tiles. The ProASIC3L VersaTile supports the following:

• All 3-input logic functions—L UT-3 equivalent

• Latch with clear or set

• D-flip-flop with clear or set

• Enable D-flip-flop with clear or set

Refer to Figure 1-4 for VersaTile configurations.

Figure 1- 3 • ProASIC3L Flash*Freeze Mode

Figure 1- 4 • VersaTile Configurations

ProASIC3L

FPGA

Flash*Freeze

Mode Control

Flash*Freeze Pin

X1 Y

X3 LUT-3 Data Y

CLK

Enable

CLR

D-FF

Data Y

CLK

CLR D-FF

LUT-3 Equivalent D-Flip-Flop with Clear or Set Enable D-Flip-Flop with Clear or Set

ProASIC3L Device Family Overview

1-6 Revision 10

User Nonvolatile FlashROM

ProASIC3L devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can

be used in diverse system applications:

• Internet Protocol addressing (wireless or fixed)

• System calibration settings

• Device serialization and/or inventory control

• Subscription-based business models (for example, set-top boxes)

• Secure key storage for secure communications algorithms

• Asset management/tracking

• Date stamping

• Version management

The FlashROM is written using the standard ProASIC3L IEEE 1532 JTAG programming interface.The

core can be individually programmed (erased and written), and on-chip AES decryption can be used

selectively to securely load data over public networks, as in security keys stored i n the FlashROM for a

user design.

The FlashROM can be programmed via the JTAG progr amming interface, and its contents can be read

back either through the JTAG programmin g interface or via direct FPGA core addressing. Note that the

FlashROM can only be programmed from the JTAG interface and cannot be programmed from the

internal logic array.

The FlashROM is programmed as 8 banks of 128 bi ts; however, reading is performed on a byte-by-byte

basis using a synchronous interface. A 7-bit address from the FPGA core defin es which of the 8 banks

and which of the 16 byte s within that bank are being read. T he three most significa nt bits (MSBs) of the

FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM

address define the byte.

The ProASIC3L development software solutions, Libero IDE and Designer, have extensive support for

the FlashROM. One such feature is auto-generation of sequential programming files for applications

requiring a unique serial number in each part. Another feature allows the inclusion of static data for

system version control. Data for the FlashROM can be generated quickly and easily using Libero IDE

and Designer software tools. Comprehen si ve pr ogramming file sup port is also in clude d to all ow for easy

programming of large numbers of parts with differing FlashROM contents.

SRAM and FIFO

ProASIC3L devices have embedded SRAM blocks along their north and south sides. Each variable-

aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18, 512×9,

1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can be

configured with different bit widths on each port. For example, data can be sent through a 4-bit port a nd

read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port

(ROM emulation mode) using the UJTAG macro.

In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM

block to be con figured as a synchro nous FIFO with out using additi onal core VersaTiles. The FIFO width

and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and

Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control

unit contains the counters necessary for generation of the read and write address pointers. The

embedded SRAM/FIFO blocks can be cascaded to create larger configurations.

PLL and CCC

ProASIC3L devices provide designers with flexible clock conditioning circuit (CCC) capabilities. Each

member of the ProASIC3L family contains six CCCs. One CCC (center west side) has a PLL.

The six CCC blocks are located at the four corners and the centers of the east and west sides. One CCC

(center west side) has a PLL.

All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay

operations as well as clock spine access.

The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs

located near the CCC that have dedicated connections to the CCC block.

ProASIC3L Low Power Flash FPGAs

Revision 10 1-7

The CCC block has these key features:

• Wide input frequency range (fIN_CCC) = 1.5 MHz up to 250 MHz

• Output frequency range (fOUT_CCC) = 0.75 MHz up to 250 MHz

• 2 programmable delay typ es for clock skew minimization

• Clock frequency synthesis

Additional CCC specifications:

• Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider

configuration.

• Output duty cycle = 50% ± 1.5% or better

• Low output jitter: worst case < 2.5% × clock per iod peak-to-peak period jitter when single global

network used

• Maximum acquisition time is 300 µs

• Exceptional tolerance to input perio d jitter— allowable input jitter is up to 1.5 ns

• Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz /

fOUT_CCC

Global Clocking

ProASIC3L devices have extensive support for multiple clocking domains. In addition to the CCC and

PLL support described above, there is a comprehensive global clock distribution network.

Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant

global networks. The VersaNets can be driven by the CCC or directly accessed from the core via

multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid

distribution of high-fanout nets.

I/Os with Advanced I/O Standards

The ProASIC3L family of FPGAs features a fl exible I/O structure, supporting a range of voltages (1.2 V,

1.5 V, 1.8 V, 2.5 V, 3.0 V wide range, and 3.3 V). ProASIC3L FPGAs support different I/O standards,

including single-ended, differential, and voltage-referenced (ProASIC3EL only). The I/Os are organized

into banks, with two, four , or eight (ProASIC3EL only) banks per device. The configuration of these banks

determines the I/O standards supported (Table 1-1). For ProASIC3EL, each I/O bank is subdivided into

VREF minibanks, which are used by voltage-referenced I/Os. VREF minibanks contain 8 to 18 I/Os. All

the I/Os in a given minibank share a common VREF line. Therefore, if any I/O in a given VREF minibank

is configured as a VREF pin, the remaining I/Os in that minibank will be able to use that reference

voltage.

Each I/O module contains several input, output, and enable registers. These registers allow the

implementation of the following:

• Single-data-rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II)

• Double-data-Rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point

communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II).

ProASIC3L banks support LVPECL, LVDS, B-LVDS, and M-LVDS. B-LVDS and M-LVDS can support up

to 20 loads.

Table 1-1 • I/O Standards Supported

I/O Bank Type

Device and

Bank

Location

I/O Standard s Supported

LVTTL/

LVCMOS PCI/

PCI-X LVPECL, LVDS,

B-LVDS, M-LVDS

GTL+ 2.5 V/3.3 V, GTL

2.5 V/3.3 V, HSTL I and II,

SSTL2 I and II, SSTL3 I and II

Pro I/Os A3PE3000L ✓✓ ✓ ✓

Advanced I/Os A3P250L,

A3P600L,

A3P1000L

✓✓ ✓ Not supported

ProASIC3L Device Family Overview

1-8 Revision 10

Hot-swap (also called hot-pl ug, or hot-insertion ) is t he opera tion of h ot-insertion or hot-remova l of a card

in a powered-up system.

Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed

when the system is powered up, while the component itself is powered down, or when power supplies

are floating.

Wide Range I/O Support

ProASIC3L devices support JEDEC-define d wide range I/O opera tion. ProASIC3L devices support both

the JESD8-B specification, coverin g 3 V and 3.3 V supplies, for a n effective operati ng range of 2.7 V to

3.6 V, and JESD8-12 with its 1.2 V nominal, supporting an effective operating range of 1.14 V to 1.575 V.

Wider I/O range means d esigners can eli minate power suppl ies or powe r conditi oning comp onents from

the board or move to less costly components with greater tolerances. Wide range eases I/O bank

management and provides enhanced protection from system voltage spikes, while providing the flexibility

to easily run custom voltage applications.

Specifying I/O States During Programming

You can modify the I/O states during programming in Fl ash Pro . In F lashP ro, thi s fea tu re is sup ported for

PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information.

Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have

limited display of Pin Numbers only.

1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during

programming.

2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator

window appears.

3. Click the Specify I/O States During Programming button to display the Specify I/O States

During Programming dialog box.

4. Sort the pins as desired by clicking any of the column headers to sort the entries by that head er.

Select the I/Os you wish to modify (Figure 1-5 on page 1-9).

5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings

for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state

settings:

1 – I/O is set to drive out logic High

0 – I/O is set to drive out logic Low

Last Known State – I/O is set to the last value that was driven out prior to entering the

programming mode, and then held at that value during programming

Z -Tri-State: I/O is tristated

6. Click OK to return to the FlashPoint – Programming File Generator window.

Note: I/O States during programming are saved to the ADB and resulting programming files after

completing programming file generation.

ProASIC3L Low Power Flash FPGAs

Revision 10 1-9

Figure 1- 5 • I/O States During Programming Window

Revision 10 2-1

2 – ProASIC3L DC and Switching Characteristics

General Specifications

Operating Conditions

Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any

other conditions beyond those listed under the Recommended Operating Conditions specified in

Table 2-2 on page 2-2 is not implied.

Table 2-1 • Absolute Maximum Ratings

Symbol Parameter Limits Units

VCC DC core supply voltage –0.3 to 1.65 V

VJTAG JTAG DC voltage –0.3 to 3.75 V

VPUMP Programming voltage –0.3 to 3.75 V

VCCPLL Analog power supply (PLL) –0.3 to 1.65 V

VCCI and

VMV 3DC I/O buffer supply voltage –0.3 to 3.75 V

VI I/O input voltage –0.3 V to 3.6 V (when I/O hot insertion mode is enabled)

–0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower

(when I/O hot-in se rti o n mo de is di sa b le d )

TSTG 2Storage temperature –65 to +150 °C

TJ2Junction temperature +125 °C

Notes:

1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may

undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3.

2. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for recommended operating

limits, refer to Table 2-2 on page 2-2.

3. VMV pins must be connected to the corresponding VCCI pins. See the "Pin Descriptions" chapter in the ProASIC3L

FPGA Fabric User’s Guide for further information.

ProASIC3L DC and Switching Characteristics

2-2 Revision 10

Table 2-2 • Recommended Operating Cond itions 1

Symbol Parameter Commercial Industrial Units

TAAmbient temperature 0 to +70 –40 to +85 °C

TJJunction Temperature 0 to + 85 –40 to +100 °C

VCC 21.2 V–1.5 V wide range core voltage 1.14 to 1.575 1.14 to 1.575 V

VJTAG JTAG DC voltage 1.4 to 3.6 1.4 to 3.6 V

VPUMP 3Programming voltage Programming Mode 3.15 to 3.45 3.15 to 3.45 V

Operation 30 to 3.6 0 to 3.6 V

VCCPLL 6Analog power supply (PLL) 1.2 V–1.5 V wide range

core voltage 1.14 to 1.575 1.14 to 1.575 V

VCCI and

VMV 51.2 V DC supply voltage4 1.14 to 1.26 1.14 to 1.26 V

1.5 V DC supply voltage 1.425 to 1.575 1.425 to 1.575 V

1.8 V DC supply voltage 1.7 to 1.9 1.7 to 1.9 V

2.5 V DC supply voltage 2.3 to 2.7 2.3 to 2.7 V

3.3 V wide range DC supply voltage7 2.7 to 3.6 2.7 to 3.6 V

3.3 V DC supply voltage 3.0 to 3.6 3.0 to 3.6 V

LVDS differential I/O 2.375 to 2.625 2.375 to 2.625 V

LVPECL differential I/O 3.0 to 3.6 3.0 to 3.6 V

Notes:

1. All parameters representing voltages are measured with respect to GND unless otherwise specified.

2. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O

standard are given in Table 2-13 on page 2-10. VCCI should be at the same voltage within a given I/O bank.

3. VPUMP can be left floating during normal operation (not programming mode).

4. For ProASIC®3L devices, VCCI

≥

VCC.

5. VMV pins must be connected to the corresponding VCCI pins. See the "Pin Descriptions" chapter of the ProASIC3L

FPGA Fabric User’s Guide for further information.

6. VCCPLL pins should be tied to VCC pins. See the "Pin Descriptions" chapter of the ProASIC3L FPGA Fabric User’s

Guide for further information.

7. 3.3 V wide range is compliant to the JDEC8a specification and supports 3.0 V VCCI operation.

Table 2-3 • Flash Programmi ng Limits – Retention, Storage , and Operating Temperature1

Product

Grade

Programmin

Cycles Program Retention

(biased/unbiased) Maximum Storage

Temperature TSTG (°C) 2 Maximum Operating

Junction Temperature TJ (°C) 2

Commercial 500 20 years 110 100

Industrial 500 20 years 110 100

Notes:

1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.

2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating

conditions and absolute limits.

ProASIC3L Low Power Flash FPGAs

Revision 10 2-3

I/O Power-Up and Supply Voltage Thresholds for Power-On Reset

(Commercial and Industrial)

Sophisticated power-up management circuitry is designed into every ProASIC3 device. These circuits

ensure easy transition from the powered-off state to the powered-up state of the device. The many

different supplies can power up in any sequence with minimized current spikes or surges. In addition, the

I/O will be in a known state through the power-up sequence. The basic principl e is shown in Figure 2-1

on page 2-4 and Figure 2-2 on page 2-5.

There are five regions to consider during power-up.

ProASIC3 I/Os are activated only if ALL of the followi ng three conditions are met:

1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4 and

Figure 2-2 on page 2-5).

2. VCCI > VCC – 0.75 V (typical)

3. Chip is in the operating mode.

VCCI Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.2 V

Ramping down: 0.5 V < trip_point_down < 1.1 V

VCC Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.1 V

Ramping down: 0.5 V < trip_point_down < 1 V

VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically

built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:

• During programming, I/Os become tristated and weakly pulled up to VCCI.

• JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O

behavior.

Table 2-4 • Overshoot and Undershoot Limits 1

VCCI Average VCCI– GND Overshoot or Undershoot

Duration as a Percentage of Clock Cycle2Maximum Overshoot/

Undershoot2

2.7 V or less 10% 1.4 V

5% 1.49 V

3 V 10% 1.1 V

5% 1.19 V

3.3 V 10% 0.79 V

5% 0.88 V

3.6 V 10% 0.45 V

5% 0.54 V

Notes:

1. Based on reliability requirements at junction temperature at 85°C.

2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of

two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V.

3. This table does not provide PCI overshoot/undershoot limits.

ProASIC3L DC and Switching Characteristics

2-4 Revision 10

PLL Behavior at Brownout Condition

Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper powerup

behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout

activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1 and Figure 2-

2 on page 2-5 for more details).

When PLL power suppl y voltage and/or VCC levels dr op below th e VCC brownout l evels (0.75 V ± 0.25

V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/-Down

Behavior of Low-Power Flash Devices" chapter of the ProASIC3L FPGA Fabric User’s Guide for

information on clock and lock recovery.

Internal Power-Up Activation Sequence

1. Core

2. Input buffers

Output buffers, after 200 ns delay from input buffer activation.

Figure 2-1 • V5 Devices – I/O State as a Function of VCCI and VCC Voltage Levels

Region 1: I/O buffers are OFF

Region 2: I/O buffers are ON.

I/Os are functional (except differential inputs)

but slower because VCCI / VCC are below

specification. For the same reason, input

buffers do not meet VIH / VIL levels, and

output buffers do not meet VOH / VOL levels.

Min VCCI datasheet specification

voltage at a selected I/O

standard; i.e., 1.425 V or 1.7 V

or 2.3 V or 3.0 V

VCC

VCC = 1.425 V

Region 1: I/O Buffers are OFF

Activation trip point:

= 0.85 V ± 0.25 V

Deactivation trip point:

= 0.75 V ± 0.25 V

Activation trip point:

= 0.9 V ± 0.3 V

Deactivation trip point:

= 0.8 V ± 0.3 V

VCC = 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

I/Os meet the entire datasheet

and timer specifications for

speed, VIH / VIL, VOH / VOL,

etc.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential

but slower because VCCI

is below specification. For the

same reason, input buffers do not

meet VIH / VIL levels, and output

buffers do not meet VOH / VOL levels.

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

VCCI

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the VCC is below specification.

VCC = VCCI + VT

ProASIC3L Low Power Flash FPGAs

Revision 10 2-5

Figure 2-2 • V2 Devices – I/O State as a Function of VCCI and VCC Voltage Levels

Region 1: I/O buffers are OFF

Region 2: I/O buffers are ON.

I/Os are functional (except differential inputs)

but slower because VCCI/VCC are below

specification. For the same reason, input

buffers do not meet VIH/VIL levels, and

output buffers do not meet VOH/VOL levels.

Min VCCI datasheet specification

voltage at a selected I/O

standard; i.e., 1.14 V,1.425 V, 1.7 V,

2.3 V, or 3.0 V

VCC

VCC = 1.14 V

Region 1: I/O Buffers are OFF

Activation trip point:

= 0.85 V ± 0.2 V

Deactivation trip point:

= 0.75 V ± 0.2 V

Activation trip point:

= 0.9 V ± 0.15 V

Deactivation trip point:

= 0.8 V ± 0.15 V

VCC = 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

I/Os meet the entire datasheet

and timer specifications for

speed, VIH / VIL , VOH / VOL , etc.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential

but slower because VCCI is

below specification. For the

same reason, input buffers do not

meet VIH / VIL levels, and output

buffers do not meet VOH / VOL levels.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential inputs)

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

VCCI

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the VCC is below specification.

VCC = VCCI + VT

ProASIC3L DC and Switching Characteristics

2-6 Revision 10

Thermal Characteristics

Introduction

The temperature variable in the Designer software refers to the junction temperature, not the ambient

temperature. This is an important distinction becau se dynamic and static power consumption cause the

chip junction temperature to be higher than the ambient temperature.

EQ 1 can be used to calculate junction temperature.

TJ = Junction Temperature = ΔT + TA

EQ 1

where:

TA = Ambient Temperature

ΔT = Temperature gradient between junction (silicon) and ambient ΔT = θja * P

θja = Junction-to-ambient of the package. θja numbers are located in Table 2-5.

P = Power dissipation

Package Thermal Characteristics

The device junction-to-case thermal resistivity is θjc and the juncti on-to-ambient air thermal resistivity is

θja. The thermal characteristics for θja are shown for two air flow rates. The absolute maximum juncti on

temperature is 100°C. EQ 2 shows a sample calculation of the absolute maximum power dissipation

allowed for a 484-pin FBGA package at commercial temperature and in still air.

EQ 2

Maximum Power Allowed Max. junction temp. (°C) Max. ambient temp. (°C)–

θja(°C/W)

------------------------------------------------------------------------------------------------------------------------------------------ 100°C70°C–

20.5°C/W

------------------------------------- 1.463 W===

Table 2-5 • Package Thermal Resistivities

Package Type Device Pin Count θjc

θja

UnitsStill Air 200 ft./min. 500 ft./min.

Very Thin Quad Flat Pack (VQFP) All devices 100 10.0 35.3 29.4 27.1 C/W

Plastic Quad Flat Pack (PQFP) All devices 208 8.0 26.1 22.5 20.8 C/W

PQFP with embedded heatspreader All devices 208 3.8 16.2 13.3 11.9 C/W

Fine Pitch Ball Grid Array (FBGA) A3P250L 144 12.2 43.8 37.7 35.8 C/W

A3P600L 144 8.3 35.8 30.2 28.3 C/W

A3P1000L 144 6.3 31.6 26.2 24.2 C/W

A3P250L 256 12.0 38.6 34.7 33.0 C/W

A3P600L 256 8.5 32.0 27.5 25.8 C/W

A3P1000L 256 6.6 28.1 24.4 22.7 C/W

AGLE3000 324 TBD TBD TBD TBD C/W

A3P600L 484 9.5 27.5 21.9 20.2 C/W

A3P1000L 484 8.0 23.3 19.0 16.7 C/W

A3PE3000L 484 4.7 20.6 15.7 14.0 C/W

A3PE3000L 896 2.4 13.6 10.4 9.4 C/W

ProASIC3L Low Power Flash FPGAs

Revision 10 2-7

Temperature and Voltage Derating Factors

Calculating Power Dissipation

Quiescent Supply Current

Table 2-6 • Temperature and Voltage Derating Factors for Timi ng Delays

(normalized to TJ = 70°C, VCC = 1.14 V)

Array Voltage VCC (V)

Junction Temperature (°C)

–40°C 0°C 25°C 70°C 85°C 110°C

1.14 0.90 0.94 0.96 1.00 1.01 1.03

1.2 0.870.900.920.960.970.99

1.26 0.83 0.86 0.88 0.92 0.93 0.85

1.3 0.810.840.860.900.910.93

1.35 0.78 0.81 0.83 0.87 0.88 0.89

1.4 0.750.780.800.830.840.86

1.425 0.74 0.77 0.78 0.82 0.83 0.85

1.5 0.700.720.740.770.790.80

1.575 0.67 0.70 0.72 0.75 0.76 0.77

Table 2-7 • Quiescent Supply Current (IDD) Characte ristics, ProASIC3L Flash*Freeze Mode*

Core Voltage A3P250L A3P600L A3P1000L A3PE3 000L Units

Typical (25°C) 1.2 V 0.33 0.55 0.88 2.75 mA

1.5 V 0.5 0.83 1.33 4.2 mA

Note: *IDD includes VCC, VPUMP, VCCI, VJTAG , and VCCPLL currents. Values do not include I/O static

contribution (PDC6 and PDC7).

Table 2-8 • Quiescent Supply Current (IDD) Characteristics, ProASIC3L Sleep Mode (VCC = 0 V)*

Core Voltage A3P250L A3P600L A3P1000L A3PE3000L Units

VCCI / VJTAG = 1.2 V (per bank)

Typical (25°C) 1.2 V / 1.5 V 1.7 1.7 1.7 1.7 µA

VCCI / VJTAG = 1.5 V (per bank)

Typical (25°C) 1.2 V / 1.5 V 1.8 1.8 1.8 1.8 µA

VCCI / VJTAG = 1.8 V (per bank)

Typical (25°C) 1.2 V / 1.5 V 1.9 1.9 1.9 1.9 µA

VCCI / VJTAG = 2.5 V (per bank)

Typical (25°C) 1.2 V / 1.5 V 2.2 2.2 2.2 2.2 µA

VCCI / VJTAG = 3.3 V (per bank)

Typical (25°C) 1.2 V / 1.5 V 2.5 2.5 2.5 2.5 µA

Note: *IDD includes VCC , VPUMP, and VCCPLL currents. Values do not include I/O static contribution (PDC6 and

PDC7).

Table 2-9 • Quiescent Supply Current (IDD) Characte ristics, Shutdown Mode (VCC, VCCI = 0 V)*

Core Voltage A3PE3000L Units

Typical (25°C) 1.2 V / 1.5 V 0 µA

Note: *IDD includes VCC , VPUMP, VCCI, VJTAG, and VCCPLL currents. Values do not include I/O static

contribution (PDC6 and PDC7).

ProASIC3L DC and Switching Characteristics

2-8 Revision 10

Table 2-10 • Quiescent Supply Current (IDD), No Flash*Freeze Mode1

Core Voltage A3P250L A3P600L A3P1000L A3PE3000L Units

ICCA Current2

Typical (25°C) 1.2 V 0.33 0.55 0.88 2.75 mA

1.5 V 0.5 0.83 1.33 4.2 mA

ICCI or IJTAG Current3, 4

VCCI / VJTAG = 1.2 V (per bank)

Typical (25°C) 1.2 V / 1.5 V 1.7 1.7 1.7 1.7 µA

VCCI / VJTAG = 1.5 V (per bank)

Typical (25°C) 1.2 V / 1.5 V 1.8 1.8 1.8 1.8 µA

VCCI / VJTAG = 1.8 V (per bank)

Typical (25°C) 1.2 V / 1.5 V 1.9 1.9 1.9 1.9 µA

VCCI / VJTAG = 2.5 V (per bank)

Typical (25°C) 1.2 V / 1.5 V 2.2 2.2 2.2 2.2 µA

VCCI / VJTAG = 3.3 V (per bank)

Typical (25°C) 1.2 V / 1.5 V 2.5 2.5 2.5 2.5 µA

Notes:

1. To calculate total device IDD, multiply the number of banks used by ICCI and add ICCA contribution.

2. Includes VCC , VCCPLL, and VPUMP currents.

3. Per VCCI or VJTAG bank.

4. Values do not include I/O static contribution (PDC6 and PDC7).

ProASIC3L Low Power Flash FPGAs

Revision 10 2-9

Power per I/O Pin

Table 2-11 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings

Applicable to Pro I/O Banks

VCCI (V) Static Power

PDC6 (mW)1Dynamic Power

PAC9 (µW/MHz)2

Single-Ended

3.3 V LVTTL/LVCMOS 3.3 – 16.34

3.3 V LVTTL/LVCMOS – Schmitt trigger 3.3 – 24.49

2.5 V LVCMOS 2.5 – 4.71

2.5 V LVCMOS – Schmitt trigger 2.5 – 6.13

1.8 V LVCMOS 1.8 – 1.66

1.8 V LVCMOS – Schmitt trigger 1.8 – 1.78

1.5 V LVCMOS (JESD8-11) 1.5 – 1.01

1.5 V LVCMOS (JESD8-11) – Schmitt trigger 1.5 – 0.97

1.2 V LVCMOS 1.2 – 0.60

1.2 V LVCMOS – Schmitt tri g ge r 1.2 – 0.53

3.3 V PCI 3.3 – 17.76

3.3 V PCI – Schmitt trigger 3.3 – 19.10

3.3 V PCI-X 3.3 – 17.76

3.3 V PCI-X – Schmitt trigger 3.3 – 19.10

Voltage-Referenced

3.3 V GTL 3.3 2.90 7.07

2.5 V GTL 2.5 2.13 3.62

3.3 V GTL+ 3.3 2.81 2.97

2.5 V GTL+ 2.5 2.57 2.55

HSTL (I) 1.5 0.17 0.85

HSTL (II) 1.5 0.17 0.85

SSTL2 (I) 2.5 1.38 3.30

SSTL2 (II) 2.5 1.38 3.30

SSTL3 (I) 3.3 3.21 8.08

SSTL3 (II) 3.3 3.21 8.08

Differential

LVDS 2.5 2.26 0.95

LVPECL 3.3 5.71 1.62

Notes:

1. PDC6 is the static power (where applicable) measured on VCCI.

2. PAC9 is the total dynamic power measured on VCCI.

ProASIC3L DC and Switching Characteristics

2-10 Revision 10

Table 2-12 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings1

Applicable to Advanced I/O Ban ks

VCCI (V) Static Power

PDC6 (mW)2Dynamic Power

PAC10 (µW/MHz)3

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS 3.3 – 16.22

2.5 V LVCMOS 2.5 – 4.65

1.8 V LVCMOS 1.8 – 1.65

1.5 V LVCMOS (JESD8-11) 1.5 – 0.98

1.2 V LVCMOS 1.2 – 0.61

3.3 V PCI 3.3 – 17.64

3.3 V PCI-X 3.3 – 17.64

Differential

LVDS 2.5 2.26 0.95

LVPECL 3.3 5.72 1.63

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output slew.

2. PDC6 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCCI.

Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings

Applicable to Standard Plus I/O Banks

VCCI (V) Static Power

PDC6 (mW)1Dynamic Power

PAC9 (µW/MHz)2

Single-Ended

3.3 V LVTTL /

3.3 V LVCMOS 3.3 – 16.23

2.5 V LVCMOS 2.5 – 4.66

1.8 V LVCMOS 1.8 – 1.64

1.5 V LVCMOS (JESD8-11) 1.5 – 0.99

1.2 V LVCMOS 1.2 – 0.58

3.3 V PCI 3.3 – 17.64

3.3 V PCI-X 3.3 – 17.64

Notes:

1. PDC6 is the static power (where applicable) measured on VCCI.

2. PAC9 is the total dynamic power measured on VCCI.

ProASIC3L Low Power Flash FPGAs

Revision 10 2-11

Table 2-14 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings 1

Applicable to Pro I/Os

CLOAD (pF) VCCI (V) Static Power

PDC7 (mW)2Dynamic Power

PAC10 (µW/MHz)3

Single-Ended

3.3 V LVTTL/LVCMOS 5 3.3 – 148.00

2.5 V LVCMOS 5 2.5 – 83.23

1.8 V LVCMOS 5 1.8 – 54.58

1.5 V LVCMOS (JESD8-11) 5 1.5 – 37.05

1.2 V LVCMOS 5 1.2 – 17.94

3.3 V PCI 10 3.3 – 204.61

3.3 V PCI-X 10 3.3 – 204.61

Voltage-Referenced

3.3 V GTL 10 3.3 – 24.08

2.5 V GTL 10 2.5 – 13.52

3.3 V GTL+ 10 3.3 – 24.10

2.5 V GTL+ 10 2.5 – 13.54

HSTL (I) 20 1.5 7.08 2 6.22

HSTL (II) 20 1.5 13.88 27.22

SSTL2 (I) 30 2.5 16.69 105.56

SSTL2 (II) 30 2.5 25.91 116.60

SSTL3 (I) 30 3.3 26.02 114.87

SSTL3 (II) 30 3.3 42.21 131.76

Differential

LVDS – 2.5 7.70 89.62

LVPECL – 3.3 19.42 168.02

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output slew.

2. PDC7 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCCI.

ProASIC3L DC and Switching Characteristics

2-12 Revision 10

Table 2-15 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings 1

Applicable to Advanced I/O Ban ks

CLOAD (pF) VCCI (V) Static Power

PDC7 (mW)2Dynamic Power

PAC10 (µW/MHz)3

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS 5 3.3 – 141.97

2.5 V LVCMOS 5 2.5 – 79.98

1.8 V LVCMOS 5 1.8 – 52.26

1.5 V LVCMOS (JESD8-11) 5 1.5 – 35.62

1.2 V LVCMOS 5 1.2 – 21.29

3.3 V PCI 10 3.3 – 201.02

3.3 V PCI-X 10 3.3 – 201.02

Differential

LVDS – 2.5 7.74 89.71

LVPECL – 3.3 19.54 167.54

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output slew.

2. PDC7 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCCI.

Table 2-16 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings 1

Applicable to Standard Plus I/O Banks

CLOAD (pF) VCCI (V) Static Power

PDC7 (mW)2Dynamic Power

PAC10 (µW/MHz)3

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS 5 3.3 – 125.97

2.5 V LVCMOS 5 2.5 – 70.82

1.8 V LVCMOS 5 1.8 – 36.39

1.5 V LVCMOS (JESD8-11) 5 1.5 – 25.34

1.2 V LVCMOS 5 1.2 – 16.24

3.3 V PCI 10 3.3 – 184.92

3.3 V PCI-X 10 3.3 – 184.92

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output slew.

2. PDC7 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCCI.

ProASIC3L Low Power Flash FPGAs

Revision 10 2-13

Power Consumption of Various Internal Resources

Table 2-17 • Different Components Contributing to Dynamic Power Consumption in ProASIC3L Devices at

1.2 V VCC

Parameter Definition

Device S pe c ific Dynamic Power (µW/MHz)

A3PE3000L A3P1000L A3P600L A3P250L

PAC1 Clock contribution of a Global Rib 12.61 9.28 8.19 7.07

PAC2 Clock contribution of a Global Spine 2.66 1.59 1.19 1.01

PAC3 Clock contribution of a VersaTile row 0.56 0.52

PAC4 Clock contribution of a VersaTile used as a sequential

module 0.07

PAC5 First contribution of a VersaTile used as a sequential

module 0.05

PAC6 Second contribution of a VersaTile used as a sequential

module 0.19

PAC7 Contribution of a VersaTile used as a combinatorial

Module 0.11

PAC8 Average contribution of a routing net 0.45

PAC9 Contribution of an I/O input pin (standard-dependent) See Table 2-11 on page 2-9. th rough

Table 2-13 on page 2-10.

PAC10 Contribution of an I/O output pin (standard-dependent) See Table 2-14 on page 2-11 through

Table 2-16 on page 2-12.

PAC11 Average contribution of a RAM block during a read

operation 25.00

PAC12 Average contribution of a RAM block during a write

operation 30.00

PAC13 Dynamic contribution for PLL 1.74

Note: *For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power

spreadsheet calculator or SmartPower tool in Libero IDE.

ProASIC3L DC and Switching Characteristics

2-14 Revision 10

Table 2-18 • Different Components Contributing to Dynamic Power Consumption in ProASIC3L Devices at

1.5 V VCC

Parameter Definition

Device Specific Dynamic Power (µW/MHz)

A3PE3000L A3P1000L A3P600L A3P250L

PAC1 Clock contribution of a Global Rib 19.7 14.50 12.80 11.00

PAC2 Clock contribution of a Global Spine 4.16 2.48 1.85 1.58

PAC3 Clock contribution of a VersaTile row 0.88 0.81

PAC4 Clock contribution of a VersaTile used as a sequential

module 0.12

PAC5 First contribution of a VersaTile used as a sequential

module 0.07

PAC6 Second contribution of a VersaTile used as a sequential

module 0.29

PAC7 Contribution of a VersaTile used as a combinatorial

Module 0.29

PAC8 Average contribution of a routing net 0.70

PAC9 Contribution of an I/O in put pin (standard-dependent) See Table 2-11 on page 2-9. through

Table 2-13 on page 2-10.

PAC10 Contribution of an I/O output pin (standard-dependent) See Table 2-14 on page 2-11 through

Table 2-16 on page 2-12.

PAC11 Average contribution of a RAM block during a read

operation 25.00

PAC12 Average contribution of a RAM block during a write

operation 30.00

PAC13 Dynamic contribution for PLL 2.60

Note: *For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power

spreadsheet calculator or SmartPower tool in Libero IDE.

Table 2-19 • Different Components Contributing to the Static Power Consumption in ProASIC3L Devices

Parameter Definition

Device S pe c ific Dynamic Power (µW)

A3PE3000L A3P1000L A3P600L A3P250L

PDC1 Array static power in Active mode See Table 2-10 on page 2-8.

PDC2 Array static power in St atic (Idle) mode See Table 2-8 on page 2-7.

PDC3 Array static power in Flash*Freeze mode See Table 2-7 on page 2-7.

PDC4 Static PLL contribution at 1.2 V co re (ope rati ng mod e

only) 1.42 mW

Static PLL contribution at 1.5 V core (operati ng mod e

only) 2.55 mW

PDC5 Bank quiescent powe r (VCCI-dependent) See Table 2-7 on page 2-7, Table 2-8 on

page 2-7, Table 2-10 on page 2-8.

PDC6 I/O input pin static power (standard-dependent) See Table 2-11 on pa g e 2-9 through

Tabl e 2-13 on page 2-10.

PDC7 I/O output pin static power (standard-dependent) See Table 2-14 on page 2-11 through

Tabl e 2-16 on page 2-12.

Note: *For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power

spreadsheet calculator or SmartPower tool in Libero IDE.

ProASIC3L Low Power Flash FPGAs

Revision 10 2-15

Power Calculation Methodology

This section describes a simplified method to estimate power consumption of an application. For more

accurate and detailed power estimations, use the SmartPower tool in Libero IDE software.

The power calculation methodology described below uses the following variables:

• The number of PLLs as well as the number and the frequency of each output clock generated

• The number of combinatorial an d sequential cells used in the design

• The internal clock frequencies

• The number and the standard of I/O pins used in the design

• The number of RAM blocks used in the design

• Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-20 on

page 2-17.

• Enable rates of output buffers—guidelines are provided for typical applications in Table 2-21 on

page 2-17.

• Read rate and write rate to the memory—guidelines are provided for typical applications in

Table 2-21 on page 2-17. The calculation should be repeated for each clock domain defined in the

design.

Methodology

Total Power Consumption—PTOTAL

PTOTAL = PSTAT + PDYN

PSTAT is the total static power consumption.

PDYN is the total dynamic power consumption.

Total Static Power Consumption—PSTAT

PSTAT = (PDC1 or PDC2 or PDC3) + NBANKS* PDC5 + NINPUTS* PDC6 + NOUTPUTS* PDC7

NINPUTS is the number of I/O input buffers used in the design.

NOUTPUTS is the number of I/O output buffers used in the design.

NBANKS is the number of I/O banks powered in the design.

Total Dynamic Power Consumption—PDYN

PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL

Global Clock Contribution—PCLOCK

PCLOCK = (PAC1 + NSPINE * PAC2 + NROW * PAC3 + NS-CELL * PAC4) * FCLK

NSPINE is the number of global spines used in the user design—guidelines are provided in

the "Spine Architecture" section of the ProASIC3L FPGA Fabric User’s Guide.

NROW is the number of VersaTile rows us ed in the design—guidelines are provided in the

"Spine Architectu re" section of the ProASIC3L FPGA Fabric User’s Guide.

FCLK is the global clock signal frequency.

NS-CELL is the number of VersaTiles used as sequential modules in the design.

PAC1, PAC2, PAC3, and PAC4 are device-dependent.

Sequential Cells Contribution—PS-CELL

PS-CELL = NS-CELL * (PAC5 + α1 / 2 * PAC6) * FCLK

NS-CELL is the number of VersaTiles used as sequential modules in the design. When a

multi-tile sequential cell is used, it should be accounted for as 1.

α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-20 on

page 2-17.

FCLK is the global clock signal frequency.

ProASIC3L DC and Switching Characteristics

2-16 Revision 10

Combinatorial Cells Contribution—PC-CELL

PC-CELL = NC-CELL* α1 / 2 * PAC7 * FCLK

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.

α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-20 on

page 2-17.

FCLK is the global clock signal frequency.

Routing Net Contribution—PNET

PNET = (NS-CELL + NC-CELL) * α1 / 2 * PAC8 * FCLK

NS-CELL is the number of VersaTiles used as sequential modules in the design.

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.

α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-20 on

page 2-17.

FCLK is the global clock signal frequency.

I/O Input Buffer Contribution—PINPUTS

PINPUTS = NINPUTS * α2 / 2 * PAC9 * FCLK

NINPUTS is the number of I/O input buffers used in the design.

α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-20 on page 2-17 .

FCLK is the global clock signal frequency.

I/O Output Buffer Contribution—POUTPUTS

POUTPUTS = NOUTPUTS * α2 / 2 * β1 * PAC10 * FCLK

NOUTPUTS is the number of I/O output buffers used in the design.

α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-20 on page 2-17 .

β1 is the I/O buffer enable rate—guidelines are provided in Table 2-21 on page 2-17.

FCLK is the global clock signal frequency.

RAM Contribution—PMEMORY

PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * β2 + PAC12 * NBLOCK * FWRITE-CLOCK * β3

NBLOCKS is the number of RAM blocks used in the design.

FREAD-CLOCK is the memory read clock frequency.

β2 is the RAM enable rate for read operations.

FWRITE-CLOCK is the memory write clock frequency.

β3 is the RAM enable rate for write operations—guidelines are provided in Table 2-21 on

page 2-17.

PLL Contribution—PPLL

PPLL = PDC4 + PAC13 * FCLKOUT

FCLKOUT is the output clock frequency.1

1. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its

corresponding contribution (PAC13* FCLKOUT product) to the total PLL contribution.

ProASIC3L Low Power Flash FPGAs

Revision 10 2-17

Guidelines

Toggle Rate Definition

A toggle rate defines the freque ncy of a net or logic elem ent relative to a clock. It is a percentage. If the

toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are

some examples:

• The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the

clock frequency.

• The average toggle rate of an 8-bit counter is 25%:

– Bit 0 (LSB) = 100%

– Bit 1 = 50%

– Bit 2 = 25%

–…

– Bit 7 (MSB) = 0.78125%

– Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8

Enable Rate Definition

Output enable rate is the average percentage of time during which tristate outputs are enabled. When

nontristate output buffers are used, the enable rate should be 100%.

Table 2-20 • Toggle Rate Guidelines Recommended for Power Calculation

Component Definition Guideline

α1Toggle rate of VersaTile outputs 10%

α2I/O buffer toggle rate 10%

Table 2-21 • Enable Rate Guidelines Recommended for Power Calculation

Component Definition Guideline

β1I/O output buffer enable rate 100%

β2RAM enable rate for read operati ons 12.5%

β3RAM enable rate for write operations 12.5%

ProASIC3L DC and Switching Characteristics

2-18 Revision 10

User I/O Characteristics

Timing Model

Figure 2-3 • Timing Model

Operating Conditions: –1 Speed, Commercial Temperature Range (TJ = 70°C), Worst-Case

VCC =1.14V

DQ DQ

Combinational Cell

I/O Module

(Registered)

I/O Module

(Non-Registered)

(Registered)

I/O Module

(Non-Registered)

LVPECL (Applicable to

Advanced I/O Banks Only)L

LVPECL

(Applicable

to Advanced

I/O Banks only)

LVDS,

BLVDS,

M-LVDS

(Applicable for

Advanced I/O

Banks only)

LVTTL 3.3 V Output drive

strength = 12 mA High slew rate

Combinational Cell

I/O Module

(Non-Registered)

LVTTLOutput drive strength = 8 mA

High slew rate

I/O Module

(Non-Registered)

LVCMOS 1.5 VOutput drive strength = 4 mA

High slew rate

LVTTLOutput drive strength = 12 mA

High slew rate

I/O Module

(Non-Registered)

Input LVTTL

Clock

Input LVTTL

Clock

Input LVTTL

Clock

= 0.56 ns t

= 0.49 ns t

= 1.34 ns

= 0.87 ns t

= 2.64 ns (Advanced I/O Banks)

= 0.47 ns t

= 3.66 ns (Advanced I/O Banks)

= 0.47 ns t

= 3.97 ns (Advanced I/O Banks)

= 0.47 ns

= 0.76 ns

(Advanced I/O Banks)

CLKQ

= 0.55 ns t

OCLKQ

= 0.59 ns

SUD

= 0.43 ns t

OSUD

= 0.31 ns

= 2.64 ns

(Advanced I/O Banks)

= 0.76 ns (Advanced I/O Banks)

= 1.20 ns

CLKQ

= 0.55 ns

SUD

= 0.43 ns

= 0.76 ns

(Advanced I/O Banks)

ICLKQ

= 0.24 ns

ISUD

= 0.26 ns

= 1.05 ns

ProASIC3L Low Power Flash FPGAs

Revision 10 2-19

Figure 2-4 • Input Buffer Timing Model and Delays (example)

tPY

(R)

PAD

Vtrip

GND tPY

(F)

Vtrip

50%

VIH

VCC

VIL

tDIN

(R)

DIN

GND tDIN

(F)

50%50% VCC

PAD Y

tPY

CLK

I/O Interface

DIN

tDIN

To Array

tPY = MAX(tPY(R), tPY(F))

tDIN = MAX(tDIN(R), tDIN(F))

ProASIC3L DC and Switching Characteristics

2-20 Revision 10

Figure 2-5 • Output Buffer Model and Delays (example)

tDP

(R)

PAD VOL

tDP

(F)

Vtrip

VOH

VCC

D50% 50%

VCC

0 V

DOUT 50% 50% 0 V

tDOUT

(R) tDOUT

(F)

From Array

PAD

tDP

Std

Load

CLK

I/O Interface

DOUT

tDOUT

tDP = MAX(tDP(R), tDP(F))

tDOUT = MAX(tDOUT(R), tDOUT(F))

ProASIC3L Low Power Flash FPGAs

Revision 10 2-21

Figure 2-6 • Tristate Output Buffer Timing Model and Delays (example )

CLK

10% V

CCI

Vtrip

50%

90% VCCI

Vtrip

50% 50% t

50%

EOUT

PAD

E50%

EOUT (R)

50%t

EOUT (F)

PAD

DOUT

EOUT

I/O Interface

EOUT

ZLS

Vtrip

50%

ZHS

Vtrip

50%

EOUT

PAD

E50% 50%

EOUT (R)

EOUT (F)

50%

VCC

VCCI

VCC

VOH

VOL

, t

ZLS

, t

ZHS

EOUT

= MAX(t

EOUT

(r), t

EOUT

(f))

ProASIC3L DC and Switching Characteristics

2-22 Revision 10

Overview of I/O Performance

Summary of I/O DC Input and Output Levels – Default I/O Software

Settings

Table 2-22 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions—Software Default Settings

Applicable to Pro I/O Banks

I/O Standard

Drive

Strength

(mA)

Equiv.

Software

Default

Drive

Strength

Option1Slew

Rate

VIL VIH VOL VOH IOL3IOH3

Min.

VMax.

VMin.

VMax.2

VMax.

VMin.

VmAmA

3.3 V LVTTL /

3.3 V

LVCMOS

12 mA 12 mA High –0.3 0.8 2 3.6 0.4 2.4 12 12

3.3 V

LVCMOS

Wide Range4

100 µA 12 mA High –0.3 0.8 2 3.6 0.2 VCCI – 0.2 0.1 0.1

2.5 V

LVCMOS 12 mA 12 mA High –0.3 0.7 1.7 2.7 0.7 1.7 12 12

1.8 V

LVCMOS 12 mA 12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 12 12

1.5 V

LVCMOS 12 mA 12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12 12

1.2 V

LVCMOS 2 mA 2 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI 2 2

1.2 V

LVCMOS

Wide Range5

100 µA 2 mA High –0.3 0.3 * VCC I 0.7 * VCCI 1.575 0.1 VCCI – 0. 1 0.1 0.1

3.3 V PCI Per PCI Specification

3.3 V PCI-X Per PCI-X Specification

3.3 V GTL 25 mA6 20 m65High –0.3 VREF – 0.05 VREF + 0.05 3.6 0.4 – 25 25

2.5 V GTL 25 mA620 mA6High –0.3 VREF – 0.05 VREF + 0.05 2.7 0.4 – 25 25

3.3 V GTL+ 35 mA 35 mA High –0.3 VREF – 0.1 VREF + 0.1 3.6 0.6 – 51 51

2.5 V GTL+ 33 mA 33 mA High –0.3 VREF – 0.1 VREF + 0.1 2.7 0.6 – 40 40

HSTL (I) 8 mA 8 mA High –0.3 VREF – 0. 1 VREF + 0.1 1.575 0.4 VCCI – 0.4 8 8

HSTL (II) 15 mA5 15 mA5 High –0.3 VREF – 0.1 VREF + 0.1 1.575 0.4 VCCI – 0.4 15 15

SSTL2 (I) 15 mA 15 mA High –0.3 VREF – 0.1 VREF + 0.1 2.7 0.54 VCCI – 0.62 15 15

SSTL2 (II) 18 mA 18 mA High –0.3 VREF – 0.1 VREF + 0.1 2.7 0.35 VCCI – 0.43 18 18

SSTL3 (I) 14 mA 14 mA High –0.3 VREF – 0.1 VREF + 0.1 3.6 0.7 VCCI – 1.1 14 14

SSTL3 (II) 21 mA 21 mA High –0.3 VREF – 0.1 VREF + 0.1 3.6 0.5 VCCI – 0.9 21 21

Notes:

1. Please note that 1.2V LVCMOS and 3.3V LVCMOS wide range is applicable to 100uA drive strength only. The

configuration will NOT operate at the equivalent software.

2. Maximum VIH is 3.6 V for all I/O standards with hot-insertion is enabled.

3. Currents are measured at 85°C junction temperature.

4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

5. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.

6. Output drive strength is below JEDEC specification.

7. Output slew rate can be extracted using the IBIS models.

ProASIC3L Low Power Flash FPGAs

Revision 10 2-23

Table 2-23 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions—Software Default Settings

Applicable to Advanced I/O Ban ks

I/O Standard Drive

Strength

Equiv.

Software

Default

Drive

Strength

Option1Slew

Rate

VIL VIH VOL VOH IOL2IOH2

Min.

VMax.

VMin.

VMax.

VMin.

VmAmA

3.3 V LVTTL /

3.3 V

LVCMOS

12 mA 12 mA High –0.3 0.8 2 3.6 0.4 2.4 12 12

3.3 V

LV CM OS Wi de

Range3

100 µA 12 mA High –0.3 0.8 2 3.6 0.2 VCCI – 0.2 0.1 0.1

2.5 V

LVCMOS 12 mA 12 mA High –0.3 0.7 1.7 2.7 0.7 1.7 12 12

1.8 V

LVCMOS 12 mA 12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 12 12

1.5 V

LVCMOS 12 mA 12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12 12

1.2 V

LVCMOS 2 mA 2 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI 2 2

1.2 V

LVCMOS

Wide Range4,5

100 µA 2 mA High –0.3 0.3 * VCCI 0.7 * VCCI 1.575 0.1 VCCI – 0.1 0.1 0.1

3.3 V PCI Per PCI specifications

3.3 V PCI-X Per PCI-X specifications

Notes:

1. Please note that 1.2V LVCMOS and 3.3V LVCMOS wide range is applicable to 100 µA drive strength only. The

configuration will NOT operate at the equivalent software.

2. Currents are measured at 85°C junction temperature.

3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

4. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.

5. Applicable to devices operating at VCCI ≥ VCC.

6. Output slew rate can be extracted using the IBIS models.

ProASIC3L DC and Switching Characteristics

2-24 Revision 10

Table 2-24 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions—Software Default Settings

Applicable to Standard Plus I/O Banks

I/O Standard Drive

Strength

Equiv.

Software

Default

Drive

Strength

Option1Slew

Rate

VIL VIH VOL VOH IOL2IOH2

Min.

VMax.

VMin.

VMax.

VMin.

VmAmA

3.3 V LVTTL /

3.3 V LVCMOS 12 mA 12 mA High –0.3 0.8 2 3.6 0.4 2.4 12 12

3.3 V LVCMOS

Wide Range3100 µA 12 mA High –0.3 0.8 2 3.6 0.2 VCCI – 0.2 0.1 0.1

2.5 V LVCMOS 12 mA 12 mA High –0.3 0.7 1.7 2.7 0.7 1.7 12 12

1.8 V LVCMOS 8 mA 8 mA High –0.30.35 * VCC I 0.65 * VCCI 1.9 0.45 VCCI – 0.45 8 8

1.5 V LVCMOS 4 mA 4 mA High –0.30.35 * VCC I 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 4 4

1.2 V

LVCMOS42 mA 2 mA High –0.30.3 5 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI 2 2

1.2 V

LVCMOS

Wide Range4,5

100 µA 2 mA High –0.3 0.3 * VCCI 0.7 * VCCI 1.575 0.1 VCCI – 0.1 0.1 0.1

3.3 V PCI Per PCI specifications

3.3 V PCI-X Per PCI-X specifications

Notes:

1. Please note that 1.2V LVCMOS and 3.3V LVCMOS wide range is applicable to 100 µA drive strength only. The

configuration will NOT operate at the equivalent software.

2. Currents are measured at 85°C junction temperature.

3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

4. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.

5. Applicable to devices operating at VCCI ≥ VCC.

6. Output slew rate can be extracted using the IBIS models.

ProASIC3L Low Power Flash FPGAs

Revision 10 2-25

Table 2-25 • Summary of Maximum and Minimum DC Input Levels

Applicable to Commercial and Industrial Conditions

DC I/O Standard

Commercial1Industrial2

IIL IIH IIL3IIH4

µA µA µA µA

3.3 V LVTTL / 3.3 V LVCMOS 10 10 15 15

3.3 V LVCMOS Wide Range 10 10 15 15

2.5 V LVCMOS 10 10 15 15

1.8 V LVCMOS 10 10 15 15

1.5 V LVCMOS 10 10 15 15

1.2 V LVCMOS5 10 10 15 15

1.2 V LVCMOS Wide Range510 10 15 15

3.3 V PCI 10 10 15 15

3.3 V PCI-X 10 10 15 15

3.3 V GTL 10 10 15 15

2.5 V GTL 10 10 15 15

3.3 V GTL+ 10 10 15 15

2.5 V GTL+ 10 10 15 15

HSTL (I) 10 10 15 15

HSTL (II) 10 10 15 15

SSTL2 (I) 10 10 15 15

SSTL2 (II) 10 10 15 15

SSTL3 (I) 10 10 15 15

SSTL3 (II) 10 10 15 15

Notes:

1. Commercial range (0°C < TA < 70°C)

2. Industrial range (–40°C < TA < 85°C)

3. IIL is the input leakage current per I/O pin over recommended operation conditions where

–0.3V < VIN <VIL.

4. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

5. Applicable to devices operating at VCCI ≥ VCC.

ProASIC3L DC and Switching Characteristics

2-26 Revision 10

Summary of I/O Timing Characteristics – Default I/O Software

Settings

Table 2-26 • Summary of AC Measuring Points

Standard Input Reference V oltage

(VREF_TYP) Board Termination

Volt age (VTT_REF) Measuring T r ip Point

(Vtrip)

3.3 V LVTTL /

3.3 V LVCMOS – – 1.4 V

3.3 V LVCMOS Wide Range – – 1.4 V

2.5 V LVCMOS – – 1.2 V

1.8 V LVCMOS – – 0.90 V

1.5 V LVCMOS – – 0.75 V

1.2 V LVCMOS * – – 0.6 V

1.2 V LVCMOS Wide Range* – – 0.6 V

3.3 V PCI – – 0.285 * VCCI (RR)

0.615 * VCCI (FF))

3.3 V PCI-X – – 0.285 * VCCI (RR)

0.615 * VCCI (FF)

3.3 V GTL 0.8 V 1.2 V VREF

2.5 V GTL 0.8 V 1.2 V VREF

3.3 V GTL+ 1.0 V 1.5 V VREF

2.5 V GTL+ 1.0 V 1.5 V VREF

HSTL (I) 0.75 V 0.75 V VREF

HSTL (II) 0.75 V 0.75 V VREF

SSTL2 (I) 1.25 V 1.25 V VREF

SSTL2 (II) 1.25 V 1.25 V VREF

SSTL3 (I) 1.5 V 1.485 V VREF

SSTL3 (II) 1.5 V 1.485 V VREF

LVDS – – Cross point

LVPECL – – Cross point

Note: *Applicable only to devices operating in the 1.2 V core range.

Table 2-27 • I/O AC Parameter Definitions

Parameter Parameter Definition

tDP Data to Pad delay through the Output Buffer

tPY Pad to Data delay through the Input Buffer

tDOUT Data to Output Buffer delay through the I/O interface

tEOUT Enable to Output Buffer Tristate Control delay through the I/O interface

tDIN Input Buffer to Data delay through the I/O interface

tHZ Enable to Pad delay through the Output Buffer—High to Z

tZH Enable to Pad delay through the Output Buffer—Z to High

tLZ Enable to Pad delay through the Output Buffer—Low to Z

tZL Enable to Pad delay through the Output Buffer—Z to Low

tZHS Enable to Pad delay through the Output Buffer with delayed enable—Z to High

tZLS Enable to Pad delay through the Output Buffer with delayed enable—Z to Low

ProASIC3L Low Power Flash FPGAs

Revision 10 2-27

1.5 V DC Core Voltage

Table 2-28 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425V,

Worst Case VCCI

Pro I/O Banks

Standard

Drive Strength (mA)

Equiv. Software Default

Drive Strength Option1

Slew Rate

Capacitive Load (pF)

External Resistor (Ω)

tDOUT (ns)

tDP (ns)

tDIN (ns)

tPY (ns)

tPYS (ns)

tEOUT (ns)

tZL (ns)

tZH (ns)

tLZ (ns)

tHZ (ns)

tZLS (ns)

tZHS (ns)

Units

3.3 V LVTTL /

3.3 V LVCMOS 12 mA 12 mA High 5 – 0.50 1.89 0.03 1.34 1.85 0.33 1.93 1.42 2.51 2.77 3.64 3.13 ns

3.3 V LVCMOS

Wide Range1,2 100 µA 12 mA High 5 – – – – – – – – – – – – – ns

2.5 V L VCMOS 12 mA 12 mA High 5 – 0.50 1.92 0.03 1.58 1.97 0.33 1.96 1.59 2.58 2.68 3.67 3.30 ns

1.8 V L VCMOS 12 mA 12 mA High 5 – 0.50 2.14 0.03 1.53 2.17 0.33 2.18 1.76 2.86 3.24 3.89 3.47 ns

1.5 V L VCMOS 12 mA 12 mA High 5 – 0.50 2.46 0.03 1.69 2.36 0.33 2.51 2.04 3.03 3.35 4.22 3.75 ns

3.3 V PCI Per

PCI

spec.

– High 5 2530.50 2.15 0.03 2.10 2.84 0.33 2.19 1.53 2.51 2.77 3.90 3.24 ns

3.3 V PCI-X Per

PCI-X

spec.

– High 10 2530.50 2.15 0.03 2.10 2.84 0.33 2.19 1.53 2.51 2.77 3.90 3.24 ns

3.3 V GTL 25 mA 25 mA High 10 25 0.50 1.59 0.03 1.80 – 0.33 1.56 1.59 – – 3.27 3.30 ns

2.5 V GTL 25 mA 25 mA High 10 25 0.50 1.63 0.03 1.75 – 0.33 1.66 1.63 – – 3.37 3.34 ns

3.3 V GTL+ 35 mA 35 mA High 10 25 0.50 1.57 0.03 1.80 – 0.33 1.60 1.57 – – 3.31 3.29 ns

2.5 V GTL+ 33 mA 33 mA High 10 25 0.50 1.69 0.03 1.75 – 0.33 1.72 1.61 – – 3.43 3.32 ns

HSTL (I) 8 mA 8 mA High 20 25 0.50 2.43 0.03 2.12 – 0.33 2.48 2.41 – – 4.19 4.12 ns

HSTL (II) 15 mA 15 mA High 20 50 0.50 2.32 0.03 2.12 – 0.33 2.36 2.08 – – 4.07 3.79 ns

SSTL2 (I) 15 mA 15 mA High 30 25 0.50 1.63 0.03 1.61 – 0.33 1.66 1.41 – – 1.66 1.41 ns

SSTL2 (II) 18 mA 18 mA High 30 50 0.50 1.66 0.03 1.61 – 0.33 1.69 1.36 – – 1.69 1.36 ns

SSTL3 (I) 14 mA 14 mA High 30 25 0.50 1.77 0.03 1.54 – 0.33 1.80 1.41 – – 1.80 1.41 ns

SSTL3 (II) 21 mA 21 mA High 30 50 0.50 1.58 0.03 1.54 – 0.33 1.61 1.28 – – 1.61 1.28 ns

L VDS 24 mA 24 mA High – – 0.50 1.40 0.03 1.85 – – – – – – – – ns

L VPECL 24 mA 24 mA High – – 0.50 1.40 0.03 1.67 – – – – – – – – ns

Notes:

1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is

±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the

IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

3. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-80 for

connectivity. This resistor is not required during normal operation.

4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L DC and Switching Characteristics

2-28 Revision 10

Table 2-29 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Wo rst

Case VCCI

Advanced I/O Banks

I/O Standard

Drive Strength (mA)

Equiv. Software Default

Drive Strength Option1

Slew Rate

Capacitive Load (pF)

External Resistor (Ω)

tDOUT (ns)

tDP (ns)

tDIN (ns)

tPY (ns)

tEOUT (ns)

tZL (ns)

tZH (ns)

tLZ (ns)

tHZ (ns)

tZLS (ns)

tZHS (ns)

Units

3.3 V LVTTL /

3.3 V LVCMOS 12 mA 12 mA High 5 – 0.46 1.83 0.03 0.78 0.33 1.87 1.39 2.46 2.74 3.58 3.10 ns

3.3 V LVCMOS

Wide Range1,2 100 µA 12 mA High 5 – – – – – – – – – – – – ns

2.5 V L VCMOS 12 mA 12 mA High 5 – 0.46 1.85 0.03 1.00 0.33 1.88 1.55 2.53 2.63 3.59 3.26 ns

1.8 V LVCMOS 12 mA 12 mA High 5 – 0.46 2.04 0.03 0.93 0.33 2.08 1.73 2.83 3.12 3.79 3.45 ns

1.5 V LVCMOS 12 mA 12 mA High 5 – 0.46 2.33 0.03 1.10 0.33 2.37 2.01 3.02 3.22 4.08 3.72 ns

3.3 V PCI Per

PCI

spec.

– High 5 25 30.46 2.05 0.03 0.66 0.33 2.09 1.49 2.46 2.74 3.80 3.21 ns

3.3 V PCI-X Per

PCI-X

spec.

– High 10 253 0.46 2.05 0.03 0.64 0.33 2.09 1.49 2.46 2.74 3.80 3.21 ns

LVDS 24 mA – High – – 0.46 1.40 0.03 1.23 N/A N/A N/A N/A N/A N/A N/A ns

LVPECL 24 mA – High – – 0.46 1.38 0.03 1.08 N/A N/A N/A N/A N/A N/A N/A ns

Notes:

1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is

±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the

IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

3. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-80 for

connectivity. This resistor is not required during normal operation.

4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L Low Power Flash FPGAs

Revision 10 2-29

Table 2-30 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Wo rst

Case VCCI = 3.0 V

Standard Plus I/O Banks

I/O Standard

Drive Strength (mA)

Equiv. Software Default

Drive Strength Option1

Slew Rate

Capacitive Load (pF)

External Resistor

tDOUT (ns)

tDP (ns)

tDIN (ns)

tPY (ns)

tEOUT (ns)

tZL (ns)

tZH (ns)

tLZ (ns)

tHZ (ns)

tZLS (ns)

tZHS (ns)

Units

3.3 V LVTTL /

3.3 V LVCMOS 12 mA 12 mA High 5 – 0.46 1.56 0.03 0.77 0.33 1.59 1.20 2.14 2.47 3.30 2.91 ns

3.3 V LVCMOS

Wide Range1,2 100 µA 12 mA High 5 – – – – – – – – – – – – ns

2.5 V L VCMOS 12 mA 12 mA High 5 – 0.46 1.59 0.03 0.99 0.33 1.61 1.32 2.16 2.38 3.33 3.03 ns

1.8 V LVCMOS 8 mA 8 mA High 5 – 0.46 1.59 0.03 0.99 0.33 1.61 1.32 2.16 2.38 3.33 3.03 ns

1.5 V LVCMOS 4 mA 4 mA High 5 – 0.46 2.15 0.03 1.09 0.33 2.19 1.82 2.32 2.40 3.90 3.53 ns

3.3 V PCI Per

PCI

spec.

– High 10 25

30.46 1.77 0.03 0.65 0.33 1.80 1.31 2.14 2.47 3.51 3.02 ns

3.3 V PCI-X Per

PCI-X

spec.

– High 10 25

30.46 1.77 0.03 0.64 0.33 1.80 1.31 2.14 2.47 3.51 3.02 ns

Notes:

1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is

±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the

IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

3. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-80 for

connectivity. This resistor is not required during normal operation.

4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L DC and Switching Characteristics

2-30 Revision 10

1.2 V DC Core Voltage

Table 2-31 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.14 V,

Worst Case VCCI

Pro I/O Banks

Standard

Drive Strength (mA)

Equiv. Software Default

Drive Strength Option1

Slew Rate

Capacitive Load (pF)

External Resistor (Ω)

tDOUT (ns)

tDP (ns)

tDIN (ns)

tPY (ns)

tPYS (ns)

tEOUT (ns)

tZL (ns)

tZH (ns)

tLZ (ns)

tHZ (ns)

tZLS (ns)

tZHS (ns)

Units

3.3 V LVTTL /

3.3 V LV CMOS 12 mA 12 mA High 5 – 0.66 1.89 0.04 1.34 1.85 0.43 1.93 1.42 2.51 2.77 3.64 3.13 ns

3.3 V LVCMOS

Wide Range1,2 100 µA12 mAHigh5–––––––––––––ns

2.5 V L VCMOS 12 mA 12 mA High 5 – 0.66 1.92 0.04 1.58 1.97 0.43 1.96 1.59 2.58 2.68 3.67 3.30 ns

1.8 V L VCMOS 12 mA 12 mA High 5 – 0.66 2.14 0.04 1.53 2.17 0.43 2.18 1.76 2.86 3.24 3.89 3.47 ns

1.5 V L VCMOS 12 mA 12 mA High 5 – 0.66 2.46 0.04 1.69 2.36 0.43 2.51 2.04 3.03 3.35 4.22 3.75 ns

1.2 V LVCMOS 2 mA 2 mA High 5 – 0.66 4.12 0.04 2.02 2.99 0.43 3.83 3.37 4.06 3.84 5.48 5.02 ns

1.2 V LVCMOS

Wide Range1,3 100 µA2 mAHigh5–––––––––––––ns

3.3 V PCI Per

PCI

spec.

– High 10 2540.66 2.15 0.04 2.10 2.84 0.43 2.19 1.53 2.51 2.77 3.90 3.24 ns

3.3 V PCI-X Per

PCI-X

spec.

– High 10 2540.66 2.15 0.04 2.10 2.84 0.43 2.19 1.53 2.51 2.77 3.90 3.24 ns

3.3 V GTL 25 mA – High 10 25 0.66 1.59 0.04 1.80 – 0.43 1.56 1.59 – – 3.27 3.30 ns

2.5 V GTL 25 mA – High 10 25 0.66 1.63 0.04 1.75 – 0.43 1.66 1.63 – – 3.37 3.34 ns

3.3 V GTL+ 35 mA – High 10 25 0.66 1.57 0.04 1.80 – 0.43 1.60 1.57 – – 3.31 3.29 ns

2.5 V GTL+ 33 mA – High 10 25 0.66 1.69 0.04 1.75 – 0.43 1.72 1.61 – – 3.43 3.32 ns

HSTL (I) 8 mA – High 20 25 0.66 2.43 0.04 2.12 – 0.43 2.48 2.41 – – 4.19 4.12 ns

HSTL (II) 15 mA – High 20 50 0.66 2.32 0.04 2.12 – 0.43 2.36 2.08 – – 4.07 3.79 ns

SSTL2 (I) 15 mA – High 30 25 0.66 1.63 0.04 1.61 – 0.43 1.66 1.41 – – 1.66 1.41 ns

SSTL2 (II) 18 mA – High 30 50 0.66 1.66 0.04 1.61 – 0.43 1.69 1.36 – – 1.69 1.36 ns

SSTL3 (I) 14 mA – High 30 25 0.66 1.77 0.04 1.54 – 0.43 1.80 1.41 – – 1.80 1.41 ns

SSTL3 (II) 21 mA – High 30 50 0.66 1.58 0.04 1.54 – 0.43 1.61 1.28 – – 1.61 1.28 ns

LVDS 24 mA –High ––0.661.430.041.85–––––––– ns

LVPECL 24 mA –High ––0.661.370.041.67–––––––– ns

Notes:

1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is

±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the

IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.

4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-80 for

connectivity. This resistor is not required during normal operation.

5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L Low Power Flash FPGAs

Revision 10 2-31

Table 2-32 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.14 V, Worst Case

VCCI

Advanced I/O Banks

I/O Standard

Drive Strength (mA)

Equiv. Software Default

Drive Strength Option1

Slew Rate

Capacitive Load (pF)

External Resistor (Ω)

tDOUT (ns)

tDP (ns)

tDIN (ns)

tPY (ns)

tEOUT (ns)

tZL (ns)

tZH (ns)

tLZ (ns)

tHZ (ns)

tZLS (ns)

tZHS (ns)

Units

3.3 V LVTTL /

3.3 V LVCMOS 12 mA 12 mA High 5 pF – 0.60 1.83 0.04 0.78 0.43 1.87 1.39 2.46 2.74 3.58 3.10 ns

3.3 V LVCMOS

Wide Range1,2

100 µA 12 mA High 5 pF – – – – – – – – – – – – ns

2.5 V LVCMOS 12 mA 12 mA High 5 pF – 0.60 1.85 0.04 1.00 0.43 1.88 1.55 2.53 2.63 3.59 3.26 ns

1.8 V LVCMOS 12 mA 12 mA High 5 pF – 0.60 2.04 0.04 0.93 0.43 2.08 1.73 2.83 3.12 3.79 3.45 ns

1.5 V LVCMOS 12 mA 12 mA High 5 pF – 0.60 2.33 0.04 1.10 0.43 2.37 2.01 3.02 3.22 4.08 3.72 ns

1.2 V LVCMOS 2 mA 2 mA High 5pF – 0.60 3.17 0.04 1.55 0.43 2.11 1.76 2.38 2.46 3.76 3.41 ns

1.2 V LVCMOS

Wide Range1,3 100 µA 2 mA High 5 pF – – – – – – – – – – – – ns

3.3 V PCI Per

PCI

spec.

– High 10

pF 25 40.60 2.05 0.04 0.66 0.43 2.09 1.49 2.46 2.74 3.80 3.21 ns

3.3 V PCI-X Per

PCI-X

spec.

– High 10

pF 25 40.60 2.05 0.04 0.64 0.43 2.09 1.49 2.46 2.74 3.80 3.21 ns

LVDS 24 mA – High – – 0.60 1.40 0.04 1.23 N/A N/A N/A N/A N/A N/A N/A ns

LVPECL 24 mA – High – – 0.60 1.38 0.04 1.08 N/A N/A N/A N/A N/A N/A N/A ns

Notes:

1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is

±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the

IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.

4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-80 for

connectivity. This resistor is not required during normal operation.

5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L DC and Switching Characteristics

2-32 Revision 10

Detailed I/O DC Characteristics

Table 2-33 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.14 V, Worst Case

VCCI = 3.0 V

Standard Plus I/O Banks

I/O Standard

Drive Strength (mA)

Equiv. Software Default

Drive Strength Option1

Slew Rate

Capacitive Load (pF)

External Resistor

tDOUT (ns)

tDP (ns)

tDIN (ns)

tPY (ns)

tEOUT (ns)

tZL (ns)

tZH (ns)

tLZ (ns)

tHZ (ns)

tZLS (ns)

tZHS (ns)

Units

3.3 V LVTTL /

3.3 V LVCMOS 12 mA 12 mA High 5 pF – 0.60 1.56 0.04 0.77 0.43 1.59 1.20 2.14 2.47 3.30 2.91 ns

3.3 V LVCMOS

Wide Range1,2 100 µA 12 mA High 5 pF – – – – – – – – – – – – ns

2.5 V LVCMOS 12 mA 12 mA High 5 pF – 0.60 1.59 0.04 0.99 0.43 1.61 1.32 2.16 2.38 3.33 3.03 ns

1.8 V LVCMOS 8 mA 8 mA High 5 pF – 0.60 1.59 0.04 0.99 0.43 1.61 1.32 2.16 2.38 3.33 3.03 ns

1.5 V LVCMOS 4 mA 4 mA High 5 pF – 0.60 2.15 0.04 1.09 0.43 2.19 1.82 2.32 2.40 3.90 3.53 ns

1.2 V LVCMOS 2 mA 2 mA High 5 pF – 0.60 3.54 0.04 1.56 0.43 2.37 2.11 3.60 3.87 4.02 3.76 ns

1.2 V LVCMOS

Wide Range1,3 100 µA 2 mA High 5 pF – – – – – – – – – – – – ns

3.3 V PCI Per

PCI

spec.

– High 10 pF 25

40.60 1.77 0.04 0.65 0.43 1.80 1.31 2.14 2.47 3.51 3.02 ns

3.3 V PCI-X Per

PCI-X

spec.

– High 10 pF 25

40.60 1.77 0.04 0.64 0.43 1.80 1.31 2.14 2.47 3.51 3.02 ns

Notes:

1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is

±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the

IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.

4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-80 for

connectivity. This resistor is not required during normal operation.

5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-34 • Input Capacitance

Symbol Definition Conditions Min. Max. Units

CIN Input capacitance VIN = 0, f = 1.0 MHz 8 pF

CINCLK Input capacitance on th e clo ck pi n VIN = 0, f = 1.0 MHz 8 pF

ProASIC3L Low Power Flash FPGAs

Revision 10 2-33

Table 2-35 • I/O Output Buf f er Max imum Resistance s1

Applicable to Pro I/Os

Standard Drive Strength

RPULL-DOWN

(Ω) 2 RPULL-UP

(Ω)3

3.3 V LVTTL / 3.3 V LVCMOS 4 mA 100 300

8 mA 50 150

12 mA 25 75

16 mA 17 50

24 mA 11 33

3.3 V LVCMOS Wide Range 100 µA Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS

2.5 V LVCMOS 4 mA 100 200

8 mA 50 100

12 mA 25 50

16 mA 20 40

24 mA 11 22

1.8 V LVCMOS 2 mA 200 225

4 mA 100 112

6 mA 50 56

8 mA 50 56

12 mA 20 22

16 mA 20 22

1.5 V LVCMOS 2 mA 200 224

4 mA 100 112

6 mA 67 75

8 mA 33 37

12 mA 33 37

1.2 V LVCMOS 2 mA 158 164

1.2 V LVCMOS Wide Range 100 µA Same as regular 1.2 V LVCMOS Same as regular 1.2 V LVCMOS

3.3 V PCI/PCI-X Per PCI/PCI-X

specification 25 75

3.3 V GTL 25 mA 11 –

2.5 V GTL 25 mA 14 –

3.3 V GTL+ 35 mA 12 –

2.5 V GTL+ 33 mA 15 –

HSTL (I) 8 mA 50 50

HSTL (II) 15 mA 25 25

SSTL2 (I) 15 mA 27 31

SSTL2 (II) 18 mA 13 15

SSTL3 (I) 14 mA 44 69

SSTL3 (II) 21 mA 18 32

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend

on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer

resistances, use the corresponding IBIS models located at http://www.microsemi.com/soc/download/ibis/default.aspx.

2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec

3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec

ProASIC3L DC and Switching Characteristics

2-34 Revision 10

Table 2-36 • I/O Output Buf f er Max imum Resistance s1

Applicable to Advanced I/O Ban ks

Standard Drive

Strength RPULL-DOWN

(Ω)2 RPULL-UP

(Ω)3

3.3 V LVTTL / 3.3 V LVCMOS 2 mA 100 300

4 mA 100 300

6 mA 50 150

8 mA 50 150

12 mA 25 75

16 mA 17 50

24 mA 11 33

3.3 V LVCMOS Wide Range 100 µA Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS

2.5 V LVCMOS 2 mA 100 300

4 mA 100 300

6 mA 50 150

8 mA 50 150

12 mA 25 75

16 mA 17 50

24 mA 11 33

1.8 V LVCMOS 2 mA 100 200

4 mA 100 200

6 mA 50 100

8 mA 50 100

12 mA 25 50

16 mA 20 40

1.5 V LVCMOS 2 mA 200 224

4 mA 100 112

6 mA 67 75

8 mA 33 37

12 mA 33 37

1.2 V LVCMOS 2 mA 158 164

1.2 V LVCMOS Wide Range 100 µA Same as regular 1.2 V LVCMOS Same as regular 1.2 V LVCMOS

3.3 V PCI/PCI-X Per PCI/PCI-X

specification 25 75

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend

on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer

resistances, use the corresponding IBIS models located at http://www.microsemi.com/soc/download/ibis/default.aspx.

2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec

3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec

ProASIC3L Low Power Flash FPGAs

Revision 10 2-35

Table 2-37 • I/O Output Buf f er Max imum Resistance s1

Applicable to Standard Plus I/O Banks

Standard Drive

Strength RPULL-DOWN

(Ω)2 RPULL-UP

(Ω)3

3.3 V LVTTL / 3.3 V LVCMOS 2 mA 100 300

4 mA 100 300

6 mA 50 150

8 mA 50 150

12 mA 25 75

16 mA 25 75

3.3 V LVCMOS Wide Range 100 µA Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS

2.5 V LVCMOS 2 mA 100 200

4 mA 100 200

6 mA 50 100

8 mA 50 100

12 mA 25 50

1.8 V LVCMOS 2 mA 200 225

4 mA 100 112

6 mA 50 56

8 mA 50 56

1.5 V LVCMOS 2 mA 200 224

4 mA 100 112

1.2 V LVCMOS 2 mA 158 164

1.2 V LVCMOS Wide Range 100 µA Same as regular 1.2 V LVCMOS Same as regular 1.2 V LVCMOS

3.3 V PCI/PCI-X Per PCI/PCI-X

specification 25 75

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend

on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer

resistances, use the corresponding IBIS models located at http://www.microsemi.com/soc/download/ibis/default.aspx.

2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec

3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec

ProASIC3L DC and Switching Characteristics

2-36 Revision 10

Table 2-38 • I/O Weak Pull-Up/Pull-Down Resistances

Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values

VCCI

R(WEAK PULL-UP)1

(Ω)R(WEAK PULL-DOWN)2

(Ω)

Min. Max. Min. Max.

3.3 V 10 k 45 k 10 k 45 k

3.3 V (wide range I/Os) 10 k 45 k 10 k 45 k

2.5 V 11 k 55 k 12 k 74 k

1.8 V 18 k 70 k 17 k 110 k

1.5 V 19 k 90 k 19 k 140 k

1.2 V LVCMOS 25 k 110 k 25 k 150 k

1.2 V (wide range I/Os) 19 k 110 k 19 k 150 k

Notes:

1. R(WEAK PULL-UP-MAX) = (VCCImax – VOHspec) / I(WEAK PULL-UP-MIN)

2. R(WEAK PULL-DOWN-MAX) = (VOLspec) / I(WEAK PULL-DOWN-MIN)

ProASIC3L Low Power Flash FPGAs

Revision 10 2-37

Table 2-39 • I/O Short Currents IOSH/IOSL

Applicable to Pro I/Os

Standard Drive Strength IOSL (mA)* IOSH (mA)*

3.3 V LVTTL / 3.3 V LVCMOS 4 mA 25 27

8 mA 51 54

12 mA 103 109

16 mA 132 127

24 mA 268 181

3.3 V LVCMOS Wide Range 100 µA Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS

2.5 V LVCMOS 4 mA 16 18

8 mA 32 37

12 mA 65 74

16 mA 83 87

24 mA 169 124

1.8 V LVCMOS 2 mA 9 11

4 mA 17 22

6 mA 35 44

8 mA 45 51

12 mA 91 74

16 mA 91 74

1.5 V LVCMOS 2 mA 13 16

4 mA 25 33

6 mA 32 39

8 mA 66 55

12 mA 66 55

1.2 V LVCMOS 2 mA 20 26

1.2 V LVCMOS Wide Range 100 µA 20 26

3.3 V PCI/PCIX Per PCI/PCI-X

Specification Per PCI Curves

3.3 V GTL 25 mA 268 181

2.5 V GTL 25 mA 169 124

3.3 V GTL+ 35 mA 268 181

2.5 V GTL+ 33 mA 169 124

HSTL (I) 8 mA 32 39

HSTL (II) 15 mA 66 55

SSTL2 (I) 15 mA 83 87

SSTL2 (II) 18 mA 169 124

SSTL3 (I) 14 mA 51 54

Note: *TJ = 100°C

ProASIC3L DC and Switching Characteristics

2-38 Revision 10

Table 2-40 • I/O Short Currents IOSH/IOSL

Applicable to Advanced I/O Ban ks

Standard Drive Strength IOSL (mA)* IOSH (mA)*

3.3 V LVTTL / 3.3 V LVCMOS 2 mA 25 27

4 mA 25 27

6 mA 51 54

8 mA 51 54

12 mA 103 109

16 mA 132 127

24 mA 268 181

3.3 V LVCMOS Wide Range 100 µA Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS

2.5 V LVCMOS 2 mA 16 18

4 mA 16 18

6 mA 32 37

8 mA 32 37

12 mA 65 74

16 mA 83 87

24 mA 169 124

1.8 V LVCMOS 2 mA 9 11

4 mA 17 22

6 mA 35 44

8 mA 45 51

12 mA 91 74

16 mA 91 74

1.5 V LVCMOS 2 mA 13 16

4 mA 25 33

6 mA 32 39

8 mA 66 55

12 mA 66 55

1.2 V LVCMOS 2 mA 20 26

1.2 V LVCMOS Wide Range 100 µA 20 26

3.3 V PCI/PCI-X Per PCI/PCI-X

specification 103 109

Note: *TJ = 100°C

ProASIC3L Low Power Flash FPGAs

Revision 10 2-39

The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The

reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of

analysis.

For example, at 100°C, the short current condition would have to be sustained for more than six months

to cause a reliability concern. The I/O design does not contain any short circuit protection, but such

protection would only be needed in extremely prolonged stress conditions.

Table 2-41 • I/O Short Currents IOSH/IOSL

Applicable to Standard Plus I/O Banks

Drive Strength IOSL (mA)* IOSH (mA)*

3.3 V LVTTL / 3.3 V

LVCMOS 2 mA 25 27

4 mA 25 27

6 mA 51 54

8 mA 51 54

12 mA 103 109

16 mA 103 109

3.3 V LVCMOS Wide Range 100 µA Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS

2.5 V LVCMOS 2 mA 16 18

4 mA 16 18

6 mA 32 37

8 mA 32 37

12 mA 65 74

1.8 V LVCMOS 2 mA 9 11

4 mA 17 22

6 mA 35 44

8 mA 35 44

1.5 V LVCMOS 2 mA 13 16

4 mA 25 33

1.2 V LVCMOS 2 mA 20 26

1.2 V LVCMOS Wide Range 100 µA 20 26

3.3 V PCI/PCI-X Per PCI/PCI-X

specification 103 109

Note: TJ = 100°C

Table 2-42 • Schmitt Trigger Input Hysteresis, Hysteresis Voltage Value (Typ) for Schmitt Mode Input Buffers

Input Buffer Configura ti on Hysteresis Value (typ.)

3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode) 240 mV

2.5 V LVCMOS (Schmitt trigger mode) 140 mV

1.8 V LVCMOS (Schmitt trigger mode) 80 mV

1.5 V LVCMOS (Schmitt trigger mode) 60 mV

1.2 V LVCMOS (Schmitt trigger mode) 40 mV

ProASIC3L DC and Switching Characteristics

2-40 Revision 10

Table 2-43 • Duration of Short Circuit Event before Failure

Temperature Time before Failure

–40°C > 20 years

0°C > 20 years

25°C > 20 years

70°C 5 years

85°C 2 years

100°C 6 months

Table 2-44 • I/O Input Rise Time, Fall Time, and Related I/O Reliability

Input Buffer In put Rise/Fall Time (min.) Input Rise/Fall Time (max.) Reli ability

LVTTL/LVCMOS No requirement 10 ns * 20 years (110°C)

LVDS/B-LVDS/

M-LVDS/LVPECL No requirement 10 ns * 10 years (100°C)

Note: *The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low,

then the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the

rise/fall times, the more susceptible the input signal is to the board noise. Microsemi recommends signal

integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input

signals.

ProASIC3L Low Power Flash FPGAs

Revision 10 2-41

Single-Ended I/O Characteristics

3.3 V LVTTL / 3.3 V LVCMOS

Low voltage transistor–transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V

applications. This standard uses an LVTTL input buffer and push-pull output buffer. Furthermore, all

LVCMOS 3.3 V software macros comply with LVCMOS 3.3 V wide range, as specified in the JESD8-A

specification.

Table 2-45 • Minimum and Maximum DC Input and Output Levels

Applicable to Pro I/O Banks

3.3 V LVTTL /

3.3 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive Strength Min.

VMax.

VMin.

VMax.

VMin.

VmAmAMax.

mA1Max.

mA1µA2µA2

4 mA –0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10

6 mA –0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 10 10

8 mA –0.3 0.8 2 3.6 0.4 2.4 12 12 103 109 10 10

12 mA –0.3 0.8 2 3.6 0.4 2.4 16 16 132 127 10 10

16 mA –0.3 0.8 2 3.6 0.4 2.4 24 24 268 181 10 10

24 mA –0.3 0.8 2 3.6 0.4 2.4 24 24 27 25 10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-46 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Ban ks

3.3 V LVTTL /

3.3 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive Strength Min.

VMax.

VMin.

VMax.

VMin.

VmAmA

Max.

mA1Max.

mA1µA2µA2

2 mA –0.3 0.8 2 3.6 0.4 2.4 2 2 25 27 10 10

4 mA –0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10

6 mA –0.3 0.8 2 3.6 0.4 2.4 6 6 51 54 10 10

8 mA –0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 10 10

12 mA –0.3 0.8 2 3.6 0.4 2.4 12 12 103 109 10 10

16 mA –0.3 0.8 2 3.6 0.4 2.4 16 16 132 127 10 10

24 mA –0.3 0.8 2 3.6 0.4 2.4 24 24 268 181 10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

ProASIC3L DC and Switching Characteristics

2-42 Revision 10

Table 2-47 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

3.3 V LVTTL /

3.3 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive Strength Min.

VMax.

VMin.

VMax.

VMin.

VmAmAMax.

mA1Max.

mA1µA2µA2

2 mA –0.3 0.8 2 3.6 0.4 2.4 2 2 25 27 10 10

4 mA –0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10

6 mA –0.3 0.8 2 3.6 0.4 2.4 6 6 51 54 10 10

8 mA –0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 10 10

12 mA –0.3 0.8 2 3.6 0.4 2.4 12 12 103 109 10 10

16 mA –0.3 0.8 2 3.6 0.4 2.4 16 16 103 109 10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Figure 2-7 • AC Loading

Table 2-48 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V) Input High (V) Measuring Poin t* (V) CLOAD (pF)

03.31.45

Note: *Measuring point = Vtrip. See Table 2-26 on page 2-26 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 5 pF

R = 1 k R to VCCI for tLZ / tZL / tZLS

R to GND for tHZ / tZH / tZHS

5 pF for tZH / tZHS / tZL / tZLS

5 pF for tHZ / tLZ

ProASIC3L Low Power Flash FPGAs

Revision 10 2-43

Timing Characteristics

1.5 V DC Core Voltage

Table 2-49 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1. 42 5 V, Wor s t-C as e VCCI = 3.0 V

Applicable to Pro I/O Banks

Drive

Strength Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.59 5.48 0.04 1.58 2.17 0.38 5.58 4.40 2.42 2.20 7.60 6.42 ns

–1 0.50 4.66 0.03 1.34 1.85 0.33 4.75 3.75 2.06 1.87 6.46 5.46 ns

8 mA Std. 0.59 4.48 0.04 1.58 2.17 0.38 4.56 3.76 2.73 2.76 6.57 5.78 ns

–1 0.50 3.81 0.03 1.34 1.85 0.33 3.88 3.20 2.33 2.35 5.59 4.91 ns

12 mA Std. 0.59 3.77 0.04 1.58 2.17 0.38 3.84 3.28 2.95 3.12 5.85 5.29 ns

–1 0.50 3.21 0.03 1.34 1.85 0.33 3.27 2.79 2.51 2.65 4.98 4.50 ns

16 mA Std. 0.59 3.57 0.04 1.58 2.17 0.38 3.63 3.18 2.99 3.22 5.64 5.19 ns

–1 0.50 3.03 0.03 1.34 1.85 0.33 3.09 2.70 2.54 2.74 4.80 4.41 ns

24 mA Std. 0.59 3.46 0.04 1.58 2.17 0.38 3.52 3.19 3.05 3.57 5.54 5.20 ns

–1 0.50 2.94 0.03 1.34 1.85 0.33 3.00 2.71 2.59 3.03 4.71 4.42 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-50 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1. 42 5 V, Wor s t-C as e VCCI = 3.0 V

Applicable to Pro I/O Banks

Drive

Strength Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.59 3.08 0.04 1.58 2.17 0.38 3.14 2.36 2.42 2.33 5.15 4.38 ns

–1 0.50 2.62 0.03 1.34 1.85 0.33 2.67 2.01 2.06 1.98 4.38 3.72 ns

8 mA Std. 0.59 2.53 0.04 1.58 2.17 0.38 2.58 1.89 2.74 2.89 4.59 3.90 ns

–1 0.50 2.16 0.03 1.34 1.85 0.33 2.20 1.61 2.33 2.46 3.91 3.32 ns

12 mA Std. 0.59 2.22 0.04 1.58 2.17 0.38 2.27 1.67 2.95 3.25 4.28 3.68 ns

–1 0.50 1.89 0.03 1.34 1.85 0.33 1.93 1.42 2.51 2.77 3.64 3.13 ns

16 mA Std. 0.59 2.17 0.04 1.58 2.17 0.38 2.21 1.63 3.00 3.35 4.23 3.64 ns

–1 0.50 1.85 0.03 1.34 1.85 0.33 1.88 1.38 2.55 2.85 3.59 3.09 ns

24 mA Std. 0.59 2.19 0.04 1.58 2.17 0.38 2.24 1.57 3.05 3.71 4.25 3.58 ns

–1 0.50 1.87 0.03 1.34 1.85 0.33 1.90 1.33 2.59 3.16 3.61 3.05 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L DC and Switching Characteristics

2-44 Revision 10

Table 2-51 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1. 42 5 V, Wor s t-C as e VCCI = 3.0 V

Applicable to Advanced I/O Ban ks

Drive

Strength Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.54 5.11 0.04 0.91 0.38 5.21 4.33 2.38 2.21 7.22 6.34 ns

–1 0.46 4.35 0.03 0.78 0.33 4.43 3.68 2.02 1.88 6.14 5.40 ns

6 mA Std. 0.54 4.30 0.04 0.91 0. 38 4.38 3.75 2.68 2.74 6.39 5.76 ns

–1 0.46 3.66 0.03 0.78 0.33 3.73 3.19 2.28 2.33 5.44 4.90 ns

8 mA Std. 0.54 4.30 0.04 0.91 0. 38 4.38 3.75 2.68 2.74 6.39 5.76 ns

–1 0.46 3.66 0.03 0.78 0.33 3.73 3.19 2.28 2.33 5.44 4.90 ns

12 mA Std. 0.54 3.68 0.04 0.91 0.38 3.75 3.32 2.89 3.07 5.76 5.33 ns

–1 0.46 3.13 0.03 0.78 0.33 3.19 2.82 2.45 2.62 4.90 4.53 ns

16 mA Std. 0.54 3.50 0.04 0.91 0.38 3.56 3.21 2.93 3.16 5.57 5.23 ns

–1 0.46 2.97 0.03 0.78 0.33 3.03 2.73 2.49 2.69 4.74 4.45 ns

24 mA Std. 0.54 3.39 0.04 0.91 0.38 3.45 3.25 2.99 3.50 5.47 5.26 ns

–1 0.46 2.88 0.03 0.78 0.33 2.94 2.76 2.54 2.97 4.65 4.48 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-52 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1. 42 5 V, Wor s t-C as e VCCI = 3.0 V

Applicable to Advanced I/O Ban ks

Drive

Strength Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.54 2.90 0.04 0.91 0. 38 2.96 2.28 2.38 2.35 4.97 4.29 ns

–1 0.46 2.47 0.03 0.78 0.33 2.52 1.94 2.03 2.00 4.23 3.65 ns

6 mA Std. 0.54 2.41 0.04 0.91 0. 38 2.46 1.84 2.69 2.88 4.47 3.85 ns

–1 0.46 2.05 0.03 0.78 0.33 2.09 1.57 2.29 2.45 3.80 3.28 ns

8 mA Std. 0.54 2.41 0.04 0.91 0. 38 2.46 1.84 2.69 2.88 4.47 3.85 ns

–1 0.46 2.05 0.03 0.78 0.33 2.09 1.57 2.29 2.45 3.80 3.28 ns

12 mA Std. 0.54 2.16 0.04 0.91 0.38 2.20 1.63 2.89 3.22 4.21 3.64 ns

–-1 0.46 1.83 0.03 0.78 0.33 1.87 1.39 2.46 2.74 3.58 3.10 ns

16 mA Std. 0.54 2.11 0.04 0.91 0.38 2.15 1.59 2.94 3.31 4.17 3.61 ns

–-1 0.46 1.80 0.03 0.78 0.33 1.83 1.36 2.50 2.82 3.54 3.07 ns

24 mA Std. 0.54 2.14 0.04 0.91 0.38 2.17 1.55 2.99 3.65 4.19 3.56 ns

–1 0.46 1.82 0.03 0.78 0.33 1.85 1.32 2.54 3.11 3.56 3.03 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L Low Power Flash FPGAs

Revision 10 2-45

Table 2-53 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1. 42 5 V, Wor s t-C as e VCCI = 3.0 V

Applicable to Standard Plus I/O Banks

Drive

Strength Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.54 4.61 0.04 0.90 0. 38 4.70 3.91 2.05 1.99 6.71 5.92 ns

–1 0.46 3.92 0.03 0.77 0.33 4.00 3.32 1.74 1.69 5.71 5.04 ns

6 mA Std. 0.54 3.80 0.04 0.90 0. 38 3.87 3.40 2.32 2.47 5.88 5.41 ns

–1 0.46 3.23 0.03 0.77 0.33 3.29 2.89 1.98 2.10 5.00 4.60 ns

8 mA Std. 0.54 3.80 0.04 0.90 0. 38 3.87 3.40 2.32 2.47 5.88 5.41 ns

–1 0.46 3.23 0.03 0.77 0.33 3.29 2.89 1.98 2.10 5.00 4.60 ns

12 mA Std. 0.54 3.22 0.04 0.90 0.38 3.28 3.00 2.51 2.77 5.30 5.01 ns

–1 0.46 2.74 0.03 0.77 0.33 2.79 2.55 2.14 2.36 4.51 4.27 ns

16 mA Std. 0.54 3.22 0.04 0.90 0.38 3.28 3.00 2.51 2.77 5.30 5.01 ns

–1 0.46 2.74 0.03 0.77 0.33 2.79 2.55 2.14 2.36 4.51 4.27 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-54 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1. 42 5 V, Wor s t-C as e VCCI = 3.0 V

Applicable to Standard Plus I/O Banks

Drive

Strength Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.54 2.51 0.04 0.90 0. 38 2.56 2.01 2.05 2.10 4.57 4.02 ns

–1 0.46 2.14 0.03 0.77 0.33 2.18 1.71 1.74 1.79 3.89 3.42 ns

6 mA Std. 0.54 2.05 0.04 0.90 0. 38 2.09 1.61 2.32 2.59 4.10 3.62 ns

–1 0.46 1.74 0.03 0.77 0.33 1.78 1.37 1.97 2.20 3.49 3.08 ns

8 mA Std. 0.54 2.05 0.04 0.90 0. 38 2.09 1.61 2.32 2.59 4.10 3.62 ns

–1 0.46 1.74 0.03 0.77 0.33 1.78 1.37 1.97 2.20 3.49 3.08 ns

12 mA Std. 0.54 1.83 0.04 0.90 0.38 1.86 1.41 2.51 2.90 3.88 3.42 ns

–1 0.46 1.56 0.03 0.77 0.33 1.59 1.20 2.14 2.47 3.30 2.91 ns

16 mA Std. 0.54 1.83 0.04 0.90 0.38 1.86 1.41 2.51 2.90 3.88 3.42 ns

–1 0.46 1.56 0.03 0.77 0.33 1.59 1.20 2.14 2.47 3.30 2.91 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L DC and Switching Characteristics

2-46 Revision 10

1.2 V DC Core Voltage

Table 2-55 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Pro I/O Banks

Drive

Strength Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.77 5.48 0.05 1.58 2.17 0.50 5.58 4.40 2.42 2.20 7.60 6.42 ns

–1 0.66 4.66 0.04 1.34 1.85 0.43 4.75 3.75 2.06 1.87 6.46 5.46 ns

8 mA Std. 0.77 4.48 0.05 1.58 2.17 0.50 4.56 3.76 2.73 2.76 6.57 5.78 ns

–1 0.66 3.81 0.04 1.34 1.85 0.43 3.88 3.20 2.33 2.35 5.59 4.91 ns

12 mA Std. 0.77 3.77 0.05 1.58 2.17 0. 50 3.84 3.28 2.95 3.12 5.85 5.29 ns

–1 0.66 3.21 0.04 1.34 1.85 0.43 3.27 2.79 2.51 2.65 4.98 4.50 ns

16 mA Std. 0.77 3.57 0.05 1.58 2.17 0. 50 3.63 3.18 2.99 3.22 5.64 5.19 ns

–1 0.66 3.03 0.04 1.34 1.85 0.43 3.09 2.70 2.54 2.74 4.80 4.41 ns

24 mA Std. 0.77 3.46 0.05 1.58 2.17 0. 50 3.52 3.19 3.05 3.57 5.54 5.20 ns

–1 0.66 2.94 0.04 1.34 1.85 0.43 3.00 2.71 2.59 3.03 4.71 4.42 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

Table 2-56 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Applicable to Pro I/O Banks

Drive

Strength Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.77 3.08 0.05 1.58 2.17 0.50 3.14 2.36 2.42 2.33 5.15 4.38 ns

–1 0.66 2.62 0.04 1.34 1.85 0.43 2.67 2.01 2.06 1.98 4.38 3.72 ns

8 mA Std. 0.77 2.53 0.05 1.58 2.17 0.50 2.58 1.89 2.74 2.89 4.59 3.90 ns

–1 0.66 2.16 0.04 1.34 1.85 0.43 2.20 1.61 2.33 2.46 3.91 3.32 ns

12 mA Std. 0.77 2.22 0.05 1.58 2.17 0.50 2.27 1.67 2.95 3.25 4.28 3.68 ns

–1 0.66 1.89 0.04 1.34 1.85 0.43 1.93 1.42 2.51 2.77 3.64 3.13 ns

16 mA Std. 0.77 2.17 0.05 1.58 2.17 0. 50 2.21 1.63 3.00 3.35 4.23 3.64 ns

–1 0.66 1.85 0.04 1.34 1.85 0.43 1.88 1.38 2.55 2.85 3.59 3.09 ns

24 mA Std. 0.77 2.19 0.05 1.58 2.17 0. 50 2.24 1.57 3.05 3.71 4.25 3.58 ns

–1 0.66 1.87 0.04 1.34 1.85 0.43 1.90 1.33 2.59 3.16 3.61 3.05 ns

Notes: