General Description
The GD16504 is a high performance
monolithic integrated 2.488 Gbit/s Clock
and Data Recovery (CDR) device appli-
cable for optical communication systems
including:
uSDH STM-16
uSONET OC-48.
The CDR contains all circuits needed for
reliable acquisition and lock of the VCO
phase onto the incoming data.
The electrical input sensitivity is better
than 20 mV. Optical receivers with sensi-
tivity better than -34 dBm have been ob-
tained without optical pre-amplification.
The device meets all ITU-T jitter require-
ments when used with the recommended
loop filter (jitter tolerance, -transfer and
-generation).
The integrated 1:16 demultiplexer with
differential ECL outputs ensures a simple
and universal interface to the system
CMOS ASICs.
The 155 MHz output clock is maintained
within 500 ppm tolerance even in ab-
sence of data.
A triggerable Frame Alignment circuit de-
tecting the occurrence of a framing pat-
tern and aligning data at the 16 bit output
interface. Once the frame is found, the
circuit detects and flags all A1A1A2A2
sequences at the aligned byte boundary.
All high speed I/O levels are ECL com-
patible. The data input has improved
sensitivity and is connected via a 50 Ω
loop through transmission line to mini-
mize stub related reflections.
It is packed in a plastic fpBGA with inter-
nal 50 Ωtransmission lines, heat trans-
port to PCB, reduced mechanical stress
and removed requirement for a heat sink.
All signals are available in two outher
ring for easy routing.
It is also available in a 68 pin leaded
Multi Layer Ceramic (MLC) package with
50 Ωtransmission lines and cavity down
for easy cooling/heat sinking.
Preliminary
Features
lClock and Data Recovery at
2.488 Gbit/s.
lSDH STM-16, SONET OC-48 com-
patible.
lDifferential Data inputs better than
20 mV sensitivity for BER 10-9.
lDifferential ECL Data and Clock
outputs.
lAcquisition time < 500 µs.
lFew external passive components
needed.
l50 ΩLoop-Through data inputs for
higher sensitivity.
lFrame Detection and user triggered
alignment at 16 bits boundary.
lSingle supply operation.
lPower dissipation: 2.5 W
lAvailable in:
–144 ld. fpBGA
–68 pin Multi Layer Ceramic leaded
package with 50 Ωtransmission
lines.
lGD16504-68BA is 100% interchange-
able with GD16045, only loop filter
has to be changed.
Applications
lClock and Data Recovery for:
–SDH STM-16
–SONET OC-48 systems
2.5 Gbit/s
Clock and Data
Recovery Circuit
GD16504
Data Sheet Rev. 04
+
-
Lock
Detect
Circuit
Clock
Divide
Frame Align.
Dec.
:4
De-
MUX
4:2
MUX
Charge
Pump
VCO
Phase
Frequency
Detector
Bang
Bang
Phase
Detector
FFINN
FFIN
SON
SIPO
SIPI
SINI
SINO
SEL1
SEL2
REFCKN
REFCK
SOP
VSOPEN
FP
FPN
CKOUN
CKOUT
DOUN0
DOUT0
DOUN15
VDD
VDDA
VEE
VEEA
VCSREF
DOUT15
TCK
SELTCK
VCTL
OUCHP
LOCK
U
DI DODO
LD
DI
LOS
U
D
U
V
D
D
R
R
Functional Details
The main application of the GD16504 is
as Clcok and Data Recovery in optical
communication systems including:
uSDH STM-16
uSONET OC-48
It integrates:
ua Voltage Controlled Oscillator (VCO)
ua Lock Detect Circuit
ua Frequency Detector (PFD)
ua 1:16 DeMUX with framer.
ua Bang-Bang Phase Detector
into a clock and data recovery circuit
followed by a 1:16 demultiplexer with
differential ECL data and clock outputs.
VCO
The VCO is a low noise LC-type differen-
tial oscillator running 2.488 GHz. Tuning
is done by applying a voltage to the
VCTL pin.
Lock Detect Circuit
The Lock Detect Circuit continuously
monitors the difference between the ref-
erence clock, which is at 1/16 of the data
rate, and the divided VCO clock. If the
reference clock and the divided VCO fre-
quency differs by more than 500 ppm (or
2000 ppm, selectable), it switches the
PFD into the PLL in order to pull the VCO
back inside the lock-in range. This mode
is called the acquisition mode. Once
the VCO is inside the lock-range the
lock-detection circuit switches the Bang-
Bang phase detector into the PLL in or-
der to lock to the data signal. This mode
is called CDR mode. The status of the
lock-detection circuit is given by output
pin LOCK. In acquisition mode LOCK is
low.
In acquisition mode a PFD is used to
ensure predictable lock up conditions for
the GD16504 by locking the VCO to an
external reference clock source. It is only
used during acquisition and pulls the
VCO into the lock range where the Bang-
Bang phase detector is capable of ac-
quiring lock. The PFD is made with digital
set/reset cells giving it a true phase and
frequency characteristic. The reference
clock input, REFCK, to the PFD is at 1/16
of the data rate.
Bang-Bang Phase Detector
The Bang-Bang phase detector is used
in CDR mode as a true digital type
phase detector, producing a binary out-
put. It samples the incoming data twice
each bit period, once on the transition of
the previous bit period and once in the
middle of the bit period. When a transi-
tion occurs between 2 consecutive bits -
the value of the sample in the transition
between the bits determines whether the
VCO clock leads or lags the data. Hence
the Phase Locked Loop (PLL) is con-
trolled by the bit transition point, thereby
ensuring that data is sampled in the mid-
dle of the eye, once the system is in CDR
mode. The external loop filter controls
the characteristics of the PLL.
Figure 1. Loop Filter
The binary output of either the PFD or
the Bang-Bang phase detector (depend-
ing of the mode of the lock-detection cir-
cuit) is fed to a charge pump capable of
sinking or sourcing current or tristating.
The output of the charge pump is filtered
through the loop filter and controls the
tuning-voltage of the VCO.
A result of the continuous lock-detect
monitoring circuit is that the VCO fre-
quency never deviates more than
500 ppm (2000 ppm) from the reference
clock before the PLL is considered to be
’Out of Lock’. Hence the acquisition time
is predictable and short and the output
clock CKOUT is always kept within the
500 ppm (2000 ppm) limits ensuring safe
clocking of down stream circuitry.
The LOCK Signal
The LOCK output may be used to gener-
ate Loss of Signal (LOS). The time for
LOCK to assert is predictable and short,
equal to the time to go into lock, but the
time for LOCK to de-assert must be con-
sidered. When the line is down (i.e. no in-
formation received) the optical receiver
circuit may produce random noise. It is
possible that this random noise will keep
the GD16504 within the 500 ppm
(2000 ppm) range of the line frequency,
hence LOCK will remain asserted for a
non-deterministic time. This may be pre-
vented by injecting a small current at the
loop filter node, which actively pulls the
PLL out of the lock range when the out-
put of the phase detector acts randomly.
The negligible penalty paid is a static
phase error. However, due to the nature
of the phase detector the error will be
small (few degrees), forcing the loop to
be at one edge of the error-function
shaped transfer characteristic of the
detector.
If a LOS is detected by the optical circuit
in front of GD16504, the SEL1 and SEL2
may be configured to force the PLL to
use the Frequency Detector providing a
stable output clock locked only to refer-
ence input regardless of Lock Detect sta-
tus and at the same time force all outputs
to logic low.
The configuration signals (SEL1 and
SEL2) may be tied to VDD or VEE di-
rectly. The combination resets all Flip
Flops, and sets both Up and Down active
at the input of the Charge Pump, leaving
the output in the middle of its output
range. Since the circuit is self synchro-
nizing, reset need not be asserted during
power up.
Data Sheet Rev. 04 GD16504 Page 2
VCTL
82R
330R
100nF
OUCHP
Data Inputs
The input amplifier (pins SIPI / SINI and
SIPO / SINO) is designed as a limiting
amplifier with a sensitivity better than
±20 mV (differential). The inputs may be
either AC or DC coupled. In either case
input termination is made through pins
SIPO / SINO. If the inputs are AC-
coupled the amplifier features an internal
offset cancelling DC feedback path. All
four AC coupling capacitors should be
identical for optimum performance. No-
tice that the offset cancellation will only
work when the input is differential and
AC- coupled as shown in the Figure 3.
Figure 2. DC Coupled Input (Ignoring
internal offset compensation)
Figure 3. AC Coupled Input (Using
internal offset compensation)
Following the CDR block the data is 1:16
demultiplexed with frame detect and
alignment, and output together with a
155 MHz clock. The data and clock out-
puts are differential ECL outputs that
should be terminated via 50 Ωto -2 V.
The GD16504 includes a serial open col-
lector output intended to loop data to
GD16505 as shown in Figure 4 below.
Figure 4. Test Link Connection between
GD16504 and GD16505
Frame Alignment
The Frame Detect Alignment (FDA) cir-
cuit uses the available 48 A1 bytes in the
incoming data stream to align byte wise
and search for valid Frame Sequences
(A1-A1-A2-A2). At the falling edge of the
FFIN signal, the FDA starts looking for
valid A1’s in the incoming data stream,
regardless of byte boundary. To align at
the byte boundary, at least 7 A1’s should
be valid in a row, followed by more than
2 valid A1’s for each erroneous A1.
When the byte alignment is locked, the
FDA asserts FP at the first occurrence of
A1-A1-A2-A2, which must be valid. Note
that the A1 used for byte alignment could
be the same as used for the frame align-
ment, meaning that a sequence of 7 A1’s
followed by 2 A2’s will result in 100%
alignment. When a frame has been found
and the FFIN is not triggered, only frame
sequences (A1-A1-A2-A2) occurring at
the previously aligned byte boundary is
detected. This way the circuit serves two
functions.
When acquiring Frame Alignment, the
assertion of the FFIN / FFINN signal
starts the FDA alignment and when the
first valid sequence is found, the byte
boundary is fixed and the FP / FPN out-
put signal is pulsed. The byte boundary
is held until the next falling edge on FFIN
/ FFINN, and only valid sequences at the
fixed byte boundary will be flagged by the
FP / FPN signal. This allows the user to
control when to align, and to have
flagged all valid sequences once align-
ment is achieved.
Note that all valid sequences (7 A1’s fol-
lowed by 2 A2’s) will be flagged, regard-
less of their mutual distance.
The mean time to align and detect a
frame pulse (BER = 0) is 0.5 x Frame
(62.5 µs), since the FDA will align and
pulse FP upon reception of the first
Frame Sequence.
GD16504-68BA
The 68 pin CQFP has a reduced pin
count, this will affect some at the differ-
ential signals that will become single
ended.
The unconnected (inverted) input is bi-
ased to -1.3 V internally on the chip. This
will give the threshold at the single ended
signal.
Affected signals are:
uInputs: FFIN and REFCK
uOutput: FP
Data Sheet Rev. 04 GD16504 Page 3
+
-
+
-
SIPSOP
SON SIN
GD16504 GD16505
SIPO
50R
From LINE
From LINE
VTT
VTT
50R
8k
8k
26dB
SINO
SINI
SIPI
+
-
SIPO
50R
From LINE
From LINE
VTT
VTT
50R
8k
8k
26dB
SINO
SINI
SIPI
+
-
Pin List
Mnemonic: Pin No.:
144 EA 68 BA
Pin Type: Description:
SIP, SIPO E1, F1 62, 61 Anl. IN Loop-through serial positive differential input.
Optimised for max. sensitivity; may be used as ECL input.
SIN, SINO D1, C1 63, 64 Anl. IN Loop-through serial negative differential input.
Optimised for max. sensitivity; may be used as ECL input.
SOP, SON J1, H1 58, 59 CML OUT Buffered differential serial data output. High speed Open Col-
lector Drain output to be used in conjunction with GD16505 for
remote/optical loop back. Consult GIGA for information.
DOUT0, DOUN0
DOUT1, DOUN1
DOUT2, DOUN2
DOUT3, DOUN3
DOUT4, DOUN4
DOUT5, DOUN5
DOUT6, DOUN6
DOUT7, DOUN7
DOUT8, DOUN8
DOUT9, DOUN9
DOUT10, DOUN10
DOUT11, DOUN11
DOUT12, DOUN12
DOUT13, DOUN13
DOUT14, DOUN14
DOUT15, DOUN15
A11, A10
B12, A12
D11, C12
D12, E11
F12, F11
G12, G11
H12, H11
J12, J11
L12, K12
M11, M12
M9, M10
L8, L9
M7, M8
M6, L7
M4, M5
L3, M3
12, 11
15, 13
19, 16
22, 20
24, 23
27, 25
29, 28
32, 30
36, 33
39, 37
41, 40
44, 42
46, 45
49, 47
53, 50
56, 54
ECL OUT Retimed differential data output from DeMUX, bit 15 is the first
received. After frame synchronisation, the data is byte-aligned
with the first A2 byte placed at bit 15 through 8.
When LOCK = “0" or SEL1= ”1" and SEL2 = “0" (LOS),
all outputs will be logic low
REFCK, REFCKN A6, A7 6, N/A ECL IN 155 MHz reference clock input. Both biased to -1.3 V in 68BA
version
CKOUT, CKOUN A9, B9 10, 8 ECL OUT Regenerated differential output clock, 155 MHz.
SEL1, SEL2 A1, E12 67, 18 ECL IN Single-ended inputs, PLL set-up of Internal/ External switch
mode and LOCK:
SEL1 SEL2
0 0 Auto lock, 500ppm.
0 1 Global Reset for test purpose only.
1 0 Manual, Phase/ Freq. det, 500 ppm,LOS mode.
1 1 Manual, Phase detector, 2000 ppm.
The LOS mode cause all 16 data outputs, FP and LOCK into
logic low.
FFIN, FFINN B8, A8 7, N/A ECL IN Frame FINd signal. A falling edge at this input activates the
frame search. Single ended in 68-pin CQFP.
LOCK B6 5 ECL OUT Single ended CDR Lock alarm output. When low, the divided
VCO freq. deviates more than 500/2000 ppm from REFCK.
When system is unlocked, all 16 data outputs and FP will be
logic low. When SEL1 = "1" and SEL2 = "0" (LOS), the LOCK
will be logic low.
FP, FPN M1, L1 57, N/A ECL OUT Frame Pulse. One pulse (6.1 ns) indicates that a valid Frame
Sequence has been detected. When LOCK = “0" SEL1 = ”1"
and SEL2 = “0" (LOS), the FP / FPN will be logic low. FP/ FPN
is also low during reset. single ended output in 68-pin CQFP.
Differential in other packages.
VCTL A3 2 Anl. IN VCO control voltage input.
OUCHP A4 3 Anl. OUT Phase detector or Phase / frequency charge pump output.
TCK A2 66 ECL IN DC - functional and parametric test clock input. Bypasses the
VCO when SELTCK is high.
Data Sheet Rev. 04 GD16504 Page 4
Mnemonic: Pin No.:
144 EA 68 BA
Pin Type: Description:
VDD B1, C2, D2,
D4..9, E2,
E4..9, F2,
F4..9, G1,
G2, G4..9,
H2, H4..H9,
J2, J4..J9,
K1, K2, M2
4, 9, 14, 21,
26, 31, 38,
43, 48, 55,
60, 65
PWR 0 V Power for core and ECL I/O.
VEE C3..5, C10,
D3, D10,
E3, E10,
F3, F10,
G3, G10,
H3, H10,
J3, J10,
K3..5
34, 35, 68 PWR -5 V Power for core and ECL I/O.
VDDA A5, B5 17 PWR 0 V Power for VCO
VEEA B3, B4 52 PWR -5 V Power for VCO.
SELTCK B2 1 PWR Select test clock, for DC test only, connect to VEE.
VSOPEN L2 51 PWR 0 V power for Serial Output (SOP/SON). If output is not used,
VSOPEN may be left open (or connected to VEE), saving
power. Nominal current is 0.5 mA.
VCSREF L6 N/A ANALOG Internal reference voltage, leave open
NC B7, B10,
B11, C6..9,
C11, K6..9,
K10, K11,
L10, L11,
L4, L5
N/A Not used. Reserved for future use.
Data Sheet Rev. 04 GD16504 Page 5
Package Pinout
Figure 5. Package Pinout, 144 EA - Top View (seen through the package)
Data Sheet Rev. 04 GD16504 Page 6
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
AA
BB
CC
DD
EE
FF
GG
HH
JJ
KK
LL
MM
SEL1
SINO
SIN
SIP
SIPO
SON
SOP
FPN
FP
TCK
SELCTK
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSOPEN
VDD
VCTL
VEEA
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
DOUT15
DOUN15
OUCHP
VEEA
NC
DOUT14
VDDA
VDDA
NC
DOUN14
REFCK
LOCK
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VCSREF
DOUT13
REFCKN
NC
DOUN13
DOUT12
FFINN
FFIN
DOUT11
DOUN12
CKOUT
CKOUN
DOUN11
DOUT10
DOUN0
NC
VEE
VEE
VEE
VEE
VEE
VEE
VEE
DOUN10
DOUT0
NC
NC
DOUT2
DOUN3
DOUN4
DOUN5
DOUN6
DOUN7
DOUT9
DOUN1
DOUT1
DOUN2
DOUT3
SEL2
DOUT4
DOUT5
DOUT6
DOUT7
DOUN8
DOUT8
DOUN9
Figure 6. Package Pinout, 68 BA - Top View
Data Sheet Rev. 04 GD16504 Page 7
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
VDDA
DOUN2
DOUT1
VDD
DOUN1
DOUT0
DOUN0
CKOUT
VDD
CKOUN
FFIN
REFCK
LOCK
VDD
OUCHP
VCTL
SELTCK
VEE
SEL1
TCK
VDD
SINO
SIN
SIP
SIPO
VDD
SON
SOP
FP
DOUT15
VDD
DOUN15
DOUT14
VEEA
VSOPEN
DOUN14
DOUT13
VDD
DOUN13
DOUT12
DOUN12
DOUT11
VDD
DOUN11
DOUT10
DOUN10
DOUT9
VDD
DOUN9
DOUT8
VEE
VEE
DOUN8
DOUT7
VDD
DOUN7
DOUT6
DOUN6
DOUT5
VDD
DOUN5
DOUT4
DOUN4
DOUT3
VDD
DOUN3
DOUT2
SEL2
Maximum Ratings
These are the limits beyond which the component may be damaged.
All voltages in the table are referred to VDD.
All currents in the table are defined positive out of the pin.
Symbol: Characteristic: Conditions: MIN.: TYP.: MAX.: UNIT:
VEE,V
EEA Negative Supply -7 0 V
V0ECL Output Voltage ECL VEE -0.5 0.5 V
I0ECL Output Current ECL 40 mA
I0MAX, CHPO Output Current 0.25 mA
V1ECL Input Voltage ECL VEE -0.5 0.5 V
I1ECL Input Current ECL -1.0 1.0 mA
T0Operating Temperature Junction -40 +125 °C
TSStorage Temperature -65 +150 °C
Data Sheet Rev. 04 GD16504 Page 8
DC Characteristics
TCASE =0°Cto85°C,V
EE = -4.75 to -5.25 V
θJ-C =7EC/W, for 68-pin CQFP.
All voltages in the table are referred to VDD.
All input signal and power currents in the table are defined positive into the pin.
All output signal currents are defined positive out of the pin.
Symbol: Characteristic: Conditions: MIN.: TYP.: MAX.: UNIT.:
VEE Supply Voltage -5.25 -4.75 V
IEE Supply Current 500 mA
VISINX/SIPX Minimum Data Input Swing for 10-9 BER Note 5 25 mV
VISINX/SIPX Data Input Swing Note 5 1000 mV
VICM SINX/SIPX Data Common Mode Voltage -2 -1.3 -1 V
VIL ECL ECL Input LO Voltage Note 1 VEE -1.5 V
VIH ECL ECL Input HI Voltage Note 1 -1.1 0 V
IIH ECL ECL Input HI Current VIH =-0.7 12 100 µA
IIL ECL ECL Input LO Current VIL =-1.8 0.01 -1 µA
VOH ECL ECL Output HI Voltage Note 1, 2 -1.0 -0.5 V
VOL ECL ECL Output LO Voltage Note 1, 2 VTT -1.6 V
IOH ECL ECL Output HI Current Note 3 20 23 30 mA
IOL ECL ECL Output LO Current Note 3 -2 5 8 mA
IOH CML CML Output HI Current 0 mA
IOL CML CML Output LO Current 8 mA
VVCTL VCO Control Voltage IVCTL <30mAV
EE -1 V
IOH CHP OUCHP Source Current (DC Steady) Note 4 100 µA
IOL CHP OUCHP Sink Current (DC Steady) Note 4 100 µA
Note 1: VTT = -2.0 V ±5 %
Note 2: RLOAD =50Ωto VTT
Note 3: Not tested, consistent with VOH and VOL tests.
Note 4: Output terminated to -2.5 V during test.
Note 5: Minimum data input swing to ensure 10-9 BER. It is defined as the differential (p-p) voltage between the two inputs,
i.e. as the p-p voltage on SIPI + the p-p voltage on SINI. In case of unbalanced signals it is defined as twice the minimum
voltage difference between SIPI and SINI (see figure below).
Data Sheet Rev. 04 GD16504 Page 9
SIPI
SINI
Minimum voltage difference
between SIPI and SINI
AC Characteristics
TCASE =0°Cto85°C,V
EE = -4.75 V to -5.25 V.
Figure 7. Time (TD)
Figure 8. Frame Align Signal Timing
Note: During align, A2 byte marked with * may not be valid although frame is correctly aquired (F6Hor 28H)
Symbol: Characteristic: Conditions: MIN.: TYP.: MAX.: UNIT:
JTOL Jitter Tolerance 2 Hz<F<100kHz(Note 1)
1 MHz < F< 5 MHz (Note 1)
1.5
0.15
>2
>0.35
UI16, PP
UI16, PP
JTRF Jitter Transfer 5 kHz<F<2MHz(Note 2) 0.08 0.1 dB
JCLK Output Clock Intrinsic Jitter 5 kHz<F<20MHz(Note 3)
1MHz<F<20MHz(Note 3)
0.125
0.05
UI1
UI1
TAAquisition time 223-1 PRBS 50 500 µs
LCID Consecutive Identical Digits No. bits with no transitions 400 1000 bits
DCInput Clock / REFXI frequency
deviation
Note 4 -200 200 ppm
CDUTY REFCK REFCK clock duty cycle VThresh.= -1.3 V 40 60 %
CDUTY CKOUT Output clock duty cycle VThresh.= -1.3 V, 50 Ωto -2 V 45 55 %
TTLH DATA Output data rise time 20 – 80 %, 50 Ωto -2 V 350 700 ps
TTHL DATA Output data fall time 80 – 20 %, 50 Ωto -2 V 350 700 ps
TDDOUT from CKOUT See figure 7 275 ps
TFP FP from CKOUT See figure 8 275 ps
TFF, SETUP FFIN set-up from FRAME start See figure 8 1000 600 ps
Data Sheet Rev. 04 GD16504 Page 10
DOUT
CKOUT
TD
FFIN/FFINN
TFF,SETUP
TFF
TFP
SIP/SIN
DOUT
CKOUT
FP/FPN
Symbol: Characteristic: Conditions: MIN.: TYP.: MAX.: UNIT:
TFF FFIN pulse width See figure 8 3ns
NSERIAL –PARALLEL no. of bits stored in pipelines 40 bits
Note 1: 1UI
16 = 40 ns; Data Pattern 223-1 PRBS.
Note 2: Data Pattern 223-1 PRBS. Through careful filter design, loop peaking may be controlled which is the major
contribute to Jitter Transfer.
Note 3: In the absence of input jitter, the intrinsic jitter at CKOUT as measured over a 60 seconds interval shall not exceed these
limits (1 UI1= 6.43 ns).
Note 4: Max. deviation between reference clock input and divided VCO clock when in lock.
Package Outline
Figure 9. Package 144 pfBGA
Data Sheet Rev. 04 GD16504 Page 11
Figure 10.Package 68 pin MLC
Device Marking
Ordering Information
Please order as specified below:
Product Name: Package Type: Case Temperature Range: Options:
GD16504-144EA 144 pfBGA 0..85 °C
GD16504-68BA 68 pin Ceramic (MLC) 0..85 °C
GD16504, Data Sheet Rev. 04 - Date: 11 May 1999
The information herein is assumed to be
reliable. GIGA assumes no responsibility
for the use of this information, and all such
information shall be at the users own risk.
Prices and specifications are subject to
change without notice. No patent rights or
licenses to any of the circuits described
herein are implied or granted to any third
party. GIGA does not authorise or warrant
any GIGA Product for use in life support
devices and/or systems.
Mileparken 22, DK-2740 Skovlunde
Denmark
Telephone : +45 4492 6100
Telefax : +45 4492 5900
E-mail : sales@giga.dk
Web site : http://www.giga.dk
Please check our Internet web site
for latest version of this data sheet.
Distributor:
Copyright © 1999 GIGA A/S
All rights reserved
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