2.5 Gbit/s Clock and Data Recovery Circuit GD16504 Preliminary General Description Features The GD16504 is a high performance monolithic integrated 2.488 Gbit/s Clock and Data Recovery (CDR) device applicable for optical communication systems including: u SDH STM-16 u SONET OC-48. The CDR contains all circuits needed for reliable acquisition and lock of the VCO phase onto the incoming data. The electrical input sensitivity is better than 20 mV. Optical receivers with sensitivity better than -34 dBm have been obtained without optical pre-amplification. The device meets all ITU-T jitter requirements when used with the recommended loop filter (jitter tolerance, -transfer and -generation). The integrated 1:16 demultiplexer with differential ECL outputs ensures a simple and universal interface to the system CMOS ASICs. The 155 MHz output clock is maintained within 500 ppm tolerance even in absence of data. A triggerable Frame Alignment circuit detecting the occurrence of a framing pattern and aligning data at the 16 bit output interface. Once the frame is found, the circuit detects and flags all A1A1A2A2 sequences at the aligned byte boundary. All high speed I/O levels are ECL compatible. The data input has improved sensitivity and is connected via a 50 loop through transmission line to minimize stub related reflections. It is packed in a plastic fpBGA with internal 50 transmission lines, heat transport to PCB, reduced mechanical stress and removed requirement for a heat sink. All signals are available in two outher ring for easy routing. It is also available in a 68 pin leaded Multi Layer Ceramic (MLC) package with 50 transmission lines and cavity down for easy cooling/heat sinking. FFIN FFINN l Clock and Data Recovery at 2.488 Gbit/s. l SDH STM-16, SONET OC-48 compatible. l Differential Data inputs better than 20 mV sensitivity for BER 10-9. l Differential ECL Data and Clock outputs. l Acquisition time < 500 s. l Few external passive components needed. l 50 Loop-Through data inputs for higher sensitivity. l Frame Detection and user triggered alignment at 16 bits boundary. l Single supply operation. l Power dissipation: 2.5 W l Available in: - 144 ld. fpBGA - 68 pin Multi Layer Ceramic leaded package with 50 transmission lines. l GD16504-68BA is 100% interchangeable with GD16045, only loop filter has to be changed. FP FPN Frame Align. VSOPEN CKOUT CKOUN Clock Divide SOP SON LD LOS DI SIPO SIPI + SINI - SINO Dec. Data Sheet Rev. 04 R REFCK REFCKN DOUT15 DOUN15 SELTCK TCK DI SEL1 SEL2 DOUT0 DOUN0 DeMUX :4 Lock Detect Circuit Bang Bang Phase Detector DO U D VCO 4:2 MUX V R Phase Frequency Detector U D U D Charge Pump Applications l VCTL OUCHP VDD VDDA VEE VEEA VCSREF LOCK Clock and Data Recovery for: - SDH STM-16 - SONET OC-48 systems Functional Details The main application of the GD16504 is as Clcok and Data Recovery in optical communication systems including: u SDH STM-16 u SONET OC-48 It integrates: u a Voltage Controlled Oscillator (VCO) u a Lock Detect Circuit u a Frequency Detector (PFD) u a 1:16 DeMUX with framer. u a Bang-Bang Phase Detector into a clock and data recovery circuit followed by a 1:16 demultiplexer with differential ECL data and clock outputs. tion occurs between 2 consecutive bits the value of the sample in the transition between the bits determines whether the VCO clock leads or lags the data. Hence the Phase Locked Loop (PLL) is controlled by the bit transition point, thereby ensuring that data is sampled in the middle of the eye, once the system is in CDR mode. The external loop filter controls the characteristics of the PLL. OUCHP 330R 82R 100nF VCO The VCO is a low noise LC-type differential oscillator running 2.488 GHz. Tuning is done by applying a voltage to the VCTL pin. Lock Detect Circuit The Lock Detect Circuit continuously monitors the difference between the reference clock, which is at 1/16 of the data rate, and the divided VCO clock. If the reference clock and the divided VCO frequency differs by more than 500 ppm (or 2000 ppm, selectable), it switches the PFD into the PLL in order to pull the VCO back inside the lock-in range. This mode is called the acquisition mode. Once the VCO is inside the lock-range the lock-detection circuit switches the BangBang phase detector into the PLL in order to lock to the data signal. This mode is called CDR mode. The status of the lock-detection circuit is given by output pin LOCK. In acquisition mode LOCK is low. In acquisition mode a PFD is used to ensure predictable lock up conditions for the GD16504 by locking the VCO to an external reference clock source. It is only used during acquisition and pulls the VCO into the lock range where the BangBang phase detector is capable of acquiring lock. The PFD is made with digital set/reset cells giving it a true phase and frequency characteristic. The reference clock input, REFCK, to the PFD is at 1/16 of the data rate. Bang-Bang Phase Detector The Bang-Bang phase detector is used in CDR mode as a true digital type phase detector, producing a binary output. It samples the incoming data twice each bit period, once on the transition of the previous bit period and once in the middle of the bit period. When a transi- Data Sheet Rev. 04 VCTL Figure 1. Loop Filter small (few degrees), forcing the loop to be at one edge of the error-function shaped transfer characteristic of the detector. If a LOS is detected by the optical circuit in front of GD16504, the SEL1 and SEL2 may be configured to force the PLL to use the Frequency Detector providing a stable output clock locked only to reference input regardless of Lock Detect status and at the same time force all outputs to logic low. The configuration signals (SEL1 and SEL2) may be tied to VDD or VEE directly. The combination resets all Flip Flops, and sets both Up and Down active at the input of the Charge Pump, leaving the output in the middle of its output range. Since the circuit is self synchronizing, reset need not be asserted during power up. The binary output of either the PFD or the Bang-Bang phase detector (depending of the mode of the lock-detection circuit) is fed to a charge pump capable of sinking or sourcing current or tristating. The output of the charge pump is filtered through the loop filter and controls the tuning-voltage of the VCO. A result of the continuous lock-detect monitoring circuit is that the VCO frequency never deviates more than 500 ppm (2000 ppm) from the reference clock before the PLL is considered to be 'Out of Lock'. Hence the acquisition time is predictable and short and the output clock CKOUT is always kept within the 500 ppm (2000 ppm) limits ensuring safe clocking of down stream circuitry. The LOCK Signal The LOCK output may be used to generate Loss of Signal (LOS). The time for LOCK to assert is predictable and short, equal to the time to go into lock, but the time for LOCK to de-assert must be considered. When the line is down (i.e. no information received) the optical receiver circuit may produce random noise. It is possible that this random noise will keep the GD16504 within the 500 ppm (2000 ppm) range of the line frequency, hence LOCK will remain asserted for a non-deterministic time. This may be prevented by injecting a small current at the loop filter node, which actively pulls the PLL out of the lock range when the output of the phase detector acts randomly. The negligible penalty paid is a static phase error. However, due to the nature of the phase detector the error will be GD16504 Page 2 Data Inputs The input amplifier (pins SIPI / SINI and SIPO / SINO) is designed as a limiting amplifier with a sensitivity better than 20 mV (differential). The inputs may be either AC or DC coupled. In either case input termination is made through pins SIPO / SINO. If the inputs are ACcoupled the amplifier features an internal offset cancelling DC feedback path. All four AC coupling capacitors should be identical for optimum performance. Notice that the offset cancellation will only work when the input is differential and AC- coupled as shown in the Figure 3. SIPI From LINE 8k 50R VTT 50R VTT SIPO + SINO 26dB - 8k SINI From LINE Figure 2. DC Coupled Input (Ignoring internal offset compensation) SIPI From LINE 8k VTT 50R SIPO 50R SINO VTT From LINE + 26dB - 8k SINI Figure 3. AC Coupled Input (Using internal offset compensation) Following the CDR block the data is 1:16 demultiplexed with frame detect and alignment, and output together with a 155 MHz clock. The data and clock outputs are differential ECL outputs that should be terminated via 50 to -2 V. The GD16504 includes a serial open collector output intended to loop data to GD16505 as shown in Figure 4 below. + - SOP SIP SON SIN GD16504 + GD16505 Figure 4. Test Link Connection between GD16504 and GD16505 GD16504-68BA The 68 pin CQFP has a reduced pin count, this will affect some at the differential signals that will become single ended. The unconnected (inverted) input is biased to -1.3 V internally on the chip. This will give the threshold at the single ended signal. Affected signals are: Inputs: FFIN and REFCK Output: FP u u Frame Alignment The Frame Detect Alignment (FDA) circuit uses the available 48 A1 bytes in the incoming data stream to align byte wise and search for valid Frame Sequences (A1-A1-A2-A2). At the falling edge of the FFIN signal, the FDA starts looking for valid A1's in the incoming data stream, regardless of byte boundary. To align at the byte boundary, at least 7 A1's should be valid in a row, followed by more than 2 valid A1's for each erroneous A1. When the byte alignment is locked, the FDA asserts FP at the first occurrence of A1-A1-A2-A2, which must be valid. Note that the A1 used for byte alignment could be the same as used for the frame alignment, meaning that a sequence of 7 A1's followed by 2 A2's will result in 100% alignment. When a frame has been found and the FFIN is not triggered, only frame sequences (A1-A1-A2-A2) occurring at the previously aligned byte boundary is detected. This way the circuit serves two functions. When acquiring Frame Alignment, the assertion of the FFIN / FFINN signal starts the FDA alignment and when the first valid sequence is found, the byte boundary is fixed and the FP / FPN output signal is pulsed. The byte boundary is held until the next falling edge on FFIN / FFINN, and only valid sequences at the fixed byte boundary will be flagged by the FP / FPN signal. This allows the user to control when to align, and to have flagged all valid sequences once alignment is achieved. Note that all valid sequences (7 A1's followed by 2 A2's) will be flagged, regardless of their mutual distance. The mean time to align and detect a frame pulse (BER = 0) is 0.5 x Frame (62.5 s), since the FDA will align and pulse FP upon reception of the first Frame Sequence. Data Sheet Rev. 04 GD16504 Page 3 Pin List Mnemonic: Pin No.: 144 EA 68 BA Pin Type: Description: SIP, SIPO E1, F1 62, 61 Anl. IN Loop-through serial positive differential input. Optimised for max. sensitivity; may be used as ECL input. SIN, SINO D1, C1 63, 64 Anl. IN Loop-through serial negative differential input. Optimised for max. sensitivity; may be used as ECL input. SOP, SON J1, H1 58, 59 CML OUT Buffered differential serial data output. High speed Open Collector Drain output to be used in conjunction with GD16505 for remote/optical loop back. Consult GIGA for information. DOUT0, DOUN0 DOUT1, DOUN1 DOUT2, DOUN2 DOUT3, DOUN3 DOUT4, DOUN4 DOUT5, DOUN5 DOUT6, DOUN6 DOUT7, DOUN7 DOUT8, DOUN8 DOUT9, DOUN9 DOUT10, DOUN10 DOUT11, DOUN11 DOUT12, DOUN12 DOUT13, DOUN13 DOUT14, DOUN14 DOUT15, DOUN15 A11, A10 B12, A12 D11, C12 D12, E11 F12, F11 G12, G11 H12, H11 J12, J11 L12, K12 M11, M12 M9, M10 L8, L9 M7, M8 M6, L7 M4, M5 L3, M3 12, 11 15, 13 19, 16 22, 20 24, 23 27, 25 29, 28 32, 30 36, 33 39, 37 41, 40 44, 42 46, 45 49, 47 53, 50 56, 54 ECL OUT Retimed differential data output from DeMUX, bit 15 is the first received. After frame synchronisation, the data is byte-aligned with the first A2 byte placed at bit 15 through 8. When LOCK = "0" or SEL1= "1" and SEL2 = "0" (LOS), all outputs will be logic low REFCK, REFCKN A6, A7 6, N/A ECL IN 155 MHz reference clock input. Both biased to -1.3 V in 68BA version CKOUT, CKOUN A9, B9 10, 8 ECL OUT SEL1, SEL2 A1, E12 67, 18 ECL IN Regenerated differential output clock, 155 MHz. Single-ended inputs, PLL set-up of Internal/ External switch mode and LOCK: SEL1 SEL2 0 0 Auto lock, 500ppm. 0 1 Global Reset for test purpose only. 1 0 Manual, Phase/ Freq. det, 500 ppm,LOS mode. 1 1 Manual, Phase detector, 2000 ppm. The LOS mode cause all 16 data outputs, FP and LOCK into logic low. FFIN, FFINN B8, A8 7, N/A ECL IN B6 5 ECL OUT Single ended CDR Lock alarm output. When low, the divided VCO freq. deviates more than 500/2000 ppm from REFCK. When system is unlocked, all 16 data outputs and FP will be logic low. When SEL1 = "1" and SEL2 = "0" (LOS), the LOCK will be logic low. M1, L1 57, N/A ECL OUT Frame Pulse. One pulse (6.1 ns) indicates that a valid Frame Sequence has been detected. When LOCK = "0" SEL1 = "1" and SEL2 = "0" (LOS), the FP / FPN will be logic low. FP/ FPN is also low during reset. single ended output in 68-pin CQFP. Differential in other packages. VCTL A3 2 Anl. IN OUCHP A4 3 Anl. OUT TCK A2 66 ECL IN LOCK FP, FPN Data Sheet Rev. 04 Frame FINd signal. A falling edge at this input activates the frame search. Single ended in 68-pin CQFP. VCO control voltage input. Phase detector or Phase / frequency charge pump output. DC - functional and parametric test clock input. Bypasses the VCO when SELTCK is high. GD16504 Page 4 Mnemonic: Pin No.: 144 EA 68 BA Pin Type: VDD B1, C2, D2, 4, 9, 14, 21, 26, 31, 38, D4..9, E2, 43, 48, 55, E4..9, F2, 60, 65 F4..9, G1, G2, G4..9, H2, H4..H9, J2, J4..J9, K1, K2, M2 PWR 0 V Power for core and ECL I/O. VEE C3..5, C10, D3, D10, E3, E10, F3, F10, G3, G10, H3, H10, J3, J10, K3..5 34, 35, 68 PWR -5 V Power for core and ECL I/O. VDDA A5, B5 17 PWR 0 V Power for VCO VEEA B3, B4 52 PWR -5 V Power for VCO. SELTCK B2 1 PWR Select test clock, for DC test only, connect to VEE. VSOPEN L2 51 PWR 0 V power for Serial Output (SOP/SON). If output is not used, VSOPEN may be left open (or connected to VEE), saving power. Nominal current is 0.5 mA. VCSREF L6 N/A ANALOG B7, B10, B11, C6..9, C11, K6..9, K10, K11, L10, L11, L4, L5 N/A NC Data Sheet Rev. 04 Description: Internal reference voltage, leave open Not used. Reserved for future use. GD16504 Page 5 Package Pinout 1 2 3 1 K TC T VC D C EL E VE A D VD E VE A L SE B VD C O SIN D SIN VD E SIP VD F O SIP VD G VD D H N SO J SO K D VD L FP M P N L TK S 4 D VE D VE D VE VD D VE D VD VE VD D D VD P 6 A H UC D VD E VE A D VD E VE E VE O E VD E VD E VD E A 7 K C EF 8 KN 9 N C EF IN FF C LO NC FF NC NC R K R IN NC D VD D VD D VD VD D E D VD VE E VD VD VD VD VD E VE E VE E VE NC NC NC 15 EN UT NC O D NC R CS D P SO V 5 FP D VD 1 2 D VD D VD D VD VD D D VD D D VD D VD D VD VD D D VD VD D VD D VD VD D D VD T U KO C UN O CK NC D VD D VD D VD VD D D VD 11 0 12 0 D NC NC U DO E VE NC E U DO E U DO E U DO E U DO E U DO D D T2 VE D VE D VE VD D VE D VD VE VD D VE E U DO NC NC NC 3 1 1 EF T1 N1 NC N1 U U U O D DO DO NC D D 1 T OU N OU D D V D 10 N3 N4 N5 N6 N7 N OU T1 2 N OU D T3 U DO L2 SE T4 U DO T5 U DO T6 U DO T7 U DO 8 N OU D T8 U DO 2 0 4 3 2 0 4 15 T9 N9 T1 T1 T1 T1 N1 N1 N1 U U U U U U U U U DO DO DO DO DO DO DO DO DO N OU D 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M 12 Figure 5. Package Pinout, 144 EA - Top View (seen through the package) Data Sheet Rev. 04 GD16504 Page 6 VDDA DOUN2 DOUT1 VDD DOUN1 DOUT0 DOUN0 CKOUT VDD CKOUN FFIN REFCK LOCK VDD OUCHP VCTL SELTCK 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SEL2 18 68 VEE DOUT2 19 67 SEL1 DOUN3 20 66 TCK VDD 21 65 VDD DOUT3 22 64 SINO DOUN4 23 63 SIN DOUT4 24 62 SIP DOUN5 25 61 SIPO VDD 26 60 VDD DOUT5 27 59 SON DOUN6 28 58 SOP DOUT6 29 57 FP DOUN7 30 56 DOUT15 VDD 31 55 VDD DOUT7 32 54 DOUN15 DOUN8 33 53 DOUT14 VEE 34 52 VEEA 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 VEE DOUT8 DOUN9 VDD DOUT9 DOUN10 DOUT10 DOUN11 VDD DOUT11 DOUN12 DOUT12 DOUN13 VDD DOUT13 DOUN14 VSOPEN Figure 6. Package Pinout, 68 BA - Top View Data Sheet Rev. 04 GD16504 Page 7 Maximum Ratings These are the limits beyond which the component may be damaged. All voltages in the table are referred to VDD. All currents in the table are defined positive out of the pin. Symbol: Characteristic: VEE, VEEA Negative Supply V0 ECL Output Voltage ECL I0 ECL Output Current ECL I0 MAX, CHPO Output Current V1 ECL Input Voltage ECL I1 ECL Input Current T0 Operating Temperature TS Storage Temperature Data Sheet Rev. 04 Conditions: MAX.: UNIT: -7 0 V VEE -0.5 0.5 V 40 mA 0.25 mA VEE -0.5 0.5 V ECL -1.0 1.0 mA Junction -40 +125 C -65 +150 C GD16504 MIN.: TYP.: Page 8 DC Characteristics TCASE = 0 C to 85 C, VEE = -4.75 to -5.25 V J-C = 7EC/W, for 68-pin CQFP. All voltages in the table are referred to VDD. All input signal and power currents in the table are defined positive into the pin. All output signal currents are defined positive out of the pin. Symbol: Characteristic: VEE Supply Voltage IEE Supply Current Conditions: MIN.: TYP.: -5.25 -9 MAX.: UNIT.: -4.75 V 500 mA VI SINX/SIPX Minimum Data Input Swing for 10 BER Note 5 25 mV VI SINX/SIPX Data Input Swing Note 5 1000 mV VICM SINX/SIPX Data Common Mode Voltage -1 V VIL ECL ECL Input LO Voltage Note 1 VEE -1.5 V VIH ECL ECL Input HI Voltage Note 1 -1.1 0 V IIH ECL ECL Input HI Current VIH 12 100 A IIL ECL ECL Input LO Current VIL = -1.8 0.01 -1 A VOH ECL ECL Output HI Voltage Note 1, 2 -1.0 -0.5 V VOL ECL ECL Output LO Voltage Note 1, 2 VTT -1.6 V IOH ECL ECL Output HI Current Note 3 20 23 30 mA IOL ECL ECL Output LO Current Note 3 -2 5 8 mA IOH CML CML Output HI Current 0 mA IOL CML CML Output LO Current 8 mA VVCTL VCO Control Voltage IVCTL < 30 mA IOH CHP OUCHP Source Current (DC Steady) Note 4 100 A IOL CHP OUCHP Sink Current (DC Steady) Note 4 100 A Note 1: Note 2: Note 3: Note 4: Note 5: -2 = -0.7 -1.3 VEE -1 V VTT = -2.0 V 5 % RLOAD = 50 to VTT Not tested, consistent with VOH and VOL tests. Output terminated to -2.5 V during test. Minimum data input swing to ensure 10-9 BER. It is defined as the differential (p-p) voltage between the two inputs, i.e. as the p-p voltage on SIPI + the p-p voltage on SINI. In case of unbalanced signals it is defined as twice the minimum voltage difference between SIPI and SINI (see figure below). SIPI SINI Minimum voltage difference between SIPI and SINI Data Sheet Rev. 04 GD16504 Page 9 AC Characteristics TCASE = 0 C to 85 C, VEE = -4.75 V to -5.25 V. DOUT CKOUT TD Figure 7. Time (TD) TFF,SETUP TFF FFIN/FFINN SIP/SIN DOUT CKOUT FP/FPN TFP Figure 8. Frame Align Signal Timing Note: During align, A2 byte marked with * may not be valid although frame is correctly aquired (F6H or 28H) Symbol: Characteristic: Conditions: MIN.: TYP.: JTOL Jitter Tolerance 2 Hz < F < 100 kHz (Note 1) 1 MHz < F< 5 MHz (Note 1) 1.5 0.15 >2 >0.35 JTRF Jitter Transfer 5 kHz < F < 2 MHz (Note 2) JCLK Output Clock Intrinsic Jitter 5 kHz < F < 20 MHz (Note 3) 1 MHz < F < 20 MHz (Note 3) TA Aquisition time 2 -1 PRBS LCID Consecutive Identical Digits No. bits with no transitions 400 DC Input Clock / REFXI frequency deviation Note 4 -200 200 ppm CDUTY REFCK REFCK clock duty cycle VThresh.= -1.3 V 40 60 % CDUTY CKOUT Output clock duty cycle VThresh.= -1.3 V, 50 to -2 V 45 55 % TTLH DATA Output data rise time 20 - 80 %, 50 to -2 V 350 700 ps TTHL DATA Output data fall time 80 - 20 %, 50 to -2 V 350 700 ps TD DOUT from CKOUT See figure 7 275 ps TFP FP from CKOUT See figure 8 275 ps TFF, SETUP FFIN set-up from FRAME start See figure 8 600 ps Data Sheet Rev. 04 0.08 23 GD16504 50 1000 MAX.: UNIT: UI16, PP UI16, PP 0.1 dB 0.125 0.05 UI1 UI1 500 s 1000 bits Page 10 Symbol: Characteristic: Conditions: MIN.: TFF FFIN pulse width See figure 8 3 NSERIAL -PARALLEL no. of bits stored in pipelines Note 1: Note 2: Note 3: Note 4: TYP.: MAX.: UNIT: ns 40 bits 1 UI16 = 40 ns; Data Pattern 223-1 PRBS. Data Pattern 223-1 PRBS. Through careful filter design, loop peaking may be controlled which is the major contribute to Jitter Transfer. In the absence of input jitter, the intrinsic jitter at CKOUT as measured over a 60 seconds interval shall not exceed these limits (1 UI1 = 6.43 ns). Max. deviation between reference clock input and divided VCO clock when in lock. Package Outline Figure 9. Package 144 pfBGA Data Sheet Rev. 04 GD16504 Page 11 Figure 10.Package 68 pin MLC Device Marking GD16504 <Mask ID> <Lot ID> <WW YY> Ordering Information Please order as specified below: Product Name: Package Type: Case Temperature Range: GD16504-144EA GD16504-68BA 144 pfBGA 0..85 C 68 pin Ceramic (MLC) 0..85 C Options: GD16504, Data Sheet Rev. 04 - Date: 11 May 1999 Mileparken 22, DK-2740 Skovlunde Denmark Telephone : +45 4492 6100 Telefax : +45 4492 5900 E-mail : sales@giga.dk Web site : http://www.giga.dk Please check our Internet web site for latest version of this data sheet. The information herein is assumed to be reliable. GIGA assumes no responsibility for the use of this information, and all such information shall be at the users own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. GIGA does not authorise or warrant any GIGA Product for use in life support devices and/or systems. Distributor: Copyright (c) 1999 GIGA A/S All rights reserved